2 /*******************************************************************************
4 * Module Name: hwregs - Read/write access functions for the various ACPI
5 * control and status registers.
7 ******************************************************************************/
10 * Copyright (C) 2000 - 2008, Intel Corp.
11 * All rights reserved.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
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18 * without modification.
19 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
20 * substantially similar to the "NO WARRANTY" disclaimer below
21 * ("Disclaimer") and any redistribution must be conditioned upon
22 * including a substantially similar Disclaimer requirement for further
23 * binary redistribution.
24 * 3. Neither the names of the above-listed copyright holders nor the names
25 * of any contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
28 * Alternatively, this software may be distributed under the terms of the
29 * GNU General Public License ("GPL") version 2 as published by the Free
30 * Software Foundation.
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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46 #include <acpi/acpi.h>
51 #define _COMPONENT ACPI_HARDWARE
52 ACPI_MODULE_NAME("hwregs")
54 /* Local Prototypes */
56 acpi_hw_read_multiple(u32
*value
,
57 struct acpi_generic_address
*register_a
,
58 struct acpi_generic_address
*register_b
);
61 acpi_hw_write_multiple(u32 value
,
62 struct acpi_generic_address
*register_a
,
63 struct acpi_generic_address
*register_b
);
65 /*******************************************************************************
67 * FUNCTION: acpi_hw_clear_acpi_status
73 * DESCRIPTION: Clears all fixed and general purpose status bits
75 ******************************************************************************/
77 acpi_status
acpi_hw_clear_acpi_status(void)
80 acpi_cpu_flags lock_flags
= 0;
82 ACPI_FUNCTION_TRACE(hw_clear_acpi_status
);
84 ACPI_DEBUG_PRINT((ACPI_DB_IO
, "About to write %04X to %0llX\n",
85 ACPI_BITMASK_ALL_FIXED_STATUS
,
86 acpi_gbl_xpm1a_status
.address
));
88 lock_flags
= acpi_os_acquire_lock(acpi_gbl_hardware_lock
);
90 /* Clear the fixed events in PM1 A/B */
92 status
= acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS
,
93 ACPI_BITMASK_ALL_FIXED_STATUS
);
94 if (ACPI_FAILURE(status
)) {
98 /* Clear the GPE Bits in all GPE registers in all GPE blocks */
100 status
= acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block
, NULL
);
103 acpi_os_release_lock(acpi_gbl_hardware_lock
, lock_flags
);
104 return_ACPI_STATUS(status
);
107 /*******************************************************************************
109 * FUNCTION: acpi_hw_get_register_bit_mask
111 * PARAMETERS: register_id - Index of ACPI Register to access
113 * RETURN: The bitmask to be used when accessing the register
115 * DESCRIPTION: Map register_id into a register bitmask.
117 ******************************************************************************/
119 struct acpi_bit_register_info
*acpi_hw_get_bit_register_info(u32 register_id
)
121 ACPI_FUNCTION_ENTRY();
123 if (register_id
> ACPI_BITREG_MAX
) {
124 ACPI_ERROR((AE_INFO
, "Invalid BitRegister ID: %X",
129 return (&acpi_gbl_bit_register_info
[register_id
]);
132 /******************************************************************************
134 * FUNCTION: acpi_hw_write_pm1_control
136 * PARAMETERS: pm1a_control - Value to be written to PM1A control
137 * pm1b_control - Value to be written to PM1B control
141 * DESCRIPTION: Write the PM1 A/B control registers. These registers are
142 * different than than the PM1 A/B status and enable registers
143 * in that different values can be written to the A/B registers.
144 * Most notably, the SLP_TYP bits can be different, as per the
145 * values returned from the _Sx predefined methods.
147 ******************************************************************************/
149 acpi_status
acpi_hw_write_pm1_control(u32 pm1a_control
, u32 pm1b_control
)
153 ACPI_FUNCTION_TRACE(hw_write_pm1_control
);
155 status
= acpi_write(pm1a_control
, &acpi_gbl_FADT
.xpm1a_control_block
);
156 if (ACPI_FAILURE(status
)) {
157 return_ACPI_STATUS(status
);
160 if (acpi_gbl_FADT
.xpm1b_control_block
.address
) {
162 acpi_write(pm1b_control
,
163 &acpi_gbl_FADT
.xpm1b_control_block
);
165 return_ACPI_STATUS(status
);
168 /******************************************************************************
170 * FUNCTION: acpi_hw_register_read
172 * PARAMETERS: register_id - ACPI Register ID
173 * return_value - Where the register value is returned
175 * RETURN: Status and the value read.
177 * DESCRIPTION: Read from the specified ACPI register
179 ******************************************************************************/
181 acpi_hw_register_read(u32 register_id
, u32
* return_value
)
186 ACPI_FUNCTION_TRACE(hw_register_read
);
188 switch (register_id
) {
189 case ACPI_REGISTER_PM1_STATUS
: /* PM1 A/B: 16-bit access each */
191 status
= acpi_hw_read_multiple(&value
,
192 &acpi_gbl_xpm1a_status
,
193 &acpi_gbl_xpm1b_status
);
196 case ACPI_REGISTER_PM1_ENABLE
: /* PM1 A/B: 16-bit access each */
198 status
= acpi_hw_read_multiple(&value
,
199 &acpi_gbl_xpm1a_enable
,
200 &acpi_gbl_xpm1b_enable
);
203 case ACPI_REGISTER_PM1_CONTROL
: /* PM1 A/B: 16-bit access each */
205 status
= acpi_hw_read_multiple(&value
,
209 xpm1b_control_block
);
212 case ACPI_REGISTER_PM2_CONTROL
: /* 8-bit access */
214 status
= acpi_read(&value
, &acpi_gbl_FADT
.xpm2_control_block
);
217 case ACPI_REGISTER_PM_TIMER
: /* 32-bit access */
219 status
= acpi_read(&value
, &acpi_gbl_FADT
.xpm_timer_block
);
222 case ACPI_REGISTER_SMI_COMMAND_BLOCK
: /* 8-bit access */
225 acpi_hw_read_port(acpi_gbl_FADT
.smi_command
, &value
, 8);
229 ACPI_ERROR((AE_INFO
, "Unknown Register ID: %X", register_id
));
230 status
= AE_BAD_PARAMETER
;
234 if (ACPI_SUCCESS(status
)) {
235 *return_value
= value
;
238 return_ACPI_STATUS(status
);
241 /******************************************************************************
243 * FUNCTION: acpi_hw_register_write
245 * PARAMETERS: register_id - ACPI Register ID
246 * Value - The value to write
250 * DESCRIPTION: Write to the specified ACPI register
252 * NOTE: In accordance with the ACPI specification, this function automatically
253 * preserves the value of the following bits, meaning that these bits cannot be
254 * changed via this interface:
256 * PM1_CONTROL[0] = SCI_EN
261 * 1) Hardware Ignored Bits: When software writes to a register with ignored
262 * bit fields, it preserves the ignored bit fields
263 * 2) SCI_EN: OSPM always preserves this bit position
265 ******************************************************************************/
267 acpi_status
acpi_hw_register_write(u32 register_id
, u32 value
)
272 ACPI_FUNCTION_TRACE(hw_register_write
);
274 switch (register_id
) {
275 case ACPI_REGISTER_PM1_STATUS
: /* PM1 A/B: 16-bit access each */
277 * Handle the "ignored" bit in PM1 Status. According to the ACPI
278 * specification, ignored bits are to be preserved when writing.
279 * Normally, this would mean a read/modify/write sequence. However,
280 * preserving a bit in the status register is different. Writing a
281 * one clears the status, and writing a zero preserves the status.
282 * Therefore, we must always write zero to the ignored bit.
284 * This behavior is clarified in the ACPI 4.0 specification.
286 value
&= ~ACPI_PM1_STATUS_PRESERVED_BITS
;
288 status
= acpi_hw_write_multiple(value
,
289 &acpi_gbl_xpm1a_status
,
290 &acpi_gbl_xpm1b_status
);
293 case ACPI_REGISTER_PM1_ENABLE
: /* PM1 A/B: 16-bit access */
295 status
= acpi_hw_write_multiple(value
,
296 &acpi_gbl_xpm1a_enable
,
297 &acpi_gbl_xpm1b_enable
);
300 case ACPI_REGISTER_PM1_CONTROL
: /* PM1 A/B: 16-bit access each */
303 * Perform a read first to preserve certain bits (per ACPI spec)
304 * Note: This includes SCI_EN, we never want to change this bit
306 status
= acpi_hw_read_multiple(&read_value
,
310 xpm1b_control_block
);
311 if (ACPI_FAILURE(status
)) {
315 /* Insert the bits to be preserved */
317 ACPI_INSERT_BITS(value
, ACPI_PM1_CONTROL_PRESERVED_BITS
,
320 /* Now we can write the data */
322 status
= acpi_hw_write_multiple(value
,
326 xpm1b_control_block
);
329 case ACPI_REGISTER_PM2_CONTROL
: /* 8-bit access */
332 * For control registers, all reserved bits must be preserved,
333 * as per the ACPI spec.
336 acpi_read(&read_value
, &acpi_gbl_FADT
.xpm2_control_block
);
337 if (ACPI_FAILURE(status
)) {
341 /* Insert the bits to be preserved */
343 ACPI_INSERT_BITS(value
, ACPI_PM2_CONTROL_PRESERVED_BITS
,
346 status
= acpi_write(value
, &acpi_gbl_FADT
.xpm2_control_block
);
349 case ACPI_REGISTER_PM_TIMER
: /* 32-bit access */
351 status
= acpi_write(value
, &acpi_gbl_FADT
.xpm_timer_block
);
354 case ACPI_REGISTER_SMI_COMMAND_BLOCK
: /* 8-bit access */
356 /* SMI_CMD is currently always in IO space */
359 acpi_hw_write_port(acpi_gbl_FADT
.smi_command
, value
, 8);
363 ACPI_ERROR((AE_INFO
, "Unknown Register ID: %X", register_id
));
364 status
= AE_BAD_PARAMETER
;
369 return_ACPI_STATUS(status
);
372 /******************************************************************************
374 * FUNCTION: acpi_hw_read_multiple
376 * PARAMETERS: Value - Where the register value is returned
377 * register_a - First ACPI register (required)
378 * register_b - Second ACPI register (optional)
382 * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
384 ******************************************************************************/
387 acpi_hw_read_multiple(u32
*value
,
388 struct acpi_generic_address
*register_a
,
389 struct acpi_generic_address
*register_b
)
395 /* The first register is always required */
397 status
= acpi_read(&value_a
, register_a
);
398 if (ACPI_FAILURE(status
)) {
402 /* Second register is optional */
404 if (register_b
->address
) {
405 status
= acpi_read(&value_b
, register_b
);
406 if (ACPI_FAILURE(status
)) {
412 * OR the two return values together. No shifting or masking is necessary,
413 * because of how the PM1 registers are defined in the ACPI specification:
415 * "Although the bits can be split between the two register blocks (each
416 * register block has a unique pointer within the FADT), the bit positions
417 * are maintained. The register block with unimplemented bits (that is,
418 * those implemented in the other register block) always returns zeros,
419 * and writes have no side effects"
421 *value
= (value_a
| value_b
);
425 /******************************************************************************
427 * FUNCTION: acpi_hw_write_multiple
429 * PARAMETERS: Value - The value to write
430 * register_a - First ACPI register (required)
431 * register_b - Second ACPI register (optional)
435 * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
437 ******************************************************************************/
440 acpi_hw_write_multiple(u32 value
,
441 struct acpi_generic_address
*register_a
,
442 struct acpi_generic_address
*register_b
)
446 /* The first register is always required */
448 status
= acpi_write(value
, register_a
);
449 if (ACPI_FAILURE(status
)) {
454 * Second register is optional
456 * No bit shifting or clearing is necessary, because of how the PM1
457 * registers are defined in the ACPI specification:
459 * "Although the bits can be split between the two register blocks (each
460 * register block has a unique pointer within the FADT), the bit positions
461 * are maintained. The register block with unimplemented bits (that is,
462 * those implemented in the other register block) always returns zeros,
463 * and writes have no side effects"
465 if (register_b
->address
) {
466 status
= acpi_write(value
, register_b
);