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ALSA: hda_intel: add position_fix quirk for Asus K53E
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_STANDARD = 5,
57 };
58
59 enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nosntf,
64 board_ahci_yes_fbs,
65
66 /* board IDs for specific chipsets in alphabetical order */
67 board_ahci_mcp65,
68 board_ahci_mcp77,
69 board_ahci_mcp89,
70 board_ahci_mv,
71 board_ahci_sb600,
72 board_ahci_sb700, /* for SB700 and SB800 */
73 board_ahci_vt8251,
74
75 /* aliases */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
79 board_ahci_mcp79 = board_ahci_mcp77,
80 };
81
82 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
83 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 #ifdef CONFIG_PM
88 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89 static int ahci_pci_device_resume(struct pci_dev *pdev);
90 #endif
91
92 static struct scsi_host_template ahci_sht = {
93 AHCI_SHT("ahci"),
94 };
95
96 static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
98 .hardreset = ahci_vt8251_hardreset,
99 };
100
101 static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
103 .hardreset = ahci_p5wdh_hardreset,
104 };
105
106 static const struct ata_port_info ahci_port_info[] = {
107 /* by features */
108 [board_ahci] = {
109 .flags = AHCI_FLAG_COMMON,
110 .pio_mask = ATA_PIO4,
111 .udma_mask = ATA_UDMA6,
112 .port_ops = &ahci_ops,
113 },
114 [board_ahci_ign_iferr] = {
115 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
116 .flags = AHCI_FLAG_COMMON,
117 .pio_mask = ATA_PIO4,
118 .udma_mask = ATA_UDMA6,
119 .port_ops = &ahci_ops,
120 },
121 [board_ahci_nosntf] = {
122 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
127 },
128 [board_ahci_yes_fbs] = {
129 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
134 },
135 /* by chipsets */
136 [board_ahci_mcp65] = {
137 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
138 AHCI_HFLAG_YES_NCQ),
139 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
144 [board_ahci_mcp77] = {
145 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
151 [board_ahci_mcp89] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mv] = {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
160 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
161 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_sb600] = {
167 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
168 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
169 AHCI_HFLAG_32BIT_ONLY),
170 .flags = AHCI_FLAG_COMMON,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_pmp_retry_srst_ops,
174 },
175 [board_ahci_sb700] = { /* for SB700 and SB800 */
176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
177 .flags = AHCI_FLAG_COMMON,
178 .pio_mask = ATA_PIO4,
179 .udma_mask = ATA_UDMA6,
180 .port_ops = &ahci_pmp_retry_srst_ops,
181 },
182 [board_ahci_vt8251] = {
183 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
184 .flags = AHCI_FLAG_COMMON,
185 .pio_mask = ATA_PIO4,
186 .udma_mask = ATA_UDMA6,
187 .port_ops = &ahci_vt8251_ops,
188 },
189 };
190
191 static const struct pci_device_id ahci_pci_tbl[] = {
192 /* Intel */
193 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
194 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
195 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
196 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
197 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
198 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
199 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
200 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
203 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
204 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
205 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
206 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
207 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
209 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
214 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
220 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
221 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
222 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
223 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
224 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
225 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
226 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
227 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
228 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
229 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
230 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
231 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
232 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
233 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
234 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
236 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
240 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
241 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
242 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
243 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
244 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
245 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
247 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
251 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
252 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
254 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
259
260 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
261 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
262 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
263
264 /* ATI */
265 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
266 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
267 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
268 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
269 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
270 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
271 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
272
273 /* AMD */
274 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
275 /* AMD is using RAID class only for ahci controllers */
276 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
277 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
278
279 /* VIA */
280 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
281 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
282
283 /* NVIDIA */
284 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
285 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
286 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
287 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
288 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
289 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
293 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
294 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
295 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
296 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
305 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
306 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
307 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
308 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
321 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
322 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
323 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
324 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
333 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
334 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
335 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
345 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
346 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
347 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
348 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
357 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
358 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
359 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
360 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
368
369 /* SiS */
370 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
371 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
372 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
373
374 /* ST Microelectronics */
375 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
376
377 /* Marvell */
378 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
379 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
380 { PCI_DEVICE(0x1b4b, 0x9123),
381 .class = PCI_CLASS_STORAGE_SATA_AHCI,
382 .class_mask = 0xffffff,
383 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
384 { PCI_DEVICE(0x1b4b, 0x9125),
385 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
386 { PCI_DEVICE(0x1b4b, 0x917a),
387 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
388 { PCI_DEVICE(0x1b4b, 0x91a3),
389 .driver_data = board_ahci_yes_fbs },
390
391 /* Promise */
392 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
393
394 /* Asmedia */
395 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */
396
397 /* Generic, PCI class code for AHCI */
398 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
399 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
400
401 { } /* terminate list */
402 };
403
404
405 static struct pci_driver ahci_pci_driver = {
406 .name = DRV_NAME,
407 .id_table = ahci_pci_tbl,
408 .probe = ahci_init_one,
409 .remove = ata_pci_remove_one,
410 #ifdef CONFIG_PM
411 .suspend = ahci_pci_device_suspend,
412 .resume = ahci_pci_device_resume,
413 #endif
414 };
415
416 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
417 static int marvell_enable;
418 #else
419 static int marvell_enable = 1;
420 #endif
421 module_param(marvell_enable, int, 0644);
422 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
423
424
425 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
426 struct ahci_host_priv *hpriv)
427 {
428 unsigned int force_port_map = 0;
429 unsigned int mask_port_map = 0;
430
431 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
432 dev_info(&pdev->dev, "JMB361 has only one port\n");
433 force_port_map = 1;
434 }
435
436 /*
437 * Temporary Marvell 6145 hack: PATA port presence
438 * is asserted through the standard AHCI port
439 * presence register, as bit 4 (counting from 0)
440 */
441 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
442 if (pdev->device == 0x6121)
443 mask_port_map = 0x3;
444 else
445 mask_port_map = 0xf;
446 dev_info(&pdev->dev,
447 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
448 }
449
450 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
451 mask_port_map);
452 }
453
454 static int ahci_pci_reset_controller(struct ata_host *host)
455 {
456 struct pci_dev *pdev = to_pci_dev(host->dev);
457
458 ahci_reset_controller(host);
459
460 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
461 struct ahci_host_priv *hpriv = host->private_data;
462 u16 tmp16;
463
464 /* configure PCS */
465 pci_read_config_word(pdev, 0x92, &tmp16);
466 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
467 tmp16 |= hpriv->port_map;
468 pci_write_config_word(pdev, 0x92, tmp16);
469 }
470 }
471
472 return 0;
473 }
474
475 static void ahci_pci_init_controller(struct ata_host *host)
476 {
477 struct ahci_host_priv *hpriv = host->private_data;
478 struct pci_dev *pdev = to_pci_dev(host->dev);
479 void __iomem *port_mmio;
480 u32 tmp;
481 int mv;
482
483 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
484 if (pdev->device == 0x6121)
485 mv = 2;
486 else
487 mv = 4;
488 port_mmio = __ahci_port_base(host, mv);
489
490 writel(0, port_mmio + PORT_IRQ_MASK);
491
492 /* clear port IRQ */
493 tmp = readl(port_mmio + PORT_IRQ_STAT);
494 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
495 if (tmp)
496 writel(tmp, port_mmio + PORT_IRQ_STAT);
497 }
498
499 ahci_init_controller(host);
500 }
501
502 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
503 unsigned long deadline)
504 {
505 struct ata_port *ap = link->ap;
506 bool online;
507 int rc;
508
509 DPRINTK("ENTER\n");
510
511 ahci_stop_engine(ap);
512
513 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
514 deadline, &online, NULL);
515
516 ahci_start_engine(ap);
517
518 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
519
520 /* vt8251 doesn't clear BSY on signature FIS reception,
521 * request follow-up softreset.
522 */
523 return online ? -EAGAIN : rc;
524 }
525
526 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
527 unsigned long deadline)
528 {
529 struct ata_port *ap = link->ap;
530 struct ahci_port_priv *pp = ap->private_data;
531 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
532 struct ata_taskfile tf;
533 bool online;
534 int rc;
535
536 ahci_stop_engine(ap);
537
538 /* clear D2H reception area to properly wait for D2H FIS */
539 ata_tf_init(link->device, &tf);
540 tf.command = 0x80;
541 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
542
543 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
544 deadline, &online, NULL);
545
546 ahci_start_engine(ap);
547
548 /* The pseudo configuration device on SIMG4726 attached to
549 * ASUS P5W-DH Deluxe doesn't send signature FIS after
550 * hardreset if no device is attached to the first downstream
551 * port && the pseudo device locks up on SRST w/ PMP==0. To
552 * work around this, wait for !BSY only briefly. If BSY isn't
553 * cleared, perform CLO and proceed to IDENTIFY (achieved by
554 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
555 *
556 * Wait for two seconds. Devices attached to downstream port
557 * which can't process the following IDENTIFY after this will
558 * have to be reset again. For most cases, this should
559 * suffice while making probing snappish enough.
560 */
561 if (online) {
562 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
563 ahci_check_ready);
564 if (rc)
565 ahci_kick_engine(ap);
566 }
567 return rc;
568 }
569
570 #ifdef CONFIG_PM
571 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
572 {
573 struct ata_host *host = dev_get_drvdata(&pdev->dev);
574 struct ahci_host_priv *hpriv = host->private_data;
575 void __iomem *mmio = hpriv->mmio;
576 u32 ctl;
577
578 if (mesg.event & PM_EVENT_SUSPEND &&
579 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
580 dev_err(&pdev->dev,
581 "BIOS update required for suspend/resume\n");
582 return -EIO;
583 }
584
585 if (mesg.event & PM_EVENT_SLEEP) {
586 /* AHCI spec rev1.1 section 8.3.3:
587 * Software must disable interrupts prior to requesting a
588 * transition of the HBA to D3 state.
589 */
590 ctl = readl(mmio + HOST_CTL);
591 ctl &= ~HOST_IRQ_EN;
592 writel(ctl, mmio + HOST_CTL);
593 readl(mmio + HOST_CTL); /* flush */
594 }
595
596 return ata_pci_device_suspend(pdev, mesg);
597 }
598
599 static int ahci_pci_device_resume(struct pci_dev *pdev)
600 {
601 struct ata_host *host = dev_get_drvdata(&pdev->dev);
602 int rc;
603
604 rc = ata_pci_device_do_resume(pdev);
605 if (rc)
606 return rc;
607
608 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
609 rc = ahci_pci_reset_controller(host);
610 if (rc)
611 return rc;
612
613 ahci_pci_init_controller(host);
614 }
615
616 ata_host_resume(host);
617
618 return 0;
619 }
620 #endif
621
622 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
623 {
624 int rc;
625
626 /*
627 * If the device fixup already set the dma_mask to some non-standard
628 * value, don't extend it here. This happens on STA2X11, for example.
629 */
630 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
631 return 0;
632
633 if (using_dac &&
634 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
635 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
636 if (rc) {
637 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
638 if (rc) {
639 dev_err(&pdev->dev,
640 "64-bit DMA enable failed\n");
641 return rc;
642 }
643 }
644 } else {
645 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
646 if (rc) {
647 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
648 return rc;
649 }
650 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
651 if (rc) {
652 dev_err(&pdev->dev,
653 "32-bit consistent DMA enable failed\n");
654 return rc;
655 }
656 }
657 return 0;
658 }
659
660 static void ahci_pci_print_info(struct ata_host *host)
661 {
662 struct pci_dev *pdev = to_pci_dev(host->dev);
663 u16 cc;
664 const char *scc_s;
665
666 pci_read_config_word(pdev, 0x0a, &cc);
667 if (cc == PCI_CLASS_STORAGE_IDE)
668 scc_s = "IDE";
669 else if (cc == PCI_CLASS_STORAGE_SATA)
670 scc_s = "SATA";
671 else if (cc == PCI_CLASS_STORAGE_RAID)
672 scc_s = "RAID";
673 else
674 scc_s = "unknown";
675
676 ahci_print_info(host, scc_s);
677 }
678
679 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
680 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
681 * support PMP and the 4726 either directly exports the device
682 * attached to the first downstream port or acts as a hardware storage
683 * controller and emulate a single ATA device (can be RAID 0/1 or some
684 * other configuration).
685 *
686 * When there's no device attached to the first downstream port of the
687 * 4726, "Config Disk" appears, which is a pseudo ATA device to
688 * configure the 4726. However, ATA emulation of the device is very
689 * lame. It doesn't send signature D2H Reg FIS after the initial
690 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
691 *
692 * The following function works around the problem by always using
693 * hardreset on the port and not depending on receiving signature FIS
694 * afterward. If signature FIS isn't received soon, ATA class is
695 * assumed without follow-up softreset.
696 */
697 static void ahci_p5wdh_workaround(struct ata_host *host)
698 {
699 static struct dmi_system_id sysids[] = {
700 {
701 .ident = "P5W DH Deluxe",
702 .matches = {
703 DMI_MATCH(DMI_SYS_VENDOR,
704 "ASUSTEK COMPUTER INC"),
705 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
706 },
707 },
708 { }
709 };
710 struct pci_dev *pdev = to_pci_dev(host->dev);
711
712 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
713 dmi_check_system(sysids)) {
714 struct ata_port *ap = host->ports[1];
715
716 dev_info(&pdev->dev,
717 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
718
719 ap->ops = &ahci_p5wdh_ops;
720 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
721 }
722 }
723
724 /* only some SB600 ahci controllers can do 64bit DMA */
725 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
726 {
727 static const struct dmi_system_id sysids[] = {
728 /*
729 * The oldest version known to be broken is 0901 and
730 * working is 1501 which was released on 2007-10-26.
731 * Enable 64bit DMA on 1501 and anything newer.
732 *
733 * Please read bko#9412 for more info.
734 */
735 {
736 .ident = "ASUS M2A-VM",
737 .matches = {
738 DMI_MATCH(DMI_BOARD_VENDOR,
739 "ASUSTeK Computer INC."),
740 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
741 },
742 .driver_data = "20071026", /* yyyymmdd */
743 },
744 /*
745 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
746 * support 64bit DMA.
747 *
748 * BIOS versions earlier than 1.5 had the Manufacturer DMI
749 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
750 * This spelling mistake was fixed in BIOS version 1.5, so
751 * 1.5 and later have the Manufacturer as
752 * "MICRO-STAR INTERNATIONAL CO.,LTD".
753 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
754 *
755 * BIOS versions earlier than 1.9 had a Board Product Name
756 * DMI field of "MS-7376". This was changed to be
757 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
758 * match on DMI_BOARD_NAME of "MS-7376".
759 */
760 {
761 .ident = "MSI K9A2 Platinum",
762 .matches = {
763 DMI_MATCH(DMI_BOARD_VENDOR,
764 "MICRO-STAR INTER"),
765 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
766 },
767 },
768 /*
769 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
770 * 64bit DMA.
771 *
772 * This board also had the typo mentioned above in the
773 * Manufacturer DMI field (fixed in BIOS version 1.5), so
774 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
775 */
776 {
777 .ident = "MSI K9AGM2",
778 .matches = {
779 DMI_MATCH(DMI_BOARD_VENDOR,
780 "MICRO-STAR INTER"),
781 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
782 },
783 },
784 /*
785 * All BIOS versions for the Asus M3A support 64bit DMA.
786 * (all release versions from 0301 to 1206 were tested)
787 */
788 {
789 .ident = "ASUS M3A",
790 .matches = {
791 DMI_MATCH(DMI_BOARD_VENDOR,
792 "ASUSTeK Computer INC."),
793 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
794 },
795 },
796 { }
797 };
798 const struct dmi_system_id *match;
799 int year, month, date;
800 char buf[9];
801
802 match = dmi_first_match(sysids);
803 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
804 !match)
805 return false;
806
807 if (!match->driver_data)
808 goto enable_64bit;
809
810 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
811 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
812
813 if (strcmp(buf, match->driver_data) >= 0)
814 goto enable_64bit;
815 else {
816 dev_warn(&pdev->dev,
817 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
818 match->ident);
819 return false;
820 }
821
822 enable_64bit:
823 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
824 return true;
825 }
826
827 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
828 {
829 static const struct dmi_system_id broken_systems[] = {
830 {
831 .ident = "HP Compaq nx6310",
832 .matches = {
833 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
834 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
835 },
836 /* PCI slot number of the controller */
837 .driver_data = (void *)0x1FUL,
838 },
839 {
840 .ident = "HP Compaq 6720s",
841 .matches = {
842 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
843 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
844 },
845 /* PCI slot number of the controller */
846 .driver_data = (void *)0x1FUL,
847 },
848
849 { } /* terminate list */
850 };
851 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
852
853 if (dmi) {
854 unsigned long slot = (unsigned long)dmi->driver_data;
855 /* apply the quirk only to on-board controllers */
856 return slot == PCI_SLOT(pdev->devfn);
857 }
858
859 return false;
860 }
861
862 static bool ahci_broken_suspend(struct pci_dev *pdev)
863 {
864 static const struct dmi_system_id sysids[] = {
865 /*
866 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
867 * to the harddisk doesn't become online after
868 * resuming from STR. Warn and fail suspend.
869 *
870 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
871 *
872 * Use dates instead of versions to match as HP is
873 * apparently recycling both product and version
874 * strings.
875 *
876 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
877 */
878 {
879 .ident = "dv4",
880 .matches = {
881 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
882 DMI_MATCH(DMI_PRODUCT_NAME,
883 "HP Pavilion dv4 Notebook PC"),
884 },
885 .driver_data = "20090105", /* F.30 */
886 },
887 {
888 .ident = "dv5",
889 .matches = {
890 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
891 DMI_MATCH(DMI_PRODUCT_NAME,
892 "HP Pavilion dv5 Notebook PC"),
893 },
894 .driver_data = "20090506", /* F.16 */
895 },
896 {
897 .ident = "dv6",
898 .matches = {
899 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
900 DMI_MATCH(DMI_PRODUCT_NAME,
901 "HP Pavilion dv6 Notebook PC"),
902 },
903 .driver_data = "20090423", /* F.21 */
904 },
905 {
906 .ident = "HDX18",
907 .matches = {
908 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
909 DMI_MATCH(DMI_PRODUCT_NAME,
910 "HP HDX18 Notebook PC"),
911 },
912 .driver_data = "20090430", /* F.23 */
913 },
914 /*
915 * Acer eMachines G725 has the same problem. BIOS
916 * V1.03 is known to be broken. V3.04 is known to
917 * work. Between, there are V1.06, V2.06 and V3.03
918 * that we don't have much idea about. For now,
919 * blacklist anything older than V3.04.
920 *
921 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
922 */
923 {
924 .ident = "G725",
925 .matches = {
926 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
927 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
928 },
929 .driver_data = "20091216", /* V3.04 */
930 },
931 { } /* terminate list */
932 };
933 const struct dmi_system_id *dmi = dmi_first_match(sysids);
934 int year, month, date;
935 char buf[9];
936
937 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
938 return false;
939
940 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
941 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
942
943 return strcmp(buf, dmi->driver_data) < 0;
944 }
945
946 static bool ahci_broken_online(struct pci_dev *pdev)
947 {
948 #define ENCODE_BUSDEVFN(bus, slot, func) \
949 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
950 static const struct dmi_system_id sysids[] = {
951 /*
952 * There are several gigabyte boards which use
953 * SIMG5723s configured as hardware RAID. Certain
954 * 5723 firmware revisions shipped there keep the link
955 * online but fail to answer properly to SRST or
956 * IDENTIFY when no device is attached downstream
957 * causing libata to retry quite a few times leading
958 * to excessive detection delay.
959 *
960 * As these firmwares respond to the second reset try
961 * with invalid device signature, considering unknown
962 * sig as offline works around the problem acceptably.
963 */
964 {
965 .ident = "EP45-DQ6",
966 .matches = {
967 DMI_MATCH(DMI_BOARD_VENDOR,
968 "Gigabyte Technology Co., Ltd."),
969 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
970 },
971 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
972 },
973 {
974 .ident = "EP45-DS5",
975 .matches = {
976 DMI_MATCH(DMI_BOARD_VENDOR,
977 "Gigabyte Technology Co., Ltd."),
978 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
979 },
980 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
981 },
982 { } /* terminate list */
983 };
984 #undef ENCODE_BUSDEVFN
985 const struct dmi_system_id *dmi = dmi_first_match(sysids);
986 unsigned int val;
987
988 if (!dmi)
989 return false;
990
991 val = (unsigned long)dmi->driver_data;
992
993 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
994 }
995
996 #ifdef CONFIG_ATA_ACPI
997 static void ahci_gtf_filter_workaround(struct ata_host *host)
998 {
999 static const struct dmi_system_id sysids[] = {
1000 /*
1001 * Aspire 3810T issues a bunch of SATA enable commands
1002 * via _GTF including an invalid one and one which is
1003 * rejected by the device. Among the successful ones
1004 * is FPDMA non-zero offset enable which when enabled
1005 * only on the drive side leads to NCQ command
1006 * failures. Filter it out.
1007 */
1008 {
1009 .ident = "Aspire 3810T",
1010 .matches = {
1011 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1012 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1013 },
1014 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1015 },
1016 { }
1017 };
1018 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1019 unsigned int filter;
1020 int i;
1021
1022 if (!dmi)
1023 return;
1024
1025 filter = (unsigned long)dmi->driver_data;
1026 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1027 filter, dmi->ident);
1028
1029 for (i = 0; i < host->n_ports; i++) {
1030 struct ata_port *ap = host->ports[i];
1031 struct ata_link *link;
1032 struct ata_device *dev;
1033
1034 ata_for_each_link(link, ap, EDGE)
1035 ata_for_each_dev(dev, link, ALL)
1036 dev->gtf_filter |= filter;
1037 }
1038 }
1039 #else
1040 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1041 {}
1042 #endif
1043
1044 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1045 {
1046 unsigned int board_id = ent->driver_data;
1047 struct ata_port_info pi = ahci_port_info[board_id];
1048 const struct ata_port_info *ppi[] = { &pi, NULL };
1049 struct device *dev = &pdev->dev;
1050 struct ahci_host_priv *hpriv;
1051 struct ata_host *host;
1052 int n_ports, i, rc;
1053 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1054
1055 VPRINTK("ENTER\n");
1056
1057 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1058
1059 ata_print_version_once(&pdev->dev, DRV_VERSION);
1060
1061 /* The AHCI driver can only drive the SATA ports, the PATA driver
1062 can drive them all so if both drivers are selected make sure
1063 AHCI stays out of the way */
1064 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1065 return -ENODEV;
1066
1067 /*
1068 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1069 * ahci, use ata_generic instead.
1070 */
1071 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1072 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1073 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1074 pdev->subsystem_device == 0xcb89)
1075 return -ENODEV;
1076
1077 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1078 * At the moment, we can only use the AHCI mode. Let the users know
1079 * that for SAS drives they're out of luck.
1080 */
1081 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1082 dev_info(&pdev->dev,
1083 "PDC42819 can only drive SATA devices with this driver\n");
1084
1085 /* The Connext uses non-standard BAR */
1086 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1087 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1088
1089 /* acquire resources */
1090 rc = pcim_enable_device(pdev);
1091 if (rc)
1092 return rc;
1093
1094 /* AHCI controllers often implement SFF compatible interface.
1095 * Grab all PCI BARs just in case.
1096 */
1097 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1098 if (rc == -EBUSY)
1099 pcim_pin_device(pdev);
1100 if (rc)
1101 return rc;
1102
1103 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1104 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1105 u8 map;
1106
1107 /* ICH6s share the same PCI ID for both piix and ahci
1108 * modes. Enabling ahci mode while MAP indicates
1109 * combined mode is a bad idea. Yield to ata_piix.
1110 */
1111 pci_read_config_byte(pdev, ICH_MAP, &map);
1112 if (map & 0x3) {
1113 dev_info(&pdev->dev,
1114 "controller is in combined mode, can't enable AHCI mode\n");
1115 return -ENODEV;
1116 }
1117 }
1118
1119 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1120 if (!hpriv)
1121 return -ENOMEM;
1122 hpriv->flags |= (unsigned long)pi.private_data;
1123
1124 /* MCP65 revision A1 and A2 can't do MSI */
1125 if (board_id == board_ahci_mcp65 &&
1126 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1127 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1128
1129 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1130 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1131 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1132
1133 /* only some SB600s can do 64bit DMA */
1134 if (ahci_sb600_enable_64bit(pdev))
1135 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1136
1137 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1138 pci_intx(pdev, 1);
1139
1140 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1141
1142 /* save initial config */
1143 ahci_pci_save_initial_config(pdev, hpriv);
1144
1145 /* prepare host */
1146 if (hpriv->cap & HOST_CAP_NCQ) {
1147 pi.flags |= ATA_FLAG_NCQ;
1148 /*
1149 * Auto-activate optimization is supposed to be
1150 * supported on all AHCI controllers indicating NCQ
1151 * capability, but it seems to be broken on some
1152 * chipsets including NVIDIAs.
1153 */
1154 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1155 pi.flags |= ATA_FLAG_FPDMA_AA;
1156 }
1157
1158 if (hpriv->cap & HOST_CAP_PMP)
1159 pi.flags |= ATA_FLAG_PMP;
1160
1161 ahci_set_em_messages(hpriv, &pi);
1162
1163 if (ahci_broken_system_poweroff(pdev)) {
1164 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1165 dev_info(&pdev->dev,
1166 "quirky BIOS, skipping spindown on poweroff\n");
1167 }
1168
1169 if (ahci_broken_suspend(pdev)) {
1170 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1171 dev_warn(&pdev->dev,
1172 "BIOS update required for suspend/resume\n");
1173 }
1174
1175 if (ahci_broken_online(pdev)) {
1176 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1177 dev_info(&pdev->dev,
1178 "online status unreliable, applying workaround\n");
1179 }
1180
1181 /* CAP.NP sometimes indicate the index of the last enabled
1182 * port, at other times, that of the last possible port, so
1183 * determining the maximum port number requires looking at
1184 * both CAP.NP and port_map.
1185 */
1186 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1187
1188 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1189 if (!host)
1190 return -ENOMEM;
1191 host->private_data = hpriv;
1192
1193 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1194 host->flags |= ATA_HOST_PARALLEL_SCAN;
1195 else
1196 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1197
1198 if (pi.flags & ATA_FLAG_EM)
1199 ahci_reset_em(host);
1200
1201 for (i = 0; i < host->n_ports; i++) {
1202 struct ata_port *ap = host->ports[i];
1203
1204 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1205 ata_port_pbar_desc(ap, ahci_pci_bar,
1206 0x100 + ap->port_no * 0x80, "port");
1207
1208 /* set enclosure management message type */
1209 if (ap->flags & ATA_FLAG_EM)
1210 ap->em_message_type = hpriv->em_msg_type;
1211
1212
1213 /* disabled/not-implemented port */
1214 if (!(hpriv->port_map & (1 << i)))
1215 ap->ops = &ata_dummy_port_ops;
1216 }
1217
1218 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1219 ahci_p5wdh_workaround(host);
1220
1221 /* apply gtf filter quirk */
1222 ahci_gtf_filter_workaround(host);
1223
1224 /* initialize adapter */
1225 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1226 if (rc)
1227 return rc;
1228
1229 rc = ahci_pci_reset_controller(host);
1230 if (rc)
1231 return rc;
1232
1233 ahci_pci_init_controller(host);
1234 ahci_pci_print_info(host);
1235
1236 pci_set_master(pdev);
1237 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1238 &ahci_sht);
1239 }
1240
1241 module_pci_driver(ahci_pci_driver);
1242
1243 MODULE_AUTHOR("Jeff Garzik");
1244 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1245 MODULE_LICENSE("GPL");
1246 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1247 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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