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libata: move generic hardreset code from sata_sff_hardreset() to sata_link_hardreset()
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58 static void ahci_disable_alpm(struct ata_port *ap);
59
60 enum {
61 AHCI_PCI_BAR = 5,
62 AHCI_MAX_PORTS = 32,
63 AHCI_MAX_SG = 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY = 0xffffffff,
65 AHCI_MAX_CMDS = 32,
66 AHCI_CMD_SZ = 32,
67 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
68 AHCI_RX_FIS_SZ = 256,
69 AHCI_CMD_TBL_CDB = 0x40,
70 AHCI_CMD_TBL_HDR_SZ = 0x80,
71 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
72 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
73 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
74 AHCI_RX_FIS_SZ,
75 AHCI_IRQ_ON_SG = (1 << 31),
76 AHCI_CMD_ATAPI = (1 << 5),
77 AHCI_CMD_WRITE = (1 << 6),
78 AHCI_CMD_PREFETCH = (1 << 7),
79 AHCI_CMD_RESET = (1 << 8),
80 AHCI_CMD_CLR_BUSY = (1 << 10),
81
82 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
83 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
84 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
85
86 board_ahci = 0,
87 board_ahci_vt8251 = 1,
88 board_ahci_ign_iferr = 2,
89 board_ahci_sb600 = 3,
90 board_ahci_mv = 4,
91 board_ahci_sb700 = 5,
92
93 /* global controller registers */
94 HOST_CAP = 0x00, /* host capabilities */
95 HOST_CTL = 0x04, /* global host control */
96 HOST_IRQ_STAT = 0x08, /* interrupt status */
97 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
98 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
99
100 /* HOST_CTL bits */
101 HOST_RESET = (1 << 0), /* reset controller; self-clear */
102 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
103 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
104
105 /* HOST_CAP bits */
106 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
107 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
108 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
109 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
110 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
111 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
112 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
113 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
114
115 /* registers for each SATA port */
116 PORT_LST_ADDR = 0x00, /* command list DMA addr */
117 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
118 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
119 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
120 PORT_IRQ_STAT = 0x10, /* interrupt status */
121 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
122 PORT_CMD = 0x18, /* port command */
123 PORT_TFDATA = 0x20, /* taskfile data */
124 PORT_SIG = 0x24, /* device TF signature */
125 PORT_CMD_ISSUE = 0x38, /* command issue */
126 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
127 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
128 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
129 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
130 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
131
132 /* PORT_IRQ_{STAT,MASK} bits */
133 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
134 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
135 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
136 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
137 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
138 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
139 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
140 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
141
142 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
143 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
144 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
145 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
146 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
147 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
148 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
149 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
150 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
151
152 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
153 PORT_IRQ_IF_ERR |
154 PORT_IRQ_CONNECT |
155 PORT_IRQ_PHYRDY |
156 PORT_IRQ_UNK_FIS |
157 PORT_IRQ_BAD_PMP,
158 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
159 PORT_IRQ_TF_ERR |
160 PORT_IRQ_HBUS_DATA_ERR,
161 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
162 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
163 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
164
165 /* PORT_CMD bits */
166 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
167 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
168 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
169 PORT_CMD_PMP = (1 << 17), /* PMP attached */
170 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
171 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
172 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
173 PORT_CMD_CLO = (1 << 3), /* Command list override */
174 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
175 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
176 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
177
178 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
179 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
180 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
181 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
182
183 /* hpriv->flags bits */
184 AHCI_HFLAG_NO_NCQ = (1 << 0),
185 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
186 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
187 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
188 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
189 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
190 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
191 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
192 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
193
194 /* ap->flags bits */
195
196 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
197 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
198 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
199 ATA_FLAG_IPM,
200
201 ICH_MAP = 0x90, /* ICH MAP register */
202 };
203
204 struct ahci_cmd_hdr {
205 __le32 opts;
206 __le32 status;
207 __le32 tbl_addr;
208 __le32 tbl_addr_hi;
209 __le32 reserved[4];
210 };
211
212 struct ahci_sg {
213 __le32 addr;
214 __le32 addr_hi;
215 __le32 reserved;
216 __le32 flags_size;
217 };
218
219 struct ahci_host_priv {
220 unsigned int flags; /* AHCI_HFLAG_* */
221 u32 cap; /* cap to use */
222 u32 port_map; /* port map to use */
223 u32 saved_cap; /* saved initial cap */
224 u32 saved_port_map; /* saved initial port_map */
225 };
226
227 struct ahci_port_priv {
228 struct ata_link *active_link;
229 struct ahci_cmd_hdr *cmd_slot;
230 dma_addr_t cmd_slot_dma;
231 void *cmd_tbl;
232 dma_addr_t cmd_tbl_dma;
233 void *rx_fis;
234 dma_addr_t rx_fis_dma;
235 /* for NCQ spurious interrupt analysis */
236 unsigned int ncq_saw_d2h:1;
237 unsigned int ncq_saw_dmas:1;
238 unsigned int ncq_saw_sdb:1;
239 u32 intr_mask; /* interrupts to enable */
240 };
241
242 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
243 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
244 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
245 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
246 static int ahci_port_start(struct ata_port *ap);
247 static void ahci_port_stop(struct ata_port *ap);
248 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
249 static void ahci_qc_prep(struct ata_queued_cmd *qc);
250 static u8 ahci_check_status(struct ata_port *ap);
251 static void ahci_freeze(struct ata_port *ap);
252 static void ahci_thaw(struct ata_port *ap);
253 static void ahci_pmp_attach(struct ata_port *ap);
254 static void ahci_pmp_detach(struct ata_port *ap);
255 static int ahci_softreset(struct ata_link *link, unsigned int *class,
256 unsigned long deadline);
257 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
258 unsigned long deadline);
259 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
260 unsigned long deadline);
261 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
262 unsigned long deadline);
263 static void ahci_postreset(struct ata_link *link, unsigned int *class);
264 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
265 unsigned long deadline);
266 static void ahci_error_handler(struct ata_port *ap);
267 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
268 static int ahci_port_resume(struct ata_port *ap);
269 static void ahci_dev_config(struct ata_device *dev);
270 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
271 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
272 u32 opts);
273 #ifdef CONFIG_PM
274 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
275 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
276 static int ahci_pci_device_resume(struct pci_dev *pdev);
277 #endif
278
279 static struct class_device_attribute *ahci_shost_attrs[] = {
280 &class_device_attr_link_power_management_policy,
281 NULL
282 };
283
284 static struct scsi_host_template ahci_sht = {
285 ATA_NCQ_SHT(DRV_NAME),
286 .can_queue = AHCI_MAX_CMDS - 1,
287 .sg_tablesize = AHCI_MAX_SG,
288 .dma_boundary = AHCI_DMA_BOUNDARY,
289 .shost_attrs = ahci_shost_attrs,
290 };
291
292 static struct ata_port_operations ahci_ops = {
293 .inherits = &sata_pmp_port_ops,
294
295 .sff_check_status = ahci_check_status,
296 .sff_check_altstatus = ahci_check_status,
297
298 .sff_tf_read = ahci_tf_read,
299 .qc_defer = sata_pmp_qc_defer_cmd_switch,
300 .qc_prep = ahci_qc_prep,
301 .qc_issue = ahci_qc_issue,
302
303 .freeze = ahci_freeze,
304 .thaw = ahci_thaw,
305 .softreset = ahci_softreset,
306 .hardreset = ahci_hardreset,
307 .postreset = ahci_postreset,
308 .pmp_softreset = ahci_pmp_softreset,
309 .error_handler = ahci_error_handler,
310 .post_internal_cmd = ahci_post_internal_cmd,
311 .dev_config = ahci_dev_config,
312
313 .scr_read = ahci_scr_read,
314 .scr_write = ahci_scr_write,
315 .pmp_attach = ahci_pmp_attach,
316 .pmp_detach = ahci_pmp_detach,
317
318 .enable_pm = ahci_enable_alpm,
319 .disable_pm = ahci_disable_alpm,
320 #ifdef CONFIG_PM
321 .port_suspend = ahci_port_suspend,
322 .port_resume = ahci_port_resume,
323 #endif
324 .port_start = ahci_port_start,
325 .port_stop = ahci_port_stop,
326 };
327
328 static struct ata_port_operations ahci_vt8251_ops = {
329 .inherits = &ahci_ops,
330 .hardreset = ahci_vt8251_hardreset,
331 };
332
333 static struct ata_port_operations ahci_p5wdh_ops = {
334 .inherits = &ahci_ops,
335 .hardreset = ahci_p5wdh_hardreset,
336 };
337
338 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
339
340 static const struct ata_port_info ahci_port_info[] = {
341 /* board_ahci */
342 {
343 .flags = AHCI_FLAG_COMMON,
344 .pio_mask = 0x1f, /* pio0-4 */
345 .udma_mask = ATA_UDMA6,
346 .port_ops = &ahci_ops,
347 },
348 /* board_ahci_vt8251 */
349 {
350 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
351 .flags = AHCI_FLAG_COMMON,
352 .pio_mask = 0x1f, /* pio0-4 */
353 .udma_mask = ATA_UDMA6,
354 .port_ops = &ahci_vt8251_ops,
355 },
356 /* board_ahci_ign_iferr */
357 {
358 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
359 .flags = AHCI_FLAG_COMMON,
360 .pio_mask = 0x1f, /* pio0-4 */
361 .udma_mask = ATA_UDMA6,
362 .port_ops = &ahci_ops,
363 },
364 /* board_ahci_sb600 */
365 {
366 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
367 AHCI_HFLAG_32BIT_ONLY |
368 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
369 .flags = AHCI_FLAG_COMMON,
370 .pio_mask = 0x1f, /* pio0-4 */
371 .udma_mask = ATA_UDMA6,
372 .port_ops = &ahci_ops,
373 },
374 /* board_ahci_mv */
375 {
376 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
377 AHCI_HFLAG_MV_PATA),
378 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
379 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
380 .pio_mask = 0x1f, /* pio0-4 */
381 .udma_mask = ATA_UDMA6,
382 .port_ops = &ahci_ops,
383 },
384 /* board_ahci_sb700 */
385 {
386 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
387 AHCI_HFLAG_NO_PMP),
388 .flags = AHCI_FLAG_COMMON,
389 .pio_mask = 0x1f, /* pio0-4 */
390 .udma_mask = ATA_UDMA6,
391 .port_ops = &ahci_ops,
392 },
393 };
394
395 static const struct pci_device_id ahci_pci_tbl[] = {
396 /* Intel */
397 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
398 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
399 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
400 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
401 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
402 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
403 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
404 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
405 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
406 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
407 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
408 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
409 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
410 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
411 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
412 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
413 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
414 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
415 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
416 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
417 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
418 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
419 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
420 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
421 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
422 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
423 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
424 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
425 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
426 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
427 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
428
429 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
430 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
431 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
432
433 /* ATI */
434 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
435 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
436 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
437 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
438 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
439 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
440 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
441
442 /* VIA */
443 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
444 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
445
446 /* NVIDIA */
447 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
448 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
449 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
450 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
453 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
454 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
455 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
456 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
457 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
476 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
477 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
478 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
487 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
488 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
489 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
490 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
491 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
497 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
498 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
499 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
500 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
501 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
502 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
503 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
504 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
505 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
506 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
507 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
508 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
509 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
510 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
511 { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */
512 { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */
513 { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */
514 { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */
515
516 /* SiS */
517 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
518 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
519 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
520
521 /* Marvell */
522 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
523 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
524
525 /* Generic, PCI class code for AHCI */
526 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
527 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
528
529 { } /* terminate list */
530 };
531
532
533 static struct pci_driver ahci_pci_driver = {
534 .name = DRV_NAME,
535 .id_table = ahci_pci_tbl,
536 .probe = ahci_init_one,
537 .remove = ata_pci_remove_one,
538 #ifdef CONFIG_PM
539 .suspend = ahci_pci_device_suspend,
540 .resume = ahci_pci_device_resume,
541 #endif
542 };
543
544
545 static inline int ahci_nr_ports(u32 cap)
546 {
547 return (cap & 0x1f) + 1;
548 }
549
550 static inline void __iomem *__ahci_port_base(struct ata_host *host,
551 unsigned int port_no)
552 {
553 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
554
555 return mmio + 0x100 + (port_no * 0x80);
556 }
557
558 static inline void __iomem *ahci_port_base(struct ata_port *ap)
559 {
560 return __ahci_port_base(ap->host, ap->port_no);
561 }
562
563 static void ahci_enable_ahci(void __iomem *mmio)
564 {
565 u32 tmp;
566
567 /* turn on AHCI_EN */
568 tmp = readl(mmio + HOST_CTL);
569 if (!(tmp & HOST_AHCI_EN)) {
570 tmp |= HOST_AHCI_EN;
571 writel(tmp, mmio + HOST_CTL);
572 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
573 WARN_ON(!(tmp & HOST_AHCI_EN));
574 }
575 }
576
577 /**
578 * ahci_save_initial_config - Save and fixup initial config values
579 * @pdev: target PCI device
580 * @hpriv: host private area to store config values
581 *
582 * Some registers containing configuration info might be setup by
583 * BIOS and might be cleared on reset. This function saves the
584 * initial values of those registers into @hpriv such that they
585 * can be restored after controller reset.
586 *
587 * If inconsistent, config values are fixed up by this function.
588 *
589 * LOCKING:
590 * None.
591 */
592 static void ahci_save_initial_config(struct pci_dev *pdev,
593 struct ahci_host_priv *hpriv)
594 {
595 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
596 u32 cap, port_map;
597 int i;
598 int mv;
599
600 /* make sure AHCI mode is enabled before accessing CAP */
601 ahci_enable_ahci(mmio);
602
603 /* Values prefixed with saved_ are written back to host after
604 * reset. Values without are used for driver operation.
605 */
606 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
607 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
608
609 /* some chips have errata preventing 64bit use */
610 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
611 dev_printk(KERN_INFO, &pdev->dev,
612 "controller can't do 64bit DMA, forcing 32bit\n");
613 cap &= ~HOST_CAP_64;
614 }
615
616 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
617 dev_printk(KERN_INFO, &pdev->dev,
618 "controller can't do NCQ, turning off CAP_NCQ\n");
619 cap &= ~HOST_CAP_NCQ;
620 }
621
622 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
623 dev_printk(KERN_INFO, &pdev->dev,
624 "controller can't do PMP, turning off CAP_PMP\n");
625 cap &= ~HOST_CAP_PMP;
626 }
627
628 /*
629 * Temporary Marvell 6145 hack: PATA port presence
630 * is asserted through the standard AHCI port
631 * presence register, as bit 4 (counting from 0)
632 */
633 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
634 if (pdev->device == 0x6121)
635 mv = 0x3;
636 else
637 mv = 0xf;
638 dev_printk(KERN_ERR, &pdev->dev,
639 "MV_AHCI HACK: port_map %x -> %x\n",
640 port_map,
641 port_map & mv);
642
643 port_map &= mv;
644 }
645
646 /* cross check port_map and cap.n_ports */
647 if (port_map) {
648 int map_ports = 0;
649
650 for (i = 0; i < AHCI_MAX_PORTS; i++)
651 if (port_map & (1 << i))
652 map_ports++;
653
654 /* If PI has more ports than n_ports, whine, clear
655 * port_map and let it be generated from n_ports.
656 */
657 if (map_ports > ahci_nr_ports(cap)) {
658 dev_printk(KERN_WARNING, &pdev->dev,
659 "implemented port map (0x%x) contains more "
660 "ports than nr_ports (%u), using nr_ports\n",
661 port_map, ahci_nr_ports(cap));
662 port_map = 0;
663 }
664 }
665
666 /* fabricate port_map from cap.nr_ports */
667 if (!port_map) {
668 port_map = (1 << ahci_nr_ports(cap)) - 1;
669 dev_printk(KERN_WARNING, &pdev->dev,
670 "forcing PORTS_IMPL to 0x%x\n", port_map);
671
672 /* write the fixed up value to the PI register */
673 hpriv->saved_port_map = port_map;
674 }
675
676 /* record values to use during operation */
677 hpriv->cap = cap;
678 hpriv->port_map = port_map;
679 }
680
681 /**
682 * ahci_restore_initial_config - Restore initial config
683 * @host: target ATA host
684 *
685 * Restore initial config stored by ahci_save_initial_config().
686 *
687 * LOCKING:
688 * None.
689 */
690 static void ahci_restore_initial_config(struct ata_host *host)
691 {
692 struct ahci_host_priv *hpriv = host->private_data;
693 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
694
695 writel(hpriv->saved_cap, mmio + HOST_CAP);
696 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
697 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
698 }
699
700 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
701 {
702 static const int offset[] = {
703 [SCR_STATUS] = PORT_SCR_STAT,
704 [SCR_CONTROL] = PORT_SCR_CTL,
705 [SCR_ERROR] = PORT_SCR_ERR,
706 [SCR_ACTIVE] = PORT_SCR_ACT,
707 [SCR_NOTIFICATION] = PORT_SCR_NTF,
708 };
709 struct ahci_host_priv *hpriv = ap->host->private_data;
710
711 if (sc_reg < ARRAY_SIZE(offset) &&
712 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
713 return offset[sc_reg];
714 return 0;
715 }
716
717 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
718 {
719 void __iomem *port_mmio = ahci_port_base(ap);
720 int offset = ahci_scr_offset(ap, sc_reg);
721
722 if (offset) {
723 *val = readl(port_mmio + offset);
724 return 0;
725 }
726 return -EINVAL;
727 }
728
729 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
730 {
731 void __iomem *port_mmio = ahci_port_base(ap);
732 int offset = ahci_scr_offset(ap, sc_reg);
733
734 if (offset) {
735 writel(val, port_mmio + offset);
736 return 0;
737 }
738 return -EINVAL;
739 }
740
741 static void ahci_start_engine(struct ata_port *ap)
742 {
743 void __iomem *port_mmio = ahci_port_base(ap);
744 u32 tmp;
745
746 /* start DMA */
747 tmp = readl(port_mmio + PORT_CMD);
748 tmp |= PORT_CMD_START;
749 writel(tmp, port_mmio + PORT_CMD);
750 readl(port_mmio + PORT_CMD); /* flush */
751 }
752
753 static int ahci_stop_engine(struct ata_port *ap)
754 {
755 void __iomem *port_mmio = ahci_port_base(ap);
756 u32 tmp;
757
758 tmp = readl(port_mmio + PORT_CMD);
759
760 /* check if the HBA is idle */
761 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
762 return 0;
763
764 /* setting HBA to idle */
765 tmp &= ~PORT_CMD_START;
766 writel(tmp, port_mmio + PORT_CMD);
767
768 /* wait for engine to stop. This could be as long as 500 msec */
769 tmp = ata_wait_register(port_mmio + PORT_CMD,
770 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
771 if (tmp & PORT_CMD_LIST_ON)
772 return -EIO;
773
774 return 0;
775 }
776
777 static void ahci_start_fis_rx(struct ata_port *ap)
778 {
779 void __iomem *port_mmio = ahci_port_base(ap);
780 struct ahci_host_priv *hpriv = ap->host->private_data;
781 struct ahci_port_priv *pp = ap->private_data;
782 u32 tmp;
783
784 /* set FIS registers */
785 if (hpriv->cap & HOST_CAP_64)
786 writel((pp->cmd_slot_dma >> 16) >> 16,
787 port_mmio + PORT_LST_ADDR_HI);
788 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
789
790 if (hpriv->cap & HOST_CAP_64)
791 writel((pp->rx_fis_dma >> 16) >> 16,
792 port_mmio + PORT_FIS_ADDR_HI);
793 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
794
795 /* enable FIS reception */
796 tmp = readl(port_mmio + PORT_CMD);
797 tmp |= PORT_CMD_FIS_RX;
798 writel(tmp, port_mmio + PORT_CMD);
799
800 /* flush */
801 readl(port_mmio + PORT_CMD);
802 }
803
804 static int ahci_stop_fis_rx(struct ata_port *ap)
805 {
806 void __iomem *port_mmio = ahci_port_base(ap);
807 u32 tmp;
808
809 /* disable FIS reception */
810 tmp = readl(port_mmio + PORT_CMD);
811 tmp &= ~PORT_CMD_FIS_RX;
812 writel(tmp, port_mmio + PORT_CMD);
813
814 /* wait for completion, spec says 500ms, give it 1000 */
815 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
816 PORT_CMD_FIS_ON, 10, 1000);
817 if (tmp & PORT_CMD_FIS_ON)
818 return -EBUSY;
819
820 return 0;
821 }
822
823 static void ahci_power_up(struct ata_port *ap)
824 {
825 struct ahci_host_priv *hpriv = ap->host->private_data;
826 void __iomem *port_mmio = ahci_port_base(ap);
827 u32 cmd;
828
829 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
830
831 /* spin up device */
832 if (hpriv->cap & HOST_CAP_SSS) {
833 cmd |= PORT_CMD_SPIN_UP;
834 writel(cmd, port_mmio + PORT_CMD);
835 }
836
837 /* wake up link */
838 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
839 }
840
841 static void ahci_disable_alpm(struct ata_port *ap)
842 {
843 struct ahci_host_priv *hpriv = ap->host->private_data;
844 void __iomem *port_mmio = ahci_port_base(ap);
845 u32 cmd;
846 struct ahci_port_priv *pp = ap->private_data;
847
848 /* IPM bits should be disabled by libata-core */
849 /* get the existing command bits */
850 cmd = readl(port_mmio + PORT_CMD);
851
852 /* disable ALPM and ASP */
853 cmd &= ~PORT_CMD_ASP;
854 cmd &= ~PORT_CMD_ALPE;
855
856 /* force the interface back to active */
857 cmd |= PORT_CMD_ICC_ACTIVE;
858
859 /* write out new cmd value */
860 writel(cmd, port_mmio + PORT_CMD);
861 cmd = readl(port_mmio + PORT_CMD);
862
863 /* wait 10ms to be sure we've come out of any low power state */
864 msleep(10);
865
866 /* clear out any PhyRdy stuff from interrupt status */
867 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
868
869 /* go ahead and clean out PhyRdy Change from Serror too */
870 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
871
872 /*
873 * Clear flag to indicate that we should ignore all PhyRdy
874 * state changes
875 */
876 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
877
878 /*
879 * Enable interrupts on Phy Ready.
880 */
881 pp->intr_mask |= PORT_IRQ_PHYRDY;
882 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
883
884 /*
885 * don't change the link pm policy - we can be called
886 * just to turn of link pm temporarily
887 */
888 }
889
890 static int ahci_enable_alpm(struct ata_port *ap,
891 enum link_pm policy)
892 {
893 struct ahci_host_priv *hpriv = ap->host->private_data;
894 void __iomem *port_mmio = ahci_port_base(ap);
895 u32 cmd;
896 struct ahci_port_priv *pp = ap->private_data;
897 u32 asp;
898
899 /* Make sure the host is capable of link power management */
900 if (!(hpriv->cap & HOST_CAP_ALPM))
901 return -EINVAL;
902
903 switch (policy) {
904 case MAX_PERFORMANCE:
905 case NOT_AVAILABLE:
906 /*
907 * if we came here with NOT_AVAILABLE,
908 * it just means this is the first time we
909 * have tried to enable - default to max performance,
910 * and let the user go to lower power modes on request.
911 */
912 ahci_disable_alpm(ap);
913 return 0;
914 case MIN_POWER:
915 /* configure HBA to enter SLUMBER */
916 asp = PORT_CMD_ASP;
917 break;
918 case MEDIUM_POWER:
919 /* configure HBA to enter PARTIAL */
920 asp = 0;
921 break;
922 default:
923 return -EINVAL;
924 }
925
926 /*
927 * Disable interrupts on Phy Ready. This keeps us from
928 * getting woken up due to spurious phy ready interrupts
929 * TBD - Hot plug should be done via polling now, is
930 * that even supported?
931 */
932 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
933 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
934
935 /*
936 * Set a flag to indicate that we should ignore all PhyRdy
937 * state changes since these can happen now whenever we
938 * change link state
939 */
940 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
941
942 /* get the existing command bits */
943 cmd = readl(port_mmio + PORT_CMD);
944
945 /*
946 * Set ASP based on Policy
947 */
948 cmd |= asp;
949
950 /*
951 * Setting this bit will instruct the HBA to aggressively
952 * enter a lower power link state when it's appropriate and
953 * based on the value set above for ASP
954 */
955 cmd |= PORT_CMD_ALPE;
956
957 /* write out new cmd value */
958 writel(cmd, port_mmio + PORT_CMD);
959 cmd = readl(port_mmio + PORT_CMD);
960
961 /* IPM bits should be set by libata-core */
962 return 0;
963 }
964
965 #ifdef CONFIG_PM
966 static void ahci_power_down(struct ata_port *ap)
967 {
968 struct ahci_host_priv *hpriv = ap->host->private_data;
969 void __iomem *port_mmio = ahci_port_base(ap);
970 u32 cmd, scontrol;
971
972 if (!(hpriv->cap & HOST_CAP_SSS))
973 return;
974
975 /* put device into listen mode, first set PxSCTL.DET to 0 */
976 scontrol = readl(port_mmio + PORT_SCR_CTL);
977 scontrol &= ~0xf;
978 writel(scontrol, port_mmio + PORT_SCR_CTL);
979
980 /* then set PxCMD.SUD to 0 */
981 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
982 cmd &= ~PORT_CMD_SPIN_UP;
983 writel(cmd, port_mmio + PORT_CMD);
984 }
985 #endif
986
987 static void ahci_start_port(struct ata_port *ap)
988 {
989 /* enable FIS reception */
990 ahci_start_fis_rx(ap);
991
992 /* enable DMA */
993 ahci_start_engine(ap);
994 }
995
996 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
997 {
998 int rc;
999
1000 /* disable DMA */
1001 rc = ahci_stop_engine(ap);
1002 if (rc) {
1003 *emsg = "failed to stop engine";
1004 return rc;
1005 }
1006
1007 /* disable FIS reception */
1008 rc = ahci_stop_fis_rx(ap);
1009 if (rc) {
1010 *emsg = "failed stop FIS RX";
1011 return rc;
1012 }
1013
1014 return 0;
1015 }
1016
1017 static int ahci_reset_controller(struct ata_host *host)
1018 {
1019 struct pci_dev *pdev = to_pci_dev(host->dev);
1020 struct ahci_host_priv *hpriv = host->private_data;
1021 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1022 u32 tmp;
1023
1024 /* we must be in AHCI mode, before using anything
1025 * AHCI-specific, such as HOST_RESET.
1026 */
1027 ahci_enable_ahci(mmio);
1028
1029 /* global controller reset */
1030 if (!ahci_skip_host_reset) {
1031 tmp = readl(mmio + HOST_CTL);
1032 if ((tmp & HOST_RESET) == 0) {
1033 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1034 readl(mmio + HOST_CTL); /* flush */
1035 }
1036
1037 /* reset must complete within 1 second, or
1038 * the hardware should be considered fried.
1039 */
1040 ssleep(1);
1041
1042 tmp = readl(mmio + HOST_CTL);
1043 if (tmp & HOST_RESET) {
1044 dev_printk(KERN_ERR, host->dev,
1045 "controller reset failed (0x%x)\n", tmp);
1046 return -EIO;
1047 }
1048
1049 /* turn on AHCI mode */
1050 ahci_enable_ahci(mmio);
1051
1052 /* Some registers might be cleared on reset. Restore
1053 * initial values.
1054 */
1055 ahci_restore_initial_config(host);
1056 } else
1057 dev_printk(KERN_INFO, host->dev,
1058 "skipping global host reset\n");
1059
1060 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1061 u16 tmp16;
1062
1063 /* configure PCS */
1064 pci_read_config_word(pdev, 0x92, &tmp16);
1065 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1066 tmp16 |= hpriv->port_map;
1067 pci_write_config_word(pdev, 0x92, tmp16);
1068 }
1069 }
1070
1071 return 0;
1072 }
1073
1074 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1075 int port_no, void __iomem *mmio,
1076 void __iomem *port_mmio)
1077 {
1078 const char *emsg = NULL;
1079 int rc;
1080 u32 tmp;
1081
1082 /* make sure port is not active */
1083 rc = ahci_deinit_port(ap, &emsg);
1084 if (rc)
1085 dev_printk(KERN_WARNING, &pdev->dev,
1086 "%s (%d)\n", emsg, rc);
1087
1088 /* clear SError */
1089 tmp = readl(port_mmio + PORT_SCR_ERR);
1090 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1091 writel(tmp, port_mmio + PORT_SCR_ERR);
1092
1093 /* clear port IRQ */
1094 tmp = readl(port_mmio + PORT_IRQ_STAT);
1095 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1096 if (tmp)
1097 writel(tmp, port_mmio + PORT_IRQ_STAT);
1098
1099 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1100 }
1101
1102 static void ahci_init_controller(struct ata_host *host)
1103 {
1104 struct ahci_host_priv *hpriv = host->private_data;
1105 struct pci_dev *pdev = to_pci_dev(host->dev);
1106 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1107 int i;
1108 void __iomem *port_mmio;
1109 u32 tmp;
1110 int mv;
1111
1112 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1113 if (pdev->device == 0x6121)
1114 mv = 2;
1115 else
1116 mv = 4;
1117 port_mmio = __ahci_port_base(host, mv);
1118
1119 writel(0, port_mmio + PORT_IRQ_MASK);
1120
1121 /* clear port IRQ */
1122 tmp = readl(port_mmio + PORT_IRQ_STAT);
1123 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1124 if (tmp)
1125 writel(tmp, port_mmio + PORT_IRQ_STAT);
1126 }
1127
1128 for (i = 0; i < host->n_ports; i++) {
1129 struct ata_port *ap = host->ports[i];
1130
1131 port_mmio = ahci_port_base(ap);
1132 if (ata_port_is_dummy(ap))
1133 continue;
1134
1135 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1136 }
1137
1138 tmp = readl(mmio + HOST_CTL);
1139 VPRINTK("HOST_CTL 0x%x\n", tmp);
1140 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1141 tmp = readl(mmio + HOST_CTL);
1142 VPRINTK("HOST_CTL 0x%x\n", tmp);
1143 }
1144
1145 static void ahci_dev_config(struct ata_device *dev)
1146 {
1147 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1148
1149 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1150 dev->max_sectors = 255;
1151 ata_dev_printk(dev, KERN_INFO,
1152 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1153 }
1154 }
1155
1156 static unsigned int ahci_dev_classify(struct ata_port *ap)
1157 {
1158 void __iomem *port_mmio = ahci_port_base(ap);
1159 struct ata_taskfile tf;
1160 u32 tmp;
1161
1162 tmp = readl(port_mmio + PORT_SIG);
1163 tf.lbah = (tmp >> 24) & 0xff;
1164 tf.lbam = (tmp >> 16) & 0xff;
1165 tf.lbal = (tmp >> 8) & 0xff;
1166 tf.nsect = (tmp) & 0xff;
1167
1168 return ata_dev_classify(&tf);
1169 }
1170
1171 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1172 u32 opts)
1173 {
1174 dma_addr_t cmd_tbl_dma;
1175
1176 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1177
1178 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1179 pp->cmd_slot[tag].status = 0;
1180 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1181 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1182 }
1183
1184 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1185 {
1186 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1187 struct ahci_host_priv *hpriv = ap->host->private_data;
1188 u32 tmp;
1189 int busy, rc;
1190
1191 /* do we need to kick the port? */
1192 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1193 if (!busy && !force_restart)
1194 return 0;
1195
1196 /* stop engine */
1197 rc = ahci_stop_engine(ap);
1198 if (rc)
1199 goto out_restart;
1200
1201 /* need to do CLO? */
1202 if (!busy) {
1203 rc = 0;
1204 goto out_restart;
1205 }
1206
1207 if (!(hpriv->cap & HOST_CAP_CLO)) {
1208 rc = -EOPNOTSUPP;
1209 goto out_restart;
1210 }
1211
1212 /* perform CLO */
1213 tmp = readl(port_mmio + PORT_CMD);
1214 tmp |= PORT_CMD_CLO;
1215 writel(tmp, port_mmio + PORT_CMD);
1216
1217 rc = 0;
1218 tmp = ata_wait_register(port_mmio + PORT_CMD,
1219 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1220 if (tmp & PORT_CMD_CLO)
1221 rc = -EIO;
1222
1223 /* restart engine */
1224 out_restart:
1225 ahci_start_engine(ap);
1226 return rc;
1227 }
1228
1229 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1230 struct ata_taskfile *tf, int is_cmd, u16 flags,
1231 unsigned long timeout_msec)
1232 {
1233 const u32 cmd_fis_len = 5; /* five dwords */
1234 struct ahci_port_priv *pp = ap->private_data;
1235 void __iomem *port_mmio = ahci_port_base(ap);
1236 u8 *fis = pp->cmd_tbl;
1237 u32 tmp;
1238
1239 /* prep the command */
1240 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1241 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1242
1243 /* issue & wait */
1244 writel(1, port_mmio + PORT_CMD_ISSUE);
1245
1246 if (timeout_msec) {
1247 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1248 1, timeout_msec);
1249 if (tmp & 0x1) {
1250 ahci_kick_engine(ap, 1);
1251 return -EBUSY;
1252 }
1253 } else
1254 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1255
1256 return 0;
1257 }
1258
1259 static int ahci_check_ready(struct ata_link *link)
1260 {
1261 void __iomem *mmio = link->ap->ioaddr.cmd_addr;
1262 u8 status = readl(mmio + PORT_TFDATA) & 0xFF;
1263
1264 if (!(status & ATA_BUSY))
1265 return 1;
1266 return 0;
1267 }
1268
1269 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1270 int pmp, unsigned long deadline)
1271 {
1272 struct ata_port *ap = link->ap;
1273 const char *reason = NULL;
1274 unsigned long now, msecs;
1275 struct ata_taskfile tf;
1276 int rc;
1277
1278 DPRINTK("ENTER\n");
1279
1280 if (ata_link_offline(link)) {
1281 DPRINTK("PHY reports no device\n");
1282 *class = ATA_DEV_NONE;
1283 return 0;
1284 }
1285
1286 /* prepare for SRST (AHCI-1.1 10.4.1) */
1287 rc = ahci_kick_engine(ap, 1);
1288 if (rc && rc != -EOPNOTSUPP)
1289 ata_link_printk(link, KERN_WARNING,
1290 "failed to reset engine (errno=%d)\n", rc);
1291
1292 ata_tf_init(link->device, &tf);
1293
1294 /* issue the first D2H Register FIS */
1295 msecs = 0;
1296 now = jiffies;
1297 if (time_after(now, deadline))
1298 msecs = jiffies_to_msecs(deadline - now);
1299
1300 tf.ctl |= ATA_SRST;
1301 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1302 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1303 rc = -EIO;
1304 reason = "1st FIS failed";
1305 goto fail;
1306 }
1307
1308 /* spec says at least 5us, but be generous and sleep for 1ms */
1309 msleep(1);
1310
1311 /* issue the second D2H Register FIS */
1312 tf.ctl &= ~ATA_SRST;
1313 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1314
1315 /* wait for link to become ready */
1316 rc = ata_wait_after_reset(link, deadline, ahci_check_ready);
1317 /* link occupied, -ENODEV too is an error */
1318 if (rc) {
1319 reason = "device not ready";
1320 goto fail;
1321 }
1322 *class = ahci_dev_classify(ap);
1323
1324 DPRINTK("EXIT, class=%u\n", *class);
1325 return 0;
1326
1327 fail:
1328 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1329 return rc;
1330 }
1331
1332 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1333 unsigned long deadline)
1334 {
1335 int pmp = 0;
1336
1337 if (link->ap->flags & ATA_FLAG_PMP)
1338 pmp = SATA_PMP_CTRL_PORT;
1339
1340 return ahci_do_softreset(link, class, pmp, deadline);
1341 }
1342
1343 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1344 unsigned long deadline)
1345 {
1346 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1347 struct ata_port *ap = link->ap;
1348 struct ahci_port_priv *pp = ap->private_data;
1349 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1350 struct ata_taskfile tf;
1351 bool online;
1352 int rc;
1353
1354 DPRINTK("ENTER\n");
1355
1356 ahci_stop_engine(ap);
1357
1358 /* clear D2H reception area to properly wait for D2H FIS */
1359 ata_tf_init(link->device, &tf);
1360 tf.command = 0x80;
1361 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1362
1363 rc = sata_link_hardreset(link, timing, deadline, &online,
1364 ahci_check_ready);
1365
1366 ahci_start_engine(ap);
1367
1368 *class = ATA_DEV_NONE;
1369 if (online)
1370 *class = ahci_dev_classify(ap);
1371
1372 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1373 return rc;
1374 }
1375
1376 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1377 unsigned long deadline)
1378 {
1379 struct ata_port *ap = link->ap;
1380 u32 serror;
1381 bool online;
1382 int rc;
1383
1384 DPRINTK("ENTER\n");
1385
1386 ahci_stop_engine(ap);
1387
1388 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1389 deadline, &online, NULL);
1390
1391 /* vt8251 needs SError cleared for the port to operate */
1392 ahci_scr_read(ap, SCR_ERROR, &serror);
1393 ahci_scr_write(ap, SCR_ERROR, serror);
1394
1395 ahci_start_engine(ap);
1396
1397 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1398
1399 /* vt8251 doesn't clear BSY on signature FIS reception,
1400 * request follow-up softreset.
1401 */
1402 *class = ATA_DEV_NONE;
1403 return online ? -EAGAIN : rc;
1404 }
1405
1406 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1407 unsigned long deadline)
1408 {
1409 struct ata_port *ap = link->ap;
1410 struct ahci_port_priv *pp = ap->private_data;
1411 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1412 struct ata_taskfile tf;
1413 bool online;
1414 int rc;
1415
1416 ahci_stop_engine(ap);
1417
1418 /* clear D2H reception area to properly wait for D2H FIS */
1419 ata_tf_init(link->device, &tf);
1420 tf.command = 0x80;
1421 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1422
1423 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1424 deadline, &online, NULL);
1425
1426 ahci_start_engine(ap);
1427
1428 /* The pseudo configuration device on SIMG4726 attached to
1429 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1430 * hardreset if no device is attached to the first downstream
1431 * port && the pseudo device locks up on SRST w/ PMP==0. To
1432 * work around this, wait for !BSY only briefly. If BSY isn't
1433 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1434 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1435 *
1436 * Wait for two seconds. Devices attached to downstream port
1437 * which can't process the following IDENTIFY after this will
1438 * have to be reset again. For most cases, this should
1439 * suffice while making probing snappish enough.
1440 */
1441 if (online) {
1442 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1443 ahci_check_ready);
1444 if (rc)
1445 ahci_kick_engine(ap, 0);
1446 }
1447 *class = ATA_DEV_NONE;
1448 return rc;
1449 }
1450
1451 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1452 {
1453 struct ata_port *ap = link->ap;
1454 void __iomem *port_mmio = ahci_port_base(ap);
1455 u32 new_tmp, tmp;
1456
1457 ata_std_postreset(link, class);
1458
1459 /* Make sure port's ATAPI bit is set appropriately */
1460 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1461 if (*class == ATA_DEV_ATAPI)
1462 new_tmp |= PORT_CMD_ATAPI;
1463 else
1464 new_tmp &= ~PORT_CMD_ATAPI;
1465 if (new_tmp != tmp) {
1466 writel(new_tmp, port_mmio + PORT_CMD);
1467 readl(port_mmio + PORT_CMD); /* flush */
1468 }
1469 }
1470
1471 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1472 unsigned long deadline)
1473 {
1474 return ahci_do_softreset(link, class, link->pmp, deadline);
1475 }
1476
1477 static u8 ahci_check_status(struct ata_port *ap)
1478 {
1479 void __iomem *mmio = ap->ioaddr.cmd_addr;
1480
1481 return readl(mmio + PORT_TFDATA) & 0xFF;
1482 }
1483
1484 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1485 {
1486 struct ahci_port_priv *pp = ap->private_data;
1487 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1488
1489 ata_tf_from_fis(d2h_fis, tf);
1490 }
1491
1492 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1493 {
1494 struct scatterlist *sg;
1495 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1496 unsigned int si;
1497
1498 VPRINTK("ENTER\n");
1499
1500 /*
1501 * Next, the S/G list.
1502 */
1503 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1504 dma_addr_t addr = sg_dma_address(sg);
1505 u32 sg_len = sg_dma_len(sg);
1506
1507 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1508 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1509 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1510 }
1511
1512 return si;
1513 }
1514
1515 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1516 {
1517 struct ata_port *ap = qc->ap;
1518 struct ahci_port_priv *pp = ap->private_data;
1519 int is_atapi = ata_is_atapi(qc->tf.protocol);
1520 void *cmd_tbl;
1521 u32 opts;
1522 const u32 cmd_fis_len = 5; /* five dwords */
1523 unsigned int n_elem;
1524
1525 /*
1526 * Fill in command table information. First, the header,
1527 * a SATA Register - Host to Device command FIS.
1528 */
1529 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1530
1531 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1532 if (is_atapi) {
1533 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1534 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1535 }
1536
1537 n_elem = 0;
1538 if (qc->flags & ATA_QCFLAG_DMAMAP)
1539 n_elem = ahci_fill_sg(qc, cmd_tbl);
1540
1541 /*
1542 * Fill in command slot information.
1543 */
1544 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1545 if (qc->tf.flags & ATA_TFLAG_WRITE)
1546 opts |= AHCI_CMD_WRITE;
1547 if (is_atapi)
1548 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1549
1550 ahci_fill_cmd_slot(pp, qc->tag, opts);
1551 }
1552
1553 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1554 {
1555 struct ahci_host_priv *hpriv = ap->host->private_data;
1556 struct ahci_port_priv *pp = ap->private_data;
1557 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1558 struct ata_link *link = NULL;
1559 struct ata_queued_cmd *active_qc;
1560 struct ata_eh_info *active_ehi;
1561 u32 serror;
1562
1563 /* determine active link */
1564 ata_port_for_each_link(link, ap)
1565 if (ata_link_active(link))
1566 break;
1567 if (!link)
1568 link = &ap->link;
1569
1570 active_qc = ata_qc_from_tag(ap, link->active_tag);
1571 active_ehi = &link->eh_info;
1572
1573 /* record irq stat */
1574 ata_ehi_clear_desc(host_ehi);
1575 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1576
1577 /* AHCI needs SError cleared; otherwise, it might lock up */
1578 ahci_scr_read(ap, SCR_ERROR, &serror);
1579 ahci_scr_write(ap, SCR_ERROR, serror);
1580 host_ehi->serror |= serror;
1581
1582 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1583 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1584 irq_stat &= ~PORT_IRQ_IF_ERR;
1585
1586 if (irq_stat & PORT_IRQ_TF_ERR) {
1587 /* If qc is active, charge it; otherwise, the active
1588 * link. There's no active qc on NCQ errors. It will
1589 * be determined by EH by reading log page 10h.
1590 */
1591 if (active_qc)
1592 active_qc->err_mask |= AC_ERR_DEV;
1593 else
1594 active_ehi->err_mask |= AC_ERR_DEV;
1595
1596 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1597 host_ehi->serror &= ~SERR_INTERNAL;
1598 }
1599
1600 if (irq_stat & PORT_IRQ_UNK_FIS) {
1601 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1602
1603 active_ehi->err_mask |= AC_ERR_HSM;
1604 active_ehi->action |= ATA_EH_RESET;
1605 ata_ehi_push_desc(active_ehi,
1606 "unknown FIS %08x %08x %08x %08x" ,
1607 unk[0], unk[1], unk[2], unk[3]);
1608 }
1609
1610 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1611 active_ehi->err_mask |= AC_ERR_HSM;
1612 active_ehi->action |= ATA_EH_RESET;
1613 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1614 }
1615
1616 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1617 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1618 host_ehi->action |= ATA_EH_RESET;
1619 ata_ehi_push_desc(host_ehi, "host bus error");
1620 }
1621
1622 if (irq_stat & PORT_IRQ_IF_ERR) {
1623 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1624 host_ehi->action |= ATA_EH_RESET;
1625 ata_ehi_push_desc(host_ehi, "interface fatal error");
1626 }
1627
1628 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1629 ata_ehi_hotplugged(host_ehi);
1630 ata_ehi_push_desc(host_ehi, "%s",
1631 irq_stat & PORT_IRQ_CONNECT ?
1632 "connection status changed" : "PHY RDY changed");
1633 }
1634
1635 /* okay, let's hand over to EH */
1636
1637 if (irq_stat & PORT_IRQ_FREEZE)
1638 ata_port_freeze(ap);
1639 else
1640 ata_port_abort(ap);
1641 }
1642
1643 static void ahci_port_intr(struct ata_port *ap)
1644 {
1645 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1646 struct ata_eh_info *ehi = &ap->link.eh_info;
1647 struct ahci_port_priv *pp = ap->private_data;
1648 struct ahci_host_priv *hpriv = ap->host->private_data;
1649 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1650 u32 status, qc_active;
1651 int rc;
1652
1653 status = readl(port_mmio + PORT_IRQ_STAT);
1654 writel(status, port_mmio + PORT_IRQ_STAT);
1655
1656 /* ignore BAD_PMP while resetting */
1657 if (unlikely(resetting))
1658 status &= ~PORT_IRQ_BAD_PMP;
1659
1660 /* If we are getting PhyRdy, this is
1661 * just a power state change, we should
1662 * clear out this, plus the PhyRdy/Comm
1663 * Wake bits from Serror
1664 */
1665 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1666 (status & PORT_IRQ_PHYRDY)) {
1667 status &= ~PORT_IRQ_PHYRDY;
1668 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1669 }
1670
1671 if (unlikely(status & PORT_IRQ_ERROR)) {
1672 ahci_error_intr(ap, status);
1673 return;
1674 }
1675
1676 if (status & PORT_IRQ_SDB_FIS) {
1677 /* If SNotification is available, leave notification
1678 * handling to sata_async_notification(). If not,
1679 * emulate it by snooping SDB FIS RX area.
1680 *
1681 * Snooping FIS RX area is probably cheaper than
1682 * poking SNotification but some constrollers which
1683 * implement SNotification, ICH9 for example, don't
1684 * store AN SDB FIS into receive area.
1685 */
1686 if (hpriv->cap & HOST_CAP_SNTF)
1687 sata_async_notification(ap);
1688 else {
1689 /* If the 'N' bit in word 0 of the FIS is set,
1690 * we just received asynchronous notification.
1691 * Tell libata about it.
1692 */
1693 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1694 u32 f0 = le32_to_cpu(f[0]);
1695
1696 if (f0 & (1 << 15))
1697 sata_async_notification(ap);
1698 }
1699 }
1700
1701 /* pp->active_link is valid iff any command is in flight */
1702 if (ap->qc_active && pp->active_link->sactive)
1703 qc_active = readl(port_mmio + PORT_SCR_ACT);
1704 else
1705 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1706
1707 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1708
1709 /* while resetting, invalid completions are expected */
1710 if (unlikely(rc < 0 && !resetting)) {
1711 ehi->err_mask |= AC_ERR_HSM;
1712 ehi->action |= ATA_EH_RESET;
1713 ata_port_freeze(ap);
1714 }
1715 }
1716
1717 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1718 {
1719 struct ata_host *host = dev_instance;
1720 struct ahci_host_priv *hpriv;
1721 unsigned int i, handled = 0;
1722 void __iomem *mmio;
1723 u32 irq_stat, irq_ack = 0;
1724
1725 VPRINTK("ENTER\n");
1726
1727 hpriv = host->private_data;
1728 mmio = host->iomap[AHCI_PCI_BAR];
1729
1730 /* sigh. 0xffffffff is a valid return from h/w */
1731 irq_stat = readl(mmio + HOST_IRQ_STAT);
1732 irq_stat &= hpriv->port_map;
1733 if (!irq_stat)
1734 return IRQ_NONE;
1735
1736 spin_lock(&host->lock);
1737
1738 for (i = 0; i < host->n_ports; i++) {
1739 struct ata_port *ap;
1740
1741 if (!(irq_stat & (1 << i)))
1742 continue;
1743
1744 ap = host->ports[i];
1745 if (ap) {
1746 ahci_port_intr(ap);
1747 VPRINTK("port %u\n", i);
1748 } else {
1749 VPRINTK("port %u (no irq)\n", i);
1750 if (ata_ratelimit())
1751 dev_printk(KERN_WARNING, host->dev,
1752 "interrupt on disabled port %u\n", i);
1753 }
1754
1755 irq_ack |= (1 << i);
1756 }
1757
1758 if (irq_ack) {
1759 writel(irq_ack, mmio + HOST_IRQ_STAT);
1760 handled = 1;
1761 }
1762
1763 spin_unlock(&host->lock);
1764
1765 VPRINTK("EXIT\n");
1766
1767 return IRQ_RETVAL(handled);
1768 }
1769
1770 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1771 {
1772 struct ata_port *ap = qc->ap;
1773 void __iomem *port_mmio = ahci_port_base(ap);
1774 struct ahci_port_priv *pp = ap->private_data;
1775
1776 /* Keep track of the currently active link. It will be used
1777 * in completion path to determine whether NCQ phase is in
1778 * progress.
1779 */
1780 pp->active_link = qc->dev->link;
1781
1782 if (qc->tf.protocol == ATA_PROT_NCQ)
1783 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1784 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1785 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1786
1787 return 0;
1788 }
1789
1790 static void ahci_freeze(struct ata_port *ap)
1791 {
1792 void __iomem *port_mmio = ahci_port_base(ap);
1793
1794 /* turn IRQ off */
1795 writel(0, port_mmio + PORT_IRQ_MASK);
1796 }
1797
1798 static void ahci_thaw(struct ata_port *ap)
1799 {
1800 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1801 void __iomem *port_mmio = ahci_port_base(ap);
1802 u32 tmp;
1803 struct ahci_port_priv *pp = ap->private_data;
1804
1805 /* clear IRQ */
1806 tmp = readl(port_mmio + PORT_IRQ_STAT);
1807 writel(tmp, port_mmio + PORT_IRQ_STAT);
1808 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1809
1810 /* turn IRQ back on */
1811 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1812 }
1813
1814 static void ahci_error_handler(struct ata_port *ap)
1815 {
1816 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1817 /* restart engine */
1818 ahci_stop_engine(ap);
1819 ahci_start_engine(ap);
1820 }
1821
1822 sata_pmp_error_handler(ap);
1823 }
1824
1825 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1826 {
1827 struct ata_port *ap = qc->ap;
1828
1829 /* make DMA engine forget about the failed command */
1830 if (qc->flags & ATA_QCFLAG_FAILED)
1831 ahci_kick_engine(ap, 1);
1832 }
1833
1834 static void ahci_pmp_attach(struct ata_port *ap)
1835 {
1836 void __iomem *port_mmio = ahci_port_base(ap);
1837 struct ahci_port_priv *pp = ap->private_data;
1838 u32 cmd;
1839
1840 cmd = readl(port_mmio + PORT_CMD);
1841 cmd |= PORT_CMD_PMP;
1842 writel(cmd, port_mmio + PORT_CMD);
1843
1844 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1845 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1846 }
1847
1848 static void ahci_pmp_detach(struct ata_port *ap)
1849 {
1850 void __iomem *port_mmio = ahci_port_base(ap);
1851 struct ahci_port_priv *pp = ap->private_data;
1852 u32 cmd;
1853
1854 cmd = readl(port_mmio + PORT_CMD);
1855 cmd &= ~PORT_CMD_PMP;
1856 writel(cmd, port_mmio + PORT_CMD);
1857
1858 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1859 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1860 }
1861
1862 static int ahci_port_resume(struct ata_port *ap)
1863 {
1864 ahci_power_up(ap);
1865 ahci_start_port(ap);
1866
1867 if (ap->nr_pmp_links)
1868 ahci_pmp_attach(ap);
1869 else
1870 ahci_pmp_detach(ap);
1871
1872 return 0;
1873 }
1874
1875 #ifdef CONFIG_PM
1876 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1877 {
1878 const char *emsg = NULL;
1879 int rc;
1880
1881 rc = ahci_deinit_port(ap, &emsg);
1882 if (rc == 0)
1883 ahci_power_down(ap);
1884 else {
1885 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1886 ahci_start_port(ap);
1887 }
1888
1889 return rc;
1890 }
1891
1892 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1893 {
1894 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1895 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1896 u32 ctl;
1897
1898 if (mesg.event & PM_EVENT_SLEEP) {
1899 /* AHCI spec rev1.1 section 8.3.3:
1900 * Software must disable interrupts prior to requesting a
1901 * transition of the HBA to D3 state.
1902 */
1903 ctl = readl(mmio + HOST_CTL);
1904 ctl &= ~HOST_IRQ_EN;
1905 writel(ctl, mmio + HOST_CTL);
1906 readl(mmio + HOST_CTL); /* flush */
1907 }
1908
1909 return ata_pci_device_suspend(pdev, mesg);
1910 }
1911
1912 static int ahci_pci_device_resume(struct pci_dev *pdev)
1913 {
1914 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1915 int rc;
1916
1917 rc = ata_pci_device_do_resume(pdev);
1918 if (rc)
1919 return rc;
1920
1921 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1922 rc = ahci_reset_controller(host);
1923 if (rc)
1924 return rc;
1925
1926 ahci_init_controller(host);
1927 }
1928
1929 ata_host_resume(host);
1930
1931 return 0;
1932 }
1933 #endif
1934
1935 static int ahci_port_start(struct ata_port *ap)
1936 {
1937 struct device *dev = ap->host->dev;
1938 struct ahci_port_priv *pp;
1939 void *mem;
1940 dma_addr_t mem_dma;
1941
1942 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1943 if (!pp)
1944 return -ENOMEM;
1945
1946 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1947 GFP_KERNEL);
1948 if (!mem)
1949 return -ENOMEM;
1950 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1951
1952 /*
1953 * First item in chunk of DMA memory: 32-slot command table,
1954 * 32 bytes each in size
1955 */
1956 pp->cmd_slot = mem;
1957 pp->cmd_slot_dma = mem_dma;
1958
1959 mem += AHCI_CMD_SLOT_SZ;
1960 mem_dma += AHCI_CMD_SLOT_SZ;
1961
1962 /*
1963 * Second item: Received-FIS area
1964 */
1965 pp->rx_fis = mem;
1966 pp->rx_fis_dma = mem_dma;
1967
1968 mem += AHCI_RX_FIS_SZ;
1969 mem_dma += AHCI_RX_FIS_SZ;
1970
1971 /*
1972 * Third item: data area for storing a single command
1973 * and its scatter-gather table
1974 */
1975 pp->cmd_tbl = mem;
1976 pp->cmd_tbl_dma = mem_dma;
1977
1978 /*
1979 * Save off initial list of interrupts to be enabled.
1980 * This could be changed later
1981 */
1982 pp->intr_mask = DEF_PORT_IRQ;
1983
1984 ap->private_data = pp;
1985
1986 /* engage engines, captain */
1987 return ahci_port_resume(ap);
1988 }
1989
1990 static void ahci_port_stop(struct ata_port *ap)
1991 {
1992 const char *emsg = NULL;
1993 int rc;
1994
1995 /* de-initialize port */
1996 rc = ahci_deinit_port(ap, &emsg);
1997 if (rc)
1998 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1999 }
2000
2001 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2002 {
2003 int rc;
2004
2005 if (using_dac &&
2006 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2007 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2008 if (rc) {
2009 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2010 if (rc) {
2011 dev_printk(KERN_ERR, &pdev->dev,
2012 "64-bit DMA enable failed\n");
2013 return rc;
2014 }
2015 }
2016 } else {
2017 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2018 if (rc) {
2019 dev_printk(KERN_ERR, &pdev->dev,
2020 "32-bit DMA enable failed\n");
2021 return rc;
2022 }
2023 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2024 if (rc) {
2025 dev_printk(KERN_ERR, &pdev->dev,
2026 "32-bit consistent DMA enable failed\n");
2027 return rc;
2028 }
2029 }
2030 return 0;
2031 }
2032
2033 static void ahci_print_info(struct ata_host *host)
2034 {
2035 struct ahci_host_priv *hpriv = host->private_data;
2036 struct pci_dev *pdev = to_pci_dev(host->dev);
2037 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2038 u32 vers, cap, impl, speed;
2039 const char *speed_s;
2040 u16 cc;
2041 const char *scc_s;
2042
2043 vers = readl(mmio + HOST_VERSION);
2044 cap = hpriv->cap;
2045 impl = hpriv->port_map;
2046
2047 speed = (cap >> 20) & 0xf;
2048 if (speed == 1)
2049 speed_s = "1.5";
2050 else if (speed == 2)
2051 speed_s = "3";
2052 else
2053 speed_s = "?";
2054
2055 pci_read_config_word(pdev, 0x0a, &cc);
2056 if (cc == PCI_CLASS_STORAGE_IDE)
2057 scc_s = "IDE";
2058 else if (cc == PCI_CLASS_STORAGE_SATA)
2059 scc_s = "SATA";
2060 else if (cc == PCI_CLASS_STORAGE_RAID)
2061 scc_s = "RAID";
2062 else
2063 scc_s = "unknown";
2064
2065 dev_printk(KERN_INFO, &pdev->dev,
2066 "AHCI %02x%02x.%02x%02x "
2067 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2068 ,
2069
2070 (vers >> 24) & 0xff,
2071 (vers >> 16) & 0xff,
2072 (vers >> 8) & 0xff,
2073 vers & 0xff,
2074
2075 ((cap >> 8) & 0x1f) + 1,
2076 (cap & 0x1f) + 1,
2077 speed_s,
2078 impl,
2079 scc_s);
2080
2081 dev_printk(KERN_INFO, &pdev->dev,
2082 "flags: "
2083 "%s%s%s%s%s%s%s"
2084 "%s%s%s%s%s%s%s\n"
2085 ,
2086
2087 cap & (1 << 31) ? "64bit " : "",
2088 cap & (1 << 30) ? "ncq " : "",
2089 cap & (1 << 29) ? "sntf " : "",
2090 cap & (1 << 28) ? "ilck " : "",
2091 cap & (1 << 27) ? "stag " : "",
2092 cap & (1 << 26) ? "pm " : "",
2093 cap & (1 << 25) ? "led " : "",
2094
2095 cap & (1 << 24) ? "clo " : "",
2096 cap & (1 << 19) ? "nz " : "",
2097 cap & (1 << 18) ? "only " : "",
2098 cap & (1 << 17) ? "pmp " : "",
2099 cap & (1 << 15) ? "pio " : "",
2100 cap & (1 << 14) ? "slum " : "",
2101 cap & (1 << 13) ? "part " : ""
2102 );
2103 }
2104
2105 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2106 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2107 * support PMP and the 4726 either directly exports the device
2108 * attached to the first downstream port or acts as a hardware storage
2109 * controller and emulate a single ATA device (can be RAID 0/1 or some
2110 * other configuration).
2111 *
2112 * When there's no device attached to the first downstream port of the
2113 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2114 * configure the 4726. However, ATA emulation of the device is very
2115 * lame. It doesn't send signature D2H Reg FIS after the initial
2116 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2117 *
2118 * The following function works around the problem by always using
2119 * hardreset on the port and not depending on receiving signature FIS
2120 * afterward. If signature FIS isn't received soon, ATA class is
2121 * assumed without follow-up softreset.
2122 */
2123 static void ahci_p5wdh_workaround(struct ata_host *host)
2124 {
2125 static struct dmi_system_id sysids[] = {
2126 {
2127 .ident = "P5W DH Deluxe",
2128 .matches = {
2129 DMI_MATCH(DMI_SYS_VENDOR,
2130 "ASUSTEK COMPUTER INC"),
2131 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2132 },
2133 },
2134 { }
2135 };
2136 struct pci_dev *pdev = to_pci_dev(host->dev);
2137
2138 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2139 dmi_check_system(sysids)) {
2140 struct ata_port *ap = host->ports[1];
2141
2142 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2143 "Deluxe on-board SIMG4726 workaround\n");
2144
2145 ap->ops = &ahci_p5wdh_ops;
2146 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2147 }
2148 }
2149
2150 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2151 {
2152 static int printed_version;
2153 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2154 const struct ata_port_info *ppi[] = { &pi, NULL };
2155 struct device *dev = &pdev->dev;
2156 struct ahci_host_priv *hpriv;
2157 struct ata_host *host;
2158 int n_ports, i, rc;
2159
2160 VPRINTK("ENTER\n");
2161
2162 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2163
2164 if (!printed_version++)
2165 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2166
2167 /* acquire resources */
2168 rc = pcim_enable_device(pdev);
2169 if (rc)
2170 return rc;
2171
2172 /* AHCI controllers often implement SFF compatible interface.
2173 * Grab all PCI BARs just in case.
2174 */
2175 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2176 if (rc == -EBUSY)
2177 pcim_pin_device(pdev);
2178 if (rc)
2179 return rc;
2180
2181 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2182 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2183 u8 map;
2184
2185 /* ICH6s share the same PCI ID for both piix and ahci
2186 * modes. Enabling ahci mode while MAP indicates
2187 * combined mode is a bad idea. Yield to ata_piix.
2188 */
2189 pci_read_config_byte(pdev, ICH_MAP, &map);
2190 if (map & 0x3) {
2191 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2192 "combined mode, can't enable AHCI mode\n");
2193 return -ENODEV;
2194 }
2195 }
2196
2197 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2198 if (!hpriv)
2199 return -ENOMEM;
2200 hpriv->flags |= (unsigned long)pi.private_data;
2201
2202 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2203 pci_intx(pdev, 1);
2204
2205 /* save initial config */
2206 ahci_save_initial_config(pdev, hpriv);
2207
2208 /* prepare host */
2209 if (hpriv->cap & HOST_CAP_NCQ)
2210 pi.flags |= ATA_FLAG_NCQ;
2211
2212 if (hpriv->cap & HOST_CAP_PMP)
2213 pi.flags |= ATA_FLAG_PMP;
2214
2215 /* CAP.NP sometimes indicate the index of the last enabled
2216 * port, at other times, that of the last possible port, so
2217 * determining the maximum port number requires looking at
2218 * both CAP.NP and port_map.
2219 */
2220 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2221
2222 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2223 if (!host)
2224 return -ENOMEM;
2225 host->iomap = pcim_iomap_table(pdev);
2226 host->private_data = hpriv;
2227
2228 for (i = 0; i < host->n_ports; i++) {
2229 struct ata_port *ap = host->ports[i];
2230 void __iomem *port_mmio = ahci_port_base(ap);
2231
2232 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2233 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2234 0x100 + ap->port_no * 0x80, "port");
2235
2236 /* set initial link pm policy */
2237 ap->pm_policy = NOT_AVAILABLE;
2238
2239 /* standard SATA port setup */
2240 if (hpriv->port_map & (1 << i))
2241 ap->ioaddr.cmd_addr = port_mmio;
2242
2243 /* disabled/not-implemented port */
2244 else
2245 ap->ops = &ata_dummy_port_ops;
2246 }
2247
2248 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2249 ahci_p5wdh_workaround(host);
2250
2251 /* initialize adapter */
2252 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2253 if (rc)
2254 return rc;
2255
2256 rc = ahci_reset_controller(host);
2257 if (rc)
2258 return rc;
2259
2260 ahci_init_controller(host);
2261 ahci_print_info(host);
2262
2263 pci_set_master(pdev);
2264 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2265 &ahci_sht);
2266 }
2267
2268 static int __init ahci_init(void)
2269 {
2270 return pci_register_driver(&ahci_pci_driver);
2271 }
2272
2273 static void __exit ahci_exit(void)
2274 {
2275 pci_unregister_driver(&ahci_pci_driver);
2276 }
2277
2278
2279 MODULE_AUTHOR("Jeff Garzik");
2280 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2281 MODULE_LICENSE("GPL");
2282 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2283 MODULE_VERSION(DRV_VERSION);
2284
2285 module_init(ahci_init);
2286 module_exit(ahci_exit);
Linux kernel - Deliverables
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