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ARM: 8255/1: perf: Prevent wraparound during overflow
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include "ahci.h"
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "3.0"
52
53 enum {
54 AHCI_PCI_BAR_STA2X11 = 0,
55 AHCI_PCI_BAR_ENMOTUS = 2,
56 AHCI_PCI_BAR_STANDARD = 5,
57 };
58
59 enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nomsi,
64 board_ahci_noncq,
65 board_ahci_nosntf,
66 board_ahci_yes_fbs,
67
68 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_mcp65,
70 board_ahci_mcp77,
71 board_ahci_mcp89,
72 board_ahci_mv,
73 board_ahci_sb600,
74 board_ahci_sb700, /* for SB700 and SB800 */
75 board_ahci_vt8251,
76
77 /* aliases */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
82 };
83
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
88 static bool is_mcp89_apple(struct pci_dev *pdev);
89 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 #ifdef CONFIG_PM
92 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
93 static int ahci_pci_device_resume(struct pci_dev *pdev);
94 #endif
95
96 static struct scsi_host_template ahci_sht = {
97 AHCI_SHT("ahci"),
98 };
99
100 static struct ata_port_operations ahci_vt8251_ops = {
101 .inherits = &ahci_ops,
102 .hardreset = ahci_vt8251_hardreset,
103 };
104
105 static struct ata_port_operations ahci_p5wdh_ops = {
106 .inherits = &ahci_ops,
107 .hardreset = ahci_p5wdh_hardreset,
108 };
109
110 static const struct ata_port_info ahci_port_info[] = {
111 /* by features */
112 [board_ahci] = {
113 .flags = AHCI_FLAG_COMMON,
114 .pio_mask = ATA_PIO4,
115 .udma_mask = ATA_UDMA6,
116 .port_ops = &ahci_ops,
117 },
118 [board_ahci_ign_iferr] = {
119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
120 .flags = AHCI_FLAG_COMMON,
121 .pio_mask = ATA_PIO4,
122 .udma_mask = ATA_UDMA6,
123 .port_ops = &ahci_ops,
124 },
125 [board_ahci_nomsi] = {
126 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_noncq] = {
133 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
139 [board_ahci_nosntf] = {
140 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
141 .flags = AHCI_FLAG_COMMON,
142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
145 },
146 [board_ahci_yes_fbs] = {
147 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
153 /* by chipsets */
154 [board_ahci_mcp65] = {
155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
156 AHCI_HFLAG_YES_NCQ),
157 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
161 },
162 [board_ahci_mcp77] = {
163 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
168 },
169 [board_ahci_mcp89] = {
170 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
176 [board_ahci_mv] = {
177 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
178 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
179 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
183 },
184 [board_ahci_sb600] = {
185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_pmp_retry_srst_ops,
192 },
193 [board_ahci_sb700] = { /* for SB700 and SB800 */
194 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_pmp_retry_srst_ops,
199 },
200 [board_ahci_vt8251] = {
201 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
202 .flags = AHCI_FLAG_COMMON,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_vt8251_ops,
206 },
207 };
208
209 static const struct pci_device_id ahci_pci_tbl[] = {
210 /* Intel */
211 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
212 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
213 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
214 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
215 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
216 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
217 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
218 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
221 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
222 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
223 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
224 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
225 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
226 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
237 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
239 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
240 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
241 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
242 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
243 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
245 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
246 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
247 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
248 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
250 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
251 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
252 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
253 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
254 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
255 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
258 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
259 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
260 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
261 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
262 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
265 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
266 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
267 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
268 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
270 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
271 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
272 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
273 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
274 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
275 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
276 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
277 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
278 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
279 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
280 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
281 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
282 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
283 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
284 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
285 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
294 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
295 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
298 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
299 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
300 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
301 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
304 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
305 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
306 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
307 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
308 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
309 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
310 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
311 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
312 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
313 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
314 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
315 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
316 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
317 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
318 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
319 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
320 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
321 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
322 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
323 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
324 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
325 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
328 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H RAID */
329 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
330 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
331 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
332
333 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
334 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
335 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
336 /* JMicron 362B and 362C have an AHCI function with IDE class code */
337 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
338 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
339
340 /* ATI */
341 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
342 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
343 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
344 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
345 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
346 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
347 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
348
349 /* AMD */
350 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
351 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
352 /* AMD is using RAID class only for ahci controllers */
353 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
354 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
355
356 /* VIA */
357 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
358 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
359
360 /* NVIDIA */
361 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
362 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
363 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
364 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
365 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
366 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
367 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
368 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
369 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
370 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
371 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
372 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
373 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
374 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
375 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
376 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
377 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
378 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
379 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
380 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
381 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
382 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
383 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
384 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
385 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
386 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
387 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
388 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
389 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
390 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
391 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
392 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
393 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
394 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
395 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
396 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
397 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
398 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
399 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
400 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
401 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
402 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
403 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
404 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
405 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
406 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
407 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
408 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
409 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
410 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
411 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
412 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
413 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
414 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
415 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
416 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
417 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
418 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
419 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
420 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
421 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
422 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
423 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
424 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
425 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
426 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
427 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
428 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
429 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
430 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
431 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
432 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
433 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
434 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
435 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
436 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
437 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
438 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
439 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
440 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
441 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
442 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
443 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
444 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
445
446 /* SiS */
447 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
448 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
449 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
450
451 /* ST Microelectronics */
452 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
453
454 /* Marvell */
455 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
456 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
457 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
458 .class = PCI_CLASS_STORAGE_SATA_AHCI,
459 .class_mask = 0xffffff,
460 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
461 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
462 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
463 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
464 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
465 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
466 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
467 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
468 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
469 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
470 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
471 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
472 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
473 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
474 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
475 .driver_data = board_ahci_yes_fbs },
476 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
477 .driver_data = board_ahci_yes_fbs },
478 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
479 .driver_data = board_ahci_yes_fbs },
480 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
481 .driver_data = board_ahci_yes_fbs },
482
483 /* Promise */
484 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
485 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
486
487 /* Asmedia */
488 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
489 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
490 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
491 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
492
493 /*
494 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
495 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
496 */
497 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
498 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
499
500 /* Enmotus */
501 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
502
503 /* Generic, PCI class code for AHCI */
504 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
505 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
506
507 { } /* terminate list */
508 };
509
510
511 static struct pci_driver ahci_pci_driver = {
512 .name = DRV_NAME,
513 .id_table = ahci_pci_tbl,
514 .probe = ahci_init_one,
515 .remove = ata_pci_remove_one,
516 #ifdef CONFIG_PM
517 .suspend = ahci_pci_device_suspend,
518 .resume = ahci_pci_device_resume,
519 #endif
520 };
521
522 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
523 static int marvell_enable;
524 #else
525 static int marvell_enable = 1;
526 #endif
527 module_param(marvell_enable, int, 0644);
528 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
529
530
531 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
532 struct ahci_host_priv *hpriv)
533 {
534 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
535 dev_info(&pdev->dev, "JMB361 has only one port\n");
536 hpriv->force_port_map = 1;
537 }
538
539 /*
540 * Temporary Marvell 6145 hack: PATA port presence
541 * is asserted through the standard AHCI port
542 * presence register, as bit 4 (counting from 0)
543 */
544 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
545 if (pdev->device == 0x6121)
546 hpriv->mask_port_map = 0x3;
547 else
548 hpriv->mask_port_map = 0xf;
549 dev_info(&pdev->dev,
550 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
551 }
552
553 ahci_save_initial_config(&pdev->dev, hpriv);
554 }
555
556 static int ahci_pci_reset_controller(struct ata_host *host)
557 {
558 struct pci_dev *pdev = to_pci_dev(host->dev);
559
560 ahci_reset_controller(host);
561
562 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
563 struct ahci_host_priv *hpriv = host->private_data;
564 u16 tmp16;
565
566 /* configure PCS */
567 pci_read_config_word(pdev, 0x92, &tmp16);
568 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
569 tmp16 |= hpriv->port_map;
570 pci_write_config_word(pdev, 0x92, tmp16);
571 }
572 }
573
574 return 0;
575 }
576
577 static void ahci_pci_init_controller(struct ata_host *host)
578 {
579 struct ahci_host_priv *hpriv = host->private_data;
580 struct pci_dev *pdev = to_pci_dev(host->dev);
581 void __iomem *port_mmio;
582 u32 tmp;
583 int mv;
584
585 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
586 if (pdev->device == 0x6121)
587 mv = 2;
588 else
589 mv = 4;
590 port_mmio = __ahci_port_base(host, mv);
591
592 writel(0, port_mmio + PORT_IRQ_MASK);
593
594 /* clear port IRQ */
595 tmp = readl(port_mmio + PORT_IRQ_STAT);
596 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
597 if (tmp)
598 writel(tmp, port_mmio + PORT_IRQ_STAT);
599 }
600
601 ahci_init_controller(host);
602 }
603
604 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
605 unsigned long deadline)
606 {
607 struct ata_port *ap = link->ap;
608 struct ahci_host_priv *hpriv = ap->host->private_data;
609 bool online;
610 int rc;
611
612 DPRINTK("ENTER\n");
613
614 ahci_stop_engine(ap);
615
616 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
617 deadline, &online, NULL);
618
619 hpriv->start_engine(ap);
620
621 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
622
623 /* vt8251 doesn't clear BSY on signature FIS reception,
624 * request follow-up softreset.
625 */
626 return online ? -EAGAIN : rc;
627 }
628
629 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
630 unsigned long deadline)
631 {
632 struct ata_port *ap = link->ap;
633 struct ahci_port_priv *pp = ap->private_data;
634 struct ahci_host_priv *hpriv = ap->host->private_data;
635 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
636 struct ata_taskfile tf;
637 bool online;
638 int rc;
639
640 ahci_stop_engine(ap);
641
642 /* clear D2H reception area to properly wait for D2H FIS */
643 ata_tf_init(link->device, &tf);
644 tf.command = ATA_BUSY;
645 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
646
647 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
648 deadline, &online, NULL);
649
650 hpriv->start_engine(ap);
651
652 /* The pseudo configuration device on SIMG4726 attached to
653 * ASUS P5W-DH Deluxe doesn't send signature FIS after
654 * hardreset if no device is attached to the first downstream
655 * port && the pseudo device locks up on SRST w/ PMP==0. To
656 * work around this, wait for !BSY only briefly. If BSY isn't
657 * cleared, perform CLO and proceed to IDENTIFY (achieved by
658 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
659 *
660 * Wait for two seconds. Devices attached to downstream port
661 * which can't process the following IDENTIFY after this will
662 * have to be reset again. For most cases, this should
663 * suffice while making probing snappish enough.
664 */
665 if (online) {
666 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
667 ahci_check_ready);
668 if (rc)
669 ahci_kick_engine(ap);
670 }
671 return rc;
672 }
673
674 #ifdef CONFIG_PM
675 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
676 {
677 struct ata_host *host = pci_get_drvdata(pdev);
678 struct ahci_host_priv *hpriv = host->private_data;
679 void __iomem *mmio = hpriv->mmio;
680 u32 ctl;
681
682 if (mesg.event & PM_EVENT_SUSPEND &&
683 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
684 dev_err(&pdev->dev,
685 "BIOS update required for suspend/resume\n");
686 return -EIO;
687 }
688
689 if (mesg.event & PM_EVENT_SLEEP) {
690 /* AHCI spec rev1.1 section 8.3.3:
691 * Software must disable interrupts prior to requesting a
692 * transition of the HBA to D3 state.
693 */
694 ctl = readl(mmio + HOST_CTL);
695 ctl &= ~HOST_IRQ_EN;
696 writel(ctl, mmio + HOST_CTL);
697 readl(mmio + HOST_CTL); /* flush */
698 }
699
700 return ata_pci_device_suspend(pdev, mesg);
701 }
702
703 static int ahci_pci_device_resume(struct pci_dev *pdev)
704 {
705 struct ata_host *host = pci_get_drvdata(pdev);
706 int rc;
707
708 rc = ata_pci_device_do_resume(pdev);
709 if (rc)
710 return rc;
711
712 /* Apple BIOS helpfully mangles the registers on resume */
713 if (is_mcp89_apple(pdev))
714 ahci_mcp89_apple_enable(pdev);
715
716 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
717 rc = ahci_pci_reset_controller(host);
718 if (rc)
719 return rc;
720
721 ahci_pci_init_controller(host);
722 }
723
724 ata_host_resume(host);
725
726 return 0;
727 }
728 #endif
729
730 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
731 {
732 int rc;
733
734 /*
735 * If the device fixup already set the dma_mask to some non-standard
736 * value, don't extend it here. This happens on STA2X11, for example.
737 */
738 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
739 return 0;
740
741 if (using_dac &&
742 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
743 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
744 if (rc) {
745 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
746 if (rc) {
747 dev_err(&pdev->dev,
748 "64-bit DMA enable failed\n");
749 return rc;
750 }
751 }
752 } else {
753 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
754 if (rc) {
755 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
756 return rc;
757 }
758 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
759 if (rc) {
760 dev_err(&pdev->dev,
761 "32-bit consistent DMA enable failed\n");
762 return rc;
763 }
764 }
765 return 0;
766 }
767
768 static void ahci_pci_print_info(struct ata_host *host)
769 {
770 struct pci_dev *pdev = to_pci_dev(host->dev);
771 u16 cc;
772 const char *scc_s;
773
774 pci_read_config_word(pdev, 0x0a, &cc);
775 if (cc == PCI_CLASS_STORAGE_IDE)
776 scc_s = "IDE";
777 else if (cc == PCI_CLASS_STORAGE_SATA)
778 scc_s = "SATA";
779 else if (cc == PCI_CLASS_STORAGE_RAID)
780 scc_s = "RAID";
781 else
782 scc_s = "unknown";
783
784 ahci_print_info(host, scc_s);
785 }
786
787 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
788 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
789 * support PMP and the 4726 either directly exports the device
790 * attached to the first downstream port or acts as a hardware storage
791 * controller and emulate a single ATA device (can be RAID 0/1 or some
792 * other configuration).
793 *
794 * When there's no device attached to the first downstream port of the
795 * 4726, "Config Disk" appears, which is a pseudo ATA device to
796 * configure the 4726. However, ATA emulation of the device is very
797 * lame. It doesn't send signature D2H Reg FIS after the initial
798 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
799 *
800 * The following function works around the problem by always using
801 * hardreset on the port and not depending on receiving signature FIS
802 * afterward. If signature FIS isn't received soon, ATA class is
803 * assumed without follow-up softreset.
804 */
805 static void ahci_p5wdh_workaround(struct ata_host *host)
806 {
807 static const struct dmi_system_id sysids[] = {
808 {
809 .ident = "P5W DH Deluxe",
810 .matches = {
811 DMI_MATCH(DMI_SYS_VENDOR,
812 "ASUSTEK COMPUTER INC"),
813 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
814 },
815 },
816 { }
817 };
818 struct pci_dev *pdev = to_pci_dev(host->dev);
819
820 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
821 dmi_check_system(sysids)) {
822 struct ata_port *ap = host->ports[1];
823
824 dev_info(&pdev->dev,
825 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
826
827 ap->ops = &ahci_p5wdh_ops;
828 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
829 }
830 }
831
832 /*
833 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
834 * booting in BIOS compatibility mode. We restore the registers but not ID.
835 */
836 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
837 {
838 u32 val;
839
840 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
841
842 pci_read_config_dword(pdev, 0xf8, &val);
843 val |= 1 << 0x1b;
844 /* the following changes the device ID, but appears not to affect function */
845 /* val = (val & ~0xf0000000) | 0x80000000; */
846 pci_write_config_dword(pdev, 0xf8, val);
847
848 pci_read_config_dword(pdev, 0x54c, &val);
849 val |= 1 << 0xc;
850 pci_write_config_dword(pdev, 0x54c, val);
851
852 pci_read_config_dword(pdev, 0x4a4, &val);
853 val &= 0xff;
854 val |= 0x01060100;
855 pci_write_config_dword(pdev, 0x4a4, val);
856
857 pci_read_config_dword(pdev, 0x54c, &val);
858 val &= ~(1 << 0xc);
859 pci_write_config_dword(pdev, 0x54c, val);
860
861 pci_read_config_dword(pdev, 0xf8, &val);
862 val &= ~(1 << 0x1b);
863 pci_write_config_dword(pdev, 0xf8, val);
864 }
865
866 static bool is_mcp89_apple(struct pci_dev *pdev)
867 {
868 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
869 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
870 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
871 pdev->subsystem_device == 0xcb89;
872 }
873
874 /* only some SB600 ahci controllers can do 64bit DMA */
875 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
876 {
877 static const struct dmi_system_id sysids[] = {
878 /*
879 * The oldest version known to be broken is 0901 and
880 * working is 1501 which was released on 2007-10-26.
881 * Enable 64bit DMA on 1501 and anything newer.
882 *
883 * Please read bko#9412 for more info.
884 */
885 {
886 .ident = "ASUS M2A-VM",
887 .matches = {
888 DMI_MATCH(DMI_BOARD_VENDOR,
889 "ASUSTeK Computer INC."),
890 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
891 },
892 .driver_data = "20071026", /* yyyymmdd */
893 },
894 /*
895 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
896 * support 64bit DMA.
897 *
898 * BIOS versions earlier than 1.5 had the Manufacturer DMI
899 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
900 * This spelling mistake was fixed in BIOS version 1.5, so
901 * 1.5 and later have the Manufacturer as
902 * "MICRO-STAR INTERNATIONAL CO.,LTD".
903 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
904 *
905 * BIOS versions earlier than 1.9 had a Board Product Name
906 * DMI field of "MS-7376". This was changed to be
907 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
908 * match on DMI_BOARD_NAME of "MS-7376".
909 */
910 {
911 .ident = "MSI K9A2 Platinum",
912 .matches = {
913 DMI_MATCH(DMI_BOARD_VENDOR,
914 "MICRO-STAR INTER"),
915 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
916 },
917 },
918 /*
919 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
920 * 64bit DMA.
921 *
922 * This board also had the typo mentioned above in the
923 * Manufacturer DMI field (fixed in BIOS version 1.5), so
924 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
925 */
926 {
927 .ident = "MSI K9AGM2",
928 .matches = {
929 DMI_MATCH(DMI_BOARD_VENDOR,
930 "MICRO-STAR INTER"),
931 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
932 },
933 },
934 /*
935 * All BIOS versions for the Asus M3A support 64bit DMA.
936 * (all release versions from 0301 to 1206 were tested)
937 */
938 {
939 .ident = "ASUS M3A",
940 .matches = {
941 DMI_MATCH(DMI_BOARD_VENDOR,
942 "ASUSTeK Computer INC."),
943 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
944 },
945 },
946 { }
947 };
948 const struct dmi_system_id *match;
949 int year, month, date;
950 char buf[9];
951
952 match = dmi_first_match(sysids);
953 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
954 !match)
955 return false;
956
957 if (!match->driver_data)
958 goto enable_64bit;
959
960 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
961 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
962
963 if (strcmp(buf, match->driver_data) >= 0)
964 goto enable_64bit;
965 else {
966 dev_warn(&pdev->dev,
967 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
968 match->ident);
969 return false;
970 }
971
972 enable_64bit:
973 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
974 return true;
975 }
976
977 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
978 {
979 static const struct dmi_system_id broken_systems[] = {
980 {
981 .ident = "HP Compaq nx6310",
982 .matches = {
983 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
984 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
985 },
986 /* PCI slot number of the controller */
987 .driver_data = (void *)0x1FUL,
988 },
989 {
990 .ident = "HP Compaq 6720s",
991 .matches = {
992 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
993 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
994 },
995 /* PCI slot number of the controller */
996 .driver_data = (void *)0x1FUL,
997 },
998
999 { } /* terminate list */
1000 };
1001 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1002
1003 if (dmi) {
1004 unsigned long slot = (unsigned long)dmi->driver_data;
1005 /* apply the quirk only to on-board controllers */
1006 return slot == PCI_SLOT(pdev->devfn);
1007 }
1008
1009 return false;
1010 }
1011
1012 static bool ahci_broken_suspend(struct pci_dev *pdev)
1013 {
1014 static const struct dmi_system_id sysids[] = {
1015 /*
1016 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1017 * to the harddisk doesn't become online after
1018 * resuming from STR. Warn and fail suspend.
1019 *
1020 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1021 *
1022 * Use dates instead of versions to match as HP is
1023 * apparently recycling both product and version
1024 * strings.
1025 *
1026 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1027 */
1028 {
1029 .ident = "dv4",
1030 .matches = {
1031 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1032 DMI_MATCH(DMI_PRODUCT_NAME,
1033 "HP Pavilion dv4 Notebook PC"),
1034 },
1035 .driver_data = "20090105", /* F.30 */
1036 },
1037 {
1038 .ident = "dv5",
1039 .matches = {
1040 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1041 DMI_MATCH(DMI_PRODUCT_NAME,
1042 "HP Pavilion dv5 Notebook PC"),
1043 },
1044 .driver_data = "20090506", /* F.16 */
1045 },
1046 {
1047 .ident = "dv6",
1048 .matches = {
1049 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1050 DMI_MATCH(DMI_PRODUCT_NAME,
1051 "HP Pavilion dv6 Notebook PC"),
1052 },
1053 .driver_data = "20090423", /* F.21 */
1054 },
1055 {
1056 .ident = "HDX18",
1057 .matches = {
1058 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1059 DMI_MATCH(DMI_PRODUCT_NAME,
1060 "HP HDX18 Notebook PC"),
1061 },
1062 .driver_data = "20090430", /* F.23 */
1063 },
1064 /*
1065 * Acer eMachines G725 has the same problem. BIOS
1066 * V1.03 is known to be broken. V3.04 is known to
1067 * work. Between, there are V1.06, V2.06 and V3.03
1068 * that we don't have much idea about. For now,
1069 * blacklist anything older than V3.04.
1070 *
1071 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1072 */
1073 {
1074 .ident = "G725",
1075 .matches = {
1076 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1077 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1078 },
1079 .driver_data = "20091216", /* V3.04 */
1080 },
1081 { } /* terminate list */
1082 };
1083 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1084 int year, month, date;
1085 char buf[9];
1086
1087 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1088 return false;
1089
1090 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1091 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1092
1093 return strcmp(buf, dmi->driver_data) < 0;
1094 }
1095
1096 static bool ahci_broken_online(struct pci_dev *pdev)
1097 {
1098 #define ENCODE_BUSDEVFN(bus, slot, func) \
1099 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1100 static const struct dmi_system_id sysids[] = {
1101 /*
1102 * There are several gigabyte boards which use
1103 * SIMG5723s configured as hardware RAID. Certain
1104 * 5723 firmware revisions shipped there keep the link
1105 * online but fail to answer properly to SRST or
1106 * IDENTIFY when no device is attached downstream
1107 * causing libata to retry quite a few times leading
1108 * to excessive detection delay.
1109 *
1110 * As these firmwares respond to the second reset try
1111 * with invalid device signature, considering unknown
1112 * sig as offline works around the problem acceptably.
1113 */
1114 {
1115 .ident = "EP45-DQ6",
1116 .matches = {
1117 DMI_MATCH(DMI_BOARD_VENDOR,
1118 "Gigabyte Technology Co., Ltd."),
1119 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1120 },
1121 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1122 },
1123 {
1124 .ident = "EP45-DS5",
1125 .matches = {
1126 DMI_MATCH(DMI_BOARD_VENDOR,
1127 "Gigabyte Technology Co., Ltd."),
1128 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1129 },
1130 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1131 },
1132 { } /* terminate list */
1133 };
1134 #undef ENCODE_BUSDEVFN
1135 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1136 unsigned int val;
1137
1138 if (!dmi)
1139 return false;
1140
1141 val = (unsigned long)dmi->driver_data;
1142
1143 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1144 }
1145
1146 static bool ahci_broken_devslp(struct pci_dev *pdev)
1147 {
1148 /* device with broken DEVSLP but still showing SDS capability */
1149 static const struct pci_device_id ids[] = {
1150 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1151 {}
1152 };
1153
1154 return pci_match_id(ids, pdev);
1155 }
1156
1157 #ifdef CONFIG_ATA_ACPI
1158 static void ahci_gtf_filter_workaround(struct ata_host *host)
1159 {
1160 static const struct dmi_system_id sysids[] = {
1161 /*
1162 * Aspire 3810T issues a bunch of SATA enable commands
1163 * via _GTF including an invalid one and one which is
1164 * rejected by the device. Among the successful ones
1165 * is FPDMA non-zero offset enable which when enabled
1166 * only on the drive side leads to NCQ command
1167 * failures. Filter it out.
1168 */
1169 {
1170 .ident = "Aspire 3810T",
1171 .matches = {
1172 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1173 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1174 },
1175 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1176 },
1177 { }
1178 };
1179 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1180 unsigned int filter;
1181 int i;
1182
1183 if (!dmi)
1184 return;
1185
1186 filter = (unsigned long)dmi->driver_data;
1187 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1188 filter, dmi->ident);
1189
1190 for (i = 0; i < host->n_ports; i++) {
1191 struct ata_port *ap = host->ports[i];
1192 struct ata_link *link;
1193 struct ata_device *dev;
1194
1195 ata_for_each_link(link, ap, EDGE)
1196 ata_for_each_dev(dev, link, ALL)
1197 dev->gtf_filter |= filter;
1198 }
1199 }
1200 #else
1201 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1202 {}
1203 #endif
1204
1205 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1206 struct ahci_host_priv *hpriv)
1207 {
1208 int rc, nvec;
1209
1210 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1211 goto intx;
1212
1213 nvec = pci_msi_vec_count(pdev);
1214 if (nvec < 0)
1215 goto intx;
1216
1217 /*
1218 * If number of MSIs is less than number of ports then Sharing Last
1219 * Message mode could be enforced. In this case assume that advantage
1220 * of multipe MSIs is negated and use single MSI mode instead.
1221 */
1222 if (nvec < n_ports)
1223 goto single_msi;
1224
1225 rc = pci_enable_msi_exact(pdev, nvec);
1226 if (rc == -ENOSPC)
1227 goto single_msi;
1228 else if (rc < 0)
1229 goto intx;
1230
1231 /* fallback to single MSI mode if the controller enforced MRSM mode */
1232 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1233 pci_disable_msi(pdev);
1234 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1235 goto single_msi;
1236 }
1237
1238 if (nvec > 1)
1239 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1240
1241 return nvec;
1242
1243 single_msi:
1244 if (pci_enable_msi(pdev))
1245 goto intx;
1246 return 1;
1247
1248 intx:
1249 pci_intx(pdev, 1);
1250 return 0;
1251 }
1252
1253 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1254 {
1255 unsigned int board_id = ent->driver_data;
1256 struct ata_port_info pi = ahci_port_info[board_id];
1257 const struct ata_port_info *ppi[] = { &pi, NULL };
1258 struct device *dev = &pdev->dev;
1259 struct ahci_host_priv *hpriv;
1260 struct ata_host *host;
1261 int n_ports, i, rc;
1262 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1263
1264 VPRINTK("ENTER\n");
1265
1266 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1267
1268 ata_print_version_once(&pdev->dev, DRV_VERSION);
1269
1270 /* The AHCI driver can only drive the SATA ports, the PATA driver
1271 can drive them all so if both drivers are selected make sure
1272 AHCI stays out of the way */
1273 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1274 return -ENODEV;
1275
1276 /* Apple BIOS on MCP89 prevents us using AHCI */
1277 if (is_mcp89_apple(pdev))
1278 ahci_mcp89_apple_enable(pdev);
1279
1280 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1281 * At the moment, we can only use the AHCI mode. Let the users know
1282 * that for SAS drives they're out of luck.
1283 */
1284 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1285 dev_info(&pdev->dev,
1286 "PDC42819 can only drive SATA devices with this driver\n");
1287
1288 /* Both Connext and Enmotus devices use non-standard BARs */
1289 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1290 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1291 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1292 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1293
1294 /*
1295 * The JMicron chip 361/363 contains one SATA controller and one
1296 * PATA controller,for powering on these both controllers, we must
1297 * follow the sequence one by one, otherwise one of them can not be
1298 * powered on successfully, so here we disable the async suspend
1299 * method for these chips.
1300 */
1301 if (pdev->vendor == PCI_VENDOR_ID_JMICRON &&
1302 (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 ||
1303 pdev->device == PCI_DEVICE_ID_JMICRON_JMB361))
1304 device_disable_async_suspend(&pdev->dev);
1305
1306 /* acquire resources */
1307 rc = pcim_enable_device(pdev);
1308 if (rc)
1309 return rc;
1310
1311 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1312 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1313 u8 map;
1314
1315 /* ICH6s share the same PCI ID for both piix and ahci
1316 * modes. Enabling ahci mode while MAP indicates
1317 * combined mode is a bad idea. Yield to ata_piix.
1318 */
1319 pci_read_config_byte(pdev, ICH_MAP, &map);
1320 if (map & 0x3) {
1321 dev_info(&pdev->dev,
1322 "controller is in combined mode, can't enable AHCI mode\n");
1323 return -ENODEV;
1324 }
1325 }
1326
1327 /* AHCI controllers often implement SFF compatible interface.
1328 * Grab all PCI BARs just in case.
1329 */
1330 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1331 if (rc == -EBUSY)
1332 pcim_pin_device(pdev);
1333 if (rc)
1334 return rc;
1335
1336 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1337 if (!hpriv)
1338 return -ENOMEM;
1339 hpriv->flags |= (unsigned long)pi.private_data;
1340
1341 /* MCP65 revision A1 and A2 can't do MSI */
1342 if (board_id == board_ahci_mcp65 &&
1343 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1344 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1345
1346 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1347 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1348 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1349
1350 /* only some SB600s can do 64bit DMA */
1351 if (ahci_sb600_enable_64bit(pdev))
1352 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1353
1354 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1355
1356 /* must set flag prior to save config in order to take effect */
1357 if (ahci_broken_devslp(pdev))
1358 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1359
1360 /* save initial config */
1361 ahci_pci_save_initial_config(pdev, hpriv);
1362
1363 /* prepare host */
1364 if (hpriv->cap & HOST_CAP_NCQ) {
1365 pi.flags |= ATA_FLAG_NCQ;
1366 /*
1367 * Auto-activate optimization is supposed to be
1368 * supported on all AHCI controllers indicating NCQ
1369 * capability, but it seems to be broken on some
1370 * chipsets including NVIDIAs.
1371 */
1372 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1373 pi.flags |= ATA_FLAG_FPDMA_AA;
1374
1375 /*
1376 * All AHCI controllers should be forward-compatible
1377 * with the new auxiliary field. This code should be
1378 * conditionalized if any buggy AHCI controllers are
1379 * encountered.
1380 */
1381 pi.flags |= ATA_FLAG_FPDMA_AUX;
1382 }
1383
1384 if (hpriv->cap & HOST_CAP_PMP)
1385 pi.flags |= ATA_FLAG_PMP;
1386
1387 ahci_set_em_messages(hpriv, &pi);
1388
1389 if (ahci_broken_system_poweroff(pdev)) {
1390 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1391 dev_info(&pdev->dev,
1392 "quirky BIOS, skipping spindown on poweroff\n");
1393 }
1394
1395 if (ahci_broken_suspend(pdev)) {
1396 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1397 dev_warn(&pdev->dev,
1398 "BIOS update required for suspend/resume\n");
1399 }
1400
1401 if (ahci_broken_online(pdev)) {
1402 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1403 dev_info(&pdev->dev,
1404 "online status unreliable, applying workaround\n");
1405 }
1406
1407 /* CAP.NP sometimes indicate the index of the last enabled
1408 * port, at other times, that of the last possible port, so
1409 * determining the maximum port number requires looking at
1410 * both CAP.NP and port_map.
1411 */
1412 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1413
1414 ahci_init_interrupts(pdev, n_ports, hpriv);
1415
1416 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1417 if (!host)
1418 return -ENOMEM;
1419 host->private_data = hpriv;
1420
1421 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1422 host->flags |= ATA_HOST_PARALLEL_SCAN;
1423 else
1424 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1425
1426 if (pi.flags & ATA_FLAG_EM)
1427 ahci_reset_em(host);
1428
1429 for (i = 0; i < host->n_ports; i++) {
1430 struct ata_port *ap = host->ports[i];
1431
1432 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1433 ata_port_pbar_desc(ap, ahci_pci_bar,
1434 0x100 + ap->port_no * 0x80, "port");
1435
1436 /* set enclosure management message type */
1437 if (ap->flags & ATA_FLAG_EM)
1438 ap->em_message_type = hpriv->em_msg_type;
1439
1440
1441 /* disabled/not-implemented port */
1442 if (!(hpriv->port_map & (1 << i)))
1443 ap->ops = &ata_dummy_port_ops;
1444 }
1445
1446 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1447 ahci_p5wdh_workaround(host);
1448
1449 /* apply gtf filter quirk */
1450 ahci_gtf_filter_workaround(host);
1451
1452 /* initialize adapter */
1453 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1454 if (rc)
1455 return rc;
1456
1457 rc = ahci_pci_reset_controller(host);
1458 if (rc)
1459 return rc;
1460
1461 ahci_pci_init_controller(host);
1462 ahci_pci_print_info(host);
1463
1464 pci_set_master(pdev);
1465
1466 return ahci_host_activate(host, pdev->irq, &ahci_sht);
1467 }
1468
1469 module_pci_driver(ahci_pci_driver);
1470
1471 MODULE_AUTHOR("Jeff Garzik");
1472 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1473 MODULE_LICENSE("GPL");
1474 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1475 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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