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iommu/exynos: Fix checkpatch warning
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include "ahci.h"
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "3.0"
52
53 enum {
54 AHCI_PCI_BAR_STA2X11 = 0,
55 AHCI_PCI_BAR_ENMOTUS = 2,
56 AHCI_PCI_BAR_STANDARD = 5,
57 };
58
59 enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_noncq,
64 board_ahci_nosntf,
65 board_ahci_yes_fbs,
66
67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
69 board_ahci_mcp77,
70 board_ahci_mcp89,
71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
81 };
82
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
87 static bool is_mcp89_apple(struct pci_dev *pdev);
88 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 #ifdef CONFIG_PM
91 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92 static int ahci_pci_device_resume(struct pci_dev *pdev);
93 #endif
94
95 static struct scsi_host_template ahci_sht = {
96 AHCI_SHT("ahci"),
97 };
98
99 static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
101 .hardreset = ahci_vt8251_hardreset,
102 };
103
104 static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
106 .hardreset = ahci_p5wdh_hardreset,
107 };
108
109 static const struct ata_port_info ahci_port_info[] = {
110 /* by features */
111 [board_ahci] = {
112 .flags = AHCI_FLAG_COMMON,
113 .pio_mask = ATA_PIO4,
114 .udma_mask = ATA_UDMA6,
115 .port_ops = &ahci_ops,
116 },
117 [board_ahci_ign_iferr] = {
118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
123 },
124 [board_ahci_noncq] = {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
131 [board_ahci_nosntf] = {
132 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
137 },
138 [board_ahci_yes_fbs] = {
139 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
145 /* by chipsets */
146 [board_ahci_mcp65] = {
147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
148 AHCI_HFLAG_YES_NCQ),
149 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
154 [board_ahci_mcp77] = {
155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
161 [board_ahci_mcp89] = {
162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
167 },
168 [board_ahci_mv] = {
169 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
170 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
171 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
176 [board_ahci_sb600] = {
177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_pmp_retry_srst_ops,
184 },
185 [board_ahci_sb700] = { /* for SB700 and SB800 */
186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_pmp_retry_srst_ops,
191 },
192 [board_ahci_vt8251] = {
193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
197 .port_ops = &ahci_vt8251_ops,
198 },
199 };
200
201 static const struct pci_device_id ahci_pci_tbl[] = {
202 /* Intel */
203 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
204 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
205 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
206 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
207 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
208 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
209 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
213 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
214 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
217 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
231 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
232 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
233 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
234 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
235 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
237 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
238 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
239 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
240 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
241 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
243 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
250 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
251 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
254 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
257 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
264 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
270 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
271 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
272 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
277 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
295 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
296 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
297 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
300 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
304 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
305 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
308
309 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
310 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
311 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
312 /* JMicron 362B and 362C have an AHCI function with IDE class code */
313 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
314 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
315
316 /* ATI */
317 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
318 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
319 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
320 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
321 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
322 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
323 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
324
325 /* AMD */
326 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
327 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
328 /* AMD is using RAID class only for ahci controllers */
329 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
330 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
331
332 /* VIA */
333 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
334 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
335
336 /* NVIDIA */
337 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
338 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
340 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
341 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
342 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
343 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
344 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
345 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
352 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
380 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
404 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
416 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
421
422 /* SiS */
423 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
424 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
425 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
426
427 /* ST Microelectronics */
428 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
429
430 /* Marvell */
431 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
432 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
433 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
434 .class = PCI_CLASS_STORAGE_SATA_AHCI,
435 .class_mask = 0xffffff,
436 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
437 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
438 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
439 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
440 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
441 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
442 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
443 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
444 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
445 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
446 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
447 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
448 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
449 .driver_data = board_ahci_yes_fbs },
450 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
451 .driver_data = board_ahci_yes_fbs },
452
453 /* Promise */
454 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
455
456 /* Asmedia */
457 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
458 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
459 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
460 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
461
462 /*
463 * Samsung SSDs found on some macbooks. NCQ times out.
464 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
465 */
466 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
467
468 /* Enmotus */
469 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
470
471 /* Generic, PCI class code for AHCI */
472 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
473 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
474
475 { } /* terminate list */
476 };
477
478
479 static struct pci_driver ahci_pci_driver = {
480 .name = DRV_NAME,
481 .id_table = ahci_pci_tbl,
482 .probe = ahci_init_one,
483 .remove = ata_pci_remove_one,
484 #ifdef CONFIG_PM
485 .suspend = ahci_pci_device_suspend,
486 .resume = ahci_pci_device_resume,
487 #endif
488 };
489
490 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
491 static int marvell_enable;
492 #else
493 static int marvell_enable = 1;
494 #endif
495 module_param(marvell_enable, int, 0644);
496 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
497
498
499 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
500 struct ahci_host_priv *hpriv)
501 {
502 unsigned int force_port_map = 0;
503 unsigned int mask_port_map = 0;
504
505 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
506 dev_info(&pdev->dev, "JMB361 has only one port\n");
507 force_port_map = 1;
508 }
509
510 /*
511 * Temporary Marvell 6145 hack: PATA port presence
512 * is asserted through the standard AHCI port
513 * presence register, as bit 4 (counting from 0)
514 */
515 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
516 if (pdev->device == 0x6121)
517 mask_port_map = 0x3;
518 else
519 mask_port_map = 0xf;
520 dev_info(&pdev->dev,
521 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
522 }
523
524 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
525 mask_port_map);
526 }
527
528 static int ahci_pci_reset_controller(struct ata_host *host)
529 {
530 struct pci_dev *pdev = to_pci_dev(host->dev);
531
532 ahci_reset_controller(host);
533
534 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
535 struct ahci_host_priv *hpriv = host->private_data;
536 u16 tmp16;
537
538 /* configure PCS */
539 pci_read_config_word(pdev, 0x92, &tmp16);
540 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
541 tmp16 |= hpriv->port_map;
542 pci_write_config_word(pdev, 0x92, tmp16);
543 }
544 }
545
546 return 0;
547 }
548
549 static void ahci_pci_init_controller(struct ata_host *host)
550 {
551 struct ahci_host_priv *hpriv = host->private_data;
552 struct pci_dev *pdev = to_pci_dev(host->dev);
553 void __iomem *port_mmio;
554 u32 tmp;
555 int mv;
556
557 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
558 if (pdev->device == 0x6121)
559 mv = 2;
560 else
561 mv = 4;
562 port_mmio = __ahci_port_base(host, mv);
563
564 writel(0, port_mmio + PORT_IRQ_MASK);
565
566 /* clear port IRQ */
567 tmp = readl(port_mmio + PORT_IRQ_STAT);
568 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
569 if (tmp)
570 writel(tmp, port_mmio + PORT_IRQ_STAT);
571 }
572
573 ahci_init_controller(host);
574 }
575
576 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
577 unsigned long deadline)
578 {
579 struct ata_port *ap = link->ap;
580 struct ahci_host_priv *hpriv = ap->host->private_data;
581 bool online;
582 int rc;
583
584 DPRINTK("ENTER\n");
585
586 ahci_stop_engine(ap);
587
588 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
589 deadline, &online, NULL);
590
591 hpriv->start_engine(ap);
592
593 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
594
595 /* vt8251 doesn't clear BSY on signature FIS reception,
596 * request follow-up softreset.
597 */
598 return online ? -EAGAIN : rc;
599 }
600
601 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
602 unsigned long deadline)
603 {
604 struct ata_port *ap = link->ap;
605 struct ahci_port_priv *pp = ap->private_data;
606 struct ahci_host_priv *hpriv = ap->host->private_data;
607 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
608 struct ata_taskfile tf;
609 bool online;
610 int rc;
611
612 ahci_stop_engine(ap);
613
614 /* clear D2H reception area to properly wait for D2H FIS */
615 ata_tf_init(link->device, &tf);
616 tf.command = ATA_BUSY;
617 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
618
619 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
620 deadline, &online, NULL);
621
622 hpriv->start_engine(ap);
623
624 /* The pseudo configuration device on SIMG4726 attached to
625 * ASUS P5W-DH Deluxe doesn't send signature FIS after
626 * hardreset if no device is attached to the first downstream
627 * port && the pseudo device locks up on SRST w/ PMP==0. To
628 * work around this, wait for !BSY only briefly. If BSY isn't
629 * cleared, perform CLO and proceed to IDENTIFY (achieved by
630 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
631 *
632 * Wait for two seconds. Devices attached to downstream port
633 * which can't process the following IDENTIFY after this will
634 * have to be reset again. For most cases, this should
635 * suffice while making probing snappish enough.
636 */
637 if (online) {
638 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
639 ahci_check_ready);
640 if (rc)
641 ahci_kick_engine(ap);
642 }
643 return rc;
644 }
645
646 #ifdef CONFIG_PM
647 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
648 {
649 struct ata_host *host = pci_get_drvdata(pdev);
650 struct ahci_host_priv *hpriv = host->private_data;
651 void __iomem *mmio = hpriv->mmio;
652 u32 ctl;
653
654 if (mesg.event & PM_EVENT_SUSPEND &&
655 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
656 dev_err(&pdev->dev,
657 "BIOS update required for suspend/resume\n");
658 return -EIO;
659 }
660
661 if (mesg.event & PM_EVENT_SLEEP) {
662 /* AHCI spec rev1.1 section 8.3.3:
663 * Software must disable interrupts prior to requesting a
664 * transition of the HBA to D3 state.
665 */
666 ctl = readl(mmio + HOST_CTL);
667 ctl &= ~HOST_IRQ_EN;
668 writel(ctl, mmio + HOST_CTL);
669 readl(mmio + HOST_CTL); /* flush */
670 }
671
672 return ata_pci_device_suspend(pdev, mesg);
673 }
674
675 static int ahci_pci_device_resume(struct pci_dev *pdev)
676 {
677 struct ata_host *host = pci_get_drvdata(pdev);
678 int rc;
679
680 rc = ata_pci_device_do_resume(pdev);
681 if (rc)
682 return rc;
683
684 /* Apple BIOS helpfully mangles the registers on resume */
685 if (is_mcp89_apple(pdev))
686 ahci_mcp89_apple_enable(pdev);
687
688 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
689 rc = ahci_pci_reset_controller(host);
690 if (rc)
691 return rc;
692
693 ahci_pci_init_controller(host);
694 }
695
696 ata_host_resume(host);
697
698 return 0;
699 }
700 #endif
701
702 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
703 {
704 int rc;
705
706 /*
707 * If the device fixup already set the dma_mask to some non-standard
708 * value, don't extend it here. This happens on STA2X11, for example.
709 */
710 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
711 return 0;
712
713 if (using_dac &&
714 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
715 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
716 if (rc) {
717 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
718 if (rc) {
719 dev_err(&pdev->dev,
720 "64-bit DMA enable failed\n");
721 return rc;
722 }
723 }
724 } else {
725 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
726 if (rc) {
727 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
728 return rc;
729 }
730 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
731 if (rc) {
732 dev_err(&pdev->dev,
733 "32-bit consistent DMA enable failed\n");
734 return rc;
735 }
736 }
737 return 0;
738 }
739
740 static void ahci_pci_print_info(struct ata_host *host)
741 {
742 struct pci_dev *pdev = to_pci_dev(host->dev);
743 u16 cc;
744 const char *scc_s;
745
746 pci_read_config_word(pdev, 0x0a, &cc);
747 if (cc == PCI_CLASS_STORAGE_IDE)
748 scc_s = "IDE";
749 else if (cc == PCI_CLASS_STORAGE_SATA)
750 scc_s = "SATA";
751 else if (cc == PCI_CLASS_STORAGE_RAID)
752 scc_s = "RAID";
753 else
754 scc_s = "unknown";
755
756 ahci_print_info(host, scc_s);
757 }
758
759 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
760 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
761 * support PMP and the 4726 either directly exports the device
762 * attached to the first downstream port or acts as a hardware storage
763 * controller and emulate a single ATA device (can be RAID 0/1 or some
764 * other configuration).
765 *
766 * When there's no device attached to the first downstream port of the
767 * 4726, "Config Disk" appears, which is a pseudo ATA device to
768 * configure the 4726. However, ATA emulation of the device is very
769 * lame. It doesn't send signature D2H Reg FIS after the initial
770 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
771 *
772 * The following function works around the problem by always using
773 * hardreset on the port and not depending on receiving signature FIS
774 * afterward. If signature FIS isn't received soon, ATA class is
775 * assumed without follow-up softreset.
776 */
777 static void ahci_p5wdh_workaround(struct ata_host *host)
778 {
779 static struct dmi_system_id sysids[] = {
780 {
781 .ident = "P5W DH Deluxe",
782 .matches = {
783 DMI_MATCH(DMI_SYS_VENDOR,
784 "ASUSTEK COMPUTER INC"),
785 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
786 },
787 },
788 { }
789 };
790 struct pci_dev *pdev = to_pci_dev(host->dev);
791
792 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
793 dmi_check_system(sysids)) {
794 struct ata_port *ap = host->ports[1];
795
796 dev_info(&pdev->dev,
797 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
798
799 ap->ops = &ahci_p5wdh_ops;
800 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
801 }
802 }
803
804 /*
805 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
806 * booting in BIOS compatibility mode. We restore the registers but not ID.
807 */
808 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
809 {
810 u32 val;
811
812 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
813
814 pci_read_config_dword(pdev, 0xf8, &val);
815 val |= 1 << 0x1b;
816 /* the following changes the device ID, but appears not to affect function */
817 /* val = (val & ~0xf0000000) | 0x80000000; */
818 pci_write_config_dword(pdev, 0xf8, val);
819
820 pci_read_config_dword(pdev, 0x54c, &val);
821 val |= 1 << 0xc;
822 pci_write_config_dword(pdev, 0x54c, val);
823
824 pci_read_config_dword(pdev, 0x4a4, &val);
825 val &= 0xff;
826 val |= 0x01060100;
827 pci_write_config_dword(pdev, 0x4a4, val);
828
829 pci_read_config_dword(pdev, 0x54c, &val);
830 val &= ~(1 << 0xc);
831 pci_write_config_dword(pdev, 0x54c, val);
832
833 pci_read_config_dword(pdev, 0xf8, &val);
834 val &= ~(1 << 0x1b);
835 pci_write_config_dword(pdev, 0xf8, val);
836 }
837
838 static bool is_mcp89_apple(struct pci_dev *pdev)
839 {
840 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
841 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
842 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
843 pdev->subsystem_device == 0xcb89;
844 }
845
846 /* only some SB600 ahci controllers can do 64bit DMA */
847 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
848 {
849 static const struct dmi_system_id sysids[] = {
850 /*
851 * The oldest version known to be broken is 0901 and
852 * working is 1501 which was released on 2007-10-26.
853 * Enable 64bit DMA on 1501 and anything newer.
854 *
855 * Please read bko#9412 for more info.
856 */
857 {
858 .ident = "ASUS M2A-VM",
859 .matches = {
860 DMI_MATCH(DMI_BOARD_VENDOR,
861 "ASUSTeK Computer INC."),
862 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
863 },
864 .driver_data = "20071026", /* yyyymmdd */
865 },
866 /*
867 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
868 * support 64bit DMA.
869 *
870 * BIOS versions earlier than 1.5 had the Manufacturer DMI
871 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
872 * This spelling mistake was fixed in BIOS version 1.5, so
873 * 1.5 and later have the Manufacturer as
874 * "MICRO-STAR INTERNATIONAL CO.,LTD".
875 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
876 *
877 * BIOS versions earlier than 1.9 had a Board Product Name
878 * DMI field of "MS-7376". This was changed to be
879 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
880 * match on DMI_BOARD_NAME of "MS-7376".
881 */
882 {
883 .ident = "MSI K9A2 Platinum",
884 .matches = {
885 DMI_MATCH(DMI_BOARD_VENDOR,
886 "MICRO-STAR INTER"),
887 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
888 },
889 },
890 /*
891 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
892 * 64bit DMA.
893 *
894 * This board also had the typo mentioned above in the
895 * Manufacturer DMI field (fixed in BIOS version 1.5), so
896 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
897 */
898 {
899 .ident = "MSI K9AGM2",
900 .matches = {
901 DMI_MATCH(DMI_BOARD_VENDOR,
902 "MICRO-STAR INTER"),
903 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
904 },
905 },
906 /*
907 * All BIOS versions for the Asus M3A support 64bit DMA.
908 * (all release versions from 0301 to 1206 were tested)
909 */
910 {
911 .ident = "ASUS M3A",
912 .matches = {
913 DMI_MATCH(DMI_BOARD_VENDOR,
914 "ASUSTeK Computer INC."),
915 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
916 },
917 },
918 { }
919 };
920 const struct dmi_system_id *match;
921 int year, month, date;
922 char buf[9];
923
924 match = dmi_first_match(sysids);
925 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
926 !match)
927 return false;
928
929 if (!match->driver_data)
930 goto enable_64bit;
931
932 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
933 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
934
935 if (strcmp(buf, match->driver_data) >= 0)
936 goto enable_64bit;
937 else {
938 dev_warn(&pdev->dev,
939 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
940 match->ident);
941 return false;
942 }
943
944 enable_64bit:
945 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
946 return true;
947 }
948
949 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
950 {
951 static const struct dmi_system_id broken_systems[] = {
952 {
953 .ident = "HP Compaq nx6310",
954 .matches = {
955 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
956 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
957 },
958 /* PCI slot number of the controller */
959 .driver_data = (void *)0x1FUL,
960 },
961 {
962 .ident = "HP Compaq 6720s",
963 .matches = {
964 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
965 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
966 },
967 /* PCI slot number of the controller */
968 .driver_data = (void *)0x1FUL,
969 },
970
971 { } /* terminate list */
972 };
973 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
974
975 if (dmi) {
976 unsigned long slot = (unsigned long)dmi->driver_data;
977 /* apply the quirk only to on-board controllers */
978 return slot == PCI_SLOT(pdev->devfn);
979 }
980
981 return false;
982 }
983
984 static bool ahci_broken_suspend(struct pci_dev *pdev)
985 {
986 static const struct dmi_system_id sysids[] = {
987 /*
988 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
989 * to the harddisk doesn't become online after
990 * resuming from STR. Warn and fail suspend.
991 *
992 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
993 *
994 * Use dates instead of versions to match as HP is
995 * apparently recycling both product and version
996 * strings.
997 *
998 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
999 */
1000 {
1001 .ident = "dv4",
1002 .matches = {
1003 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1004 DMI_MATCH(DMI_PRODUCT_NAME,
1005 "HP Pavilion dv4 Notebook PC"),
1006 },
1007 .driver_data = "20090105", /* F.30 */
1008 },
1009 {
1010 .ident = "dv5",
1011 .matches = {
1012 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1013 DMI_MATCH(DMI_PRODUCT_NAME,
1014 "HP Pavilion dv5 Notebook PC"),
1015 },
1016 .driver_data = "20090506", /* F.16 */
1017 },
1018 {
1019 .ident = "dv6",
1020 .matches = {
1021 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1022 DMI_MATCH(DMI_PRODUCT_NAME,
1023 "HP Pavilion dv6 Notebook PC"),
1024 },
1025 .driver_data = "20090423", /* F.21 */
1026 },
1027 {
1028 .ident = "HDX18",
1029 .matches = {
1030 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1031 DMI_MATCH(DMI_PRODUCT_NAME,
1032 "HP HDX18 Notebook PC"),
1033 },
1034 .driver_data = "20090430", /* F.23 */
1035 },
1036 /*
1037 * Acer eMachines G725 has the same problem. BIOS
1038 * V1.03 is known to be broken. V3.04 is known to
1039 * work. Between, there are V1.06, V2.06 and V3.03
1040 * that we don't have much idea about. For now,
1041 * blacklist anything older than V3.04.
1042 *
1043 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1044 */
1045 {
1046 .ident = "G725",
1047 .matches = {
1048 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1049 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1050 },
1051 .driver_data = "20091216", /* V3.04 */
1052 },
1053 { } /* terminate list */
1054 };
1055 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1056 int year, month, date;
1057 char buf[9];
1058
1059 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1060 return false;
1061
1062 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1063 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1064
1065 return strcmp(buf, dmi->driver_data) < 0;
1066 }
1067
1068 static bool ahci_broken_online(struct pci_dev *pdev)
1069 {
1070 #define ENCODE_BUSDEVFN(bus, slot, func) \
1071 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1072 static const struct dmi_system_id sysids[] = {
1073 /*
1074 * There are several gigabyte boards which use
1075 * SIMG5723s configured as hardware RAID. Certain
1076 * 5723 firmware revisions shipped there keep the link
1077 * online but fail to answer properly to SRST or
1078 * IDENTIFY when no device is attached downstream
1079 * causing libata to retry quite a few times leading
1080 * to excessive detection delay.
1081 *
1082 * As these firmwares respond to the second reset try
1083 * with invalid device signature, considering unknown
1084 * sig as offline works around the problem acceptably.
1085 */
1086 {
1087 .ident = "EP45-DQ6",
1088 .matches = {
1089 DMI_MATCH(DMI_BOARD_VENDOR,
1090 "Gigabyte Technology Co., Ltd."),
1091 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1092 },
1093 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1094 },
1095 {
1096 .ident = "EP45-DS5",
1097 .matches = {
1098 DMI_MATCH(DMI_BOARD_VENDOR,
1099 "Gigabyte Technology Co., Ltd."),
1100 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1101 },
1102 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1103 },
1104 { } /* terminate list */
1105 };
1106 #undef ENCODE_BUSDEVFN
1107 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1108 unsigned int val;
1109
1110 if (!dmi)
1111 return false;
1112
1113 val = (unsigned long)dmi->driver_data;
1114
1115 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1116 }
1117
1118 #ifdef CONFIG_ATA_ACPI
1119 static void ahci_gtf_filter_workaround(struct ata_host *host)
1120 {
1121 static const struct dmi_system_id sysids[] = {
1122 /*
1123 * Aspire 3810T issues a bunch of SATA enable commands
1124 * via _GTF including an invalid one and one which is
1125 * rejected by the device. Among the successful ones
1126 * is FPDMA non-zero offset enable which when enabled
1127 * only on the drive side leads to NCQ command
1128 * failures. Filter it out.
1129 */
1130 {
1131 .ident = "Aspire 3810T",
1132 .matches = {
1133 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1134 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1135 },
1136 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1137 },
1138 { }
1139 };
1140 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1141 unsigned int filter;
1142 int i;
1143
1144 if (!dmi)
1145 return;
1146
1147 filter = (unsigned long)dmi->driver_data;
1148 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1149 filter, dmi->ident);
1150
1151 for (i = 0; i < host->n_ports; i++) {
1152 struct ata_port *ap = host->ports[i];
1153 struct ata_link *link;
1154 struct ata_device *dev;
1155
1156 ata_for_each_link(link, ap, EDGE)
1157 ata_for_each_dev(dev, link, ALL)
1158 dev->gtf_filter |= filter;
1159 }
1160 }
1161 #else
1162 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1163 {}
1164 #endif
1165
1166 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1167 struct ahci_host_priv *hpriv)
1168 {
1169 int rc, nvec;
1170
1171 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1172 goto intx;
1173
1174 nvec = pci_msi_vec_count(pdev);
1175 if (nvec < 0)
1176 goto intx;
1177
1178 /*
1179 * If number of MSIs is less than number of ports then Sharing Last
1180 * Message mode could be enforced. In this case assume that advantage
1181 * of multipe MSIs is negated and use single MSI mode instead.
1182 */
1183 if (nvec < n_ports)
1184 goto single_msi;
1185
1186 rc = pci_enable_msi_exact(pdev, nvec);
1187 if (rc == -ENOSPC)
1188 goto single_msi;
1189 else if (rc < 0)
1190 goto intx;
1191
1192 /* fallback to single MSI mode if the controller enforced MRSM mode */
1193 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1194 pci_disable_msi(pdev);
1195 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1196 goto single_msi;
1197 }
1198
1199 return nvec;
1200
1201 single_msi:
1202 if (pci_enable_msi(pdev))
1203 goto intx;
1204 return 1;
1205
1206 intx:
1207 pci_intx(pdev, 1);
1208 return 0;
1209 }
1210
1211 /**
1212 * ahci_host_activate - start AHCI host, request IRQs and register it
1213 * @host: target ATA host
1214 * @irq: base IRQ number to request
1215 * @n_msis: number of MSIs allocated for this host
1216 * @irq_handler: irq_handler used when requesting IRQs
1217 * @irq_flags: irq_flags used when requesting IRQs
1218 *
1219 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1220 * when multiple MSIs were allocated. That is one MSI per port, starting
1221 * from @irq.
1222 *
1223 * LOCKING:
1224 * Inherited from calling layer (may sleep).
1225 *
1226 * RETURNS:
1227 * 0 on success, -errno otherwise.
1228 */
1229 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1230 {
1231 int i, rc;
1232
1233 /* Sharing Last Message among several ports is not supported */
1234 if (n_msis < host->n_ports)
1235 return -EINVAL;
1236
1237 rc = ata_host_start(host);
1238 if (rc)
1239 return rc;
1240
1241 for (i = 0; i < host->n_ports; i++) {
1242 struct ahci_port_priv *pp = host->ports[i]->private_data;
1243
1244 /* Do not receive interrupts sent by dummy ports */
1245 if (!pp) {
1246 disable_irq(irq + i);
1247 continue;
1248 }
1249
1250 rc = devm_request_threaded_irq(host->dev, irq + i,
1251 ahci_hw_interrupt,
1252 ahci_thread_fn, IRQF_SHARED,
1253 pp->irq_desc, host->ports[i]);
1254 if (rc)
1255 goto out_free_irqs;
1256 }
1257
1258 for (i = 0; i < host->n_ports; i++)
1259 ata_port_desc(host->ports[i], "irq %d", irq + i);
1260
1261 rc = ata_host_register(host, &ahci_sht);
1262 if (rc)
1263 goto out_free_all_irqs;
1264
1265 return 0;
1266
1267 out_free_all_irqs:
1268 i = host->n_ports;
1269 out_free_irqs:
1270 for (i--; i >= 0; i--)
1271 devm_free_irq(host->dev, irq + i, host->ports[i]);
1272
1273 return rc;
1274 }
1275
1276 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1277 {
1278 unsigned int board_id = ent->driver_data;
1279 struct ata_port_info pi = ahci_port_info[board_id];
1280 const struct ata_port_info *ppi[] = { &pi, NULL };
1281 struct device *dev = &pdev->dev;
1282 struct ahci_host_priv *hpriv;
1283 struct ata_host *host;
1284 int n_ports, n_msis, i, rc;
1285 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1286
1287 VPRINTK("ENTER\n");
1288
1289 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1290
1291 ata_print_version_once(&pdev->dev, DRV_VERSION);
1292
1293 /* The AHCI driver can only drive the SATA ports, the PATA driver
1294 can drive them all so if both drivers are selected make sure
1295 AHCI stays out of the way */
1296 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1297 return -ENODEV;
1298
1299 /* Apple BIOS on MCP89 prevents us using AHCI */
1300 if (is_mcp89_apple(pdev))
1301 ahci_mcp89_apple_enable(pdev);
1302
1303 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1304 * At the moment, we can only use the AHCI mode. Let the users know
1305 * that for SAS drives they're out of luck.
1306 */
1307 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1308 dev_info(&pdev->dev,
1309 "PDC42819 can only drive SATA devices with this driver\n");
1310
1311 /* Both Connext and Enmotus devices use non-standard BARs */
1312 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1313 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1314 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1315 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1316
1317 /* acquire resources */
1318 rc = pcim_enable_device(pdev);
1319 if (rc)
1320 return rc;
1321
1322 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1323 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1324 u8 map;
1325
1326 /* ICH6s share the same PCI ID for both piix and ahci
1327 * modes. Enabling ahci mode while MAP indicates
1328 * combined mode is a bad idea. Yield to ata_piix.
1329 */
1330 pci_read_config_byte(pdev, ICH_MAP, &map);
1331 if (map & 0x3) {
1332 dev_info(&pdev->dev,
1333 "controller is in combined mode, can't enable AHCI mode\n");
1334 return -ENODEV;
1335 }
1336 }
1337
1338 /* AHCI controllers often implement SFF compatible interface.
1339 * Grab all PCI BARs just in case.
1340 */
1341 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1342 if (rc == -EBUSY)
1343 pcim_pin_device(pdev);
1344 if (rc)
1345 return rc;
1346
1347 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1348 if (!hpriv)
1349 return -ENOMEM;
1350 hpriv->flags |= (unsigned long)pi.private_data;
1351
1352 /* MCP65 revision A1 and A2 can't do MSI */
1353 if (board_id == board_ahci_mcp65 &&
1354 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1355 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1356
1357 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1358 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1359 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1360
1361 /* only some SB600s can do 64bit DMA */
1362 if (ahci_sb600_enable_64bit(pdev))
1363 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1364
1365 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1366
1367 /* save initial config */
1368 ahci_pci_save_initial_config(pdev, hpriv);
1369
1370 /* prepare host */
1371 if (hpriv->cap & HOST_CAP_NCQ) {
1372 pi.flags |= ATA_FLAG_NCQ;
1373 /*
1374 * Auto-activate optimization is supposed to be
1375 * supported on all AHCI controllers indicating NCQ
1376 * capability, but it seems to be broken on some
1377 * chipsets including NVIDIAs.
1378 */
1379 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1380 pi.flags |= ATA_FLAG_FPDMA_AA;
1381
1382 /*
1383 * All AHCI controllers should be forward-compatible
1384 * with the new auxiliary field. This code should be
1385 * conditionalized if any buggy AHCI controllers are
1386 * encountered.
1387 */
1388 pi.flags |= ATA_FLAG_FPDMA_AUX;
1389 }
1390
1391 if (hpriv->cap & HOST_CAP_PMP)
1392 pi.flags |= ATA_FLAG_PMP;
1393
1394 ahci_set_em_messages(hpriv, &pi);
1395
1396 if (ahci_broken_system_poweroff(pdev)) {
1397 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1398 dev_info(&pdev->dev,
1399 "quirky BIOS, skipping spindown on poweroff\n");
1400 }
1401
1402 if (ahci_broken_suspend(pdev)) {
1403 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1404 dev_warn(&pdev->dev,
1405 "BIOS update required for suspend/resume\n");
1406 }
1407
1408 if (ahci_broken_online(pdev)) {
1409 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1410 dev_info(&pdev->dev,
1411 "online status unreliable, applying workaround\n");
1412 }
1413
1414 /* CAP.NP sometimes indicate the index of the last enabled
1415 * port, at other times, that of the last possible port, so
1416 * determining the maximum port number requires looking at
1417 * both CAP.NP and port_map.
1418 */
1419 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1420
1421 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1422 if (n_msis > 1)
1423 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1424
1425 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1426 if (!host)
1427 return -ENOMEM;
1428 host->private_data = hpriv;
1429
1430 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1431 host->flags |= ATA_HOST_PARALLEL_SCAN;
1432 else
1433 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1434
1435 if (pi.flags & ATA_FLAG_EM)
1436 ahci_reset_em(host);
1437
1438 for (i = 0; i < host->n_ports; i++) {
1439 struct ata_port *ap = host->ports[i];
1440
1441 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1442 ata_port_pbar_desc(ap, ahci_pci_bar,
1443 0x100 + ap->port_no * 0x80, "port");
1444
1445 /* set enclosure management message type */
1446 if (ap->flags & ATA_FLAG_EM)
1447 ap->em_message_type = hpriv->em_msg_type;
1448
1449
1450 /* disabled/not-implemented port */
1451 if (!(hpriv->port_map & (1 << i)))
1452 ap->ops = &ata_dummy_port_ops;
1453 }
1454
1455 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1456 ahci_p5wdh_workaround(host);
1457
1458 /* apply gtf filter quirk */
1459 ahci_gtf_filter_workaround(host);
1460
1461 /* initialize adapter */
1462 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1463 if (rc)
1464 return rc;
1465
1466 rc = ahci_pci_reset_controller(host);
1467 if (rc)
1468 return rc;
1469
1470 ahci_pci_init_controller(host);
1471 ahci_pci_print_info(host);
1472
1473 pci_set_master(pdev);
1474
1475 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1476 return ahci_host_activate(host, pdev->irq, n_msis);
1477
1478 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1479 &ahci_sht);
1480 }
1481
1482 module_pci_driver(ahci_pci_driver);
1483
1484 MODULE_AUTHOR("Jeff Garzik");
1485 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1486 MODULE_LICENSE("GPL");
1487 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1488 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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