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seccomp: Add SECCOMP_RET_TRAP
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_STANDARD = 5,
57 };
58
59 enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nosntf,
64 board_ahci_yes_fbs,
65
66 /* board IDs for specific chipsets in alphabetical order */
67 board_ahci_mcp65,
68 board_ahci_mcp77,
69 board_ahci_mcp89,
70 board_ahci_mv,
71 board_ahci_sb600,
72 board_ahci_sb700, /* for SB700 and SB800 */
73 board_ahci_vt8251,
74
75 /* aliases */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
79 board_ahci_mcp79 = board_ahci_mcp77,
80 };
81
82 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
83 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 #ifdef CONFIG_PM
88 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89 static int ahci_pci_device_resume(struct pci_dev *pdev);
90 #endif
91
92 static struct scsi_host_template ahci_sht = {
93 AHCI_SHT("ahci"),
94 };
95
96 static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
98 .hardreset = ahci_vt8251_hardreset,
99 };
100
101 static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
103 .hardreset = ahci_p5wdh_hardreset,
104 };
105
106 static const struct ata_port_info ahci_port_info[] = {
107 /* by features */
108 [board_ahci] =
109 {
110 .flags = AHCI_FLAG_COMMON,
111 .pio_mask = ATA_PIO4,
112 .udma_mask = ATA_UDMA6,
113 .port_ops = &ahci_ops,
114 },
115 [board_ahci_ign_iferr] =
116 {
117 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
118 .flags = AHCI_FLAG_COMMON,
119 .pio_mask = ATA_PIO4,
120 .udma_mask = ATA_UDMA6,
121 .port_ops = &ahci_ops,
122 },
123 [board_ahci_nosntf] =
124 {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
131 [board_ahci_yes_fbs] =
132 {
133 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
139 /* by chipsets */
140 [board_ahci_mcp65] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
143 AHCI_HFLAG_YES_NCQ),
144 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_mcp77] =
150 {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
152 .flags = AHCI_FLAG_COMMON,
153 .pio_mask = ATA_PIO4,
154 .udma_mask = ATA_UDMA6,
155 .port_ops = &ahci_ops,
156 },
157 [board_ahci_mcp89] =
158 {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
164 },
165 [board_ahci_mv] =
166 {
167 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
168 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
169 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_sb600] =
175 {
176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
177 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
178 AHCI_HFLAG_32BIT_ONLY),
179 .flags = AHCI_FLAG_COMMON,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_pmp_retry_srst_ops,
183 },
184 [board_ahci_sb700] = /* for SB700 and SB800 */
185 {
186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_pmp_retry_srst_ops,
191 },
192 [board_ahci_vt8251] =
193 {
194 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_vt8251_ops,
199 },
200 };
201
202 static const struct pci_device_id ahci_pci_tbl[] = {
203 /* Intel */
204 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
205 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
206 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
207 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
208 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
209 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
210 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
214 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
215 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
217 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
232 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
233 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
234 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
235 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
236 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
237 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
238 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
239 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
241 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
251 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
254 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
270
271 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
272 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
273 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
274
275 /* ATI */
276 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
277 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
278 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
280 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
283
284 /* AMD */
285 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
286 /* AMD is using RAID class only for ahci controllers */
287 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
288 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
289
290 /* VIA */
291 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
292 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
293
294 /* NVIDIA */
295 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
303 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
379
380 /* SiS */
381 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
382 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
383 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
384
385 /* ST Microelectronics */
386 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
387
388 /* Marvell */
389 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
390 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
391 { PCI_DEVICE(0x1b4b, 0x9123),
392 .class = PCI_CLASS_STORAGE_SATA_AHCI,
393 .class_mask = 0xffffff,
394 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
395 { PCI_DEVICE(0x1b4b, 0x9125),
396 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
397 { PCI_DEVICE(0x1b4b, 0x91a3),
398 .driver_data = board_ahci_yes_fbs },
399
400 /* Promise */
401 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
402
403 /* Asmedia */
404 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */
405
406 /* Generic, PCI class code for AHCI */
407 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
408 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
409
410 { } /* terminate list */
411 };
412
413
414 static struct pci_driver ahci_pci_driver = {
415 .name = DRV_NAME,
416 .id_table = ahci_pci_tbl,
417 .probe = ahci_init_one,
418 .remove = ata_pci_remove_one,
419 #ifdef CONFIG_PM
420 .suspend = ahci_pci_device_suspend,
421 .resume = ahci_pci_device_resume,
422 #endif
423 };
424
425 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
426 static int marvell_enable;
427 #else
428 static int marvell_enable = 1;
429 #endif
430 module_param(marvell_enable, int, 0644);
431 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
432
433
434 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
435 struct ahci_host_priv *hpriv)
436 {
437 unsigned int force_port_map = 0;
438 unsigned int mask_port_map = 0;
439
440 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
441 dev_info(&pdev->dev, "JMB361 has only one port\n");
442 force_port_map = 1;
443 }
444
445 /*
446 * Temporary Marvell 6145 hack: PATA port presence
447 * is asserted through the standard AHCI port
448 * presence register, as bit 4 (counting from 0)
449 */
450 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
451 if (pdev->device == 0x6121)
452 mask_port_map = 0x3;
453 else
454 mask_port_map = 0xf;
455 dev_info(&pdev->dev,
456 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
457 }
458
459 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
460 mask_port_map);
461 }
462
463 static int ahci_pci_reset_controller(struct ata_host *host)
464 {
465 struct pci_dev *pdev = to_pci_dev(host->dev);
466
467 ahci_reset_controller(host);
468
469 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
470 struct ahci_host_priv *hpriv = host->private_data;
471 u16 tmp16;
472
473 /* configure PCS */
474 pci_read_config_word(pdev, 0x92, &tmp16);
475 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
476 tmp16 |= hpriv->port_map;
477 pci_write_config_word(pdev, 0x92, tmp16);
478 }
479 }
480
481 return 0;
482 }
483
484 static void ahci_pci_init_controller(struct ata_host *host)
485 {
486 struct ahci_host_priv *hpriv = host->private_data;
487 struct pci_dev *pdev = to_pci_dev(host->dev);
488 void __iomem *port_mmio;
489 u32 tmp;
490 int mv;
491
492 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
493 if (pdev->device == 0x6121)
494 mv = 2;
495 else
496 mv = 4;
497 port_mmio = __ahci_port_base(host, mv);
498
499 writel(0, port_mmio + PORT_IRQ_MASK);
500
501 /* clear port IRQ */
502 tmp = readl(port_mmio + PORT_IRQ_STAT);
503 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
504 if (tmp)
505 writel(tmp, port_mmio + PORT_IRQ_STAT);
506 }
507
508 ahci_init_controller(host);
509 }
510
511 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
512 unsigned long deadline)
513 {
514 struct ata_port *ap = link->ap;
515 bool online;
516 int rc;
517
518 DPRINTK("ENTER\n");
519
520 ahci_stop_engine(ap);
521
522 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
523 deadline, &online, NULL);
524
525 ahci_start_engine(ap);
526
527 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
528
529 /* vt8251 doesn't clear BSY on signature FIS reception,
530 * request follow-up softreset.
531 */
532 return online ? -EAGAIN : rc;
533 }
534
535 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
536 unsigned long deadline)
537 {
538 struct ata_port *ap = link->ap;
539 struct ahci_port_priv *pp = ap->private_data;
540 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
541 struct ata_taskfile tf;
542 bool online;
543 int rc;
544
545 ahci_stop_engine(ap);
546
547 /* clear D2H reception area to properly wait for D2H FIS */
548 ata_tf_init(link->device, &tf);
549 tf.command = 0x80;
550 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
551
552 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
553 deadline, &online, NULL);
554
555 ahci_start_engine(ap);
556
557 /* The pseudo configuration device on SIMG4726 attached to
558 * ASUS P5W-DH Deluxe doesn't send signature FIS after
559 * hardreset if no device is attached to the first downstream
560 * port && the pseudo device locks up on SRST w/ PMP==0. To
561 * work around this, wait for !BSY only briefly. If BSY isn't
562 * cleared, perform CLO and proceed to IDENTIFY (achieved by
563 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
564 *
565 * Wait for two seconds. Devices attached to downstream port
566 * which can't process the following IDENTIFY after this will
567 * have to be reset again. For most cases, this should
568 * suffice while making probing snappish enough.
569 */
570 if (online) {
571 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
572 ahci_check_ready);
573 if (rc)
574 ahci_kick_engine(ap);
575 }
576 return rc;
577 }
578
579 #ifdef CONFIG_PM
580 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
581 {
582 struct ata_host *host = dev_get_drvdata(&pdev->dev);
583 struct ahci_host_priv *hpriv = host->private_data;
584 void __iomem *mmio = hpriv->mmio;
585 u32 ctl;
586
587 if (mesg.event & PM_EVENT_SUSPEND &&
588 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
589 dev_err(&pdev->dev,
590 "BIOS update required for suspend/resume\n");
591 return -EIO;
592 }
593
594 if (mesg.event & PM_EVENT_SLEEP) {
595 /* AHCI spec rev1.1 section 8.3.3:
596 * Software must disable interrupts prior to requesting a
597 * transition of the HBA to D3 state.
598 */
599 ctl = readl(mmio + HOST_CTL);
600 ctl &= ~HOST_IRQ_EN;
601 writel(ctl, mmio + HOST_CTL);
602 readl(mmio + HOST_CTL); /* flush */
603 }
604
605 return ata_pci_device_suspend(pdev, mesg);
606 }
607
608 static int ahci_pci_device_resume(struct pci_dev *pdev)
609 {
610 struct ata_host *host = dev_get_drvdata(&pdev->dev);
611 int rc;
612
613 rc = ata_pci_device_do_resume(pdev);
614 if (rc)
615 return rc;
616
617 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
618 rc = ahci_pci_reset_controller(host);
619 if (rc)
620 return rc;
621
622 ahci_pci_init_controller(host);
623 }
624
625 ata_host_resume(host);
626
627 return 0;
628 }
629 #endif
630
631 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
632 {
633 int rc;
634
635 /*
636 * If the device fixup already set the dma_mask to some non-standard
637 * value, don't extend it here. This happens on STA2X11, for example.
638 */
639 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
640 return 0;
641
642 if (using_dac &&
643 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
644 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
645 if (rc) {
646 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
647 if (rc) {
648 dev_err(&pdev->dev,
649 "64-bit DMA enable failed\n");
650 return rc;
651 }
652 }
653 } else {
654 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
655 if (rc) {
656 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
657 return rc;
658 }
659 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
660 if (rc) {
661 dev_err(&pdev->dev,
662 "32-bit consistent DMA enable failed\n");
663 return rc;
664 }
665 }
666 return 0;
667 }
668
669 static void ahci_pci_print_info(struct ata_host *host)
670 {
671 struct pci_dev *pdev = to_pci_dev(host->dev);
672 u16 cc;
673 const char *scc_s;
674
675 pci_read_config_word(pdev, 0x0a, &cc);
676 if (cc == PCI_CLASS_STORAGE_IDE)
677 scc_s = "IDE";
678 else if (cc == PCI_CLASS_STORAGE_SATA)
679 scc_s = "SATA";
680 else if (cc == PCI_CLASS_STORAGE_RAID)
681 scc_s = "RAID";
682 else
683 scc_s = "unknown";
684
685 ahci_print_info(host, scc_s);
686 }
687
688 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
689 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
690 * support PMP and the 4726 either directly exports the device
691 * attached to the first downstream port or acts as a hardware storage
692 * controller and emulate a single ATA device (can be RAID 0/1 or some
693 * other configuration).
694 *
695 * When there's no device attached to the first downstream port of the
696 * 4726, "Config Disk" appears, which is a pseudo ATA device to
697 * configure the 4726. However, ATA emulation of the device is very
698 * lame. It doesn't send signature D2H Reg FIS after the initial
699 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
700 *
701 * The following function works around the problem by always using
702 * hardreset on the port and not depending on receiving signature FIS
703 * afterward. If signature FIS isn't received soon, ATA class is
704 * assumed without follow-up softreset.
705 */
706 static void ahci_p5wdh_workaround(struct ata_host *host)
707 {
708 static struct dmi_system_id sysids[] = {
709 {
710 .ident = "P5W DH Deluxe",
711 .matches = {
712 DMI_MATCH(DMI_SYS_VENDOR,
713 "ASUSTEK COMPUTER INC"),
714 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
715 },
716 },
717 { }
718 };
719 struct pci_dev *pdev = to_pci_dev(host->dev);
720
721 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
722 dmi_check_system(sysids)) {
723 struct ata_port *ap = host->ports[1];
724
725 dev_info(&pdev->dev,
726 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
727
728 ap->ops = &ahci_p5wdh_ops;
729 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
730 }
731 }
732
733 /* only some SB600 ahci controllers can do 64bit DMA */
734 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
735 {
736 static const struct dmi_system_id sysids[] = {
737 /*
738 * The oldest version known to be broken is 0901 and
739 * working is 1501 which was released on 2007-10-26.
740 * Enable 64bit DMA on 1501 and anything newer.
741 *
742 * Please read bko#9412 for more info.
743 */
744 {
745 .ident = "ASUS M2A-VM",
746 .matches = {
747 DMI_MATCH(DMI_BOARD_VENDOR,
748 "ASUSTeK Computer INC."),
749 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
750 },
751 .driver_data = "20071026", /* yyyymmdd */
752 },
753 /*
754 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
755 * support 64bit DMA.
756 *
757 * BIOS versions earlier than 1.5 had the Manufacturer DMI
758 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
759 * This spelling mistake was fixed in BIOS version 1.5, so
760 * 1.5 and later have the Manufacturer as
761 * "MICRO-STAR INTERNATIONAL CO.,LTD".
762 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
763 *
764 * BIOS versions earlier than 1.9 had a Board Product Name
765 * DMI field of "MS-7376". This was changed to be
766 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
767 * match on DMI_BOARD_NAME of "MS-7376".
768 */
769 {
770 .ident = "MSI K9A2 Platinum",
771 .matches = {
772 DMI_MATCH(DMI_BOARD_VENDOR,
773 "MICRO-STAR INTER"),
774 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
775 },
776 },
777 /*
778 * All BIOS versions for the Asus M3A support 64bit DMA.
779 * (all release versions from 0301 to 1206 were tested)
780 */
781 {
782 .ident = "ASUS M3A",
783 .matches = {
784 DMI_MATCH(DMI_BOARD_VENDOR,
785 "ASUSTeK Computer INC."),
786 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
787 },
788 },
789 { }
790 };
791 const struct dmi_system_id *match;
792 int year, month, date;
793 char buf[9];
794
795 match = dmi_first_match(sysids);
796 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
797 !match)
798 return false;
799
800 if (!match->driver_data)
801 goto enable_64bit;
802
803 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
804 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
805
806 if (strcmp(buf, match->driver_data) >= 0)
807 goto enable_64bit;
808 else {
809 dev_warn(&pdev->dev,
810 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
811 match->ident);
812 return false;
813 }
814
815 enable_64bit:
816 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
817 return true;
818 }
819
820 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
821 {
822 static const struct dmi_system_id broken_systems[] = {
823 {
824 .ident = "HP Compaq nx6310",
825 .matches = {
826 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
827 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
828 },
829 /* PCI slot number of the controller */
830 .driver_data = (void *)0x1FUL,
831 },
832 {
833 .ident = "HP Compaq 6720s",
834 .matches = {
835 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
836 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
837 },
838 /* PCI slot number of the controller */
839 .driver_data = (void *)0x1FUL,
840 },
841
842 { } /* terminate list */
843 };
844 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
845
846 if (dmi) {
847 unsigned long slot = (unsigned long)dmi->driver_data;
848 /* apply the quirk only to on-board controllers */
849 return slot == PCI_SLOT(pdev->devfn);
850 }
851
852 return false;
853 }
854
855 static bool ahci_broken_suspend(struct pci_dev *pdev)
856 {
857 static const struct dmi_system_id sysids[] = {
858 /*
859 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
860 * to the harddisk doesn't become online after
861 * resuming from STR. Warn and fail suspend.
862 *
863 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
864 *
865 * Use dates instead of versions to match as HP is
866 * apparently recycling both product and version
867 * strings.
868 *
869 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
870 */
871 {
872 .ident = "dv4",
873 .matches = {
874 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
875 DMI_MATCH(DMI_PRODUCT_NAME,
876 "HP Pavilion dv4 Notebook PC"),
877 },
878 .driver_data = "20090105", /* F.30 */
879 },
880 {
881 .ident = "dv5",
882 .matches = {
883 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
884 DMI_MATCH(DMI_PRODUCT_NAME,
885 "HP Pavilion dv5 Notebook PC"),
886 },
887 .driver_data = "20090506", /* F.16 */
888 },
889 {
890 .ident = "dv6",
891 .matches = {
892 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
893 DMI_MATCH(DMI_PRODUCT_NAME,
894 "HP Pavilion dv6 Notebook PC"),
895 },
896 .driver_data = "20090423", /* F.21 */
897 },
898 {
899 .ident = "HDX18",
900 .matches = {
901 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
902 DMI_MATCH(DMI_PRODUCT_NAME,
903 "HP HDX18 Notebook PC"),
904 },
905 .driver_data = "20090430", /* F.23 */
906 },
907 /*
908 * Acer eMachines G725 has the same problem. BIOS
909 * V1.03 is known to be broken. V3.04 is known to
910 * work. Between, there are V1.06, V2.06 and V3.03
911 * that we don't have much idea about. For now,
912 * blacklist anything older than V3.04.
913 *
914 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
915 */
916 {
917 .ident = "G725",
918 .matches = {
919 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
920 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
921 },
922 .driver_data = "20091216", /* V3.04 */
923 },
924 { } /* terminate list */
925 };
926 const struct dmi_system_id *dmi = dmi_first_match(sysids);
927 int year, month, date;
928 char buf[9];
929
930 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
931 return false;
932
933 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
934 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
935
936 return strcmp(buf, dmi->driver_data) < 0;
937 }
938
939 static bool ahci_broken_online(struct pci_dev *pdev)
940 {
941 #define ENCODE_BUSDEVFN(bus, slot, func) \
942 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
943 static const struct dmi_system_id sysids[] = {
944 /*
945 * There are several gigabyte boards which use
946 * SIMG5723s configured as hardware RAID. Certain
947 * 5723 firmware revisions shipped there keep the link
948 * online but fail to answer properly to SRST or
949 * IDENTIFY when no device is attached downstream
950 * causing libata to retry quite a few times leading
951 * to excessive detection delay.
952 *
953 * As these firmwares respond to the second reset try
954 * with invalid device signature, considering unknown
955 * sig as offline works around the problem acceptably.
956 */
957 {
958 .ident = "EP45-DQ6",
959 .matches = {
960 DMI_MATCH(DMI_BOARD_VENDOR,
961 "Gigabyte Technology Co., Ltd."),
962 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
963 },
964 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
965 },
966 {
967 .ident = "EP45-DS5",
968 .matches = {
969 DMI_MATCH(DMI_BOARD_VENDOR,
970 "Gigabyte Technology Co., Ltd."),
971 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
972 },
973 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
974 },
975 { } /* terminate list */
976 };
977 #undef ENCODE_BUSDEVFN
978 const struct dmi_system_id *dmi = dmi_first_match(sysids);
979 unsigned int val;
980
981 if (!dmi)
982 return false;
983
984 val = (unsigned long)dmi->driver_data;
985
986 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
987 }
988
989 #ifdef CONFIG_ATA_ACPI
990 static void ahci_gtf_filter_workaround(struct ata_host *host)
991 {
992 static const struct dmi_system_id sysids[] = {
993 /*
994 * Aspire 3810T issues a bunch of SATA enable commands
995 * via _GTF including an invalid one and one which is
996 * rejected by the device. Among the successful ones
997 * is FPDMA non-zero offset enable which when enabled
998 * only on the drive side leads to NCQ command
999 * failures. Filter it out.
1000 */
1001 {
1002 .ident = "Aspire 3810T",
1003 .matches = {
1004 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1005 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1006 },
1007 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1008 },
1009 { }
1010 };
1011 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1012 unsigned int filter;
1013 int i;
1014
1015 if (!dmi)
1016 return;
1017
1018 filter = (unsigned long)dmi->driver_data;
1019 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1020 filter, dmi->ident);
1021
1022 for (i = 0; i < host->n_ports; i++) {
1023 struct ata_port *ap = host->ports[i];
1024 struct ata_link *link;
1025 struct ata_device *dev;
1026
1027 ata_for_each_link(link, ap, EDGE)
1028 ata_for_each_dev(dev, link, ALL)
1029 dev->gtf_filter |= filter;
1030 }
1031 }
1032 #else
1033 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1034 {}
1035 #endif
1036
1037 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1038 {
1039 unsigned int board_id = ent->driver_data;
1040 struct ata_port_info pi = ahci_port_info[board_id];
1041 const struct ata_port_info *ppi[] = { &pi, NULL };
1042 struct device *dev = &pdev->dev;
1043 struct ahci_host_priv *hpriv;
1044 struct ata_host *host;
1045 int n_ports, i, rc;
1046 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1047
1048 VPRINTK("ENTER\n");
1049
1050 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1051
1052 ata_print_version_once(&pdev->dev, DRV_VERSION);
1053
1054 /* The AHCI driver can only drive the SATA ports, the PATA driver
1055 can drive them all so if both drivers are selected make sure
1056 AHCI stays out of the way */
1057 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1058 return -ENODEV;
1059
1060 /*
1061 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1062 * ahci, use ata_generic instead.
1063 */
1064 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1065 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1066 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1067 pdev->subsystem_device == 0xcb89)
1068 return -ENODEV;
1069
1070 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1071 * At the moment, we can only use the AHCI mode. Let the users know
1072 * that for SAS drives they're out of luck.
1073 */
1074 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1075 dev_info(&pdev->dev,
1076 "PDC42819 can only drive SATA devices with this driver\n");
1077
1078 /* The Connext uses non-standard BAR */
1079 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1080 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1081
1082 /* acquire resources */
1083 rc = pcim_enable_device(pdev);
1084 if (rc)
1085 return rc;
1086
1087 /* AHCI controllers often implement SFF compatible interface.
1088 * Grab all PCI BARs just in case.
1089 */
1090 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1091 if (rc == -EBUSY)
1092 pcim_pin_device(pdev);
1093 if (rc)
1094 return rc;
1095
1096 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1097 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1098 u8 map;
1099
1100 /* ICH6s share the same PCI ID for both piix and ahci
1101 * modes. Enabling ahci mode while MAP indicates
1102 * combined mode is a bad idea. Yield to ata_piix.
1103 */
1104 pci_read_config_byte(pdev, ICH_MAP, &map);
1105 if (map & 0x3) {
1106 dev_info(&pdev->dev,
1107 "controller is in combined mode, can't enable AHCI mode\n");
1108 return -ENODEV;
1109 }
1110 }
1111
1112 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1113 if (!hpriv)
1114 return -ENOMEM;
1115 hpriv->flags |= (unsigned long)pi.private_data;
1116
1117 /* MCP65 revision A1 and A2 can't do MSI */
1118 if (board_id == board_ahci_mcp65 &&
1119 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1120 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1121
1122 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1123 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1124 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1125
1126 /* only some SB600s can do 64bit DMA */
1127 if (ahci_sb600_enable_64bit(pdev))
1128 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1129
1130 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1131 pci_intx(pdev, 1);
1132
1133 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1134
1135 /* save initial config */
1136 ahci_pci_save_initial_config(pdev, hpriv);
1137
1138 /* prepare host */
1139 if (hpriv->cap & HOST_CAP_NCQ) {
1140 pi.flags |= ATA_FLAG_NCQ;
1141 /*
1142 * Auto-activate optimization is supposed to be
1143 * supported on all AHCI controllers indicating NCQ
1144 * capability, but it seems to be broken on some
1145 * chipsets including NVIDIAs.
1146 */
1147 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1148 pi.flags |= ATA_FLAG_FPDMA_AA;
1149 }
1150
1151 if (hpriv->cap & HOST_CAP_PMP)
1152 pi.flags |= ATA_FLAG_PMP;
1153
1154 ahci_set_em_messages(hpriv, &pi);
1155
1156 if (ahci_broken_system_poweroff(pdev)) {
1157 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1158 dev_info(&pdev->dev,
1159 "quirky BIOS, skipping spindown on poweroff\n");
1160 }
1161
1162 if (ahci_broken_suspend(pdev)) {
1163 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1164 dev_warn(&pdev->dev,
1165 "BIOS update required for suspend/resume\n");
1166 }
1167
1168 if (ahci_broken_online(pdev)) {
1169 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1170 dev_info(&pdev->dev,
1171 "online status unreliable, applying workaround\n");
1172 }
1173
1174 /* CAP.NP sometimes indicate the index of the last enabled
1175 * port, at other times, that of the last possible port, so
1176 * determining the maximum port number requires looking at
1177 * both CAP.NP and port_map.
1178 */
1179 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1180
1181 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1182 if (!host)
1183 return -ENOMEM;
1184 host->private_data = hpriv;
1185
1186 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1187 host->flags |= ATA_HOST_PARALLEL_SCAN;
1188 else
1189 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1190
1191 if (pi.flags & ATA_FLAG_EM)
1192 ahci_reset_em(host);
1193
1194 for (i = 0; i < host->n_ports; i++) {
1195 struct ata_port *ap = host->ports[i];
1196
1197 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1198 ata_port_pbar_desc(ap, ahci_pci_bar,
1199 0x100 + ap->port_no * 0x80, "port");
1200
1201 /* set enclosure management message type */
1202 if (ap->flags & ATA_FLAG_EM)
1203 ap->em_message_type = hpriv->em_msg_type;
1204
1205
1206 /* disabled/not-implemented port */
1207 if (!(hpriv->port_map & (1 << i)))
1208 ap->ops = &ata_dummy_port_ops;
1209 }
1210
1211 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1212 ahci_p5wdh_workaround(host);
1213
1214 /* apply gtf filter quirk */
1215 ahci_gtf_filter_workaround(host);
1216
1217 /* initialize adapter */
1218 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1219 if (rc)
1220 return rc;
1221
1222 rc = ahci_pci_reset_controller(host);
1223 if (rc)
1224 return rc;
1225
1226 ahci_pci_init_controller(host);
1227 ahci_pci_print_info(host);
1228
1229 pci_set_master(pdev);
1230 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1231 &ahci_sht);
1232 }
1233
1234 static int __init ahci_init(void)
1235 {
1236 return pci_register_driver(&ahci_pci_driver);
1237 }
1238
1239 static void __exit ahci_exit(void)
1240 {
1241 pci_unregister_driver(&ahci_pci_driver);
1242 }
1243
1244
1245 MODULE_AUTHOR("Jeff Garzik");
1246 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1247 MODULE_LICENSE("GPL");
1248 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1249 MODULE_VERSION(DRV_VERSION);
1250
1251 module_init(ahci_init);
1252 module_exit(ahci_exit);
Linux kernel - Deliverables
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