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93bcb2cb3d35703700d8008bb60a9106d3112c35
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52
53 enum {
54 AHCI_PCI_BAR = 5,
55 AHCI_MAX_PORTS = 32,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 1,
59 AHCI_MAX_CMDS = 32,
60 AHCI_CMD_SZ = 32,
61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_RX_FIS_SZ = 256,
63 AHCI_CMD_TBL_CDB = 0x40,
64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
72 AHCI_CMD_PREFETCH = (1 << 7),
73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
79
80 board_ahci = 0,
81 board_ahci_vt8251 = 1,
82 board_ahci_ign_iferr = 2,
83 board_ahci_sb600 = 3,
84 board_ahci_mv = 4,
85
86 /* global controller registers */
87 HOST_CAP = 0x00, /* host capabilities */
88 HOST_CTL = 0x04, /* global host control */
89 HOST_IRQ_STAT = 0x08, /* interrupt status */
90 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
91 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
92
93 /* HOST_CTL bits */
94 HOST_RESET = (1 << 0), /* reset controller; self-clear */
95 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
96 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
97
98 /* HOST_CAP bits */
99 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
100 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
101 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
102 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
103 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
104 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
105 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
106
107 /* registers for each SATA port */
108 PORT_LST_ADDR = 0x00, /* command list DMA addr */
109 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
110 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
111 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
112 PORT_IRQ_STAT = 0x10, /* interrupt status */
113 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
114 PORT_CMD = 0x18, /* port command */
115 PORT_TFDATA = 0x20, /* taskfile data */
116 PORT_SIG = 0x24, /* device TF signature */
117 PORT_CMD_ISSUE = 0x38, /* command issue */
118 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
119 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
120 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
121 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
122 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
123
124 /* PORT_IRQ_{STAT,MASK} bits */
125 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
126 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
127 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
128 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
129 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
130 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
131 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
132 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
133
134 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
135 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
136 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
137 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
138 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
139 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
140 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
141 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
142 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
143
144 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
145 PORT_IRQ_IF_ERR |
146 PORT_IRQ_CONNECT |
147 PORT_IRQ_PHYRDY |
148 PORT_IRQ_UNK_FIS |
149 PORT_IRQ_BAD_PMP,
150 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
151 PORT_IRQ_TF_ERR |
152 PORT_IRQ_HBUS_DATA_ERR,
153 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
154 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
155 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
156
157 /* PORT_CMD bits */
158 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
159 PORT_CMD_PMP = (1 << 17), /* PMP attached */
160 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
161 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
162 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
163 PORT_CMD_CLO = (1 << 3), /* Command list override */
164 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
165 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
166 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
167
168 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
169 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
170 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
171 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
172
173 /* hpriv->flags bits */
174 AHCI_HFLAG_NO_NCQ = (1 << 0),
175 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
176 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
177 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
178 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
179 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
180 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
181
182 /* ap->flags bits */
183 AHCI_FLAG_NO_HOTPLUG = (1 << 24), /* ignore PxSERR.DIAG.N */
184
185 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
186 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
187 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
188 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
189 };
190
191 struct ahci_cmd_hdr {
192 u32 opts;
193 u32 status;
194 u32 tbl_addr;
195 u32 tbl_addr_hi;
196 u32 reserved[4];
197 };
198
199 struct ahci_sg {
200 u32 addr;
201 u32 addr_hi;
202 u32 reserved;
203 u32 flags_size;
204 };
205
206 struct ahci_host_priv {
207 unsigned int flags; /* AHCI_HFLAG_* */
208 u32 cap; /* cap to use */
209 u32 port_map; /* port map to use */
210 u32 saved_cap; /* saved initial cap */
211 u32 saved_port_map; /* saved initial port_map */
212 };
213
214 struct ahci_port_priv {
215 struct ata_link *active_link;
216 struct ahci_cmd_hdr *cmd_slot;
217 dma_addr_t cmd_slot_dma;
218 void *cmd_tbl;
219 dma_addr_t cmd_tbl_dma;
220 void *rx_fis;
221 dma_addr_t rx_fis_dma;
222 /* for NCQ spurious interrupt analysis */
223 unsigned int ncq_saw_d2h:1;
224 unsigned int ncq_saw_dmas:1;
225 unsigned int ncq_saw_sdb:1;
226 u32 intr_mask; /* interrupts to enable */
227 };
228
229 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
230 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
231 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
232 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
233 static void ahci_irq_clear(struct ata_port *ap);
234 static int ahci_port_start(struct ata_port *ap);
235 static void ahci_port_stop(struct ata_port *ap);
236 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
237 static void ahci_qc_prep(struct ata_queued_cmd *qc);
238 static u8 ahci_check_status(struct ata_port *ap);
239 static void ahci_freeze(struct ata_port *ap);
240 static void ahci_thaw(struct ata_port *ap);
241 static void ahci_pmp_attach(struct ata_port *ap);
242 static void ahci_pmp_detach(struct ata_port *ap);
243 static void ahci_error_handler(struct ata_port *ap);
244 static void ahci_vt8251_error_handler(struct ata_port *ap);
245 static void ahci_p5wdh_error_handler(struct ata_port *ap);
246 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
247 static int ahci_port_resume(struct ata_port *ap);
248 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
249 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
250 u32 opts);
251 #ifdef CONFIG_PM
252 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
253 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
254 static int ahci_pci_device_resume(struct pci_dev *pdev);
255 #endif
256
257 static struct scsi_host_template ahci_sht = {
258 .module = THIS_MODULE,
259 .name = DRV_NAME,
260 .ioctl = ata_scsi_ioctl,
261 .queuecommand = ata_scsi_queuecmd,
262 .change_queue_depth = ata_scsi_change_queue_depth,
263 .can_queue = AHCI_MAX_CMDS - 1,
264 .this_id = ATA_SHT_THIS_ID,
265 .sg_tablesize = AHCI_MAX_SG,
266 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
267 .emulated = ATA_SHT_EMULATED,
268 .use_clustering = AHCI_USE_CLUSTERING,
269 .proc_name = DRV_NAME,
270 .dma_boundary = AHCI_DMA_BOUNDARY,
271 .slave_configure = ata_scsi_slave_config,
272 .slave_destroy = ata_scsi_slave_destroy,
273 .bios_param = ata_std_bios_param,
274 };
275
276 static const struct ata_port_operations ahci_ops = {
277 .check_status = ahci_check_status,
278 .check_altstatus = ahci_check_status,
279 .dev_select = ata_noop_dev_select,
280
281 .tf_read = ahci_tf_read,
282
283 .qc_defer = sata_pmp_qc_defer_cmd_switch,
284 .qc_prep = ahci_qc_prep,
285 .qc_issue = ahci_qc_issue,
286
287 .irq_clear = ahci_irq_clear,
288
289 .scr_read = ahci_scr_read,
290 .scr_write = ahci_scr_write,
291
292 .freeze = ahci_freeze,
293 .thaw = ahci_thaw,
294
295 .error_handler = ahci_error_handler,
296 .post_internal_cmd = ahci_post_internal_cmd,
297
298 .pmp_attach = ahci_pmp_attach,
299 .pmp_detach = ahci_pmp_detach,
300
301 #ifdef CONFIG_PM
302 .port_suspend = ahci_port_suspend,
303 .port_resume = ahci_port_resume,
304 #endif
305
306 .port_start = ahci_port_start,
307 .port_stop = ahci_port_stop,
308 };
309
310 static const struct ata_port_operations ahci_vt8251_ops = {
311 .check_status = ahci_check_status,
312 .check_altstatus = ahci_check_status,
313 .dev_select = ata_noop_dev_select,
314
315 .tf_read = ahci_tf_read,
316
317 .qc_defer = sata_pmp_qc_defer_cmd_switch,
318 .qc_prep = ahci_qc_prep,
319 .qc_issue = ahci_qc_issue,
320
321 .irq_clear = ahci_irq_clear,
322
323 .scr_read = ahci_scr_read,
324 .scr_write = ahci_scr_write,
325
326 .freeze = ahci_freeze,
327 .thaw = ahci_thaw,
328
329 .error_handler = ahci_vt8251_error_handler,
330 .post_internal_cmd = ahci_post_internal_cmd,
331
332 .pmp_attach = ahci_pmp_attach,
333 .pmp_detach = ahci_pmp_detach,
334
335 #ifdef CONFIG_PM
336 .port_suspend = ahci_port_suspend,
337 .port_resume = ahci_port_resume,
338 #endif
339
340 .port_start = ahci_port_start,
341 .port_stop = ahci_port_stop,
342 };
343
344 static const struct ata_port_operations ahci_p5wdh_ops = {
345 .check_status = ahci_check_status,
346 .check_altstatus = ahci_check_status,
347 .dev_select = ata_noop_dev_select,
348
349 .tf_read = ahci_tf_read,
350
351 .qc_defer = sata_pmp_qc_defer_cmd_switch,
352 .qc_prep = ahci_qc_prep,
353 .qc_issue = ahci_qc_issue,
354
355 .irq_clear = ahci_irq_clear,
356
357 .scr_read = ahci_scr_read,
358 .scr_write = ahci_scr_write,
359
360 .freeze = ahci_freeze,
361 .thaw = ahci_thaw,
362
363 .error_handler = ahci_p5wdh_error_handler,
364 .post_internal_cmd = ahci_post_internal_cmd,
365
366 .pmp_attach = ahci_pmp_attach,
367 .pmp_detach = ahci_pmp_detach,
368
369 #ifdef CONFIG_PM
370 .port_suspend = ahci_port_suspend,
371 .port_resume = ahci_port_resume,
372 #endif
373
374 .port_start = ahci_port_start,
375 .port_stop = ahci_port_stop,
376 };
377
378 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
379
380 static const struct ata_port_info ahci_port_info[] = {
381 /* board_ahci */
382 {
383 .flags = AHCI_FLAG_COMMON,
384 .link_flags = AHCI_LFLAG_COMMON,
385 .pio_mask = 0x1f, /* pio0-4 */
386 .udma_mask = ATA_UDMA6,
387 .port_ops = &ahci_ops,
388 },
389 /* board_ahci_vt8251 */
390 {
391 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
392 .flags = AHCI_FLAG_COMMON,
393 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
394 .pio_mask = 0x1f, /* pio0-4 */
395 .udma_mask = ATA_UDMA6,
396 .port_ops = &ahci_vt8251_ops,
397 },
398 /* board_ahci_ign_iferr */
399 {
400 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
401 .flags = AHCI_FLAG_COMMON,
402 .link_flags = AHCI_LFLAG_COMMON,
403 .pio_mask = 0x1f, /* pio0-4 */
404 .udma_mask = ATA_UDMA6,
405 .port_ops = &ahci_ops,
406 },
407 /* board_ahci_sb600 */
408 {
409 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
410 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
411 .flags = AHCI_FLAG_COMMON,
412 .link_flags = AHCI_LFLAG_COMMON,
413 .pio_mask = 0x1f, /* pio0-4 */
414 .udma_mask = ATA_UDMA6,
415 .port_ops = &ahci_ops,
416 },
417 /* board_ahci_mv */
418 {
419 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
420 AHCI_HFLAG_MV_PATA),
421 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
422 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
423 .link_flags = AHCI_LFLAG_COMMON,
424 .pio_mask = 0x1f, /* pio0-4 */
425 .udma_mask = ATA_UDMA6,
426 .port_ops = &ahci_ops,
427 },
428 };
429
430 static const struct pci_device_id ahci_pci_tbl[] = {
431 /* Intel */
432 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
433 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
434 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
435 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
436 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
437 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
438 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
439 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
440 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
441 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
442 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
443 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
444 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
445 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
446 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
447 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
448 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
449 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
450 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
451 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
452 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
453 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
454 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
455 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
456 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
457 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
458 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
459 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
460 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
461
462 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
463 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
464 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
465
466 /* ATI */
467 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
468 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
469 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
470 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
471 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
472 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
473 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
474
475 /* VIA */
476 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
477 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
478
479 /* NVIDIA */
480 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
481 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
482 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
483 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
484 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
485 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
486 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
487 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
488 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
489 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
490 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
492 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
493 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
494 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
495 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
496 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
497 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
498 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
499 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
500 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
501 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
502 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
503 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
504 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
505 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
506 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
507 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
508 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
509 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
510 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
511 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
512 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
513 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
514 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
515 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
516 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
517 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
518 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
519 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
520 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
521 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
522 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
523 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
524 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
525 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
526 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
527 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
528 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
529 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
530 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
531 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
532
533 /* SiS */
534 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
535 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
536 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
537
538 /* Marvell */
539 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
540
541 /* Generic, PCI class code for AHCI */
542 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
543 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
544
545 { } /* terminate list */
546 };
547
548
549 static struct pci_driver ahci_pci_driver = {
550 .name = DRV_NAME,
551 .id_table = ahci_pci_tbl,
552 .probe = ahci_init_one,
553 .remove = ata_pci_remove_one,
554 #ifdef CONFIG_PM
555 .suspend = ahci_pci_device_suspend,
556 .resume = ahci_pci_device_resume,
557 #endif
558 };
559
560
561 static inline int ahci_nr_ports(u32 cap)
562 {
563 return (cap & 0x1f) + 1;
564 }
565
566 static inline void __iomem *__ahci_port_base(struct ata_host *host,
567 unsigned int port_no)
568 {
569 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
570
571 return mmio + 0x100 + (port_no * 0x80);
572 }
573
574 static inline void __iomem *ahci_port_base(struct ata_port *ap)
575 {
576 return __ahci_port_base(ap->host, ap->port_no);
577 }
578
579 /**
580 * ahci_save_initial_config - Save and fixup initial config values
581 * @pdev: target PCI device
582 * @hpriv: host private area to store config values
583 *
584 * Some registers containing configuration info might be setup by
585 * BIOS and might be cleared on reset. This function saves the
586 * initial values of those registers into @hpriv such that they
587 * can be restored after controller reset.
588 *
589 * If inconsistent, config values are fixed up by this function.
590 *
591 * LOCKING:
592 * None.
593 */
594 static void ahci_save_initial_config(struct pci_dev *pdev,
595 struct ahci_host_priv *hpriv)
596 {
597 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
598 u32 cap, port_map;
599 int i;
600
601 /* Values prefixed with saved_ are written back to host after
602 * reset. Values without are used for driver operation.
603 */
604 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
605 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
606
607 /* some chips have errata preventing 64bit use */
608 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
609 dev_printk(KERN_INFO, &pdev->dev,
610 "controller can't do 64bit DMA, forcing 32bit\n");
611 cap &= ~HOST_CAP_64;
612 }
613
614 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
615 dev_printk(KERN_INFO, &pdev->dev,
616 "controller can't do NCQ, turning off CAP_NCQ\n");
617 cap &= ~HOST_CAP_NCQ;
618 }
619
620 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
621 dev_printk(KERN_INFO, &pdev->dev,
622 "controller can't do PMP, turning off CAP_PMP\n");
623 cap &= ~HOST_CAP_PMP;
624 }
625
626 /*
627 * Temporary Marvell 6145 hack: PATA port presence
628 * is asserted through the standard AHCI port
629 * presence register, as bit 4 (counting from 0)
630 */
631 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
632 dev_printk(KERN_ERR, &pdev->dev,
633 "MV_AHCI HACK: port_map %x -> %x\n",
634 hpriv->port_map,
635 hpriv->port_map & 0xf);
636
637 port_map &= 0xf;
638 }
639
640 /* cross check port_map and cap.n_ports */
641 if (port_map) {
642 u32 tmp_port_map = port_map;
643 int n_ports = ahci_nr_ports(cap);
644
645 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
646 if (tmp_port_map & (1 << i)) {
647 n_ports--;
648 tmp_port_map &= ~(1 << i);
649 }
650 }
651
652 /* If n_ports and port_map are inconsistent, whine and
653 * clear port_map and let it be generated from n_ports.
654 */
655 if (n_ports || tmp_port_map) {
656 dev_printk(KERN_WARNING, &pdev->dev,
657 "nr_ports (%u) and implemented port map "
658 "(0x%x) don't match, using nr_ports\n",
659 ahci_nr_ports(cap), port_map);
660 port_map = 0;
661 }
662 }
663
664 /* fabricate port_map from cap.nr_ports */
665 if (!port_map) {
666 port_map = (1 << ahci_nr_ports(cap)) - 1;
667 dev_printk(KERN_WARNING, &pdev->dev,
668 "forcing PORTS_IMPL to 0x%x\n", port_map);
669
670 /* write the fixed up value to the PI register */
671 hpriv->saved_port_map = port_map;
672 }
673
674 /* record values to use during operation */
675 hpriv->cap = cap;
676 hpriv->port_map = port_map;
677 }
678
679 /**
680 * ahci_restore_initial_config - Restore initial config
681 * @host: target ATA host
682 *
683 * Restore initial config stored by ahci_save_initial_config().
684 *
685 * LOCKING:
686 * None.
687 */
688 static void ahci_restore_initial_config(struct ata_host *host)
689 {
690 struct ahci_host_priv *hpriv = host->private_data;
691 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
692
693 writel(hpriv->saved_cap, mmio + HOST_CAP);
694 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
695 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
696 }
697
698 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
699 {
700 static const int offset[] = {
701 [SCR_STATUS] = PORT_SCR_STAT,
702 [SCR_CONTROL] = PORT_SCR_CTL,
703 [SCR_ERROR] = PORT_SCR_ERR,
704 [SCR_ACTIVE] = PORT_SCR_ACT,
705 [SCR_NOTIFICATION] = PORT_SCR_NTF,
706 };
707 struct ahci_host_priv *hpriv = ap->host->private_data;
708
709 if (sc_reg < ARRAY_SIZE(offset) &&
710 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
711 return offset[sc_reg];
712 return 0;
713 }
714
715 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
716 {
717 void __iomem *port_mmio = ahci_port_base(ap);
718 int offset = ahci_scr_offset(ap, sc_reg);
719
720 if (offset) {
721 *val = readl(port_mmio + offset);
722 return 0;
723 }
724 return -EINVAL;
725 }
726
727 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
728 {
729 void __iomem *port_mmio = ahci_port_base(ap);
730 int offset = ahci_scr_offset(ap, sc_reg);
731
732 if (offset) {
733 writel(val, port_mmio + offset);
734 return 0;
735 }
736 return -EINVAL;
737 }
738
739 static void ahci_start_engine(struct ata_port *ap)
740 {
741 void __iomem *port_mmio = ahci_port_base(ap);
742 u32 tmp;
743
744 /* start DMA */
745 tmp = readl(port_mmio + PORT_CMD);
746 tmp |= PORT_CMD_START;
747 writel(tmp, port_mmio + PORT_CMD);
748 readl(port_mmio + PORT_CMD); /* flush */
749 }
750
751 static int ahci_stop_engine(struct ata_port *ap)
752 {
753 void __iomem *port_mmio = ahci_port_base(ap);
754 u32 tmp;
755
756 tmp = readl(port_mmio + PORT_CMD);
757
758 /* check if the HBA is idle */
759 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
760 return 0;
761
762 /* setting HBA to idle */
763 tmp &= ~PORT_CMD_START;
764 writel(tmp, port_mmio + PORT_CMD);
765
766 /* wait for engine to stop. This could be as long as 500 msec */
767 tmp = ata_wait_register(port_mmio + PORT_CMD,
768 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
769 if (tmp & PORT_CMD_LIST_ON)
770 return -EIO;
771
772 return 0;
773 }
774
775 static void ahci_start_fis_rx(struct ata_port *ap)
776 {
777 void __iomem *port_mmio = ahci_port_base(ap);
778 struct ahci_host_priv *hpriv = ap->host->private_data;
779 struct ahci_port_priv *pp = ap->private_data;
780 u32 tmp;
781
782 /* set FIS registers */
783 if (hpriv->cap & HOST_CAP_64)
784 writel((pp->cmd_slot_dma >> 16) >> 16,
785 port_mmio + PORT_LST_ADDR_HI);
786 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
787
788 if (hpriv->cap & HOST_CAP_64)
789 writel((pp->rx_fis_dma >> 16) >> 16,
790 port_mmio + PORT_FIS_ADDR_HI);
791 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
792
793 /* enable FIS reception */
794 tmp = readl(port_mmio + PORT_CMD);
795 tmp |= PORT_CMD_FIS_RX;
796 writel(tmp, port_mmio + PORT_CMD);
797
798 /* flush */
799 readl(port_mmio + PORT_CMD);
800 }
801
802 static int ahci_stop_fis_rx(struct ata_port *ap)
803 {
804 void __iomem *port_mmio = ahci_port_base(ap);
805 u32 tmp;
806
807 /* disable FIS reception */
808 tmp = readl(port_mmio + PORT_CMD);
809 tmp &= ~PORT_CMD_FIS_RX;
810 writel(tmp, port_mmio + PORT_CMD);
811
812 /* wait for completion, spec says 500ms, give it 1000 */
813 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
814 PORT_CMD_FIS_ON, 10, 1000);
815 if (tmp & PORT_CMD_FIS_ON)
816 return -EBUSY;
817
818 return 0;
819 }
820
821 static void ahci_power_up(struct ata_port *ap)
822 {
823 struct ahci_host_priv *hpriv = ap->host->private_data;
824 void __iomem *port_mmio = ahci_port_base(ap);
825 u32 cmd;
826
827 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
828
829 /* spin up device */
830 if (hpriv->cap & HOST_CAP_SSS) {
831 cmd |= PORT_CMD_SPIN_UP;
832 writel(cmd, port_mmio + PORT_CMD);
833 }
834
835 /* wake up link */
836 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
837 }
838
839 #ifdef CONFIG_PM
840 static void ahci_power_down(struct ata_port *ap)
841 {
842 struct ahci_host_priv *hpriv = ap->host->private_data;
843 void __iomem *port_mmio = ahci_port_base(ap);
844 u32 cmd, scontrol;
845
846 if (!(hpriv->cap & HOST_CAP_SSS))
847 return;
848
849 /* put device into listen mode, first set PxSCTL.DET to 0 */
850 scontrol = readl(port_mmio + PORT_SCR_CTL);
851 scontrol &= ~0xf;
852 writel(scontrol, port_mmio + PORT_SCR_CTL);
853
854 /* then set PxCMD.SUD to 0 */
855 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
856 cmd &= ~PORT_CMD_SPIN_UP;
857 writel(cmd, port_mmio + PORT_CMD);
858 }
859 #endif
860
861 static void ahci_start_port(struct ata_port *ap)
862 {
863 /* enable FIS reception */
864 ahci_start_fis_rx(ap);
865
866 /* enable DMA */
867 ahci_start_engine(ap);
868 }
869
870 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
871 {
872 int rc;
873
874 /* disable DMA */
875 rc = ahci_stop_engine(ap);
876 if (rc) {
877 *emsg = "failed to stop engine";
878 return rc;
879 }
880
881 /* disable FIS reception */
882 rc = ahci_stop_fis_rx(ap);
883 if (rc) {
884 *emsg = "failed stop FIS RX";
885 return rc;
886 }
887
888 return 0;
889 }
890
891 static int ahci_reset_controller(struct ata_host *host)
892 {
893 struct pci_dev *pdev = to_pci_dev(host->dev);
894 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
895 u32 tmp;
896
897 /* we must be in AHCI mode, before using anything
898 * AHCI-specific, such as HOST_RESET.
899 */
900 tmp = readl(mmio + HOST_CTL);
901 if (!(tmp & HOST_AHCI_EN))
902 writel(tmp | HOST_AHCI_EN, mmio + HOST_CTL);
903
904 /* global controller reset */
905 if ((tmp & HOST_RESET) == 0) {
906 writel(tmp | HOST_RESET, mmio + HOST_CTL);
907 readl(mmio + HOST_CTL); /* flush */
908 }
909
910 /* reset must complete within 1 second, or
911 * the hardware should be considered fried.
912 */
913 ssleep(1);
914
915 tmp = readl(mmio + HOST_CTL);
916 if (tmp & HOST_RESET) {
917 dev_printk(KERN_ERR, host->dev,
918 "controller reset failed (0x%x)\n", tmp);
919 return -EIO;
920 }
921
922 /* turn on AHCI mode */
923 writel(HOST_AHCI_EN, mmio + HOST_CTL);
924 (void) readl(mmio + HOST_CTL); /* flush */
925
926 /* some registers might be cleared on reset. restore initial values */
927 ahci_restore_initial_config(host);
928
929 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
930 u16 tmp16;
931
932 /* configure PCS */
933 pci_read_config_word(pdev, 0x92, &tmp16);
934 tmp16 |= 0xf;
935 pci_write_config_word(pdev, 0x92, tmp16);
936 }
937
938 return 0;
939 }
940
941 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
942 int port_no, void __iomem *mmio,
943 void __iomem *port_mmio)
944 {
945 const char *emsg = NULL;
946 int rc;
947 u32 tmp;
948
949 /* make sure port is not active */
950 rc = ahci_deinit_port(ap, &emsg);
951 if (rc)
952 dev_printk(KERN_WARNING, &pdev->dev,
953 "%s (%d)\n", emsg, rc);
954
955 /* clear SError */
956 tmp = readl(port_mmio + PORT_SCR_ERR);
957 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
958 writel(tmp, port_mmio + PORT_SCR_ERR);
959
960 /* clear port IRQ */
961 tmp = readl(port_mmio + PORT_IRQ_STAT);
962 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
963 if (tmp)
964 writel(tmp, port_mmio + PORT_IRQ_STAT);
965
966 writel(1 << port_no, mmio + HOST_IRQ_STAT);
967 }
968
969 static void ahci_init_controller(struct ata_host *host)
970 {
971 struct ahci_host_priv *hpriv = host->private_data;
972 struct pci_dev *pdev = to_pci_dev(host->dev);
973 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
974 int i;
975 void __iomem *port_mmio;
976 u32 tmp;
977
978 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
979 port_mmio = __ahci_port_base(host, 4);
980
981 writel(0, port_mmio + PORT_IRQ_MASK);
982
983 /* clear port IRQ */
984 tmp = readl(port_mmio + PORT_IRQ_STAT);
985 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
986 if (tmp)
987 writel(tmp, port_mmio + PORT_IRQ_STAT);
988 }
989
990 for (i = 0; i < host->n_ports; i++) {
991 struct ata_port *ap = host->ports[i];
992
993 port_mmio = ahci_port_base(ap);
994 if (ata_port_is_dummy(ap))
995 continue;
996
997 ahci_port_init(pdev, ap, i, mmio, port_mmio);
998 }
999
1000 tmp = readl(mmio + HOST_CTL);
1001 VPRINTK("HOST_CTL 0x%x\n", tmp);
1002 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1003 tmp = readl(mmio + HOST_CTL);
1004 VPRINTK("HOST_CTL 0x%x\n", tmp);
1005 }
1006
1007 static unsigned int ahci_dev_classify(struct ata_port *ap)
1008 {
1009 void __iomem *port_mmio = ahci_port_base(ap);
1010 struct ata_taskfile tf;
1011 u32 tmp;
1012
1013 tmp = readl(port_mmio + PORT_SIG);
1014 tf.lbah = (tmp >> 24) & 0xff;
1015 tf.lbam = (tmp >> 16) & 0xff;
1016 tf.lbal = (tmp >> 8) & 0xff;
1017 tf.nsect = (tmp) & 0xff;
1018
1019 return ata_dev_classify(&tf);
1020 }
1021
1022 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1023 u32 opts)
1024 {
1025 dma_addr_t cmd_tbl_dma;
1026
1027 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1028
1029 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1030 pp->cmd_slot[tag].status = 0;
1031 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1032 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1033 }
1034
1035 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1036 {
1037 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1038 struct ahci_host_priv *hpriv = ap->host->private_data;
1039 u32 tmp;
1040 int busy, rc;
1041
1042 /* do we need to kick the port? */
1043 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1044 if (!busy && !force_restart)
1045 return 0;
1046
1047 /* stop engine */
1048 rc = ahci_stop_engine(ap);
1049 if (rc)
1050 goto out_restart;
1051
1052 /* need to do CLO? */
1053 if (!busy) {
1054 rc = 0;
1055 goto out_restart;
1056 }
1057
1058 if (!(hpriv->cap & HOST_CAP_CLO)) {
1059 rc = -EOPNOTSUPP;
1060 goto out_restart;
1061 }
1062
1063 /* perform CLO */
1064 tmp = readl(port_mmio + PORT_CMD);
1065 tmp |= PORT_CMD_CLO;
1066 writel(tmp, port_mmio + PORT_CMD);
1067
1068 rc = 0;
1069 tmp = ata_wait_register(port_mmio + PORT_CMD,
1070 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1071 if (tmp & PORT_CMD_CLO)
1072 rc = -EIO;
1073
1074 /* restart engine */
1075 out_restart:
1076 ahci_start_engine(ap);
1077 return rc;
1078 }
1079
1080 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1081 struct ata_taskfile *tf, int is_cmd, u16 flags,
1082 unsigned long timeout_msec)
1083 {
1084 const u32 cmd_fis_len = 5; /* five dwords */
1085 struct ahci_port_priv *pp = ap->private_data;
1086 void __iomem *port_mmio = ahci_port_base(ap);
1087 u8 *fis = pp->cmd_tbl;
1088 u32 tmp;
1089
1090 /* prep the command */
1091 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1092 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1093
1094 /* issue & wait */
1095 writel(1, port_mmio + PORT_CMD_ISSUE);
1096
1097 if (timeout_msec) {
1098 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1099 1, timeout_msec);
1100 if (tmp & 0x1) {
1101 ahci_kick_engine(ap, 1);
1102 return -EBUSY;
1103 }
1104 } else
1105 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1106
1107 return 0;
1108 }
1109
1110 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1111 int pmp, unsigned long deadline)
1112 {
1113 struct ata_port *ap = link->ap;
1114 const char *reason = NULL;
1115 unsigned long now, msecs;
1116 struct ata_taskfile tf;
1117 int rc;
1118
1119 DPRINTK("ENTER\n");
1120
1121 if (ata_link_offline(link)) {
1122 DPRINTK("PHY reports no device\n");
1123 *class = ATA_DEV_NONE;
1124 return 0;
1125 }
1126
1127 /* prepare for SRST (AHCI-1.1 10.4.1) */
1128 rc = ahci_kick_engine(ap, 1);
1129 if (rc)
1130 ata_link_printk(link, KERN_WARNING,
1131 "failed to reset engine (errno=%d)", rc);
1132
1133 ata_tf_init(link->device, &tf);
1134
1135 /* issue the first D2H Register FIS */
1136 msecs = 0;
1137 now = jiffies;
1138 if (time_after(now, deadline))
1139 msecs = jiffies_to_msecs(deadline - now);
1140
1141 tf.ctl |= ATA_SRST;
1142 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1143 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1144 rc = -EIO;
1145 reason = "1st FIS failed";
1146 goto fail;
1147 }
1148
1149 /* spec says at least 5us, but be generous and sleep for 1ms */
1150 msleep(1);
1151
1152 /* issue the second D2H Register FIS */
1153 tf.ctl &= ~ATA_SRST;
1154 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1155
1156 /* wait a while before checking status */
1157 ata_wait_after_reset(ap, deadline);
1158
1159 rc = ata_wait_ready(ap, deadline);
1160 /* link occupied, -ENODEV too is an error */
1161 if (rc) {
1162 reason = "device not ready";
1163 goto fail;
1164 }
1165 *class = ahci_dev_classify(ap);
1166
1167 DPRINTK("EXIT, class=%u\n", *class);
1168 return 0;
1169
1170 fail:
1171 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1172 return rc;
1173 }
1174
1175 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1176 unsigned long deadline)
1177 {
1178 int pmp = 0;
1179
1180 if (link->ap->flags & ATA_FLAG_PMP)
1181 pmp = SATA_PMP_CTRL_PORT;
1182
1183 return ahci_do_softreset(link, class, pmp, deadline);
1184 }
1185
1186 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1187 unsigned long deadline)
1188 {
1189 struct ata_port *ap = link->ap;
1190 struct ahci_port_priv *pp = ap->private_data;
1191 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1192 struct ata_taskfile tf;
1193 int rc;
1194
1195 DPRINTK("ENTER\n");
1196
1197 ahci_stop_engine(ap);
1198
1199 /* clear D2H reception area to properly wait for D2H FIS */
1200 ata_tf_init(link->device, &tf);
1201 tf.command = 0x80;
1202 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1203
1204 rc = sata_std_hardreset(link, class, deadline);
1205
1206 ahci_start_engine(ap);
1207
1208 if (rc == 0 && ata_link_online(link))
1209 *class = ahci_dev_classify(ap);
1210 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1211 *class = ATA_DEV_NONE;
1212
1213 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1214 return rc;
1215 }
1216
1217 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1218 unsigned long deadline)
1219 {
1220 struct ata_port *ap = link->ap;
1221 u32 serror;
1222 int rc;
1223
1224 DPRINTK("ENTER\n");
1225
1226 ahci_stop_engine(ap);
1227
1228 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1229 deadline);
1230
1231 /* vt8251 needs SError cleared for the port to operate */
1232 ahci_scr_read(ap, SCR_ERROR, &serror);
1233 ahci_scr_write(ap, SCR_ERROR, serror);
1234
1235 ahci_start_engine(ap);
1236
1237 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1238
1239 /* vt8251 doesn't clear BSY on signature FIS reception,
1240 * request follow-up softreset.
1241 */
1242 return rc ?: -EAGAIN;
1243 }
1244
1245 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1246 unsigned long deadline)
1247 {
1248 struct ata_port *ap = link->ap;
1249 struct ahci_port_priv *pp = ap->private_data;
1250 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1251 struct ata_taskfile tf;
1252 int rc;
1253
1254 ahci_stop_engine(ap);
1255
1256 /* clear D2H reception area to properly wait for D2H FIS */
1257 ata_tf_init(link->device, &tf);
1258 tf.command = 0x80;
1259 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1260
1261 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1262 deadline);
1263
1264 ahci_start_engine(ap);
1265
1266 if (rc || ata_link_offline(link))
1267 return rc;
1268
1269 /* spec mandates ">= 2ms" before checking status */
1270 msleep(150);
1271
1272 /* The pseudo configuration device on SIMG4726 attached to
1273 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1274 * hardreset if no device is attached to the first downstream
1275 * port && the pseudo device locks up on SRST w/ PMP==0. To
1276 * work around this, wait for !BSY only briefly. If BSY isn't
1277 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1278 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1279 *
1280 * Wait for two seconds. Devices attached to downstream port
1281 * which can't process the following IDENTIFY after this will
1282 * have to be reset again. For most cases, this should
1283 * suffice while making probing snappish enough.
1284 */
1285 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1286 if (rc)
1287 ahci_kick_engine(ap, 0);
1288
1289 return 0;
1290 }
1291
1292 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1293 {
1294 struct ata_port *ap = link->ap;
1295 void __iomem *port_mmio = ahci_port_base(ap);
1296 u32 new_tmp, tmp;
1297
1298 ata_std_postreset(link, class);
1299
1300 /* Make sure port's ATAPI bit is set appropriately */
1301 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1302 if (*class == ATA_DEV_ATAPI)
1303 new_tmp |= PORT_CMD_ATAPI;
1304 else
1305 new_tmp &= ~PORT_CMD_ATAPI;
1306 if (new_tmp != tmp) {
1307 writel(new_tmp, port_mmio + PORT_CMD);
1308 readl(port_mmio + PORT_CMD); /* flush */
1309 }
1310 }
1311
1312 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1313 unsigned long deadline)
1314 {
1315 return ahci_do_softreset(link, class, link->pmp, deadline);
1316 }
1317
1318 static u8 ahci_check_status(struct ata_port *ap)
1319 {
1320 void __iomem *mmio = ap->ioaddr.cmd_addr;
1321
1322 return readl(mmio + PORT_TFDATA) & 0xFF;
1323 }
1324
1325 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1326 {
1327 struct ahci_port_priv *pp = ap->private_data;
1328 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1329
1330 ata_tf_from_fis(d2h_fis, tf);
1331 }
1332
1333 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1334 {
1335 struct scatterlist *sg;
1336 struct ahci_sg *ahci_sg;
1337 unsigned int n_sg = 0;
1338
1339 VPRINTK("ENTER\n");
1340
1341 /*
1342 * Next, the S/G list.
1343 */
1344 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1345 ata_for_each_sg(sg, qc) {
1346 dma_addr_t addr = sg_dma_address(sg);
1347 u32 sg_len = sg_dma_len(sg);
1348
1349 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1350 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1351 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1352
1353 ahci_sg++;
1354 n_sg++;
1355 }
1356
1357 return n_sg;
1358 }
1359
1360 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1361 {
1362 struct ata_port *ap = qc->ap;
1363 struct ahci_port_priv *pp = ap->private_data;
1364 int is_atapi = is_atapi_taskfile(&qc->tf);
1365 void *cmd_tbl;
1366 u32 opts;
1367 const u32 cmd_fis_len = 5; /* five dwords */
1368 unsigned int n_elem;
1369
1370 /*
1371 * Fill in command table information. First, the header,
1372 * a SATA Register - Host to Device command FIS.
1373 */
1374 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1375
1376 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1377 if (is_atapi) {
1378 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1379 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1380 }
1381
1382 n_elem = 0;
1383 if (qc->flags & ATA_QCFLAG_DMAMAP)
1384 n_elem = ahci_fill_sg(qc, cmd_tbl);
1385
1386 /*
1387 * Fill in command slot information.
1388 */
1389 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1390 if (qc->tf.flags & ATA_TFLAG_WRITE)
1391 opts |= AHCI_CMD_WRITE;
1392 if (is_atapi)
1393 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1394
1395 ahci_fill_cmd_slot(pp, qc->tag, opts);
1396 }
1397
1398 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1399 {
1400 struct ahci_host_priv *hpriv = ap->host->private_data;
1401 struct ahci_port_priv *pp = ap->private_data;
1402 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1403 struct ata_link *link = NULL;
1404 struct ata_queued_cmd *active_qc;
1405 struct ata_eh_info *active_ehi;
1406 u32 serror;
1407
1408 /* determine active link */
1409 ata_port_for_each_link(link, ap)
1410 if (ata_link_active(link))
1411 break;
1412 if (!link)
1413 link = &ap->link;
1414
1415 active_qc = ata_qc_from_tag(ap, link->active_tag);
1416 active_ehi = &link->eh_info;
1417
1418 /* record irq stat */
1419 ata_ehi_clear_desc(host_ehi);
1420 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1421
1422 /* AHCI needs SError cleared; otherwise, it might lock up */
1423 ahci_scr_read(ap, SCR_ERROR, &serror);
1424 ahci_scr_write(ap, SCR_ERROR, serror);
1425 host_ehi->serror |= serror;
1426
1427 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1428 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1429 irq_stat &= ~PORT_IRQ_IF_ERR;
1430
1431 if (irq_stat & PORT_IRQ_TF_ERR) {
1432 /* If qc is active, charge it; otherwise, the active
1433 * link. There's no active qc on NCQ errors. It will
1434 * be determined by EH by reading log page 10h.
1435 */
1436 if (active_qc)
1437 active_qc->err_mask |= AC_ERR_DEV;
1438 else
1439 active_ehi->err_mask |= AC_ERR_DEV;
1440
1441 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1442 host_ehi->serror &= ~SERR_INTERNAL;
1443 }
1444
1445 if (irq_stat & PORT_IRQ_UNK_FIS) {
1446 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1447
1448 active_ehi->err_mask |= AC_ERR_HSM;
1449 active_ehi->action |= ATA_EH_SOFTRESET;
1450 ata_ehi_push_desc(active_ehi,
1451 "unknown FIS %08x %08x %08x %08x" ,
1452 unk[0], unk[1], unk[2], unk[3]);
1453 }
1454
1455 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1456 active_ehi->err_mask |= AC_ERR_HSM;
1457 active_ehi->action |= ATA_EH_SOFTRESET;
1458 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1459 }
1460
1461 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1462 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1463 host_ehi->action |= ATA_EH_SOFTRESET;
1464 ata_ehi_push_desc(host_ehi, "host bus error");
1465 }
1466
1467 if (irq_stat & PORT_IRQ_IF_ERR) {
1468 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1469 host_ehi->action |= ATA_EH_SOFTRESET;
1470 ata_ehi_push_desc(host_ehi, "interface fatal error");
1471 }
1472
1473 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1474 ata_ehi_hotplugged(host_ehi);
1475 ata_ehi_push_desc(host_ehi, "%s",
1476 irq_stat & PORT_IRQ_CONNECT ?
1477 "connection status changed" : "PHY RDY changed");
1478 }
1479
1480 /* okay, let's hand over to EH */
1481
1482 if (irq_stat & PORT_IRQ_FREEZE)
1483 ata_port_freeze(ap);
1484 else
1485 ata_port_abort(ap);
1486 }
1487
1488 static void ahci_port_intr(struct ata_port *ap)
1489 {
1490 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1491 struct ata_eh_info *ehi = &ap->link.eh_info;
1492 struct ahci_port_priv *pp = ap->private_data;
1493 struct ahci_host_priv *hpriv = ap->host->private_data;
1494 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1495 u32 status, qc_active;
1496 int rc, known_irq = 0;
1497
1498 status = readl(port_mmio + PORT_IRQ_STAT);
1499 writel(status, port_mmio + PORT_IRQ_STAT);
1500
1501 /* ignore BAD_PMP while resetting */
1502 if (unlikely(resetting))
1503 status &= ~PORT_IRQ_BAD_PMP;
1504
1505 if (unlikely(status & PORT_IRQ_ERROR)) {
1506 ahci_error_intr(ap, status);
1507 return;
1508 }
1509
1510 if (status & PORT_IRQ_SDB_FIS) {
1511 /* If SNotification is available, leave notification
1512 * handling to sata_async_notification(). If not,
1513 * emulate it by snooping SDB FIS RX area.
1514 *
1515 * Snooping FIS RX area is probably cheaper than
1516 * poking SNotification but some constrollers which
1517 * implement SNotification, ICH9 for example, don't
1518 * store AN SDB FIS into receive area.
1519 */
1520 if (hpriv->cap & HOST_CAP_SNTF)
1521 sata_async_notification(ap);
1522 else {
1523 /* If the 'N' bit in word 0 of the FIS is set,
1524 * we just received asynchronous notification.
1525 * Tell libata about it.
1526 */
1527 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1528 u32 f0 = le32_to_cpu(f[0]);
1529
1530 if (f0 & (1 << 15))
1531 sata_async_notification(ap);
1532 }
1533 }
1534
1535 /* pp->active_link is valid iff any command is in flight */
1536 if (ap->qc_active && pp->active_link->sactive)
1537 qc_active = readl(port_mmio + PORT_SCR_ACT);
1538 else
1539 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1540
1541 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1542
1543 /* If resetting, spurious or invalid completions are expected,
1544 * return unconditionally.
1545 */
1546 if (resetting)
1547 return;
1548
1549 if (rc > 0)
1550 return;
1551 if (rc < 0) {
1552 ehi->err_mask |= AC_ERR_HSM;
1553 ehi->action |= ATA_EH_SOFTRESET;
1554 ata_port_freeze(ap);
1555 return;
1556 }
1557
1558 /* hmmm... a spurious interrupt */
1559
1560 /* if !NCQ, ignore. No modern ATA device has broken HSM
1561 * implementation for non-NCQ commands.
1562 */
1563 if (!ap->link.sactive)
1564 return;
1565
1566 if (status & PORT_IRQ_D2H_REG_FIS) {
1567 if (!pp->ncq_saw_d2h)
1568 ata_port_printk(ap, KERN_INFO,
1569 "D2H reg with I during NCQ, "
1570 "this message won't be printed again\n");
1571 pp->ncq_saw_d2h = 1;
1572 known_irq = 1;
1573 }
1574
1575 if (status & PORT_IRQ_DMAS_FIS) {
1576 if (!pp->ncq_saw_dmas)
1577 ata_port_printk(ap, KERN_INFO,
1578 "DMAS FIS during NCQ, "
1579 "this message won't be printed again\n");
1580 pp->ncq_saw_dmas = 1;
1581 known_irq = 1;
1582 }
1583
1584 if (status & PORT_IRQ_SDB_FIS) {
1585 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1586
1587 if (le32_to_cpu(f[1])) {
1588 /* SDB FIS containing spurious completions
1589 * might be dangerous, whine and fail commands
1590 * with HSM violation. EH will turn off NCQ
1591 * after several such failures.
1592 */
1593 ata_ehi_push_desc(ehi,
1594 "spurious completions during NCQ "
1595 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1596 readl(port_mmio + PORT_CMD_ISSUE),
1597 readl(port_mmio + PORT_SCR_ACT),
1598 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1599 ehi->err_mask |= AC_ERR_HSM;
1600 ehi->action |= ATA_EH_SOFTRESET;
1601 ata_port_freeze(ap);
1602 } else {
1603 if (!pp->ncq_saw_sdb)
1604 ata_port_printk(ap, KERN_INFO,
1605 "spurious SDB FIS %08x:%08x during NCQ, "
1606 "this message won't be printed again\n",
1607 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1608 pp->ncq_saw_sdb = 1;
1609 }
1610 known_irq = 1;
1611 }
1612
1613 if (!known_irq)
1614 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1615 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1616 status, ap->link.active_tag, ap->link.sactive);
1617 }
1618
1619 static void ahci_irq_clear(struct ata_port *ap)
1620 {
1621 /* TODO */
1622 }
1623
1624 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1625 {
1626 struct ata_host *host = dev_instance;
1627 struct ahci_host_priv *hpriv;
1628 unsigned int i, handled = 0;
1629 void __iomem *mmio;
1630 u32 irq_stat, irq_ack = 0;
1631
1632 VPRINTK("ENTER\n");
1633
1634 hpriv = host->private_data;
1635 mmio = host->iomap[AHCI_PCI_BAR];
1636
1637 /* sigh. 0xffffffff is a valid return from h/w */
1638 irq_stat = readl(mmio + HOST_IRQ_STAT);
1639 irq_stat &= hpriv->port_map;
1640 if (!irq_stat)
1641 return IRQ_NONE;
1642
1643 spin_lock(&host->lock);
1644
1645 for (i = 0; i < host->n_ports; i++) {
1646 struct ata_port *ap;
1647
1648 if (!(irq_stat & (1 << i)))
1649 continue;
1650
1651 ap = host->ports[i];
1652 if (ap) {
1653 ahci_port_intr(ap);
1654 VPRINTK("port %u\n", i);
1655 } else {
1656 VPRINTK("port %u (no irq)\n", i);
1657 if (ata_ratelimit())
1658 dev_printk(KERN_WARNING, host->dev,
1659 "interrupt on disabled port %u\n", i);
1660 }
1661
1662 irq_ack |= (1 << i);
1663 }
1664
1665 if (irq_ack) {
1666 writel(irq_ack, mmio + HOST_IRQ_STAT);
1667 handled = 1;
1668 }
1669
1670 spin_unlock(&host->lock);
1671
1672 VPRINTK("EXIT\n");
1673
1674 return IRQ_RETVAL(handled);
1675 }
1676
1677 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1678 {
1679 struct ata_port *ap = qc->ap;
1680 void __iomem *port_mmio = ahci_port_base(ap);
1681 struct ahci_port_priv *pp = ap->private_data;
1682
1683 /* Keep track of the currently active link. It will be used
1684 * in completion path to determine whether NCQ phase is in
1685 * progress.
1686 */
1687 pp->active_link = qc->dev->link;
1688
1689 if (qc->tf.protocol == ATA_PROT_NCQ)
1690 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1691 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1692 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1693
1694 return 0;
1695 }
1696
1697 static void ahci_freeze(struct ata_port *ap)
1698 {
1699 void __iomem *port_mmio = ahci_port_base(ap);
1700
1701 /* turn IRQ off */
1702 writel(0, port_mmio + PORT_IRQ_MASK);
1703 }
1704
1705 static void ahci_thaw(struct ata_port *ap)
1706 {
1707 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1708 void __iomem *port_mmio = ahci_port_base(ap);
1709 u32 tmp;
1710 struct ahci_port_priv *pp = ap->private_data;
1711
1712 /* clear IRQ */
1713 tmp = readl(port_mmio + PORT_IRQ_STAT);
1714 writel(tmp, port_mmio + PORT_IRQ_STAT);
1715 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1716
1717 /* turn IRQ back on */
1718 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1719 }
1720
1721 static void ahci_error_handler(struct ata_port *ap)
1722 {
1723 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1724 /* restart engine */
1725 ahci_stop_engine(ap);
1726 ahci_start_engine(ap);
1727 }
1728
1729 /* perform recovery */
1730 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1731 ahci_hardreset, ahci_postreset,
1732 sata_pmp_std_prereset, ahci_pmp_softreset,
1733 sata_pmp_std_hardreset, sata_pmp_std_postreset);
1734 }
1735
1736 static void ahci_vt8251_error_handler(struct ata_port *ap)
1737 {
1738 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1739 /* restart engine */
1740 ahci_stop_engine(ap);
1741 ahci_start_engine(ap);
1742 }
1743
1744 /* perform recovery */
1745 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1746 ahci_postreset);
1747 }
1748
1749 static void ahci_p5wdh_error_handler(struct ata_port *ap)
1750 {
1751 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1752 /* restart engine */
1753 ahci_stop_engine(ap);
1754 ahci_start_engine(ap);
1755 }
1756
1757 /* perform recovery */
1758 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1759 ahci_postreset);
1760 }
1761
1762 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1763 {
1764 struct ata_port *ap = qc->ap;
1765
1766 /* make DMA engine forget about the failed command */
1767 if (qc->flags & ATA_QCFLAG_FAILED)
1768 ahci_kick_engine(ap, 1);
1769 }
1770
1771 static void ahci_pmp_attach(struct ata_port *ap)
1772 {
1773 void __iomem *port_mmio = ahci_port_base(ap);
1774 struct ahci_port_priv *pp = ap->private_data;
1775 u32 cmd;
1776
1777 cmd = readl(port_mmio + PORT_CMD);
1778 cmd |= PORT_CMD_PMP;
1779 writel(cmd, port_mmio + PORT_CMD);
1780
1781 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1782 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1783 }
1784
1785 static void ahci_pmp_detach(struct ata_port *ap)
1786 {
1787 void __iomem *port_mmio = ahci_port_base(ap);
1788 struct ahci_port_priv *pp = ap->private_data;
1789 u32 cmd;
1790
1791 cmd = readl(port_mmio + PORT_CMD);
1792 cmd &= ~PORT_CMD_PMP;
1793 writel(cmd, port_mmio + PORT_CMD);
1794
1795 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1796 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1797 }
1798
1799 static int ahci_port_resume(struct ata_port *ap)
1800 {
1801 ahci_power_up(ap);
1802 ahci_start_port(ap);
1803
1804 if (ap->nr_pmp_links)
1805 ahci_pmp_attach(ap);
1806 else
1807 ahci_pmp_detach(ap);
1808
1809 return 0;
1810 }
1811
1812 #ifdef CONFIG_PM
1813 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1814 {
1815 const char *emsg = NULL;
1816 int rc;
1817
1818 rc = ahci_deinit_port(ap, &emsg);
1819 if (rc == 0)
1820 ahci_power_down(ap);
1821 else {
1822 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1823 ahci_start_port(ap);
1824 }
1825
1826 return rc;
1827 }
1828
1829 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1830 {
1831 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1832 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1833 u32 ctl;
1834
1835 if (mesg.event == PM_EVENT_SUSPEND) {
1836 /* AHCI spec rev1.1 section 8.3.3:
1837 * Software must disable interrupts prior to requesting a
1838 * transition of the HBA to D3 state.
1839 */
1840 ctl = readl(mmio + HOST_CTL);
1841 ctl &= ~HOST_IRQ_EN;
1842 writel(ctl, mmio + HOST_CTL);
1843 readl(mmio + HOST_CTL); /* flush */
1844 }
1845
1846 return ata_pci_device_suspend(pdev, mesg);
1847 }
1848
1849 static int ahci_pci_device_resume(struct pci_dev *pdev)
1850 {
1851 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1852 int rc;
1853
1854 rc = ata_pci_device_do_resume(pdev);
1855 if (rc)
1856 return rc;
1857
1858 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1859 rc = ahci_reset_controller(host);
1860 if (rc)
1861 return rc;
1862
1863 ahci_init_controller(host);
1864 }
1865
1866 ata_host_resume(host);
1867
1868 return 0;
1869 }
1870 #endif
1871
1872 static int ahci_port_start(struct ata_port *ap)
1873 {
1874 struct device *dev = ap->host->dev;
1875 struct ahci_port_priv *pp;
1876 void *mem;
1877 dma_addr_t mem_dma;
1878 int rc;
1879
1880 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1881 if (!pp)
1882 return -ENOMEM;
1883
1884 rc = ata_pad_alloc(ap, dev);
1885 if (rc)
1886 return rc;
1887
1888 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1889 GFP_KERNEL);
1890 if (!mem)
1891 return -ENOMEM;
1892 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1893
1894 /*
1895 * First item in chunk of DMA memory: 32-slot command table,
1896 * 32 bytes each in size
1897 */
1898 pp->cmd_slot = mem;
1899 pp->cmd_slot_dma = mem_dma;
1900
1901 mem += AHCI_CMD_SLOT_SZ;
1902 mem_dma += AHCI_CMD_SLOT_SZ;
1903
1904 /*
1905 * Second item: Received-FIS area
1906 */
1907 pp->rx_fis = mem;
1908 pp->rx_fis_dma = mem_dma;
1909
1910 mem += AHCI_RX_FIS_SZ;
1911 mem_dma += AHCI_RX_FIS_SZ;
1912
1913 /*
1914 * Third item: data area for storing a single command
1915 * and its scatter-gather table
1916 */
1917 pp->cmd_tbl = mem;
1918 pp->cmd_tbl_dma = mem_dma;
1919
1920 /*
1921 * Save off initial list of interrupts to be enabled.
1922 * This could be changed later
1923 */
1924 pp->intr_mask = DEF_PORT_IRQ;
1925
1926 ap->private_data = pp;
1927
1928 /* engage engines, captain */
1929 return ahci_port_resume(ap);
1930 }
1931
1932 static void ahci_port_stop(struct ata_port *ap)
1933 {
1934 const char *emsg = NULL;
1935 int rc;
1936
1937 /* de-initialize port */
1938 rc = ahci_deinit_port(ap, &emsg);
1939 if (rc)
1940 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1941 }
1942
1943 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1944 {
1945 int rc;
1946
1947 if (using_dac &&
1948 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1949 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1950 if (rc) {
1951 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1952 if (rc) {
1953 dev_printk(KERN_ERR, &pdev->dev,
1954 "64-bit DMA enable failed\n");
1955 return rc;
1956 }
1957 }
1958 } else {
1959 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1960 if (rc) {
1961 dev_printk(KERN_ERR, &pdev->dev,
1962 "32-bit DMA enable failed\n");
1963 return rc;
1964 }
1965 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1966 if (rc) {
1967 dev_printk(KERN_ERR, &pdev->dev,
1968 "32-bit consistent DMA enable failed\n");
1969 return rc;
1970 }
1971 }
1972 return 0;
1973 }
1974
1975 static void ahci_print_info(struct ata_host *host)
1976 {
1977 struct ahci_host_priv *hpriv = host->private_data;
1978 struct pci_dev *pdev = to_pci_dev(host->dev);
1979 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1980 u32 vers, cap, impl, speed;
1981 const char *speed_s;
1982 u16 cc;
1983 const char *scc_s;
1984
1985 vers = readl(mmio + HOST_VERSION);
1986 cap = hpriv->cap;
1987 impl = hpriv->port_map;
1988
1989 speed = (cap >> 20) & 0xf;
1990 if (speed == 1)
1991 speed_s = "1.5";
1992 else if (speed == 2)
1993 speed_s = "3";
1994 else
1995 speed_s = "?";
1996
1997 pci_read_config_word(pdev, 0x0a, &cc);
1998 if (cc == PCI_CLASS_STORAGE_IDE)
1999 scc_s = "IDE";
2000 else if (cc == PCI_CLASS_STORAGE_SATA)
2001 scc_s = "SATA";
2002 else if (cc == PCI_CLASS_STORAGE_RAID)
2003 scc_s = "RAID";
2004 else
2005 scc_s = "unknown";
2006
2007 dev_printk(KERN_INFO, &pdev->dev,
2008 "AHCI %02x%02x.%02x%02x "
2009 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2010 ,
2011
2012 (vers >> 24) & 0xff,
2013 (vers >> 16) & 0xff,
2014 (vers >> 8) & 0xff,
2015 vers & 0xff,
2016
2017 ((cap >> 8) & 0x1f) + 1,
2018 (cap & 0x1f) + 1,
2019 speed_s,
2020 impl,
2021 scc_s);
2022
2023 dev_printk(KERN_INFO, &pdev->dev,
2024 "flags: "
2025 "%s%s%s%s%s%s%s"
2026 "%s%s%s%s%s%s%s\n"
2027 ,
2028
2029 cap & (1 << 31) ? "64bit " : "",
2030 cap & (1 << 30) ? "ncq " : "",
2031 cap & (1 << 29) ? "sntf " : "",
2032 cap & (1 << 28) ? "ilck " : "",
2033 cap & (1 << 27) ? "stag " : "",
2034 cap & (1 << 26) ? "pm " : "",
2035 cap & (1 << 25) ? "led " : "",
2036
2037 cap & (1 << 24) ? "clo " : "",
2038 cap & (1 << 19) ? "nz " : "",
2039 cap & (1 << 18) ? "only " : "",
2040 cap & (1 << 17) ? "pmp " : "",
2041 cap & (1 << 15) ? "pio " : "",
2042 cap & (1 << 14) ? "slum " : "",
2043 cap & (1 << 13) ? "part " : ""
2044 );
2045 }
2046
2047 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2048 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2049 * support PMP and the 4726 either directly exports the device
2050 * attached to the first downstream port or acts as a hardware storage
2051 * controller and emulate a single ATA device (can be RAID 0/1 or some
2052 * other configuration).
2053 *
2054 * When there's no device attached to the first downstream port of the
2055 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2056 * configure the 4726. However, ATA emulation of the device is very
2057 * lame. It doesn't send signature D2H Reg FIS after the initial
2058 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2059 *
2060 * The following function works around the problem by always using
2061 * hardreset on the port and not depending on receiving signature FIS
2062 * afterward. If signature FIS isn't received soon, ATA class is
2063 * assumed without follow-up softreset.
2064 */
2065 static void ahci_p5wdh_workaround(struct ata_host *host)
2066 {
2067 static struct dmi_system_id sysids[] = {
2068 {
2069 .ident = "P5W DH Deluxe",
2070 .matches = {
2071 DMI_MATCH(DMI_SYS_VENDOR,
2072 "ASUSTEK COMPUTER INC"),
2073 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2074 },
2075 },
2076 { }
2077 };
2078 struct pci_dev *pdev = to_pci_dev(host->dev);
2079
2080 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2081 dmi_check_system(sysids)) {
2082 struct ata_port *ap = host->ports[1];
2083
2084 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2085 "Deluxe on-board SIMG4726 workaround\n");
2086
2087 ap->ops = &ahci_p5wdh_ops;
2088 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2089 }
2090 }
2091
2092 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2093 {
2094 static int printed_version;
2095 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2096 const struct ata_port_info *ppi[] = { &pi, NULL };
2097 struct device *dev = &pdev->dev;
2098 struct ahci_host_priv *hpriv;
2099 struct ata_host *host;
2100 int i, rc;
2101
2102 VPRINTK("ENTER\n");
2103
2104 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2105
2106 if (!printed_version++)
2107 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2108
2109 /* acquire resources */
2110 rc = pcim_enable_device(pdev);
2111 if (rc)
2112 return rc;
2113
2114 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2115 if (rc == -EBUSY)
2116 pcim_pin_device(pdev);
2117 if (rc)
2118 return rc;
2119
2120 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2121 if (!hpriv)
2122 return -ENOMEM;
2123 hpriv->flags |= (unsigned long)pi.private_data;
2124
2125 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2126 pci_intx(pdev, 1);
2127
2128 /* save initial config */
2129 ahci_save_initial_config(pdev, hpriv);
2130
2131 /* prepare host */
2132 if (hpriv->cap & HOST_CAP_NCQ)
2133 pi.flags |= ATA_FLAG_NCQ;
2134
2135 if (hpriv->cap & HOST_CAP_PMP)
2136 pi.flags |= ATA_FLAG_PMP;
2137
2138 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
2139 if (!host)
2140 return -ENOMEM;
2141 host->iomap = pcim_iomap_table(pdev);
2142 host->private_data = hpriv;
2143
2144 for (i = 0; i < host->n_ports; i++) {
2145 struct ata_port *ap = host->ports[i];
2146 void __iomem *port_mmio = ahci_port_base(ap);
2147
2148 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2149 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2150 0x100 + ap->port_no * 0x80, "port");
2151
2152 /* standard SATA port setup */
2153 if (hpriv->port_map & (1 << i))
2154 ap->ioaddr.cmd_addr = port_mmio;
2155
2156 /* disabled/not-implemented port */
2157 else
2158 ap->ops = &ata_dummy_port_ops;
2159 }
2160
2161 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2162 ahci_p5wdh_workaround(host);
2163
2164 /* initialize adapter */
2165 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2166 if (rc)
2167 return rc;
2168
2169 rc = ahci_reset_controller(host);
2170 if (rc)
2171 return rc;
2172
2173 ahci_init_controller(host);
2174 ahci_print_info(host);
2175
2176 pci_set_master(pdev);
2177 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2178 &ahci_sht);
2179 }
2180
2181 static int __init ahci_init(void)
2182 {
2183 return pci_register_driver(&ahci_pci_driver);
2184 }
2185
2186 static void __exit ahci_exit(void)
2187 {
2188 pci_unregister_driver(&ahci_pci_driver);
2189 }
2190
2191
2192 MODULE_AUTHOR("Jeff Garzik");
2193 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2194 MODULE_LICENSE("GPL");
2195 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2196 MODULE_VERSION(DRV_VERSION);
2197
2198 module_init(ahci_init);
2199 module_exit(ahci_exit);
Linux kernel - Deliverables
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