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x86: arch/x86/kernel/machine_kexec_32.c: remove extra semicolons
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58 static void ahci_disable_alpm(struct ata_port *ap);
59
60 enum {
61 AHCI_PCI_BAR = 5,
62 AHCI_MAX_PORTS = 32,
63 AHCI_MAX_SG = 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY = 0xffffffff,
65 AHCI_MAX_CMDS = 32,
66 AHCI_CMD_SZ = 32,
67 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
68 AHCI_RX_FIS_SZ = 256,
69 AHCI_CMD_TBL_CDB = 0x40,
70 AHCI_CMD_TBL_HDR_SZ = 0x80,
71 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
72 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
73 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
74 AHCI_RX_FIS_SZ,
75 AHCI_IRQ_ON_SG = (1 << 31),
76 AHCI_CMD_ATAPI = (1 << 5),
77 AHCI_CMD_WRITE = (1 << 6),
78 AHCI_CMD_PREFETCH = (1 << 7),
79 AHCI_CMD_RESET = (1 << 8),
80 AHCI_CMD_CLR_BUSY = (1 << 10),
81
82 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
83 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
84 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
85
86 board_ahci = 0,
87 board_ahci_vt8251 = 1,
88 board_ahci_ign_iferr = 2,
89 board_ahci_sb600 = 3,
90 board_ahci_mv = 4,
91 board_ahci_sb700 = 5,
92 board_ahci_mcp65 = 6,
93
94 /* global controller registers */
95 HOST_CAP = 0x00, /* host capabilities */
96 HOST_CTL = 0x04, /* global host control */
97 HOST_IRQ_STAT = 0x08, /* interrupt status */
98 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
99 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
100
101 /* HOST_CTL bits */
102 HOST_RESET = (1 << 0), /* reset controller; self-clear */
103 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
104 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
105
106 /* HOST_CAP bits */
107 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
108 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
109 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
110 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
111 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
112 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
113 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
114 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
115
116 /* registers for each SATA port */
117 PORT_LST_ADDR = 0x00, /* command list DMA addr */
118 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
119 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
120 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
121 PORT_IRQ_STAT = 0x10, /* interrupt status */
122 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
123 PORT_CMD = 0x18, /* port command */
124 PORT_TFDATA = 0x20, /* taskfile data */
125 PORT_SIG = 0x24, /* device TF signature */
126 PORT_CMD_ISSUE = 0x38, /* command issue */
127 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
128 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
129 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
130 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
131 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
132
133 /* PORT_IRQ_{STAT,MASK} bits */
134 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
135 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
136 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
137 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
138 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
139 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
140 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
141 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
142
143 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
144 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
145 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
146 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
147 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
148 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
149 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
150 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
151 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
152
153 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
154 PORT_IRQ_IF_ERR |
155 PORT_IRQ_CONNECT |
156 PORT_IRQ_PHYRDY |
157 PORT_IRQ_UNK_FIS |
158 PORT_IRQ_BAD_PMP,
159 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
160 PORT_IRQ_TF_ERR |
161 PORT_IRQ_HBUS_DATA_ERR,
162 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
163 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
164 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
165
166 /* PORT_CMD bits */
167 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
168 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
169 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
170 PORT_CMD_PMP = (1 << 17), /* PMP attached */
171 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
172 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
173 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
174 PORT_CMD_CLO = (1 << 3), /* Command list override */
175 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
176 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
177 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
178
179 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
180 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
181 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
182 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
183
184 /* hpriv->flags bits */
185 AHCI_HFLAG_NO_NCQ = (1 << 0),
186 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
187 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
188 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
189 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
190 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
191 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
192 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
193 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
194 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
195
196 /* ap->flags bits */
197
198 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
199 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
200 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
201 ATA_FLAG_IPM,
202
203 ICH_MAP = 0x90, /* ICH MAP register */
204 };
205
206 struct ahci_cmd_hdr {
207 __le32 opts;
208 __le32 status;
209 __le32 tbl_addr;
210 __le32 tbl_addr_hi;
211 __le32 reserved[4];
212 };
213
214 struct ahci_sg {
215 __le32 addr;
216 __le32 addr_hi;
217 __le32 reserved;
218 __le32 flags_size;
219 };
220
221 struct ahci_host_priv {
222 unsigned int flags; /* AHCI_HFLAG_* */
223 u32 cap; /* cap to use */
224 u32 port_map; /* port map to use */
225 u32 saved_cap; /* saved initial cap */
226 u32 saved_port_map; /* saved initial port_map */
227 };
228
229 struct ahci_port_priv {
230 struct ata_link *active_link;
231 struct ahci_cmd_hdr *cmd_slot;
232 dma_addr_t cmd_slot_dma;
233 void *cmd_tbl;
234 dma_addr_t cmd_tbl_dma;
235 void *rx_fis;
236 dma_addr_t rx_fis_dma;
237 /* for NCQ spurious interrupt analysis */
238 unsigned int ncq_saw_d2h:1;
239 unsigned int ncq_saw_dmas:1;
240 unsigned int ncq_saw_sdb:1;
241 u32 intr_mask; /* interrupts to enable */
242 };
243
244 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
245 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
246 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
247 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
248 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
249 static int ahci_port_start(struct ata_port *ap);
250 static void ahci_port_stop(struct ata_port *ap);
251 static void ahci_qc_prep(struct ata_queued_cmd *qc);
252 static void ahci_freeze(struct ata_port *ap);
253 static void ahci_thaw(struct ata_port *ap);
254 static void ahci_pmp_attach(struct ata_port *ap);
255 static void ahci_pmp_detach(struct ata_port *ap);
256 static int ahci_softreset(struct ata_link *link, unsigned int *class,
257 unsigned long deadline);
258 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
259 unsigned long deadline);
260 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
261 unsigned long deadline);
262 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
263 unsigned long deadline);
264 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
265 unsigned long deadline);
266 static void ahci_postreset(struct ata_link *link, unsigned int *class);
267 static void ahci_error_handler(struct ata_port *ap);
268 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
269 static int ahci_port_resume(struct ata_port *ap);
270 static void ahci_dev_config(struct ata_device *dev);
271 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
272 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
273 u32 opts);
274 #ifdef CONFIG_PM
275 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
276 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
277 static int ahci_pci_device_resume(struct pci_dev *pdev);
278 #endif
279
280 static struct device_attribute *ahci_shost_attrs[] = {
281 &dev_attr_link_power_management_policy,
282 NULL
283 };
284
285 static struct scsi_host_template ahci_sht = {
286 ATA_NCQ_SHT(DRV_NAME),
287 .can_queue = AHCI_MAX_CMDS - 1,
288 .sg_tablesize = AHCI_MAX_SG,
289 .dma_boundary = AHCI_DMA_BOUNDARY,
290 .shost_attrs = ahci_shost_attrs,
291 };
292
293 static struct ata_port_operations ahci_ops = {
294 .inherits = &sata_pmp_port_ops,
295
296 .qc_defer = sata_pmp_qc_defer_cmd_switch,
297 .qc_prep = ahci_qc_prep,
298 .qc_issue = ahci_qc_issue,
299 .qc_fill_rtf = ahci_qc_fill_rtf,
300
301 .freeze = ahci_freeze,
302 .thaw = ahci_thaw,
303 .softreset = ahci_softreset,
304 .hardreset = ahci_hardreset,
305 .postreset = ahci_postreset,
306 .pmp_softreset = ahci_softreset,
307 .error_handler = ahci_error_handler,
308 .post_internal_cmd = ahci_post_internal_cmd,
309 .dev_config = ahci_dev_config,
310
311 .scr_read = ahci_scr_read,
312 .scr_write = ahci_scr_write,
313 .pmp_attach = ahci_pmp_attach,
314 .pmp_detach = ahci_pmp_detach,
315
316 .enable_pm = ahci_enable_alpm,
317 .disable_pm = ahci_disable_alpm,
318 #ifdef CONFIG_PM
319 .port_suspend = ahci_port_suspend,
320 .port_resume = ahci_port_resume,
321 #endif
322 .port_start = ahci_port_start,
323 .port_stop = ahci_port_stop,
324 };
325
326 static struct ata_port_operations ahci_vt8251_ops = {
327 .inherits = &ahci_ops,
328 .hardreset = ahci_vt8251_hardreset,
329 };
330
331 static struct ata_port_operations ahci_p5wdh_ops = {
332 .inherits = &ahci_ops,
333 .hardreset = ahci_p5wdh_hardreset,
334 };
335
336 static struct ata_port_operations ahci_sb600_ops = {
337 .inherits = &ahci_ops,
338 .softreset = ahci_sb600_softreset,
339 .pmp_softreset = ahci_sb600_softreset,
340 };
341
342 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
343
344 static const struct ata_port_info ahci_port_info[] = {
345 /* board_ahci */
346 {
347 .flags = AHCI_FLAG_COMMON,
348 .pio_mask = 0x1f, /* pio0-4 */
349 .udma_mask = ATA_UDMA6,
350 .port_ops = &ahci_ops,
351 },
352 /* board_ahci_vt8251 */
353 {
354 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
355 .flags = AHCI_FLAG_COMMON,
356 .pio_mask = 0x1f, /* pio0-4 */
357 .udma_mask = ATA_UDMA6,
358 .port_ops = &ahci_vt8251_ops,
359 },
360 /* board_ahci_ign_iferr */
361 {
362 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
363 .flags = AHCI_FLAG_COMMON,
364 .pio_mask = 0x1f, /* pio0-4 */
365 .udma_mask = ATA_UDMA6,
366 .port_ops = &ahci_ops,
367 },
368 /* board_ahci_sb600 */
369 {
370 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
371 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
372 AHCI_HFLAG_SECT255),
373 .flags = AHCI_FLAG_COMMON,
374 .pio_mask = 0x1f, /* pio0-4 */
375 .udma_mask = ATA_UDMA6,
376 .port_ops = &ahci_sb600_ops,
377 },
378 /* board_ahci_mv */
379 {
380 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
381 AHCI_HFLAG_MV_PATA),
382 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
383 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
384 .pio_mask = 0x1f, /* pio0-4 */
385 .udma_mask = ATA_UDMA6,
386 .port_ops = &ahci_ops,
387 },
388 /* board_ahci_sb700 */
389 {
390 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
391 .flags = AHCI_FLAG_COMMON,
392 .pio_mask = 0x1f, /* pio0-4 */
393 .udma_mask = ATA_UDMA6,
394 .port_ops = &ahci_sb600_ops,
395 },
396 /* board_ahci_mcp65 */
397 {
398 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
399 .flags = AHCI_FLAG_COMMON,
400 .pio_mask = 0x1f, /* pio0-4 */
401 .udma_mask = ATA_UDMA6,
402 .port_ops = &ahci_ops,
403 },
404 };
405
406 static const struct pci_device_id ahci_pci_tbl[] = {
407 /* Intel */
408 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
409 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
410 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
411 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
412 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
413 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
414 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
415 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
416 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
417 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
418 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
419 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
420 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
421 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
422 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
423 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
424 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
425 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
426 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
427 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
428 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
429 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
430 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
431 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
432 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
433 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
434 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
435 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
436 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
437 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
438 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
439
440 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
441 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
442 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
443
444 /* ATI */
445 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
446 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
447 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
448 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
449 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
450 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
451 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
452
453 /* VIA */
454 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
455 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
456
457 /* NVIDIA */
458 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
459 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
460 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
461 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
462 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
463 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
464 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
465 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
466 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
470 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
471 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
472 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
473 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
474 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
475 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
476 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
477 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
478 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
479 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
480 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
481 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
482 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
483 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
484 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
485 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
486 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
487 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
488 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
489 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
490 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
491 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
492 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
493 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
494 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
495 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
496 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
497 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
498 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
499 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
500 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
501 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
502 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
503 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
504 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
505 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
506 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
507 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
508 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
509 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
510 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
511 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
512 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
513 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
514 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
515 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
516 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
517 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
518 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
519 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
520 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
521 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
522 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
523 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
524 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
525 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
526
527 /* SiS */
528 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
529 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
530 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
531
532 /* Marvell */
533 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
534 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
535
536 /* Generic, PCI class code for AHCI */
537 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
538 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
539
540 { } /* terminate list */
541 };
542
543
544 static struct pci_driver ahci_pci_driver = {
545 .name = DRV_NAME,
546 .id_table = ahci_pci_tbl,
547 .probe = ahci_init_one,
548 .remove = ata_pci_remove_one,
549 #ifdef CONFIG_PM
550 .suspend = ahci_pci_device_suspend,
551 .resume = ahci_pci_device_resume,
552 #endif
553 };
554
555
556 static inline int ahci_nr_ports(u32 cap)
557 {
558 return (cap & 0x1f) + 1;
559 }
560
561 static inline void __iomem *__ahci_port_base(struct ata_host *host,
562 unsigned int port_no)
563 {
564 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
565
566 return mmio + 0x100 + (port_no * 0x80);
567 }
568
569 static inline void __iomem *ahci_port_base(struct ata_port *ap)
570 {
571 return __ahci_port_base(ap->host, ap->port_no);
572 }
573
574 static void ahci_enable_ahci(void __iomem *mmio)
575 {
576 int i;
577 u32 tmp;
578
579 /* turn on AHCI_EN */
580 tmp = readl(mmio + HOST_CTL);
581 if (tmp & HOST_AHCI_EN)
582 return;
583
584 /* Some controllers need AHCI_EN to be written multiple times.
585 * Try a few times before giving up.
586 */
587 for (i = 0; i < 5; i++) {
588 tmp |= HOST_AHCI_EN;
589 writel(tmp, mmio + HOST_CTL);
590 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
591 if (tmp & HOST_AHCI_EN)
592 return;
593 msleep(10);
594 }
595
596 WARN_ON(1);
597 }
598
599 /**
600 * ahci_save_initial_config - Save and fixup initial config values
601 * @pdev: target PCI device
602 * @hpriv: host private area to store config values
603 *
604 * Some registers containing configuration info might be setup by
605 * BIOS and might be cleared on reset. This function saves the
606 * initial values of those registers into @hpriv such that they
607 * can be restored after controller reset.
608 *
609 * If inconsistent, config values are fixed up by this function.
610 *
611 * LOCKING:
612 * None.
613 */
614 static void ahci_save_initial_config(struct pci_dev *pdev,
615 struct ahci_host_priv *hpriv)
616 {
617 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
618 u32 cap, port_map;
619 int i;
620 int mv;
621
622 /* make sure AHCI mode is enabled before accessing CAP */
623 ahci_enable_ahci(mmio);
624
625 /* Values prefixed with saved_ are written back to host after
626 * reset. Values without are used for driver operation.
627 */
628 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
629 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
630
631 /* some chips have errata preventing 64bit use */
632 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
633 dev_printk(KERN_INFO, &pdev->dev,
634 "controller can't do 64bit DMA, forcing 32bit\n");
635 cap &= ~HOST_CAP_64;
636 }
637
638 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
639 dev_printk(KERN_INFO, &pdev->dev,
640 "controller can't do NCQ, turning off CAP_NCQ\n");
641 cap &= ~HOST_CAP_NCQ;
642 }
643
644 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
645 dev_printk(KERN_INFO, &pdev->dev,
646 "controller can do NCQ, turning on CAP_NCQ\n");
647 cap |= HOST_CAP_NCQ;
648 }
649
650 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
651 dev_printk(KERN_INFO, &pdev->dev,
652 "controller can't do PMP, turning off CAP_PMP\n");
653 cap &= ~HOST_CAP_PMP;
654 }
655
656 /*
657 * Temporary Marvell 6145 hack: PATA port presence
658 * is asserted through the standard AHCI port
659 * presence register, as bit 4 (counting from 0)
660 */
661 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
662 if (pdev->device == 0x6121)
663 mv = 0x3;
664 else
665 mv = 0xf;
666 dev_printk(KERN_ERR, &pdev->dev,
667 "MV_AHCI HACK: port_map %x -> %x\n",
668 port_map,
669 port_map & mv);
670
671 port_map &= mv;
672 }
673
674 /* cross check port_map and cap.n_ports */
675 if (port_map) {
676 int map_ports = 0;
677
678 for (i = 0; i < AHCI_MAX_PORTS; i++)
679 if (port_map & (1 << i))
680 map_ports++;
681
682 /* If PI has more ports than n_ports, whine, clear
683 * port_map and let it be generated from n_ports.
684 */
685 if (map_ports > ahci_nr_ports(cap)) {
686 dev_printk(KERN_WARNING, &pdev->dev,
687 "implemented port map (0x%x) contains more "
688 "ports than nr_ports (%u), using nr_ports\n",
689 port_map, ahci_nr_ports(cap));
690 port_map = 0;
691 }
692 }
693
694 /* fabricate port_map from cap.nr_ports */
695 if (!port_map) {
696 port_map = (1 << ahci_nr_ports(cap)) - 1;
697 dev_printk(KERN_WARNING, &pdev->dev,
698 "forcing PORTS_IMPL to 0x%x\n", port_map);
699
700 /* write the fixed up value to the PI register */
701 hpriv->saved_port_map = port_map;
702 }
703
704 /* record values to use during operation */
705 hpriv->cap = cap;
706 hpriv->port_map = port_map;
707 }
708
709 /**
710 * ahci_restore_initial_config - Restore initial config
711 * @host: target ATA host
712 *
713 * Restore initial config stored by ahci_save_initial_config().
714 *
715 * LOCKING:
716 * None.
717 */
718 static void ahci_restore_initial_config(struct ata_host *host)
719 {
720 struct ahci_host_priv *hpriv = host->private_data;
721 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
722
723 writel(hpriv->saved_cap, mmio + HOST_CAP);
724 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
725 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
726 }
727
728 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
729 {
730 static const int offset[] = {
731 [SCR_STATUS] = PORT_SCR_STAT,
732 [SCR_CONTROL] = PORT_SCR_CTL,
733 [SCR_ERROR] = PORT_SCR_ERR,
734 [SCR_ACTIVE] = PORT_SCR_ACT,
735 [SCR_NOTIFICATION] = PORT_SCR_NTF,
736 };
737 struct ahci_host_priv *hpriv = ap->host->private_data;
738
739 if (sc_reg < ARRAY_SIZE(offset) &&
740 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
741 return offset[sc_reg];
742 return 0;
743 }
744
745 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
746 {
747 void __iomem *port_mmio = ahci_port_base(ap);
748 int offset = ahci_scr_offset(ap, sc_reg);
749
750 if (offset) {
751 *val = readl(port_mmio + offset);
752 return 0;
753 }
754 return -EINVAL;
755 }
756
757 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
758 {
759 void __iomem *port_mmio = ahci_port_base(ap);
760 int offset = ahci_scr_offset(ap, sc_reg);
761
762 if (offset) {
763 writel(val, port_mmio + offset);
764 return 0;
765 }
766 return -EINVAL;
767 }
768
769 static void ahci_start_engine(struct ata_port *ap)
770 {
771 void __iomem *port_mmio = ahci_port_base(ap);
772 u32 tmp;
773
774 /* start DMA */
775 tmp = readl(port_mmio + PORT_CMD);
776 tmp |= PORT_CMD_START;
777 writel(tmp, port_mmio + PORT_CMD);
778 readl(port_mmio + PORT_CMD); /* flush */
779 }
780
781 static int ahci_stop_engine(struct ata_port *ap)
782 {
783 void __iomem *port_mmio = ahci_port_base(ap);
784 u32 tmp;
785
786 tmp = readl(port_mmio + PORT_CMD);
787
788 /* check if the HBA is idle */
789 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
790 return 0;
791
792 /* setting HBA to idle */
793 tmp &= ~PORT_CMD_START;
794 writel(tmp, port_mmio + PORT_CMD);
795
796 /* wait for engine to stop. This could be as long as 500 msec */
797 tmp = ata_wait_register(port_mmio + PORT_CMD,
798 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
799 if (tmp & PORT_CMD_LIST_ON)
800 return -EIO;
801
802 return 0;
803 }
804
805 static void ahci_start_fis_rx(struct ata_port *ap)
806 {
807 void __iomem *port_mmio = ahci_port_base(ap);
808 struct ahci_host_priv *hpriv = ap->host->private_data;
809 struct ahci_port_priv *pp = ap->private_data;
810 u32 tmp;
811
812 /* set FIS registers */
813 if (hpriv->cap & HOST_CAP_64)
814 writel((pp->cmd_slot_dma >> 16) >> 16,
815 port_mmio + PORT_LST_ADDR_HI);
816 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
817
818 if (hpriv->cap & HOST_CAP_64)
819 writel((pp->rx_fis_dma >> 16) >> 16,
820 port_mmio + PORT_FIS_ADDR_HI);
821 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
822
823 /* enable FIS reception */
824 tmp = readl(port_mmio + PORT_CMD);
825 tmp |= PORT_CMD_FIS_RX;
826 writel(tmp, port_mmio + PORT_CMD);
827
828 /* flush */
829 readl(port_mmio + PORT_CMD);
830 }
831
832 static int ahci_stop_fis_rx(struct ata_port *ap)
833 {
834 void __iomem *port_mmio = ahci_port_base(ap);
835 u32 tmp;
836
837 /* disable FIS reception */
838 tmp = readl(port_mmio + PORT_CMD);
839 tmp &= ~PORT_CMD_FIS_RX;
840 writel(tmp, port_mmio + PORT_CMD);
841
842 /* wait for completion, spec says 500ms, give it 1000 */
843 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
844 PORT_CMD_FIS_ON, 10, 1000);
845 if (tmp & PORT_CMD_FIS_ON)
846 return -EBUSY;
847
848 return 0;
849 }
850
851 static void ahci_power_up(struct ata_port *ap)
852 {
853 struct ahci_host_priv *hpriv = ap->host->private_data;
854 void __iomem *port_mmio = ahci_port_base(ap);
855 u32 cmd;
856
857 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
858
859 /* spin up device */
860 if (hpriv->cap & HOST_CAP_SSS) {
861 cmd |= PORT_CMD_SPIN_UP;
862 writel(cmd, port_mmio + PORT_CMD);
863 }
864
865 /* wake up link */
866 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
867 }
868
869 static void ahci_disable_alpm(struct ata_port *ap)
870 {
871 struct ahci_host_priv *hpriv = ap->host->private_data;
872 void __iomem *port_mmio = ahci_port_base(ap);
873 u32 cmd;
874 struct ahci_port_priv *pp = ap->private_data;
875
876 /* IPM bits should be disabled by libata-core */
877 /* get the existing command bits */
878 cmd = readl(port_mmio + PORT_CMD);
879
880 /* disable ALPM and ASP */
881 cmd &= ~PORT_CMD_ASP;
882 cmd &= ~PORT_CMD_ALPE;
883
884 /* force the interface back to active */
885 cmd |= PORT_CMD_ICC_ACTIVE;
886
887 /* write out new cmd value */
888 writel(cmd, port_mmio + PORT_CMD);
889 cmd = readl(port_mmio + PORT_CMD);
890
891 /* wait 10ms to be sure we've come out of any low power state */
892 msleep(10);
893
894 /* clear out any PhyRdy stuff from interrupt status */
895 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
896
897 /* go ahead and clean out PhyRdy Change from Serror too */
898 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
899
900 /*
901 * Clear flag to indicate that we should ignore all PhyRdy
902 * state changes
903 */
904 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
905
906 /*
907 * Enable interrupts on Phy Ready.
908 */
909 pp->intr_mask |= PORT_IRQ_PHYRDY;
910 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
911
912 /*
913 * don't change the link pm policy - we can be called
914 * just to turn of link pm temporarily
915 */
916 }
917
918 static int ahci_enable_alpm(struct ata_port *ap,
919 enum link_pm policy)
920 {
921 struct ahci_host_priv *hpriv = ap->host->private_data;
922 void __iomem *port_mmio = ahci_port_base(ap);
923 u32 cmd;
924 struct ahci_port_priv *pp = ap->private_data;
925 u32 asp;
926
927 /* Make sure the host is capable of link power management */
928 if (!(hpriv->cap & HOST_CAP_ALPM))
929 return -EINVAL;
930
931 switch (policy) {
932 case MAX_PERFORMANCE:
933 case NOT_AVAILABLE:
934 /*
935 * if we came here with NOT_AVAILABLE,
936 * it just means this is the first time we
937 * have tried to enable - default to max performance,
938 * and let the user go to lower power modes on request.
939 */
940 ahci_disable_alpm(ap);
941 return 0;
942 case MIN_POWER:
943 /* configure HBA to enter SLUMBER */
944 asp = PORT_CMD_ASP;
945 break;
946 case MEDIUM_POWER:
947 /* configure HBA to enter PARTIAL */
948 asp = 0;
949 break;
950 default:
951 return -EINVAL;
952 }
953
954 /*
955 * Disable interrupts on Phy Ready. This keeps us from
956 * getting woken up due to spurious phy ready interrupts
957 * TBD - Hot plug should be done via polling now, is
958 * that even supported?
959 */
960 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
961 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
962
963 /*
964 * Set a flag to indicate that we should ignore all PhyRdy
965 * state changes since these can happen now whenever we
966 * change link state
967 */
968 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
969
970 /* get the existing command bits */
971 cmd = readl(port_mmio + PORT_CMD);
972
973 /*
974 * Set ASP based on Policy
975 */
976 cmd |= asp;
977
978 /*
979 * Setting this bit will instruct the HBA to aggressively
980 * enter a lower power link state when it's appropriate and
981 * based on the value set above for ASP
982 */
983 cmd |= PORT_CMD_ALPE;
984
985 /* write out new cmd value */
986 writel(cmd, port_mmio + PORT_CMD);
987 cmd = readl(port_mmio + PORT_CMD);
988
989 /* IPM bits should be set by libata-core */
990 return 0;
991 }
992
993 #ifdef CONFIG_PM
994 static void ahci_power_down(struct ata_port *ap)
995 {
996 struct ahci_host_priv *hpriv = ap->host->private_data;
997 void __iomem *port_mmio = ahci_port_base(ap);
998 u32 cmd, scontrol;
999
1000 if (!(hpriv->cap & HOST_CAP_SSS))
1001 return;
1002
1003 /* put device into listen mode, first set PxSCTL.DET to 0 */
1004 scontrol = readl(port_mmio + PORT_SCR_CTL);
1005 scontrol &= ~0xf;
1006 writel(scontrol, port_mmio + PORT_SCR_CTL);
1007
1008 /* then set PxCMD.SUD to 0 */
1009 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1010 cmd &= ~PORT_CMD_SPIN_UP;
1011 writel(cmd, port_mmio + PORT_CMD);
1012 }
1013 #endif
1014
1015 static void ahci_start_port(struct ata_port *ap)
1016 {
1017 /* enable FIS reception */
1018 ahci_start_fis_rx(ap);
1019
1020 /* enable DMA */
1021 ahci_start_engine(ap);
1022 }
1023
1024 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1025 {
1026 int rc;
1027
1028 /* disable DMA */
1029 rc = ahci_stop_engine(ap);
1030 if (rc) {
1031 *emsg = "failed to stop engine";
1032 return rc;
1033 }
1034
1035 /* disable FIS reception */
1036 rc = ahci_stop_fis_rx(ap);
1037 if (rc) {
1038 *emsg = "failed stop FIS RX";
1039 return rc;
1040 }
1041
1042 return 0;
1043 }
1044
1045 static int ahci_reset_controller(struct ata_host *host)
1046 {
1047 struct pci_dev *pdev = to_pci_dev(host->dev);
1048 struct ahci_host_priv *hpriv = host->private_data;
1049 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1050 u32 tmp;
1051
1052 /* we must be in AHCI mode, before using anything
1053 * AHCI-specific, such as HOST_RESET.
1054 */
1055 ahci_enable_ahci(mmio);
1056
1057 /* global controller reset */
1058 if (!ahci_skip_host_reset) {
1059 tmp = readl(mmio + HOST_CTL);
1060 if ((tmp & HOST_RESET) == 0) {
1061 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1062 readl(mmio + HOST_CTL); /* flush */
1063 }
1064
1065 /* reset must complete within 1 second, or
1066 * the hardware should be considered fried.
1067 */
1068 ssleep(1);
1069
1070 tmp = readl(mmio + HOST_CTL);
1071 if (tmp & HOST_RESET) {
1072 dev_printk(KERN_ERR, host->dev,
1073 "controller reset failed (0x%x)\n", tmp);
1074 return -EIO;
1075 }
1076
1077 /* turn on AHCI mode */
1078 ahci_enable_ahci(mmio);
1079
1080 /* Some registers might be cleared on reset. Restore
1081 * initial values.
1082 */
1083 ahci_restore_initial_config(host);
1084 } else
1085 dev_printk(KERN_INFO, host->dev,
1086 "skipping global host reset\n");
1087
1088 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1089 u16 tmp16;
1090
1091 /* configure PCS */
1092 pci_read_config_word(pdev, 0x92, &tmp16);
1093 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1094 tmp16 |= hpriv->port_map;
1095 pci_write_config_word(pdev, 0x92, tmp16);
1096 }
1097 }
1098
1099 return 0;
1100 }
1101
1102 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1103 int port_no, void __iomem *mmio,
1104 void __iomem *port_mmio)
1105 {
1106 const char *emsg = NULL;
1107 int rc;
1108 u32 tmp;
1109
1110 /* make sure port is not active */
1111 rc = ahci_deinit_port(ap, &emsg);
1112 if (rc)
1113 dev_printk(KERN_WARNING, &pdev->dev,
1114 "%s (%d)\n", emsg, rc);
1115
1116 /* clear SError */
1117 tmp = readl(port_mmio + PORT_SCR_ERR);
1118 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1119 writel(tmp, port_mmio + PORT_SCR_ERR);
1120
1121 /* clear port IRQ */
1122 tmp = readl(port_mmio + PORT_IRQ_STAT);
1123 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1124 if (tmp)
1125 writel(tmp, port_mmio + PORT_IRQ_STAT);
1126
1127 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1128 }
1129
1130 static void ahci_init_controller(struct ata_host *host)
1131 {
1132 struct ahci_host_priv *hpriv = host->private_data;
1133 struct pci_dev *pdev = to_pci_dev(host->dev);
1134 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1135 int i;
1136 void __iomem *port_mmio;
1137 u32 tmp;
1138 int mv;
1139
1140 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1141 if (pdev->device == 0x6121)
1142 mv = 2;
1143 else
1144 mv = 4;
1145 port_mmio = __ahci_port_base(host, mv);
1146
1147 writel(0, port_mmio + PORT_IRQ_MASK);
1148
1149 /* clear port IRQ */
1150 tmp = readl(port_mmio + PORT_IRQ_STAT);
1151 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1152 if (tmp)
1153 writel(tmp, port_mmio + PORT_IRQ_STAT);
1154 }
1155
1156 for (i = 0; i < host->n_ports; i++) {
1157 struct ata_port *ap = host->ports[i];
1158
1159 port_mmio = ahci_port_base(ap);
1160 if (ata_port_is_dummy(ap))
1161 continue;
1162
1163 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1164 }
1165
1166 tmp = readl(mmio + HOST_CTL);
1167 VPRINTK("HOST_CTL 0x%x\n", tmp);
1168 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1169 tmp = readl(mmio + HOST_CTL);
1170 VPRINTK("HOST_CTL 0x%x\n", tmp);
1171 }
1172
1173 static void ahci_dev_config(struct ata_device *dev)
1174 {
1175 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1176
1177 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1178 dev->max_sectors = 255;
1179 ata_dev_printk(dev, KERN_INFO,
1180 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1181 }
1182 }
1183
1184 static unsigned int ahci_dev_classify(struct ata_port *ap)
1185 {
1186 void __iomem *port_mmio = ahci_port_base(ap);
1187 struct ata_taskfile tf;
1188 u32 tmp;
1189
1190 tmp = readl(port_mmio + PORT_SIG);
1191 tf.lbah = (tmp >> 24) & 0xff;
1192 tf.lbam = (tmp >> 16) & 0xff;
1193 tf.lbal = (tmp >> 8) & 0xff;
1194 tf.nsect = (tmp) & 0xff;
1195
1196 return ata_dev_classify(&tf);
1197 }
1198
1199 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1200 u32 opts)
1201 {
1202 dma_addr_t cmd_tbl_dma;
1203
1204 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1205
1206 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1207 pp->cmd_slot[tag].status = 0;
1208 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1209 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1210 }
1211
1212 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1213 {
1214 void __iomem *port_mmio = ahci_port_base(ap);
1215 struct ahci_host_priv *hpriv = ap->host->private_data;
1216 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1217 u32 tmp;
1218 int busy, rc;
1219
1220 /* do we need to kick the port? */
1221 busy = status & (ATA_BUSY | ATA_DRQ);
1222 if (!busy && !force_restart)
1223 return 0;
1224
1225 /* stop engine */
1226 rc = ahci_stop_engine(ap);
1227 if (rc)
1228 goto out_restart;
1229
1230 /* need to do CLO? */
1231 if (!busy) {
1232 rc = 0;
1233 goto out_restart;
1234 }
1235
1236 if (!(hpriv->cap & HOST_CAP_CLO)) {
1237 rc = -EOPNOTSUPP;
1238 goto out_restart;
1239 }
1240
1241 /* perform CLO */
1242 tmp = readl(port_mmio + PORT_CMD);
1243 tmp |= PORT_CMD_CLO;
1244 writel(tmp, port_mmio + PORT_CMD);
1245
1246 rc = 0;
1247 tmp = ata_wait_register(port_mmio + PORT_CMD,
1248 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1249 if (tmp & PORT_CMD_CLO)
1250 rc = -EIO;
1251
1252 /* restart engine */
1253 out_restart:
1254 ahci_start_engine(ap);
1255 return rc;
1256 }
1257
1258 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1259 struct ata_taskfile *tf, int is_cmd, u16 flags,
1260 unsigned long timeout_msec)
1261 {
1262 const u32 cmd_fis_len = 5; /* five dwords */
1263 struct ahci_port_priv *pp = ap->private_data;
1264 void __iomem *port_mmio = ahci_port_base(ap);
1265 u8 *fis = pp->cmd_tbl;
1266 u32 tmp;
1267
1268 /* prep the command */
1269 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1270 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1271
1272 /* issue & wait */
1273 writel(1, port_mmio + PORT_CMD_ISSUE);
1274
1275 if (timeout_msec) {
1276 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1277 1, timeout_msec);
1278 if (tmp & 0x1) {
1279 ahci_kick_engine(ap, 1);
1280 return -EBUSY;
1281 }
1282 } else
1283 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1284
1285 return 0;
1286 }
1287
1288 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1289 int pmp, unsigned long deadline,
1290 int (*check_ready)(struct ata_link *link))
1291 {
1292 struct ata_port *ap = link->ap;
1293 const char *reason = NULL;
1294 unsigned long now, msecs;
1295 struct ata_taskfile tf;
1296 int rc;
1297
1298 DPRINTK("ENTER\n");
1299
1300 /* prepare for SRST (AHCI-1.1 10.4.1) */
1301 rc = ahci_kick_engine(ap, 1);
1302 if (rc && rc != -EOPNOTSUPP)
1303 ata_link_printk(link, KERN_WARNING,
1304 "failed to reset engine (errno=%d)\n", rc);
1305
1306 ata_tf_init(link->device, &tf);
1307
1308 /* issue the first D2H Register FIS */
1309 msecs = 0;
1310 now = jiffies;
1311 if (time_after(now, deadline))
1312 msecs = jiffies_to_msecs(deadline - now);
1313
1314 tf.ctl |= ATA_SRST;
1315 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1316 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1317 rc = -EIO;
1318 reason = "1st FIS failed";
1319 goto fail;
1320 }
1321
1322 /* spec says at least 5us, but be generous and sleep for 1ms */
1323 msleep(1);
1324
1325 /* issue the second D2H Register FIS */
1326 tf.ctl &= ~ATA_SRST;
1327 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1328
1329 /* wait for link to become ready */
1330 rc = ata_wait_after_reset(link, deadline, check_ready);
1331 /* link occupied, -ENODEV too is an error */
1332 if (rc) {
1333 reason = "device not ready";
1334 goto fail;
1335 }
1336 *class = ahci_dev_classify(ap);
1337
1338 DPRINTK("EXIT, class=%u\n", *class);
1339 return 0;
1340
1341 fail:
1342 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1343 return rc;
1344 }
1345
1346 static int ahci_check_ready(struct ata_link *link)
1347 {
1348 void __iomem *port_mmio = ahci_port_base(link->ap);
1349 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1350
1351 return ata_check_ready(status);
1352 }
1353
1354 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1355 unsigned long deadline)
1356 {
1357 int pmp = sata_srst_pmp(link);
1358
1359 DPRINTK("ENTER\n");
1360
1361 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1362 }
1363
1364 static int ahci_sb600_check_ready(struct ata_link *link)
1365 {
1366 void __iomem *port_mmio = ahci_port_base(link->ap);
1367 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1368 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1369
1370 /*
1371 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1372 * which can save timeout delay.
1373 */
1374 if (irq_status & PORT_IRQ_BAD_PMP)
1375 return -EIO;
1376
1377 return ata_check_ready(status);
1378 }
1379
1380 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1381 unsigned long deadline)
1382 {
1383 struct ata_port *ap = link->ap;
1384 void __iomem *port_mmio = ahci_port_base(ap);
1385 int pmp = sata_srst_pmp(link);
1386 int rc;
1387 u32 irq_sts;
1388
1389 DPRINTK("ENTER\n");
1390
1391 rc = ahci_do_softreset(link, class, pmp, deadline,
1392 ahci_sb600_check_ready);
1393
1394 /*
1395 * Soft reset fails on some ATI chips with IPMS set when PMP
1396 * is enabled but SATA HDD/ODD is connected to SATA port,
1397 * do soft reset again to port 0.
1398 */
1399 if (rc == -EIO) {
1400 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1401 if (irq_sts & PORT_IRQ_BAD_PMP) {
1402 ata_link_printk(link, KERN_WARNING,
1403 "failed due to HW bug, retry pmp=0\n");
1404 rc = ahci_do_softreset(link, class, 0, deadline,
1405 ahci_check_ready);
1406 }
1407 }
1408
1409 return rc;
1410 }
1411
1412 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1413 unsigned long deadline)
1414 {
1415 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1416 struct ata_port *ap = link->ap;
1417 struct ahci_port_priv *pp = ap->private_data;
1418 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1419 struct ata_taskfile tf;
1420 bool online;
1421 int rc;
1422
1423 DPRINTK("ENTER\n");
1424
1425 ahci_stop_engine(ap);
1426
1427 /* clear D2H reception area to properly wait for D2H FIS */
1428 ata_tf_init(link->device, &tf);
1429 tf.command = 0x80;
1430 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1431
1432 rc = sata_link_hardreset(link, timing, deadline, &online,
1433 ahci_check_ready);
1434
1435 ahci_start_engine(ap);
1436
1437 if (online)
1438 *class = ahci_dev_classify(ap);
1439
1440 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1441 return rc;
1442 }
1443
1444 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1445 unsigned long deadline)
1446 {
1447 struct ata_port *ap = link->ap;
1448 bool online;
1449 int rc;
1450
1451 DPRINTK("ENTER\n");
1452
1453 ahci_stop_engine(ap);
1454
1455 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1456 deadline, &online, NULL);
1457
1458 ahci_start_engine(ap);
1459
1460 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1461
1462 /* vt8251 doesn't clear BSY on signature FIS reception,
1463 * request follow-up softreset.
1464 */
1465 return online ? -EAGAIN : rc;
1466 }
1467
1468 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1469 unsigned long deadline)
1470 {
1471 struct ata_port *ap = link->ap;
1472 struct ahci_port_priv *pp = ap->private_data;
1473 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1474 struct ata_taskfile tf;
1475 bool online;
1476 int rc;
1477
1478 ahci_stop_engine(ap);
1479
1480 /* clear D2H reception area to properly wait for D2H FIS */
1481 ata_tf_init(link->device, &tf);
1482 tf.command = 0x80;
1483 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1484
1485 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1486 deadline, &online, NULL);
1487
1488 ahci_start_engine(ap);
1489
1490 /* The pseudo configuration device on SIMG4726 attached to
1491 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1492 * hardreset if no device is attached to the first downstream
1493 * port && the pseudo device locks up on SRST w/ PMP==0. To
1494 * work around this, wait for !BSY only briefly. If BSY isn't
1495 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1496 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1497 *
1498 * Wait for two seconds. Devices attached to downstream port
1499 * which can't process the following IDENTIFY after this will
1500 * have to be reset again. For most cases, this should
1501 * suffice while making probing snappish enough.
1502 */
1503 if (online) {
1504 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1505 ahci_check_ready);
1506 if (rc)
1507 ahci_kick_engine(ap, 0);
1508 }
1509 return rc;
1510 }
1511
1512 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1513 {
1514 struct ata_port *ap = link->ap;
1515 void __iomem *port_mmio = ahci_port_base(ap);
1516 u32 new_tmp, tmp;
1517
1518 ata_std_postreset(link, class);
1519
1520 /* Make sure port's ATAPI bit is set appropriately */
1521 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1522 if (*class == ATA_DEV_ATAPI)
1523 new_tmp |= PORT_CMD_ATAPI;
1524 else
1525 new_tmp &= ~PORT_CMD_ATAPI;
1526 if (new_tmp != tmp) {
1527 writel(new_tmp, port_mmio + PORT_CMD);
1528 readl(port_mmio + PORT_CMD); /* flush */
1529 }
1530 }
1531
1532 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1533 {
1534 struct scatterlist *sg;
1535 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1536 unsigned int si;
1537
1538 VPRINTK("ENTER\n");
1539
1540 /*
1541 * Next, the S/G list.
1542 */
1543 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1544 dma_addr_t addr = sg_dma_address(sg);
1545 u32 sg_len = sg_dma_len(sg);
1546
1547 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1548 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1549 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1550 }
1551
1552 return si;
1553 }
1554
1555 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1556 {
1557 struct ata_port *ap = qc->ap;
1558 struct ahci_port_priv *pp = ap->private_data;
1559 int is_atapi = ata_is_atapi(qc->tf.protocol);
1560 void *cmd_tbl;
1561 u32 opts;
1562 const u32 cmd_fis_len = 5; /* five dwords */
1563 unsigned int n_elem;
1564
1565 /*
1566 * Fill in command table information. First, the header,
1567 * a SATA Register - Host to Device command FIS.
1568 */
1569 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1570
1571 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1572 if (is_atapi) {
1573 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1574 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1575 }
1576
1577 n_elem = 0;
1578 if (qc->flags & ATA_QCFLAG_DMAMAP)
1579 n_elem = ahci_fill_sg(qc, cmd_tbl);
1580
1581 /*
1582 * Fill in command slot information.
1583 */
1584 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1585 if (qc->tf.flags & ATA_TFLAG_WRITE)
1586 opts |= AHCI_CMD_WRITE;
1587 if (is_atapi)
1588 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1589
1590 ahci_fill_cmd_slot(pp, qc->tag, opts);
1591 }
1592
1593 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1594 {
1595 struct ahci_host_priv *hpriv = ap->host->private_data;
1596 struct ahci_port_priv *pp = ap->private_data;
1597 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1598 struct ata_link *link = NULL;
1599 struct ata_queued_cmd *active_qc;
1600 struct ata_eh_info *active_ehi;
1601 u32 serror;
1602
1603 /* determine active link */
1604 ata_port_for_each_link(link, ap)
1605 if (ata_link_active(link))
1606 break;
1607 if (!link)
1608 link = &ap->link;
1609
1610 active_qc = ata_qc_from_tag(ap, link->active_tag);
1611 active_ehi = &link->eh_info;
1612
1613 /* record irq stat */
1614 ata_ehi_clear_desc(host_ehi);
1615 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1616
1617 /* AHCI needs SError cleared; otherwise, it might lock up */
1618 ahci_scr_read(ap, SCR_ERROR, &serror);
1619 ahci_scr_write(ap, SCR_ERROR, serror);
1620 host_ehi->serror |= serror;
1621
1622 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1623 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1624 irq_stat &= ~PORT_IRQ_IF_ERR;
1625
1626 if (irq_stat & PORT_IRQ_TF_ERR) {
1627 /* If qc is active, charge it; otherwise, the active
1628 * link. There's no active qc on NCQ errors. It will
1629 * be determined by EH by reading log page 10h.
1630 */
1631 if (active_qc)
1632 active_qc->err_mask |= AC_ERR_DEV;
1633 else
1634 active_ehi->err_mask |= AC_ERR_DEV;
1635
1636 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1637 host_ehi->serror &= ~SERR_INTERNAL;
1638 }
1639
1640 if (irq_stat & PORT_IRQ_UNK_FIS) {
1641 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1642
1643 active_ehi->err_mask |= AC_ERR_HSM;
1644 active_ehi->action |= ATA_EH_RESET;
1645 ata_ehi_push_desc(active_ehi,
1646 "unknown FIS %08x %08x %08x %08x" ,
1647 unk[0], unk[1], unk[2], unk[3]);
1648 }
1649
1650 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1651 active_ehi->err_mask |= AC_ERR_HSM;
1652 active_ehi->action |= ATA_EH_RESET;
1653 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1654 }
1655
1656 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1657 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1658 host_ehi->action |= ATA_EH_RESET;
1659 ata_ehi_push_desc(host_ehi, "host bus error");
1660 }
1661
1662 if (irq_stat & PORT_IRQ_IF_ERR) {
1663 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1664 host_ehi->action |= ATA_EH_RESET;
1665 ata_ehi_push_desc(host_ehi, "interface fatal error");
1666 }
1667
1668 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1669 ata_ehi_hotplugged(host_ehi);
1670 ata_ehi_push_desc(host_ehi, "%s",
1671 irq_stat & PORT_IRQ_CONNECT ?
1672 "connection status changed" : "PHY RDY changed");
1673 }
1674
1675 /* okay, let's hand over to EH */
1676
1677 if (irq_stat & PORT_IRQ_FREEZE)
1678 ata_port_freeze(ap);
1679 else
1680 ata_port_abort(ap);
1681 }
1682
1683 static void ahci_port_intr(struct ata_port *ap)
1684 {
1685 void __iomem *port_mmio = ahci_port_base(ap);
1686 struct ata_eh_info *ehi = &ap->link.eh_info;
1687 struct ahci_port_priv *pp = ap->private_data;
1688 struct ahci_host_priv *hpriv = ap->host->private_data;
1689 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1690 u32 status, qc_active;
1691 int rc;
1692
1693 status = readl(port_mmio + PORT_IRQ_STAT);
1694 writel(status, port_mmio + PORT_IRQ_STAT);
1695
1696 /* ignore BAD_PMP while resetting */
1697 if (unlikely(resetting))
1698 status &= ~PORT_IRQ_BAD_PMP;
1699
1700 /* If we are getting PhyRdy, this is
1701 * just a power state change, we should
1702 * clear out this, plus the PhyRdy/Comm
1703 * Wake bits from Serror
1704 */
1705 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1706 (status & PORT_IRQ_PHYRDY)) {
1707 status &= ~PORT_IRQ_PHYRDY;
1708 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1709 }
1710
1711 if (unlikely(status & PORT_IRQ_ERROR)) {
1712 ahci_error_intr(ap, status);
1713 return;
1714 }
1715
1716 if (status & PORT_IRQ_SDB_FIS) {
1717 /* If SNotification is available, leave notification
1718 * handling to sata_async_notification(). If not,
1719 * emulate it by snooping SDB FIS RX area.
1720 *
1721 * Snooping FIS RX area is probably cheaper than
1722 * poking SNotification but some constrollers which
1723 * implement SNotification, ICH9 for example, don't
1724 * store AN SDB FIS into receive area.
1725 */
1726 if (hpriv->cap & HOST_CAP_SNTF)
1727 sata_async_notification(ap);
1728 else {
1729 /* If the 'N' bit in word 0 of the FIS is set,
1730 * we just received asynchronous notification.
1731 * Tell libata about it.
1732 */
1733 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1734 u32 f0 = le32_to_cpu(f[0]);
1735
1736 if (f0 & (1 << 15))
1737 sata_async_notification(ap);
1738 }
1739 }
1740
1741 /* pp->active_link is valid iff any command is in flight */
1742 if (ap->qc_active && pp->active_link->sactive)
1743 qc_active = readl(port_mmio + PORT_SCR_ACT);
1744 else
1745 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1746
1747 rc = ata_qc_complete_multiple(ap, qc_active);
1748
1749 /* while resetting, invalid completions are expected */
1750 if (unlikely(rc < 0 && !resetting)) {
1751 ehi->err_mask |= AC_ERR_HSM;
1752 ehi->action |= ATA_EH_RESET;
1753 ata_port_freeze(ap);
1754 }
1755 }
1756
1757 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1758 {
1759 struct ata_host *host = dev_instance;
1760 struct ahci_host_priv *hpriv;
1761 unsigned int i, handled = 0;
1762 void __iomem *mmio;
1763 u32 irq_stat, irq_ack = 0;
1764
1765 VPRINTK("ENTER\n");
1766
1767 hpriv = host->private_data;
1768 mmio = host->iomap[AHCI_PCI_BAR];
1769
1770 /* sigh. 0xffffffff is a valid return from h/w */
1771 irq_stat = readl(mmio + HOST_IRQ_STAT);
1772 irq_stat &= hpriv->port_map;
1773 if (!irq_stat)
1774 return IRQ_NONE;
1775
1776 spin_lock(&host->lock);
1777
1778 for (i = 0; i < host->n_ports; i++) {
1779 struct ata_port *ap;
1780
1781 if (!(irq_stat & (1 << i)))
1782 continue;
1783
1784 ap = host->ports[i];
1785 if (ap) {
1786 ahci_port_intr(ap);
1787 VPRINTK("port %u\n", i);
1788 } else {
1789 VPRINTK("port %u (no irq)\n", i);
1790 if (ata_ratelimit())
1791 dev_printk(KERN_WARNING, host->dev,
1792 "interrupt on disabled port %u\n", i);
1793 }
1794
1795 irq_ack |= (1 << i);
1796 }
1797
1798 if (irq_ack) {
1799 writel(irq_ack, mmio + HOST_IRQ_STAT);
1800 handled = 1;
1801 }
1802
1803 spin_unlock(&host->lock);
1804
1805 VPRINTK("EXIT\n");
1806
1807 return IRQ_RETVAL(handled);
1808 }
1809
1810 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1811 {
1812 struct ata_port *ap = qc->ap;
1813 void __iomem *port_mmio = ahci_port_base(ap);
1814 struct ahci_port_priv *pp = ap->private_data;
1815
1816 /* Keep track of the currently active link. It will be used
1817 * in completion path to determine whether NCQ phase is in
1818 * progress.
1819 */
1820 pp->active_link = qc->dev->link;
1821
1822 if (qc->tf.protocol == ATA_PROT_NCQ)
1823 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1824 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1825 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1826
1827 return 0;
1828 }
1829
1830 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1831 {
1832 struct ahci_port_priv *pp = qc->ap->private_data;
1833 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1834
1835 ata_tf_from_fis(d2h_fis, &qc->result_tf);
1836 return true;
1837 }
1838
1839 static void ahci_freeze(struct ata_port *ap)
1840 {
1841 void __iomem *port_mmio = ahci_port_base(ap);
1842
1843 /* turn IRQ off */
1844 writel(0, port_mmio + PORT_IRQ_MASK);
1845 }
1846
1847 static void ahci_thaw(struct ata_port *ap)
1848 {
1849 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1850 void __iomem *port_mmio = ahci_port_base(ap);
1851 u32 tmp;
1852 struct ahci_port_priv *pp = ap->private_data;
1853
1854 /* clear IRQ */
1855 tmp = readl(port_mmio + PORT_IRQ_STAT);
1856 writel(tmp, port_mmio + PORT_IRQ_STAT);
1857 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1858
1859 /* turn IRQ back on */
1860 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1861 }
1862
1863 static void ahci_error_handler(struct ata_port *ap)
1864 {
1865 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1866 /* restart engine */
1867 ahci_stop_engine(ap);
1868 ahci_start_engine(ap);
1869 }
1870
1871 sata_pmp_error_handler(ap);
1872 }
1873
1874 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1875 {
1876 struct ata_port *ap = qc->ap;
1877
1878 /* make DMA engine forget about the failed command */
1879 if (qc->flags & ATA_QCFLAG_FAILED)
1880 ahci_kick_engine(ap, 1);
1881 }
1882
1883 static void ahci_pmp_attach(struct ata_port *ap)
1884 {
1885 void __iomem *port_mmio = ahci_port_base(ap);
1886 struct ahci_port_priv *pp = ap->private_data;
1887 u32 cmd;
1888
1889 cmd = readl(port_mmio + PORT_CMD);
1890 cmd |= PORT_CMD_PMP;
1891 writel(cmd, port_mmio + PORT_CMD);
1892
1893 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1894 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1895 }
1896
1897 static void ahci_pmp_detach(struct ata_port *ap)
1898 {
1899 void __iomem *port_mmio = ahci_port_base(ap);
1900 struct ahci_port_priv *pp = ap->private_data;
1901 u32 cmd;
1902
1903 cmd = readl(port_mmio + PORT_CMD);
1904 cmd &= ~PORT_CMD_PMP;
1905 writel(cmd, port_mmio + PORT_CMD);
1906
1907 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1908 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1909 }
1910
1911 static int ahci_port_resume(struct ata_port *ap)
1912 {
1913 ahci_power_up(ap);
1914 ahci_start_port(ap);
1915
1916 if (sata_pmp_attached(ap))
1917 ahci_pmp_attach(ap);
1918 else
1919 ahci_pmp_detach(ap);
1920
1921 return 0;
1922 }
1923
1924 #ifdef CONFIG_PM
1925 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1926 {
1927 const char *emsg = NULL;
1928 int rc;
1929
1930 rc = ahci_deinit_port(ap, &emsg);
1931 if (rc == 0)
1932 ahci_power_down(ap);
1933 else {
1934 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1935 ahci_start_port(ap);
1936 }
1937
1938 return rc;
1939 }
1940
1941 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1942 {
1943 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1944 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1945 u32 ctl;
1946
1947 if (mesg.event & PM_EVENT_SLEEP) {
1948 /* AHCI spec rev1.1 section 8.3.3:
1949 * Software must disable interrupts prior to requesting a
1950 * transition of the HBA to D3 state.
1951 */
1952 ctl = readl(mmio + HOST_CTL);
1953 ctl &= ~HOST_IRQ_EN;
1954 writel(ctl, mmio + HOST_CTL);
1955 readl(mmio + HOST_CTL); /* flush */
1956 }
1957
1958 return ata_pci_device_suspend(pdev, mesg);
1959 }
1960
1961 static int ahci_pci_device_resume(struct pci_dev *pdev)
1962 {
1963 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1964 int rc;
1965
1966 rc = ata_pci_device_do_resume(pdev);
1967 if (rc)
1968 return rc;
1969
1970 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1971 rc = ahci_reset_controller(host);
1972 if (rc)
1973 return rc;
1974
1975 ahci_init_controller(host);
1976 }
1977
1978 ata_host_resume(host);
1979
1980 return 0;
1981 }
1982 #endif
1983
1984 static int ahci_port_start(struct ata_port *ap)
1985 {
1986 struct device *dev = ap->host->dev;
1987 struct ahci_port_priv *pp;
1988 void *mem;
1989 dma_addr_t mem_dma;
1990
1991 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1992 if (!pp)
1993 return -ENOMEM;
1994
1995 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1996 GFP_KERNEL);
1997 if (!mem)
1998 return -ENOMEM;
1999 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2000
2001 /*
2002 * First item in chunk of DMA memory: 32-slot command table,
2003 * 32 bytes each in size
2004 */
2005 pp->cmd_slot = mem;
2006 pp->cmd_slot_dma = mem_dma;
2007
2008 mem += AHCI_CMD_SLOT_SZ;
2009 mem_dma += AHCI_CMD_SLOT_SZ;
2010
2011 /*
2012 * Second item: Received-FIS area
2013 */
2014 pp->rx_fis = mem;
2015 pp->rx_fis_dma = mem_dma;
2016
2017 mem += AHCI_RX_FIS_SZ;
2018 mem_dma += AHCI_RX_FIS_SZ;
2019
2020 /*
2021 * Third item: data area for storing a single command
2022 * and its scatter-gather table
2023 */
2024 pp->cmd_tbl = mem;
2025 pp->cmd_tbl_dma = mem_dma;
2026
2027 /*
2028 * Save off initial list of interrupts to be enabled.
2029 * This could be changed later
2030 */
2031 pp->intr_mask = DEF_PORT_IRQ;
2032
2033 ap->private_data = pp;
2034
2035 /* engage engines, captain */
2036 return ahci_port_resume(ap);
2037 }
2038
2039 static void ahci_port_stop(struct ata_port *ap)
2040 {
2041 const char *emsg = NULL;
2042 int rc;
2043
2044 /* de-initialize port */
2045 rc = ahci_deinit_port(ap, &emsg);
2046 if (rc)
2047 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2048 }
2049
2050 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2051 {
2052 int rc;
2053
2054 if (using_dac &&
2055 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2056 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2057 if (rc) {
2058 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2059 if (rc) {
2060 dev_printk(KERN_ERR, &pdev->dev,
2061 "64-bit DMA enable failed\n");
2062 return rc;
2063 }
2064 }
2065 } else {
2066 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2067 if (rc) {
2068 dev_printk(KERN_ERR, &pdev->dev,
2069 "32-bit DMA enable failed\n");
2070 return rc;
2071 }
2072 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2073 if (rc) {
2074 dev_printk(KERN_ERR, &pdev->dev,
2075 "32-bit consistent DMA enable failed\n");
2076 return rc;
2077 }
2078 }
2079 return 0;
2080 }
2081
2082 static void ahci_print_info(struct ata_host *host)
2083 {
2084 struct ahci_host_priv *hpriv = host->private_data;
2085 struct pci_dev *pdev = to_pci_dev(host->dev);
2086 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2087 u32 vers, cap, impl, speed;
2088 const char *speed_s;
2089 u16 cc;
2090 const char *scc_s;
2091
2092 vers = readl(mmio + HOST_VERSION);
2093 cap = hpriv->cap;
2094 impl = hpriv->port_map;
2095
2096 speed = (cap >> 20) & 0xf;
2097 if (speed == 1)
2098 speed_s = "1.5";
2099 else if (speed == 2)
2100 speed_s = "3";
2101 else
2102 speed_s = "?";
2103
2104 pci_read_config_word(pdev, 0x0a, &cc);
2105 if (cc == PCI_CLASS_STORAGE_IDE)
2106 scc_s = "IDE";
2107 else if (cc == PCI_CLASS_STORAGE_SATA)
2108 scc_s = "SATA";
2109 else if (cc == PCI_CLASS_STORAGE_RAID)
2110 scc_s = "RAID";
2111 else
2112 scc_s = "unknown";
2113
2114 dev_printk(KERN_INFO, &pdev->dev,
2115 "AHCI %02x%02x.%02x%02x "
2116 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2117 ,
2118
2119 (vers >> 24) & 0xff,
2120 (vers >> 16) & 0xff,
2121 (vers >> 8) & 0xff,
2122 vers & 0xff,
2123
2124 ((cap >> 8) & 0x1f) + 1,
2125 (cap & 0x1f) + 1,
2126 speed_s,
2127 impl,
2128 scc_s);
2129
2130 dev_printk(KERN_INFO, &pdev->dev,
2131 "flags: "
2132 "%s%s%s%s%s%s%s"
2133 "%s%s%s%s%s%s%s\n"
2134 ,
2135
2136 cap & (1 << 31) ? "64bit " : "",
2137 cap & (1 << 30) ? "ncq " : "",
2138 cap & (1 << 29) ? "sntf " : "",
2139 cap & (1 << 28) ? "ilck " : "",
2140 cap & (1 << 27) ? "stag " : "",
2141 cap & (1 << 26) ? "pm " : "",
2142 cap & (1 << 25) ? "led " : "",
2143
2144 cap & (1 << 24) ? "clo " : "",
2145 cap & (1 << 19) ? "nz " : "",
2146 cap & (1 << 18) ? "only " : "",
2147 cap & (1 << 17) ? "pmp " : "",
2148 cap & (1 << 15) ? "pio " : "",
2149 cap & (1 << 14) ? "slum " : "",
2150 cap & (1 << 13) ? "part " : ""
2151 );
2152 }
2153
2154 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2155 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2156 * support PMP and the 4726 either directly exports the device
2157 * attached to the first downstream port or acts as a hardware storage
2158 * controller and emulate a single ATA device (can be RAID 0/1 or some
2159 * other configuration).
2160 *
2161 * When there's no device attached to the first downstream port of the
2162 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2163 * configure the 4726. However, ATA emulation of the device is very
2164 * lame. It doesn't send signature D2H Reg FIS after the initial
2165 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2166 *
2167 * The following function works around the problem by always using
2168 * hardreset on the port and not depending on receiving signature FIS
2169 * afterward. If signature FIS isn't received soon, ATA class is
2170 * assumed without follow-up softreset.
2171 */
2172 static void ahci_p5wdh_workaround(struct ata_host *host)
2173 {
2174 static struct dmi_system_id sysids[] = {
2175 {
2176 .ident = "P5W DH Deluxe",
2177 .matches = {
2178 DMI_MATCH(DMI_SYS_VENDOR,
2179 "ASUSTEK COMPUTER INC"),
2180 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2181 },
2182 },
2183 { }
2184 };
2185 struct pci_dev *pdev = to_pci_dev(host->dev);
2186
2187 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2188 dmi_check_system(sysids)) {
2189 struct ata_port *ap = host->ports[1];
2190
2191 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2192 "Deluxe on-board SIMG4726 workaround\n");
2193
2194 ap->ops = &ahci_p5wdh_ops;
2195 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2196 }
2197 }
2198
2199 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2200 {
2201 static int printed_version;
2202 unsigned int board_id = ent->driver_data;
2203 struct ata_port_info pi = ahci_port_info[board_id];
2204 const struct ata_port_info *ppi[] = { &pi, NULL };
2205 struct device *dev = &pdev->dev;
2206 struct ahci_host_priv *hpriv;
2207 struct ata_host *host;
2208 int n_ports, i, rc;
2209
2210 VPRINTK("ENTER\n");
2211
2212 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2213
2214 if (!printed_version++)
2215 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2216
2217 /* acquire resources */
2218 rc = pcim_enable_device(pdev);
2219 if (rc)
2220 return rc;
2221
2222 /* AHCI controllers often implement SFF compatible interface.
2223 * Grab all PCI BARs just in case.
2224 */
2225 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2226 if (rc == -EBUSY)
2227 pcim_pin_device(pdev);
2228 if (rc)
2229 return rc;
2230
2231 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2232 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2233 u8 map;
2234
2235 /* ICH6s share the same PCI ID for both piix and ahci
2236 * modes. Enabling ahci mode while MAP indicates
2237 * combined mode is a bad idea. Yield to ata_piix.
2238 */
2239 pci_read_config_byte(pdev, ICH_MAP, &map);
2240 if (map & 0x3) {
2241 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2242 "combined mode, can't enable AHCI mode\n");
2243 return -ENODEV;
2244 }
2245 }
2246
2247 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2248 if (!hpriv)
2249 return -ENOMEM;
2250 hpriv->flags |= (unsigned long)pi.private_data;
2251
2252 /* MCP65 revision A1 and A2 can't do MSI */
2253 if (board_id == board_ahci_mcp65 &&
2254 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2255 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2256
2257 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2258 pci_intx(pdev, 1);
2259
2260 /* save initial config */
2261 ahci_save_initial_config(pdev, hpriv);
2262
2263 /* prepare host */
2264 if (hpriv->cap & HOST_CAP_NCQ)
2265 pi.flags |= ATA_FLAG_NCQ;
2266
2267 if (hpriv->cap & HOST_CAP_PMP)
2268 pi.flags |= ATA_FLAG_PMP;
2269
2270 /* CAP.NP sometimes indicate the index of the last enabled
2271 * port, at other times, that of the last possible port, so
2272 * determining the maximum port number requires looking at
2273 * both CAP.NP and port_map.
2274 */
2275 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2276
2277 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2278 if (!host)
2279 return -ENOMEM;
2280 host->iomap = pcim_iomap_table(pdev);
2281 host->private_data = hpriv;
2282
2283 for (i = 0; i < host->n_ports; i++) {
2284 struct ata_port *ap = host->ports[i];
2285
2286 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2287 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2288 0x100 + ap->port_no * 0x80, "port");
2289
2290 /* set initial link pm policy */
2291 ap->pm_policy = NOT_AVAILABLE;
2292
2293 /* disabled/not-implemented port */
2294 if (!(hpriv->port_map & (1 << i)))
2295 ap->ops = &ata_dummy_port_ops;
2296 }
2297
2298 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2299 ahci_p5wdh_workaround(host);
2300
2301 /* initialize adapter */
2302 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2303 if (rc)
2304 return rc;
2305
2306 rc = ahci_reset_controller(host);
2307 if (rc)
2308 return rc;
2309
2310 ahci_init_controller(host);
2311 ahci_print_info(host);
2312
2313 pci_set_master(pdev);
2314 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2315 &ahci_sht);
2316 }
2317
2318 static int __init ahci_init(void)
2319 {
2320 return pci_register_driver(&ahci_pci_driver);
2321 }
2322
2323 static void __exit ahci_exit(void)
2324 {
2325 pci_unregister_driver(&ahci_pci_driver);
2326 }
2327
2328
2329 MODULE_AUTHOR("Jeff Garzik");
2330 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2331 MODULE_LICENSE("GPL");
2332 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2333 MODULE_VERSION(DRV_VERSION);
2334
2335 module_init(ahci_init);
2336 module_exit(ahci_exit);
Linux kernel - Deliverables
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