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irqchip/gic-v3-its: Add missing cache flushes
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_CAVIUM = 0,
57 AHCI_PCI_BAR_ENMOTUS = 2,
58 AHCI_PCI_BAR_STANDARD = 5,
59 };
60
61 enum board_ids {
62 /* board IDs by feature in alphabetical order */
63 board_ahci,
64 board_ahci_ign_iferr,
65 board_ahci_nomsi,
66 board_ahci_noncq,
67 board_ahci_nosntf,
68 board_ahci_yes_fbs,
69
70 /* board IDs for specific chipsets in alphabetical order */
71 board_ahci_avn,
72 board_ahci_mcp65,
73 board_ahci_mcp77,
74 board_ahci_mcp89,
75 board_ahci_mv,
76 board_ahci_sb600,
77 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_vt8251,
79
80 /* aliases */
81 board_ahci_mcp_linux = board_ahci_mcp65,
82 board_ahci_mcp67 = board_ahci_mcp65,
83 board_ahci_mcp73 = board_ahci_mcp65,
84 board_ahci_mcp79 = board_ahci_mcp77,
85 };
86
87 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
88 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
93 static bool is_mcp89_apple(struct pci_dev *pdev);
94 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
96 #ifdef CONFIG_PM
97 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
98 static int ahci_pci_device_resume(struct pci_dev *pdev);
99 #endif
100
101 static struct scsi_host_template ahci_sht = {
102 AHCI_SHT("ahci"),
103 };
104
105 static struct ata_port_operations ahci_vt8251_ops = {
106 .inherits = &ahci_ops,
107 .hardreset = ahci_vt8251_hardreset,
108 };
109
110 static struct ata_port_operations ahci_p5wdh_ops = {
111 .inherits = &ahci_ops,
112 .hardreset = ahci_p5wdh_hardreset,
113 };
114
115 static struct ata_port_operations ahci_avn_ops = {
116 .inherits = &ahci_ops,
117 .hardreset = ahci_avn_hardreset,
118 };
119
120 static const struct ata_port_info ahci_port_info[] = {
121 /* by features */
122 [board_ahci] = {
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
127 },
128 [board_ahci_ign_iferr] = {
129 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
134 },
135 [board_ahci_nomsi] = {
136 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
141 },
142 [board_ahci_noncq] = {
143 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_nosntf] = {
150 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
151 .flags = AHCI_FLAG_COMMON,
152 .pio_mask = ATA_PIO4,
153 .udma_mask = ATA_UDMA6,
154 .port_ops = &ahci_ops,
155 },
156 [board_ahci_yes_fbs] = {
157 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
158 .flags = AHCI_FLAG_COMMON,
159 .pio_mask = ATA_PIO4,
160 .udma_mask = ATA_UDMA6,
161 .port_ops = &ahci_ops,
162 },
163 /* by chipsets */
164 [board_ahci_avn] = {
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_avn_ops,
169 },
170 [board_ahci_mcp65] = {
171 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
172 AHCI_HFLAG_YES_NCQ),
173 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_ops,
177 },
178 [board_ahci_mcp77] = {
179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
184 },
185 [board_ahci_mcp89] = {
186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
191 },
192 [board_ahci_mv] = {
193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
194 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
195 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
199 },
200 [board_ahci_sb600] = {
201 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
202 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
203 AHCI_HFLAG_32BIT_ONLY),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_pmp_retry_srst_ops,
208 },
209 [board_ahci_sb700] = { /* for SB700 and SB800 */
210 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_pmp_retry_srst_ops,
215 },
216 [board_ahci_vt8251] = {
217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
218 .flags = AHCI_FLAG_COMMON,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_vt8251_ops,
222 },
223 };
224
225 static const struct pci_device_id ahci_pci_tbl[] = {
226 /* Intel */
227 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
228 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
229 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
230 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
231 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
232 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
233 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
234 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
235 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
236 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
237 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
238 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
239 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
240 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
241 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
242 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
243 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
244 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
245 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
246 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
247 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
248 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
249 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
250 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
251 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
252 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
254 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
255 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
256 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
257 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
258 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
259 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
260 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
261 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
262 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
263 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
264 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
265 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
266 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
267 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
268 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
269 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
270 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
271 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
272 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
273 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
274 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
275 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
276 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
277 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
278 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
279 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
280 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
281 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
282 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
283 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
284 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
285 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
286 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
287 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
288 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
289 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
290 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
291 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
292 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
293 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
294 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
295 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
296 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
297 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
298 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
299 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
300 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
301 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
302 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
303 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
304 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
305 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
306 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
307 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
308 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
309 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
310 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
311 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
312 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
313 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
314 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
315 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
316 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
317 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
318 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
319 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
320 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
321 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
322 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
323 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
324 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
325 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
326 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
327 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
328 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
329 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
330 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
331 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
332 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
333 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
334 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
335 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
336 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
337 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
338 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
339 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
340 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
341 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
342 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
343 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
344 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
345 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
346 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
347
348 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
349 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
350 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
351 /* JMicron 362B and 362C have an AHCI function with IDE class code */
352 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
353 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
354 /* May need to update quirk_jmicron_async_suspend() for additions */
355
356 /* ATI */
357 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
358 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
359 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
360 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
361 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
362 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
363 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
364
365 /* AMD */
366 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
367 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
368 /* AMD is using RAID class only for ahci controllers */
369 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
370 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
371
372 /* VIA */
373 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
374 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
375
376 /* NVIDIA */
377 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
378 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
379 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
380 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
381 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
382 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
383 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
384 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
385 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
386 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
387 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
388 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
389 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
390 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
391 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
392 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
393 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
394 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
395 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
396 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
397 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
398 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
399 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
400 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
401 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
402 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
403 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
404 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
405 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
406 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
407 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
408 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
409 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
410 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
411 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
412 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
413 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
414 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
415 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
416 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
417 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
418 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
419 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
420 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
421 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
422 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
423 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
424 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
425 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
426 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
427 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
428 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
429 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
430 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
431 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
432 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
433 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
434 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
435 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
436 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
437 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
438 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
439 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
440 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
441 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
442 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
443 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
444 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
445 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
446 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
447 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
448 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
449 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
450 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
451 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
452 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
453 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
454 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
455 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
456 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
457 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
458 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
459 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
460 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
461
462 /* SiS */
463 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
464 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
465 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
466
467 /* ST Microelectronics */
468 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
469
470 /* Marvell */
471 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
472 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
473 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
474 .class = PCI_CLASS_STORAGE_SATA_AHCI,
475 .class_mask = 0xffffff,
476 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
477 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
478 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
479 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
480 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
481 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
482 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
483 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
484 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
485 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
486 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
487 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
488 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
489 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
490 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
491 .driver_data = board_ahci_yes_fbs },
492 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
493 .driver_data = board_ahci_yes_fbs },
494 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
495 .driver_data = board_ahci_yes_fbs },
496 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
497 .driver_data = board_ahci_yes_fbs },
498
499 /* Promise */
500 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
501 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
502
503 /* Asmedia */
504 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
505 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
506 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
507 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
508
509 /*
510 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
511 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
512 */
513 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
514 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
515
516 /* Enmotus */
517 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
518
519 /* Generic, PCI class code for AHCI */
520 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
521 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
522
523 { } /* terminate list */
524 };
525
526
527 static struct pci_driver ahci_pci_driver = {
528 .name = DRV_NAME,
529 .id_table = ahci_pci_tbl,
530 .probe = ahci_init_one,
531 .remove = ata_pci_remove_one,
532 #ifdef CONFIG_PM
533 .suspend = ahci_pci_device_suspend,
534 .resume = ahci_pci_device_resume,
535 #endif
536 };
537
538 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
539 static int marvell_enable;
540 #else
541 static int marvell_enable = 1;
542 #endif
543 module_param(marvell_enable, int, 0644);
544 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
545
546
547 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
548 struct ahci_host_priv *hpriv)
549 {
550 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
551 dev_info(&pdev->dev, "JMB361 has only one port\n");
552 hpriv->force_port_map = 1;
553 }
554
555 /*
556 * Temporary Marvell 6145 hack: PATA port presence
557 * is asserted through the standard AHCI port
558 * presence register, as bit 4 (counting from 0)
559 */
560 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
561 if (pdev->device == 0x6121)
562 hpriv->mask_port_map = 0x3;
563 else
564 hpriv->mask_port_map = 0xf;
565 dev_info(&pdev->dev,
566 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
567 }
568
569 ahci_save_initial_config(&pdev->dev, hpriv);
570 }
571
572 static int ahci_pci_reset_controller(struct ata_host *host)
573 {
574 struct pci_dev *pdev = to_pci_dev(host->dev);
575
576 ahci_reset_controller(host);
577
578 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
579 struct ahci_host_priv *hpriv = host->private_data;
580 u16 tmp16;
581
582 /* configure PCS */
583 pci_read_config_word(pdev, 0x92, &tmp16);
584 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
585 tmp16 |= hpriv->port_map;
586 pci_write_config_word(pdev, 0x92, tmp16);
587 }
588 }
589
590 return 0;
591 }
592
593 static void ahci_pci_init_controller(struct ata_host *host)
594 {
595 struct ahci_host_priv *hpriv = host->private_data;
596 struct pci_dev *pdev = to_pci_dev(host->dev);
597 void __iomem *port_mmio;
598 u32 tmp;
599 int mv;
600
601 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
602 if (pdev->device == 0x6121)
603 mv = 2;
604 else
605 mv = 4;
606 port_mmio = __ahci_port_base(host, mv);
607
608 writel(0, port_mmio + PORT_IRQ_MASK);
609
610 /* clear port IRQ */
611 tmp = readl(port_mmio + PORT_IRQ_STAT);
612 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
613 if (tmp)
614 writel(tmp, port_mmio + PORT_IRQ_STAT);
615 }
616
617 ahci_init_controller(host);
618 }
619
620 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
621 unsigned long deadline)
622 {
623 struct ata_port *ap = link->ap;
624 struct ahci_host_priv *hpriv = ap->host->private_data;
625 bool online;
626 int rc;
627
628 DPRINTK("ENTER\n");
629
630 ahci_stop_engine(ap);
631
632 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
633 deadline, &online, NULL);
634
635 hpriv->start_engine(ap);
636
637 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
638
639 /* vt8251 doesn't clear BSY on signature FIS reception,
640 * request follow-up softreset.
641 */
642 return online ? -EAGAIN : rc;
643 }
644
645 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
646 unsigned long deadline)
647 {
648 struct ata_port *ap = link->ap;
649 struct ahci_port_priv *pp = ap->private_data;
650 struct ahci_host_priv *hpriv = ap->host->private_data;
651 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
652 struct ata_taskfile tf;
653 bool online;
654 int rc;
655
656 ahci_stop_engine(ap);
657
658 /* clear D2H reception area to properly wait for D2H FIS */
659 ata_tf_init(link->device, &tf);
660 tf.command = ATA_BUSY;
661 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
662
663 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
664 deadline, &online, NULL);
665
666 hpriv->start_engine(ap);
667
668 /* The pseudo configuration device on SIMG4726 attached to
669 * ASUS P5W-DH Deluxe doesn't send signature FIS after
670 * hardreset if no device is attached to the first downstream
671 * port && the pseudo device locks up on SRST w/ PMP==0. To
672 * work around this, wait for !BSY only briefly. If BSY isn't
673 * cleared, perform CLO and proceed to IDENTIFY (achieved by
674 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
675 *
676 * Wait for two seconds. Devices attached to downstream port
677 * which can't process the following IDENTIFY after this will
678 * have to be reset again. For most cases, this should
679 * suffice while making probing snappish enough.
680 */
681 if (online) {
682 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
683 ahci_check_ready);
684 if (rc)
685 ahci_kick_engine(ap);
686 }
687 return rc;
688 }
689
690 /*
691 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
692 *
693 * It has been observed with some SSDs that the timing of events in the
694 * link synchronization phase can leave the port in a state that can not
695 * be recovered by a SATA-hard-reset alone. The failing signature is
696 * SStatus.DET stuck at 1 ("Device presence detected but Phy
697 * communication not established"). It was found that unloading and
698 * reloading the driver when this problem occurs allows the drive
699 * connection to be recovered (DET advanced to 0x3). The critical
700 * component of reloading the driver is that the port state machines are
701 * reset by bouncing "port enable" in the AHCI PCS configuration
702 * register. So, reproduce that effect by bouncing a port whenever we
703 * see DET==1 after a reset.
704 */
705 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
706 unsigned long deadline)
707 {
708 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
709 struct ata_port *ap = link->ap;
710 struct ahci_port_priv *pp = ap->private_data;
711 struct ahci_host_priv *hpriv = ap->host->private_data;
712 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
713 unsigned long tmo = deadline - jiffies;
714 struct ata_taskfile tf;
715 bool online;
716 int rc, i;
717
718 DPRINTK("ENTER\n");
719
720 ahci_stop_engine(ap);
721
722 for (i = 0; i < 2; i++) {
723 u16 val;
724 u32 sstatus;
725 int port = ap->port_no;
726 struct ata_host *host = ap->host;
727 struct pci_dev *pdev = to_pci_dev(host->dev);
728
729 /* clear D2H reception area to properly wait for D2H FIS */
730 ata_tf_init(link->device, &tf);
731 tf.command = ATA_BUSY;
732 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
733
734 rc = sata_link_hardreset(link, timing, deadline, &online,
735 ahci_check_ready);
736
737 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
738 (sstatus & 0xf) != 1)
739 break;
740
741 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
742 port);
743
744 pci_read_config_word(pdev, 0x92, &val);
745 val &= ~(1 << port);
746 pci_write_config_word(pdev, 0x92, val);
747 ata_msleep(ap, 1000);
748 val |= 1 << port;
749 pci_write_config_word(pdev, 0x92, val);
750 deadline += tmo;
751 }
752
753 hpriv->start_engine(ap);
754
755 if (online)
756 *class = ahci_dev_classify(ap);
757
758 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
759 return rc;
760 }
761
762
763 #ifdef CONFIG_PM
764 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
765 {
766 struct ata_host *host = pci_get_drvdata(pdev);
767 struct ahci_host_priv *hpriv = host->private_data;
768 void __iomem *mmio = hpriv->mmio;
769 u32 ctl;
770
771 if (mesg.event & PM_EVENT_SUSPEND &&
772 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
773 dev_err(&pdev->dev,
774 "BIOS update required for suspend/resume\n");
775 return -EIO;
776 }
777
778 if (mesg.event & PM_EVENT_SLEEP) {
779 /* AHCI spec rev1.1 section 8.3.3:
780 * Software must disable interrupts prior to requesting a
781 * transition of the HBA to D3 state.
782 */
783 ctl = readl(mmio + HOST_CTL);
784 ctl &= ~HOST_IRQ_EN;
785 writel(ctl, mmio + HOST_CTL);
786 readl(mmio + HOST_CTL); /* flush */
787 }
788
789 return ata_pci_device_suspend(pdev, mesg);
790 }
791
792 static int ahci_pci_device_resume(struct pci_dev *pdev)
793 {
794 struct ata_host *host = pci_get_drvdata(pdev);
795 int rc;
796
797 rc = ata_pci_device_do_resume(pdev);
798 if (rc)
799 return rc;
800
801 /* Apple BIOS helpfully mangles the registers on resume */
802 if (is_mcp89_apple(pdev))
803 ahci_mcp89_apple_enable(pdev);
804
805 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
806 rc = ahci_pci_reset_controller(host);
807 if (rc)
808 return rc;
809
810 ahci_pci_init_controller(host);
811 }
812
813 ata_host_resume(host);
814
815 return 0;
816 }
817 #endif
818
819 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
820 {
821 int rc;
822
823 /*
824 * If the device fixup already set the dma_mask to some non-standard
825 * value, don't extend it here. This happens on STA2X11, for example.
826 */
827 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
828 return 0;
829
830 if (using_dac &&
831 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
832 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
833 if (rc) {
834 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
835 if (rc) {
836 dev_err(&pdev->dev,
837 "64-bit DMA enable failed\n");
838 return rc;
839 }
840 }
841 } else {
842 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
843 if (rc) {
844 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
845 return rc;
846 }
847 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
848 if (rc) {
849 dev_err(&pdev->dev,
850 "32-bit consistent DMA enable failed\n");
851 return rc;
852 }
853 }
854 return 0;
855 }
856
857 static void ahci_pci_print_info(struct ata_host *host)
858 {
859 struct pci_dev *pdev = to_pci_dev(host->dev);
860 u16 cc;
861 const char *scc_s;
862
863 pci_read_config_word(pdev, 0x0a, &cc);
864 if (cc == PCI_CLASS_STORAGE_IDE)
865 scc_s = "IDE";
866 else if (cc == PCI_CLASS_STORAGE_SATA)
867 scc_s = "SATA";
868 else if (cc == PCI_CLASS_STORAGE_RAID)
869 scc_s = "RAID";
870 else
871 scc_s = "unknown";
872
873 ahci_print_info(host, scc_s);
874 }
875
876 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
877 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
878 * support PMP and the 4726 either directly exports the device
879 * attached to the first downstream port or acts as a hardware storage
880 * controller and emulate a single ATA device (can be RAID 0/1 or some
881 * other configuration).
882 *
883 * When there's no device attached to the first downstream port of the
884 * 4726, "Config Disk" appears, which is a pseudo ATA device to
885 * configure the 4726. However, ATA emulation of the device is very
886 * lame. It doesn't send signature D2H Reg FIS after the initial
887 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
888 *
889 * The following function works around the problem by always using
890 * hardreset on the port and not depending on receiving signature FIS
891 * afterward. If signature FIS isn't received soon, ATA class is
892 * assumed without follow-up softreset.
893 */
894 static void ahci_p5wdh_workaround(struct ata_host *host)
895 {
896 static const struct dmi_system_id sysids[] = {
897 {
898 .ident = "P5W DH Deluxe",
899 .matches = {
900 DMI_MATCH(DMI_SYS_VENDOR,
901 "ASUSTEK COMPUTER INC"),
902 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
903 },
904 },
905 { }
906 };
907 struct pci_dev *pdev = to_pci_dev(host->dev);
908
909 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
910 dmi_check_system(sysids)) {
911 struct ata_port *ap = host->ports[1];
912
913 dev_info(&pdev->dev,
914 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
915
916 ap->ops = &ahci_p5wdh_ops;
917 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
918 }
919 }
920
921 /*
922 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
923 * booting in BIOS compatibility mode. We restore the registers but not ID.
924 */
925 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
926 {
927 u32 val;
928
929 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
930
931 pci_read_config_dword(pdev, 0xf8, &val);
932 val |= 1 << 0x1b;
933 /* the following changes the device ID, but appears not to affect function */
934 /* val = (val & ~0xf0000000) | 0x80000000; */
935 pci_write_config_dword(pdev, 0xf8, val);
936
937 pci_read_config_dword(pdev, 0x54c, &val);
938 val |= 1 << 0xc;
939 pci_write_config_dword(pdev, 0x54c, val);
940
941 pci_read_config_dword(pdev, 0x4a4, &val);
942 val &= 0xff;
943 val |= 0x01060100;
944 pci_write_config_dword(pdev, 0x4a4, val);
945
946 pci_read_config_dword(pdev, 0x54c, &val);
947 val &= ~(1 << 0xc);
948 pci_write_config_dword(pdev, 0x54c, val);
949
950 pci_read_config_dword(pdev, 0xf8, &val);
951 val &= ~(1 << 0x1b);
952 pci_write_config_dword(pdev, 0xf8, val);
953 }
954
955 static bool is_mcp89_apple(struct pci_dev *pdev)
956 {
957 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
958 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
959 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
960 pdev->subsystem_device == 0xcb89;
961 }
962
963 /* only some SB600 ahci controllers can do 64bit DMA */
964 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
965 {
966 static const struct dmi_system_id sysids[] = {
967 /*
968 * The oldest version known to be broken is 0901 and
969 * working is 1501 which was released on 2007-10-26.
970 * Enable 64bit DMA on 1501 and anything newer.
971 *
972 * Please read bko#9412 for more info.
973 */
974 {
975 .ident = "ASUS M2A-VM",
976 .matches = {
977 DMI_MATCH(DMI_BOARD_VENDOR,
978 "ASUSTeK Computer INC."),
979 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
980 },
981 .driver_data = "20071026", /* yyyymmdd */
982 },
983 /*
984 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
985 * support 64bit DMA.
986 *
987 * BIOS versions earlier than 1.5 had the Manufacturer DMI
988 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
989 * This spelling mistake was fixed in BIOS version 1.5, so
990 * 1.5 and later have the Manufacturer as
991 * "MICRO-STAR INTERNATIONAL CO.,LTD".
992 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
993 *
994 * BIOS versions earlier than 1.9 had a Board Product Name
995 * DMI field of "MS-7376". This was changed to be
996 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
997 * match on DMI_BOARD_NAME of "MS-7376".
998 */
999 {
1000 .ident = "MSI K9A2 Platinum",
1001 .matches = {
1002 DMI_MATCH(DMI_BOARD_VENDOR,
1003 "MICRO-STAR INTER"),
1004 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1005 },
1006 },
1007 /*
1008 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1009 * 64bit DMA.
1010 *
1011 * This board also had the typo mentioned above in the
1012 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1013 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1014 */
1015 {
1016 .ident = "MSI K9AGM2",
1017 .matches = {
1018 DMI_MATCH(DMI_BOARD_VENDOR,
1019 "MICRO-STAR INTER"),
1020 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1021 },
1022 },
1023 /*
1024 * All BIOS versions for the Asus M3A support 64bit DMA.
1025 * (all release versions from 0301 to 1206 were tested)
1026 */
1027 {
1028 .ident = "ASUS M3A",
1029 .matches = {
1030 DMI_MATCH(DMI_BOARD_VENDOR,
1031 "ASUSTeK Computer INC."),
1032 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1033 },
1034 },
1035 { }
1036 };
1037 const struct dmi_system_id *match;
1038 int year, month, date;
1039 char buf[9];
1040
1041 match = dmi_first_match(sysids);
1042 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1043 !match)
1044 return false;
1045
1046 if (!match->driver_data)
1047 goto enable_64bit;
1048
1049 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1050 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1051
1052 if (strcmp(buf, match->driver_data) >= 0)
1053 goto enable_64bit;
1054 else {
1055 dev_warn(&pdev->dev,
1056 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1057 match->ident);
1058 return false;
1059 }
1060
1061 enable_64bit:
1062 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1063 return true;
1064 }
1065
1066 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1067 {
1068 static const struct dmi_system_id broken_systems[] = {
1069 {
1070 .ident = "HP Compaq nx6310",
1071 .matches = {
1072 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1073 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1074 },
1075 /* PCI slot number of the controller */
1076 .driver_data = (void *)0x1FUL,
1077 },
1078 {
1079 .ident = "HP Compaq 6720s",
1080 .matches = {
1081 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1082 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1083 },
1084 /* PCI slot number of the controller */
1085 .driver_data = (void *)0x1FUL,
1086 },
1087
1088 { } /* terminate list */
1089 };
1090 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1091
1092 if (dmi) {
1093 unsigned long slot = (unsigned long)dmi->driver_data;
1094 /* apply the quirk only to on-board controllers */
1095 return slot == PCI_SLOT(pdev->devfn);
1096 }
1097
1098 return false;
1099 }
1100
1101 static bool ahci_broken_suspend(struct pci_dev *pdev)
1102 {
1103 static const struct dmi_system_id sysids[] = {
1104 /*
1105 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1106 * to the harddisk doesn't become online after
1107 * resuming from STR. Warn and fail suspend.
1108 *
1109 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1110 *
1111 * Use dates instead of versions to match as HP is
1112 * apparently recycling both product and version
1113 * strings.
1114 *
1115 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1116 */
1117 {
1118 .ident = "dv4",
1119 .matches = {
1120 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1121 DMI_MATCH(DMI_PRODUCT_NAME,
1122 "HP Pavilion dv4 Notebook PC"),
1123 },
1124 .driver_data = "20090105", /* F.30 */
1125 },
1126 {
1127 .ident = "dv5",
1128 .matches = {
1129 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1130 DMI_MATCH(DMI_PRODUCT_NAME,
1131 "HP Pavilion dv5 Notebook PC"),
1132 },
1133 .driver_data = "20090506", /* F.16 */
1134 },
1135 {
1136 .ident = "dv6",
1137 .matches = {
1138 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1139 DMI_MATCH(DMI_PRODUCT_NAME,
1140 "HP Pavilion dv6 Notebook PC"),
1141 },
1142 .driver_data = "20090423", /* F.21 */
1143 },
1144 {
1145 .ident = "HDX18",
1146 .matches = {
1147 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1148 DMI_MATCH(DMI_PRODUCT_NAME,
1149 "HP HDX18 Notebook PC"),
1150 },
1151 .driver_data = "20090430", /* F.23 */
1152 },
1153 /*
1154 * Acer eMachines G725 has the same problem. BIOS
1155 * V1.03 is known to be broken. V3.04 is known to
1156 * work. Between, there are V1.06, V2.06 and V3.03
1157 * that we don't have much idea about. For now,
1158 * blacklist anything older than V3.04.
1159 *
1160 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1161 */
1162 {
1163 .ident = "G725",
1164 .matches = {
1165 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1166 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1167 },
1168 .driver_data = "20091216", /* V3.04 */
1169 },
1170 { } /* terminate list */
1171 };
1172 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1173 int year, month, date;
1174 char buf[9];
1175
1176 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1177 return false;
1178
1179 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1180 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1181
1182 return strcmp(buf, dmi->driver_data) < 0;
1183 }
1184
1185 static bool ahci_broken_online(struct pci_dev *pdev)
1186 {
1187 #define ENCODE_BUSDEVFN(bus, slot, func) \
1188 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1189 static const struct dmi_system_id sysids[] = {
1190 /*
1191 * There are several gigabyte boards which use
1192 * SIMG5723s configured as hardware RAID. Certain
1193 * 5723 firmware revisions shipped there keep the link
1194 * online but fail to answer properly to SRST or
1195 * IDENTIFY when no device is attached downstream
1196 * causing libata to retry quite a few times leading
1197 * to excessive detection delay.
1198 *
1199 * As these firmwares respond to the second reset try
1200 * with invalid device signature, considering unknown
1201 * sig as offline works around the problem acceptably.
1202 */
1203 {
1204 .ident = "EP45-DQ6",
1205 .matches = {
1206 DMI_MATCH(DMI_BOARD_VENDOR,
1207 "Gigabyte Technology Co., Ltd."),
1208 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1209 },
1210 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1211 },
1212 {
1213 .ident = "EP45-DS5",
1214 .matches = {
1215 DMI_MATCH(DMI_BOARD_VENDOR,
1216 "Gigabyte Technology Co., Ltd."),
1217 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1218 },
1219 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1220 },
1221 { } /* terminate list */
1222 };
1223 #undef ENCODE_BUSDEVFN
1224 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1225 unsigned int val;
1226
1227 if (!dmi)
1228 return false;
1229
1230 val = (unsigned long)dmi->driver_data;
1231
1232 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1233 }
1234
1235 static bool ahci_broken_devslp(struct pci_dev *pdev)
1236 {
1237 /* device with broken DEVSLP but still showing SDS capability */
1238 static const struct pci_device_id ids[] = {
1239 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1240 {}
1241 };
1242
1243 return pci_match_id(ids, pdev);
1244 }
1245
1246 #ifdef CONFIG_ATA_ACPI
1247 static void ahci_gtf_filter_workaround(struct ata_host *host)
1248 {
1249 static const struct dmi_system_id sysids[] = {
1250 /*
1251 * Aspire 3810T issues a bunch of SATA enable commands
1252 * via _GTF including an invalid one and one which is
1253 * rejected by the device. Among the successful ones
1254 * is FPDMA non-zero offset enable which when enabled
1255 * only on the drive side leads to NCQ command
1256 * failures. Filter it out.
1257 */
1258 {
1259 .ident = "Aspire 3810T",
1260 .matches = {
1261 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1262 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1263 },
1264 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1265 },
1266 { }
1267 };
1268 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1269 unsigned int filter;
1270 int i;
1271
1272 if (!dmi)
1273 return;
1274
1275 filter = (unsigned long)dmi->driver_data;
1276 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1277 filter, dmi->ident);
1278
1279 for (i = 0; i < host->n_ports; i++) {
1280 struct ata_port *ap = host->ports[i];
1281 struct ata_link *link;
1282 struct ata_device *dev;
1283
1284 ata_for_each_link(link, ap, EDGE)
1285 ata_for_each_dev(dev, link, ALL)
1286 dev->gtf_filter |= filter;
1287 }
1288 }
1289 #else
1290 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1291 {}
1292 #endif
1293
1294 /*
1295 * ahci_init_msix() only implements single MSI-X support, not multiple
1296 * MSI-X per-port interrupts. This is needed for host controllers that only
1297 * have MSI-X support implemented, but no MSI or intx.
1298 */
1299 static int ahci_init_msix(struct pci_dev *pdev, unsigned int n_ports,
1300 struct ahci_host_priv *hpriv)
1301 {
1302 int rc, nvec;
1303 struct msix_entry entry = {};
1304
1305 /* Do not init MSI-X if MSI is disabled for the device */
1306 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1307 return -ENODEV;
1308
1309 nvec = pci_msix_vec_count(pdev);
1310 if (nvec < 0)
1311 return nvec;
1312
1313 if (!nvec) {
1314 rc = -ENODEV;
1315 goto fail;
1316 }
1317
1318 /*
1319 * There can be more than one vector (e.g. for error detection or
1320 * hdd hotplug). Only the first vector (entry.entry = 0) is used.
1321 */
1322 rc = pci_enable_msix_exact(pdev, &entry, 1);
1323 if (rc < 0)
1324 goto fail;
1325
1326 hpriv->irq = entry.vector;
1327
1328 return 1;
1329 fail:
1330 dev_err(&pdev->dev,
1331 "failed to enable MSI-X with error %d, # of vectors: %d\n",
1332 rc, nvec);
1333
1334 return rc;
1335 }
1336
1337 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1338 struct ahci_host_priv *hpriv)
1339 {
1340 int rc, nvec;
1341
1342 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1343 return -ENODEV;
1344
1345 nvec = pci_msi_vec_count(pdev);
1346 if (nvec < 0)
1347 return nvec;
1348
1349 /*
1350 * If number of MSIs is less than number of ports then Sharing Last
1351 * Message mode could be enforced. In this case assume that advantage
1352 * of multipe MSIs is negated and use single MSI mode instead.
1353 */
1354 if (nvec < n_ports)
1355 goto single_msi;
1356
1357 rc = pci_enable_msi_exact(pdev, nvec);
1358 if (rc == -ENOSPC)
1359 goto single_msi;
1360 if (rc < 0)
1361 return rc;
1362
1363 /* fallback to single MSI mode if the controller enforced MRSM mode */
1364 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1365 pci_disable_msi(pdev);
1366 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1367 goto single_msi;
1368 }
1369
1370 if (nvec > 1)
1371 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1372
1373 goto out;
1374
1375 single_msi:
1376 nvec = 1;
1377
1378 rc = pci_enable_msi(pdev);
1379 if (rc < 0)
1380 return rc;
1381 out:
1382 hpriv->irq = pdev->irq;
1383
1384 return nvec;
1385 }
1386
1387 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1388 struct ahci_host_priv *hpriv)
1389 {
1390 int nvec;
1391
1392 nvec = ahci_init_msi(pdev, n_ports, hpriv);
1393 if (nvec >= 0)
1394 return nvec;
1395
1396 /*
1397 * Currently, MSI-X support only implements single IRQ mode and
1398 * exists for controllers which can't do other types of IRQ. Only
1399 * set it up if MSI fails.
1400 */
1401 nvec = ahci_init_msix(pdev, n_ports, hpriv);
1402 if (nvec >= 0)
1403 return nvec;
1404
1405 /* lagacy intx interrupts */
1406 pci_intx(pdev, 1);
1407 hpriv->irq = pdev->irq;
1408
1409 return 0;
1410 }
1411
1412 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1413 {
1414 unsigned int board_id = ent->driver_data;
1415 struct ata_port_info pi = ahci_port_info[board_id];
1416 const struct ata_port_info *ppi[] = { &pi, NULL };
1417 struct device *dev = &pdev->dev;
1418 struct ahci_host_priv *hpriv;
1419 struct ata_host *host;
1420 int n_ports, i, rc;
1421 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1422
1423 VPRINTK("ENTER\n");
1424
1425 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1426
1427 ata_print_version_once(&pdev->dev, DRV_VERSION);
1428
1429 /* The AHCI driver can only drive the SATA ports, the PATA driver
1430 can drive them all so if both drivers are selected make sure
1431 AHCI stays out of the way */
1432 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1433 return -ENODEV;
1434
1435 /* Apple BIOS on MCP89 prevents us using AHCI */
1436 if (is_mcp89_apple(pdev))
1437 ahci_mcp89_apple_enable(pdev);
1438
1439 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1440 * At the moment, we can only use the AHCI mode. Let the users know
1441 * that for SAS drives they're out of luck.
1442 */
1443 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1444 dev_info(&pdev->dev,
1445 "PDC42819 can only drive SATA devices with this driver\n");
1446
1447 /* Some devices use non-standard BARs */
1448 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1449 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1450 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1451 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1452 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1453 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1454
1455 /* acquire resources */
1456 rc = pcim_enable_device(pdev);
1457 if (rc)
1458 return rc;
1459
1460 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1461 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1462 u8 map;
1463
1464 /* ICH6s share the same PCI ID for both piix and ahci
1465 * modes. Enabling ahci mode while MAP indicates
1466 * combined mode is a bad idea. Yield to ata_piix.
1467 */
1468 pci_read_config_byte(pdev, ICH_MAP, &map);
1469 if (map & 0x3) {
1470 dev_info(&pdev->dev,
1471 "controller is in combined mode, can't enable AHCI mode\n");
1472 return -ENODEV;
1473 }
1474 }
1475
1476 /* AHCI controllers often implement SFF compatible interface.
1477 * Grab all PCI BARs just in case.
1478 */
1479 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1480 if (rc == -EBUSY)
1481 pcim_pin_device(pdev);
1482 if (rc)
1483 return rc;
1484
1485 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1486 if (!hpriv)
1487 return -ENOMEM;
1488 hpriv->flags |= (unsigned long)pi.private_data;
1489
1490 /* MCP65 revision A1 and A2 can't do MSI */
1491 if (board_id == board_ahci_mcp65 &&
1492 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1493 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1494
1495 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1496 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1497 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1498
1499 /* only some SB600s can do 64bit DMA */
1500 if (ahci_sb600_enable_64bit(pdev))
1501 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1502
1503 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1504
1505 /* must set flag prior to save config in order to take effect */
1506 if (ahci_broken_devslp(pdev))
1507 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1508
1509 /* save initial config */
1510 ahci_pci_save_initial_config(pdev, hpriv);
1511
1512 /* prepare host */
1513 if (hpriv->cap & HOST_CAP_NCQ) {
1514 pi.flags |= ATA_FLAG_NCQ;
1515 /*
1516 * Auto-activate optimization is supposed to be
1517 * supported on all AHCI controllers indicating NCQ
1518 * capability, but it seems to be broken on some
1519 * chipsets including NVIDIAs.
1520 */
1521 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1522 pi.flags |= ATA_FLAG_FPDMA_AA;
1523
1524 /*
1525 * All AHCI controllers should be forward-compatible
1526 * with the new auxiliary field. This code should be
1527 * conditionalized if any buggy AHCI controllers are
1528 * encountered.
1529 */
1530 pi.flags |= ATA_FLAG_FPDMA_AUX;
1531 }
1532
1533 if (hpriv->cap & HOST_CAP_PMP)
1534 pi.flags |= ATA_FLAG_PMP;
1535
1536 ahci_set_em_messages(hpriv, &pi);
1537
1538 if (ahci_broken_system_poweroff(pdev)) {
1539 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1540 dev_info(&pdev->dev,
1541 "quirky BIOS, skipping spindown on poweroff\n");
1542 }
1543
1544 if (ahci_broken_suspend(pdev)) {
1545 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1546 dev_warn(&pdev->dev,
1547 "BIOS update required for suspend/resume\n");
1548 }
1549
1550 if (ahci_broken_online(pdev)) {
1551 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1552 dev_info(&pdev->dev,
1553 "online status unreliable, applying workaround\n");
1554 }
1555
1556 /* CAP.NP sometimes indicate the index of the last enabled
1557 * port, at other times, that of the last possible port, so
1558 * determining the maximum port number requires looking at
1559 * both CAP.NP and port_map.
1560 */
1561 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1562
1563 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1564 if (!host)
1565 return -ENOMEM;
1566 host->private_data = hpriv;
1567
1568 ahci_init_interrupts(pdev, n_ports, hpriv);
1569
1570 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1571 host->flags |= ATA_HOST_PARALLEL_SCAN;
1572 else
1573 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1574
1575 if (pi.flags & ATA_FLAG_EM)
1576 ahci_reset_em(host);
1577
1578 for (i = 0; i < host->n_ports; i++) {
1579 struct ata_port *ap = host->ports[i];
1580
1581 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1582 ata_port_pbar_desc(ap, ahci_pci_bar,
1583 0x100 + ap->port_no * 0x80, "port");
1584
1585 /* set enclosure management message type */
1586 if (ap->flags & ATA_FLAG_EM)
1587 ap->em_message_type = hpriv->em_msg_type;
1588
1589
1590 /* disabled/not-implemented port */
1591 if (!(hpriv->port_map & (1 << i)))
1592 ap->ops = &ata_dummy_port_ops;
1593 }
1594
1595 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1596 ahci_p5wdh_workaround(host);
1597
1598 /* apply gtf filter quirk */
1599 ahci_gtf_filter_workaround(host);
1600
1601 /* initialize adapter */
1602 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1603 if (rc)
1604 return rc;
1605
1606 rc = ahci_pci_reset_controller(host);
1607 if (rc)
1608 return rc;
1609
1610 ahci_pci_init_controller(host);
1611 ahci_pci_print_info(host);
1612
1613 pci_set_master(pdev);
1614
1615 return ahci_host_activate(host, &ahci_sht);
1616 }
1617
1618 module_pci_driver(ahci_pci_driver);
1619
1620 MODULE_AUTHOR("Jeff Garzik");
1621 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1622 MODULE_LICENSE("GPL");
1623 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1624 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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