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libata: implement and use ops inheritance
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58 static void ahci_disable_alpm(struct ata_port *ap);
59
60 enum {
61 AHCI_PCI_BAR = 5,
62 AHCI_MAX_PORTS = 32,
63 AHCI_MAX_SG = 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY = 0xffffffff,
65 AHCI_MAX_CMDS = 32,
66 AHCI_CMD_SZ = 32,
67 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
68 AHCI_RX_FIS_SZ = 256,
69 AHCI_CMD_TBL_CDB = 0x40,
70 AHCI_CMD_TBL_HDR_SZ = 0x80,
71 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
72 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
73 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
74 AHCI_RX_FIS_SZ,
75 AHCI_IRQ_ON_SG = (1 << 31),
76 AHCI_CMD_ATAPI = (1 << 5),
77 AHCI_CMD_WRITE = (1 << 6),
78 AHCI_CMD_PREFETCH = (1 << 7),
79 AHCI_CMD_RESET = (1 << 8),
80 AHCI_CMD_CLR_BUSY = (1 << 10),
81
82 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
83 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
84 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
85
86 board_ahci = 0,
87 board_ahci_vt8251 = 1,
88 board_ahci_ign_iferr = 2,
89 board_ahci_sb600 = 3,
90 board_ahci_mv = 4,
91 board_ahci_sb700 = 5,
92
93 /* global controller registers */
94 HOST_CAP = 0x00, /* host capabilities */
95 HOST_CTL = 0x04, /* global host control */
96 HOST_IRQ_STAT = 0x08, /* interrupt status */
97 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
98 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
99
100 /* HOST_CTL bits */
101 HOST_RESET = (1 << 0), /* reset controller; self-clear */
102 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
103 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
104
105 /* HOST_CAP bits */
106 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
107 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
108 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
109 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
110 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
111 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
112 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
113 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
114
115 /* registers for each SATA port */
116 PORT_LST_ADDR = 0x00, /* command list DMA addr */
117 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
118 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
119 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
120 PORT_IRQ_STAT = 0x10, /* interrupt status */
121 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
122 PORT_CMD = 0x18, /* port command */
123 PORT_TFDATA = 0x20, /* taskfile data */
124 PORT_SIG = 0x24, /* device TF signature */
125 PORT_CMD_ISSUE = 0x38, /* command issue */
126 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
127 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
128 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
129 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
130 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
131
132 /* PORT_IRQ_{STAT,MASK} bits */
133 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
134 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
135 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
136 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
137 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
138 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
139 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
140 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
141
142 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
143 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
144 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
145 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
146 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
147 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
148 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
149 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
150 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
151
152 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
153 PORT_IRQ_IF_ERR |
154 PORT_IRQ_CONNECT |
155 PORT_IRQ_PHYRDY |
156 PORT_IRQ_UNK_FIS |
157 PORT_IRQ_BAD_PMP,
158 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
159 PORT_IRQ_TF_ERR |
160 PORT_IRQ_HBUS_DATA_ERR,
161 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
162 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
163 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
164
165 /* PORT_CMD bits */
166 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
167 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
168 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
169 PORT_CMD_PMP = (1 << 17), /* PMP attached */
170 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
171 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
172 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
173 PORT_CMD_CLO = (1 << 3), /* Command list override */
174 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
175 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
176 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
177
178 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
179 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
180 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
181 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
182
183 /* hpriv->flags bits */
184 AHCI_HFLAG_NO_NCQ = (1 << 0),
185 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
186 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
187 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
188 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
189 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
190 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
191 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
192 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
193
194 /* ap->flags bits */
195
196 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
197 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
198 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
199 ATA_FLAG_IPM,
200
201 ICH_MAP = 0x90, /* ICH MAP register */
202 };
203
204 struct ahci_cmd_hdr {
205 __le32 opts;
206 __le32 status;
207 __le32 tbl_addr;
208 __le32 tbl_addr_hi;
209 __le32 reserved[4];
210 };
211
212 struct ahci_sg {
213 __le32 addr;
214 __le32 addr_hi;
215 __le32 reserved;
216 __le32 flags_size;
217 };
218
219 struct ahci_host_priv {
220 unsigned int flags; /* AHCI_HFLAG_* */
221 u32 cap; /* cap to use */
222 u32 port_map; /* port map to use */
223 u32 saved_cap; /* saved initial cap */
224 u32 saved_port_map; /* saved initial port_map */
225 };
226
227 struct ahci_port_priv {
228 struct ata_link *active_link;
229 struct ahci_cmd_hdr *cmd_slot;
230 dma_addr_t cmd_slot_dma;
231 void *cmd_tbl;
232 dma_addr_t cmd_tbl_dma;
233 void *rx_fis;
234 dma_addr_t rx_fis_dma;
235 /* for NCQ spurious interrupt analysis */
236 unsigned int ncq_saw_d2h:1;
237 unsigned int ncq_saw_dmas:1;
238 unsigned int ncq_saw_sdb:1;
239 u32 intr_mask; /* interrupts to enable */
240 };
241
242 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
243 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
244 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
245 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
246 static int ahci_port_start(struct ata_port *ap);
247 static void ahci_port_stop(struct ata_port *ap);
248 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
249 static void ahci_qc_prep(struct ata_queued_cmd *qc);
250 static u8 ahci_check_status(struct ata_port *ap);
251 static void ahci_freeze(struct ata_port *ap);
252 static void ahci_thaw(struct ata_port *ap);
253 static void ahci_pmp_attach(struct ata_port *ap);
254 static void ahci_pmp_detach(struct ata_port *ap);
255 static void ahci_error_handler(struct ata_port *ap);
256 static void ahci_vt8251_error_handler(struct ata_port *ap);
257 static void ahci_p5wdh_error_handler(struct ata_port *ap);
258 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
259 static int ahci_port_resume(struct ata_port *ap);
260 static void ahci_dev_config(struct ata_device *dev);
261 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
262 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
263 u32 opts);
264 #ifdef CONFIG_PM
265 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
266 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
267 static int ahci_pci_device_resume(struct pci_dev *pdev);
268 #endif
269
270 static struct class_device_attribute *ahci_shost_attrs[] = {
271 &class_device_attr_link_power_management_policy,
272 NULL
273 };
274
275 static struct scsi_host_template ahci_sht = {
276 ATA_NCQ_SHT(DRV_NAME),
277 .can_queue = AHCI_MAX_CMDS - 1,
278 .sg_tablesize = AHCI_MAX_SG,
279 .dma_boundary = AHCI_DMA_BOUNDARY,
280 .shost_attrs = ahci_shost_attrs,
281 };
282
283 static struct ata_port_operations ahci_ops = {
284 .inherits = &sata_pmp_port_ops,
285
286 .check_status = ahci_check_status,
287 .check_altstatus = ahci_check_status,
288
289 .tf_read = ahci_tf_read,
290 .qc_defer = sata_pmp_qc_defer_cmd_switch,
291 .qc_prep = ahci_qc_prep,
292 .qc_issue = ahci_qc_issue,
293
294 .freeze = ahci_freeze,
295 .thaw = ahci_thaw,
296 .error_handler = ahci_error_handler,
297 .post_internal_cmd = ahci_post_internal_cmd,
298 .dev_config = ahci_dev_config,
299
300 .scr_read = ahci_scr_read,
301 .scr_write = ahci_scr_write,
302 .pmp_attach = ahci_pmp_attach,
303 .pmp_detach = ahci_pmp_detach,
304
305 .enable_pm = ahci_enable_alpm,
306 .disable_pm = ahci_disable_alpm,
307 #ifdef CONFIG_PM
308 .port_suspend = ahci_port_suspend,
309 .port_resume = ahci_port_resume,
310 #endif
311 .port_start = ahci_port_start,
312 .port_stop = ahci_port_stop,
313 };
314
315 static struct ata_port_operations ahci_vt8251_ops = {
316 .inherits = &ahci_ops,
317 .error_handler = ahci_vt8251_error_handler,
318 };
319
320 static struct ata_port_operations ahci_p5wdh_ops = {
321 .inherits = &ahci_ops,
322 .error_handler = ahci_p5wdh_error_handler,
323 };
324
325 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
326
327 static const struct ata_port_info ahci_port_info[] = {
328 /* board_ahci */
329 {
330 .flags = AHCI_FLAG_COMMON,
331 .pio_mask = 0x1f, /* pio0-4 */
332 .udma_mask = ATA_UDMA6,
333 .port_ops = &ahci_ops,
334 },
335 /* board_ahci_vt8251 */
336 {
337 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
338 .flags = AHCI_FLAG_COMMON,
339 .pio_mask = 0x1f, /* pio0-4 */
340 .udma_mask = ATA_UDMA6,
341 .port_ops = &ahci_vt8251_ops,
342 },
343 /* board_ahci_ign_iferr */
344 {
345 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
346 .flags = AHCI_FLAG_COMMON,
347 .pio_mask = 0x1f, /* pio0-4 */
348 .udma_mask = ATA_UDMA6,
349 .port_ops = &ahci_ops,
350 },
351 /* board_ahci_sb600 */
352 {
353 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
354 AHCI_HFLAG_32BIT_ONLY |
355 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
356 .flags = AHCI_FLAG_COMMON,
357 .pio_mask = 0x1f, /* pio0-4 */
358 .udma_mask = ATA_UDMA6,
359 .port_ops = &ahci_ops,
360 },
361 /* board_ahci_mv */
362 {
363 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
364 AHCI_HFLAG_MV_PATA),
365 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
366 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
367 .pio_mask = 0x1f, /* pio0-4 */
368 .udma_mask = ATA_UDMA6,
369 .port_ops = &ahci_ops,
370 },
371 /* board_ahci_sb700 */
372 {
373 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
374 AHCI_HFLAG_NO_PMP),
375 .flags = AHCI_FLAG_COMMON,
376 .pio_mask = 0x1f, /* pio0-4 */
377 .udma_mask = ATA_UDMA6,
378 .port_ops = &ahci_ops,
379 },
380 };
381
382 static const struct pci_device_id ahci_pci_tbl[] = {
383 /* Intel */
384 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
385 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
386 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
387 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
388 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
389 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
390 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
391 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
392 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
393 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
394 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
395 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
396 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
397 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
398 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
399 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
400 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
401 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
402 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
403 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
404 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
405 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
406 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
407 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
408 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
409 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
410 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
411 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
412 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
413 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
414 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
415
416 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
417 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
418 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
419
420 /* ATI */
421 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
422 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
423 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
424 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
425 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
426 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
427 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
428
429 /* VIA */
430 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
431 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
432
433 /* NVIDIA */
434 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
435 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
436 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
437 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
438 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
439 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
440 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
441 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
442 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
445 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
446 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
447 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
448 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
449 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
450 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
451 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
452 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
453 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
454 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
479 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
480 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
482 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
483 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
491 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
492 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
493 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
494 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
495 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
496 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
497 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
498 { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */
499 { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */
500 { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */
501 { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */
502
503 /* SiS */
504 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
505 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
506 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
507
508 /* Marvell */
509 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
510 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
511
512 /* Generic, PCI class code for AHCI */
513 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
514 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
515
516 { } /* terminate list */
517 };
518
519
520 static struct pci_driver ahci_pci_driver = {
521 .name = DRV_NAME,
522 .id_table = ahci_pci_tbl,
523 .probe = ahci_init_one,
524 .remove = ata_pci_remove_one,
525 #ifdef CONFIG_PM
526 .suspend = ahci_pci_device_suspend,
527 .resume = ahci_pci_device_resume,
528 #endif
529 };
530
531
532 static inline int ahci_nr_ports(u32 cap)
533 {
534 return (cap & 0x1f) + 1;
535 }
536
537 static inline void __iomem *__ahci_port_base(struct ata_host *host,
538 unsigned int port_no)
539 {
540 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
541
542 return mmio + 0x100 + (port_no * 0x80);
543 }
544
545 static inline void __iomem *ahci_port_base(struct ata_port *ap)
546 {
547 return __ahci_port_base(ap->host, ap->port_no);
548 }
549
550 static void ahci_enable_ahci(void __iomem *mmio)
551 {
552 u32 tmp;
553
554 /* turn on AHCI_EN */
555 tmp = readl(mmio + HOST_CTL);
556 if (!(tmp & HOST_AHCI_EN)) {
557 tmp |= HOST_AHCI_EN;
558 writel(tmp, mmio + HOST_CTL);
559 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
560 WARN_ON(!(tmp & HOST_AHCI_EN));
561 }
562 }
563
564 /**
565 * ahci_save_initial_config - Save and fixup initial config values
566 * @pdev: target PCI device
567 * @hpriv: host private area to store config values
568 *
569 * Some registers containing configuration info might be setup by
570 * BIOS and might be cleared on reset. This function saves the
571 * initial values of those registers into @hpriv such that they
572 * can be restored after controller reset.
573 *
574 * If inconsistent, config values are fixed up by this function.
575 *
576 * LOCKING:
577 * None.
578 */
579 static void ahci_save_initial_config(struct pci_dev *pdev,
580 struct ahci_host_priv *hpriv)
581 {
582 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
583 u32 cap, port_map;
584 int i;
585 int mv;
586
587 /* make sure AHCI mode is enabled before accessing CAP */
588 ahci_enable_ahci(mmio);
589
590 /* Values prefixed with saved_ are written back to host after
591 * reset. Values without are used for driver operation.
592 */
593 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
594 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
595
596 /* some chips have errata preventing 64bit use */
597 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
598 dev_printk(KERN_INFO, &pdev->dev,
599 "controller can't do 64bit DMA, forcing 32bit\n");
600 cap &= ~HOST_CAP_64;
601 }
602
603 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
604 dev_printk(KERN_INFO, &pdev->dev,
605 "controller can't do NCQ, turning off CAP_NCQ\n");
606 cap &= ~HOST_CAP_NCQ;
607 }
608
609 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
610 dev_printk(KERN_INFO, &pdev->dev,
611 "controller can't do PMP, turning off CAP_PMP\n");
612 cap &= ~HOST_CAP_PMP;
613 }
614
615 /*
616 * Temporary Marvell 6145 hack: PATA port presence
617 * is asserted through the standard AHCI port
618 * presence register, as bit 4 (counting from 0)
619 */
620 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
621 if (pdev->device == 0x6121)
622 mv = 0x3;
623 else
624 mv = 0xf;
625 dev_printk(KERN_ERR, &pdev->dev,
626 "MV_AHCI HACK: port_map %x -> %x\n",
627 port_map,
628 port_map & mv);
629
630 port_map &= mv;
631 }
632
633 /* cross check port_map and cap.n_ports */
634 if (port_map) {
635 int map_ports = 0;
636
637 for (i = 0; i < AHCI_MAX_PORTS; i++)
638 if (port_map & (1 << i))
639 map_ports++;
640
641 /* If PI has more ports than n_ports, whine, clear
642 * port_map and let it be generated from n_ports.
643 */
644 if (map_ports > ahci_nr_ports(cap)) {
645 dev_printk(KERN_WARNING, &pdev->dev,
646 "implemented port map (0x%x) contains more "
647 "ports than nr_ports (%u), using nr_ports\n",
648 port_map, ahci_nr_ports(cap));
649 port_map = 0;
650 }
651 }
652
653 /* fabricate port_map from cap.nr_ports */
654 if (!port_map) {
655 port_map = (1 << ahci_nr_ports(cap)) - 1;
656 dev_printk(KERN_WARNING, &pdev->dev,
657 "forcing PORTS_IMPL to 0x%x\n", port_map);
658
659 /* write the fixed up value to the PI register */
660 hpriv->saved_port_map = port_map;
661 }
662
663 /* record values to use during operation */
664 hpriv->cap = cap;
665 hpriv->port_map = port_map;
666 }
667
668 /**
669 * ahci_restore_initial_config - Restore initial config
670 * @host: target ATA host
671 *
672 * Restore initial config stored by ahci_save_initial_config().
673 *
674 * LOCKING:
675 * None.
676 */
677 static void ahci_restore_initial_config(struct ata_host *host)
678 {
679 struct ahci_host_priv *hpriv = host->private_data;
680 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
681
682 writel(hpriv->saved_cap, mmio + HOST_CAP);
683 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
684 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
685 }
686
687 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
688 {
689 static const int offset[] = {
690 [SCR_STATUS] = PORT_SCR_STAT,
691 [SCR_CONTROL] = PORT_SCR_CTL,
692 [SCR_ERROR] = PORT_SCR_ERR,
693 [SCR_ACTIVE] = PORT_SCR_ACT,
694 [SCR_NOTIFICATION] = PORT_SCR_NTF,
695 };
696 struct ahci_host_priv *hpriv = ap->host->private_data;
697
698 if (sc_reg < ARRAY_SIZE(offset) &&
699 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
700 return offset[sc_reg];
701 return 0;
702 }
703
704 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
705 {
706 void __iomem *port_mmio = ahci_port_base(ap);
707 int offset = ahci_scr_offset(ap, sc_reg);
708
709 if (offset) {
710 *val = readl(port_mmio + offset);
711 return 0;
712 }
713 return -EINVAL;
714 }
715
716 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
717 {
718 void __iomem *port_mmio = ahci_port_base(ap);
719 int offset = ahci_scr_offset(ap, sc_reg);
720
721 if (offset) {
722 writel(val, port_mmio + offset);
723 return 0;
724 }
725 return -EINVAL;
726 }
727
728 static void ahci_start_engine(struct ata_port *ap)
729 {
730 void __iomem *port_mmio = ahci_port_base(ap);
731 u32 tmp;
732
733 /* start DMA */
734 tmp = readl(port_mmio + PORT_CMD);
735 tmp |= PORT_CMD_START;
736 writel(tmp, port_mmio + PORT_CMD);
737 readl(port_mmio + PORT_CMD); /* flush */
738 }
739
740 static int ahci_stop_engine(struct ata_port *ap)
741 {
742 void __iomem *port_mmio = ahci_port_base(ap);
743 u32 tmp;
744
745 tmp = readl(port_mmio + PORT_CMD);
746
747 /* check if the HBA is idle */
748 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
749 return 0;
750
751 /* setting HBA to idle */
752 tmp &= ~PORT_CMD_START;
753 writel(tmp, port_mmio + PORT_CMD);
754
755 /* wait for engine to stop. This could be as long as 500 msec */
756 tmp = ata_wait_register(port_mmio + PORT_CMD,
757 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
758 if (tmp & PORT_CMD_LIST_ON)
759 return -EIO;
760
761 return 0;
762 }
763
764 static void ahci_start_fis_rx(struct ata_port *ap)
765 {
766 void __iomem *port_mmio = ahci_port_base(ap);
767 struct ahci_host_priv *hpriv = ap->host->private_data;
768 struct ahci_port_priv *pp = ap->private_data;
769 u32 tmp;
770
771 /* set FIS registers */
772 if (hpriv->cap & HOST_CAP_64)
773 writel((pp->cmd_slot_dma >> 16) >> 16,
774 port_mmio + PORT_LST_ADDR_HI);
775 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
776
777 if (hpriv->cap & HOST_CAP_64)
778 writel((pp->rx_fis_dma >> 16) >> 16,
779 port_mmio + PORT_FIS_ADDR_HI);
780 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
781
782 /* enable FIS reception */
783 tmp = readl(port_mmio + PORT_CMD);
784 tmp |= PORT_CMD_FIS_RX;
785 writel(tmp, port_mmio + PORT_CMD);
786
787 /* flush */
788 readl(port_mmio + PORT_CMD);
789 }
790
791 static int ahci_stop_fis_rx(struct ata_port *ap)
792 {
793 void __iomem *port_mmio = ahci_port_base(ap);
794 u32 tmp;
795
796 /* disable FIS reception */
797 tmp = readl(port_mmio + PORT_CMD);
798 tmp &= ~PORT_CMD_FIS_RX;
799 writel(tmp, port_mmio + PORT_CMD);
800
801 /* wait for completion, spec says 500ms, give it 1000 */
802 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
803 PORT_CMD_FIS_ON, 10, 1000);
804 if (tmp & PORT_CMD_FIS_ON)
805 return -EBUSY;
806
807 return 0;
808 }
809
810 static void ahci_power_up(struct ata_port *ap)
811 {
812 struct ahci_host_priv *hpriv = ap->host->private_data;
813 void __iomem *port_mmio = ahci_port_base(ap);
814 u32 cmd;
815
816 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
817
818 /* spin up device */
819 if (hpriv->cap & HOST_CAP_SSS) {
820 cmd |= PORT_CMD_SPIN_UP;
821 writel(cmd, port_mmio + PORT_CMD);
822 }
823
824 /* wake up link */
825 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
826 }
827
828 static void ahci_disable_alpm(struct ata_port *ap)
829 {
830 struct ahci_host_priv *hpriv = ap->host->private_data;
831 void __iomem *port_mmio = ahci_port_base(ap);
832 u32 cmd;
833 struct ahci_port_priv *pp = ap->private_data;
834
835 /* IPM bits should be disabled by libata-core */
836 /* get the existing command bits */
837 cmd = readl(port_mmio + PORT_CMD);
838
839 /* disable ALPM and ASP */
840 cmd &= ~PORT_CMD_ASP;
841 cmd &= ~PORT_CMD_ALPE;
842
843 /* force the interface back to active */
844 cmd |= PORT_CMD_ICC_ACTIVE;
845
846 /* write out new cmd value */
847 writel(cmd, port_mmio + PORT_CMD);
848 cmd = readl(port_mmio + PORT_CMD);
849
850 /* wait 10ms to be sure we've come out of any low power state */
851 msleep(10);
852
853 /* clear out any PhyRdy stuff from interrupt status */
854 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
855
856 /* go ahead and clean out PhyRdy Change from Serror too */
857 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
858
859 /*
860 * Clear flag to indicate that we should ignore all PhyRdy
861 * state changes
862 */
863 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
864
865 /*
866 * Enable interrupts on Phy Ready.
867 */
868 pp->intr_mask |= PORT_IRQ_PHYRDY;
869 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
870
871 /*
872 * don't change the link pm policy - we can be called
873 * just to turn of link pm temporarily
874 */
875 }
876
877 static int ahci_enable_alpm(struct ata_port *ap,
878 enum link_pm policy)
879 {
880 struct ahci_host_priv *hpriv = ap->host->private_data;
881 void __iomem *port_mmio = ahci_port_base(ap);
882 u32 cmd;
883 struct ahci_port_priv *pp = ap->private_data;
884 u32 asp;
885
886 /* Make sure the host is capable of link power management */
887 if (!(hpriv->cap & HOST_CAP_ALPM))
888 return -EINVAL;
889
890 switch (policy) {
891 case MAX_PERFORMANCE:
892 case NOT_AVAILABLE:
893 /*
894 * if we came here with NOT_AVAILABLE,
895 * it just means this is the first time we
896 * have tried to enable - default to max performance,
897 * and let the user go to lower power modes on request.
898 */
899 ahci_disable_alpm(ap);
900 return 0;
901 case MIN_POWER:
902 /* configure HBA to enter SLUMBER */
903 asp = PORT_CMD_ASP;
904 break;
905 case MEDIUM_POWER:
906 /* configure HBA to enter PARTIAL */
907 asp = 0;
908 break;
909 default:
910 return -EINVAL;
911 }
912
913 /*
914 * Disable interrupts on Phy Ready. This keeps us from
915 * getting woken up due to spurious phy ready interrupts
916 * TBD - Hot plug should be done via polling now, is
917 * that even supported?
918 */
919 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
920 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
921
922 /*
923 * Set a flag to indicate that we should ignore all PhyRdy
924 * state changes since these can happen now whenever we
925 * change link state
926 */
927 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
928
929 /* get the existing command bits */
930 cmd = readl(port_mmio + PORT_CMD);
931
932 /*
933 * Set ASP based on Policy
934 */
935 cmd |= asp;
936
937 /*
938 * Setting this bit will instruct the HBA to aggressively
939 * enter a lower power link state when it's appropriate and
940 * based on the value set above for ASP
941 */
942 cmd |= PORT_CMD_ALPE;
943
944 /* write out new cmd value */
945 writel(cmd, port_mmio + PORT_CMD);
946 cmd = readl(port_mmio + PORT_CMD);
947
948 /* IPM bits should be set by libata-core */
949 return 0;
950 }
951
952 #ifdef CONFIG_PM
953 static void ahci_power_down(struct ata_port *ap)
954 {
955 struct ahci_host_priv *hpriv = ap->host->private_data;
956 void __iomem *port_mmio = ahci_port_base(ap);
957 u32 cmd, scontrol;
958
959 if (!(hpriv->cap & HOST_CAP_SSS))
960 return;
961
962 /* put device into listen mode, first set PxSCTL.DET to 0 */
963 scontrol = readl(port_mmio + PORT_SCR_CTL);
964 scontrol &= ~0xf;
965 writel(scontrol, port_mmio + PORT_SCR_CTL);
966
967 /* then set PxCMD.SUD to 0 */
968 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
969 cmd &= ~PORT_CMD_SPIN_UP;
970 writel(cmd, port_mmio + PORT_CMD);
971 }
972 #endif
973
974 static void ahci_start_port(struct ata_port *ap)
975 {
976 /* enable FIS reception */
977 ahci_start_fis_rx(ap);
978
979 /* enable DMA */
980 ahci_start_engine(ap);
981 }
982
983 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
984 {
985 int rc;
986
987 /* disable DMA */
988 rc = ahci_stop_engine(ap);
989 if (rc) {
990 *emsg = "failed to stop engine";
991 return rc;
992 }
993
994 /* disable FIS reception */
995 rc = ahci_stop_fis_rx(ap);
996 if (rc) {
997 *emsg = "failed stop FIS RX";
998 return rc;
999 }
1000
1001 return 0;
1002 }
1003
1004 static int ahci_reset_controller(struct ata_host *host)
1005 {
1006 struct pci_dev *pdev = to_pci_dev(host->dev);
1007 struct ahci_host_priv *hpriv = host->private_data;
1008 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1009 u32 tmp;
1010
1011 /* we must be in AHCI mode, before using anything
1012 * AHCI-specific, such as HOST_RESET.
1013 */
1014 ahci_enable_ahci(mmio);
1015
1016 /* global controller reset */
1017 if (!ahci_skip_host_reset) {
1018 tmp = readl(mmio + HOST_CTL);
1019 if ((tmp & HOST_RESET) == 0) {
1020 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1021 readl(mmio + HOST_CTL); /* flush */
1022 }
1023
1024 /* reset must complete within 1 second, or
1025 * the hardware should be considered fried.
1026 */
1027 ssleep(1);
1028
1029 tmp = readl(mmio + HOST_CTL);
1030 if (tmp & HOST_RESET) {
1031 dev_printk(KERN_ERR, host->dev,
1032 "controller reset failed (0x%x)\n", tmp);
1033 return -EIO;
1034 }
1035
1036 /* turn on AHCI mode */
1037 ahci_enable_ahci(mmio);
1038
1039 /* Some registers might be cleared on reset. Restore
1040 * initial values.
1041 */
1042 ahci_restore_initial_config(host);
1043 } else
1044 dev_printk(KERN_INFO, host->dev,
1045 "skipping global host reset\n");
1046
1047 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1048 u16 tmp16;
1049
1050 /* configure PCS */
1051 pci_read_config_word(pdev, 0x92, &tmp16);
1052 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1053 tmp16 |= hpriv->port_map;
1054 pci_write_config_word(pdev, 0x92, tmp16);
1055 }
1056 }
1057
1058 return 0;
1059 }
1060
1061 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1062 int port_no, void __iomem *mmio,
1063 void __iomem *port_mmio)
1064 {
1065 const char *emsg = NULL;
1066 int rc;
1067 u32 tmp;
1068
1069 /* make sure port is not active */
1070 rc = ahci_deinit_port(ap, &emsg);
1071 if (rc)
1072 dev_printk(KERN_WARNING, &pdev->dev,
1073 "%s (%d)\n", emsg, rc);
1074
1075 /* clear SError */
1076 tmp = readl(port_mmio + PORT_SCR_ERR);
1077 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1078 writel(tmp, port_mmio + PORT_SCR_ERR);
1079
1080 /* clear port IRQ */
1081 tmp = readl(port_mmio + PORT_IRQ_STAT);
1082 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1083 if (tmp)
1084 writel(tmp, port_mmio + PORT_IRQ_STAT);
1085
1086 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1087 }
1088
1089 static void ahci_init_controller(struct ata_host *host)
1090 {
1091 struct ahci_host_priv *hpriv = host->private_data;
1092 struct pci_dev *pdev = to_pci_dev(host->dev);
1093 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1094 int i;
1095 void __iomem *port_mmio;
1096 u32 tmp;
1097 int mv;
1098
1099 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1100 if (pdev->device == 0x6121)
1101 mv = 2;
1102 else
1103 mv = 4;
1104 port_mmio = __ahci_port_base(host, mv);
1105
1106 writel(0, port_mmio + PORT_IRQ_MASK);
1107
1108 /* clear port IRQ */
1109 tmp = readl(port_mmio + PORT_IRQ_STAT);
1110 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1111 if (tmp)
1112 writel(tmp, port_mmio + PORT_IRQ_STAT);
1113 }
1114
1115 for (i = 0; i < host->n_ports; i++) {
1116 struct ata_port *ap = host->ports[i];
1117
1118 port_mmio = ahci_port_base(ap);
1119 if (ata_port_is_dummy(ap))
1120 continue;
1121
1122 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1123 }
1124
1125 tmp = readl(mmio + HOST_CTL);
1126 VPRINTK("HOST_CTL 0x%x\n", tmp);
1127 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1128 tmp = readl(mmio + HOST_CTL);
1129 VPRINTK("HOST_CTL 0x%x\n", tmp);
1130 }
1131
1132 static void ahci_dev_config(struct ata_device *dev)
1133 {
1134 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1135
1136 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1137 dev->max_sectors = 255;
1138 ata_dev_printk(dev, KERN_INFO,
1139 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1140 }
1141 }
1142
1143 static unsigned int ahci_dev_classify(struct ata_port *ap)
1144 {
1145 void __iomem *port_mmio = ahci_port_base(ap);
1146 struct ata_taskfile tf;
1147 u32 tmp;
1148
1149 tmp = readl(port_mmio + PORT_SIG);
1150 tf.lbah = (tmp >> 24) & 0xff;
1151 tf.lbam = (tmp >> 16) & 0xff;
1152 tf.lbal = (tmp >> 8) & 0xff;
1153 tf.nsect = (tmp) & 0xff;
1154
1155 return ata_dev_classify(&tf);
1156 }
1157
1158 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1159 u32 opts)
1160 {
1161 dma_addr_t cmd_tbl_dma;
1162
1163 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1164
1165 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1166 pp->cmd_slot[tag].status = 0;
1167 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1168 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1169 }
1170
1171 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1172 {
1173 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1174 struct ahci_host_priv *hpriv = ap->host->private_data;
1175 u32 tmp;
1176 int busy, rc;
1177
1178 /* do we need to kick the port? */
1179 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1180 if (!busy && !force_restart)
1181 return 0;
1182
1183 /* stop engine */
1184 rc = ahci_stop_engine(ap);
1185 if (rc)
1186 goto out_restart;
1187
1188 /* need to do CLO? */
1189 if (!busy) {
1190 rc = 0;
1191 goto out_restart;
1192 }
1193
1194 if (!(hpriv->cap & HOST_CAP_CLO)) {
1195 rc = -EOPNOTSUPP;
1196 goto out_restart;
1197 }
1198
1199 /* perform CLO */
1200 tmp = readl(port_mmio + PORT_CMD);
1201 tmp |= PORT_CMD_CLO;
1202 writel(tmp, port_mmio + PORT_CMD);
1203
1204 rc = 0;
1205 tmp = ata_wait_register(port_mmio + PORT_CMD,
1206 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1207 if (tmp & PORT_CMD_CLO)
1208 rc = -EIO;
1209
1210 /* restart engine */
1211 out_restart:
1212 ahci_start_engine(ap);
1213 return rc;
1214 }
1215
1216 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1217 struct ata_taskfile *tf, int is_cmd, u16 flags,
1218 unsigned long timeout_msec)
1219 {
1220 const u32 cmd_fis_len = 5; /* five dwords */
1221 struct ahci_port_priv *pp = ap->private_data;
1222 void __iomem *port_mmio = ahci_port_base(ap);
1223 u8 *fis = pp->cmd_tbl;
1224 u32 tmp;
1225
1226 /* prep the command */
1227 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1228 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1229
1230 /* issue & wait */
1231 writel(1, port_mmio + PORT_CMD_ISSUE);
1232
1233 if (timeout_msec) {
1234 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1235 1, timeout_msec);
1236 if (tmp & 0x1) {
1237 ahci_kick_engine(ap, 1);
1238 return -EBUSY;
1239 }
1240 } else
1241 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1242
1243 return 0;
1244 }
1245
1246 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1247 int pmp, unsigned long deadline)
1248 {
1249 struct ata_port *ap = link->ap;
1250 const char *reason = NULL;
1251 unsigned long now, msecs;
1252 struct ata_taskfile tf;
1253 int rc;
1254
1255 DPRINTK("ENTER\n");
1256
1257 if (ata_link_offline(link)) {
1258 DPRINTK("PHY reports no device\n");
1259 *class = ATA_DEV_NONE;
1260 return 0;
1261 }
1262
1263 /* prepare for SRST (AHCI-1.1 10.4.1) */
1264 rc = ahci_kick_engine(ap, 1);
1265 if (rc && rc != -EOPNOTSUPP)
1266 ata_link_printk(link, KERN_WARNING,
1267 "failed to reset engine (errno=%d)\n", rc);
1268
1269 ata_tf_init(link->device, &tf);
1270
1271 /* issue the first D2H Register FIS */
1272 msecs = 0;
1273 now = jiffies;
1274 if (time_after(now, deadline))
1275 msecs = jiffies_to_msecs(deadline - now);
1276
1277 tf.ctl |= ATA_SRST;
1278 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1279 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1280 rc = -EIO;
1281 reason = "1st FIS failed";
1282 goto fail;
1283 }
1284
1285 /* spec says at least 5us, but be generous and sleep for 1ms */
1286 msleep(1);
1287
1288 /* issue the second D2H Register FIS */
1289 tf.ctl &= ~ATA_SRST;
1290 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1291
1292 /* wait a while before checking status */
1293 ata_wait_after_reset(ap, deadline);
1294
1295 rc = ata_wait_ready(ap, deadline);
1296 /* link occupied, -ENODEV too is an error */
1297 if (rc) {
1298 reason = "device not ready";
1299 goto fail;
1300 }
1301 *class = ahci_dev_classify(ap);
1302
1303 DPRINTK("EXIT, class=%u\n", *class);
1304 return 0;
1305
1306 fail:
1307 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1308 return rc;
1309 }
1310
1311 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1312 unsigned long deadline)
1313 {
1314 int pmp = 0;
1315
1316 if (link->ap->flags & ATA_FLAG_PMP)
1317 pmp = SATA_PMP_CTRL_PORT;
1318
1319 return ahci_do_softreset(link, class, pmp, deadline);
1320 }
1321
1322 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1323 unsigned long deadline)
1324 {
1325 struct ata_port *ap = link->ap;
1326 struct ahci_port_priv *pp = ap->private_data;
1327 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1328 struct ata_taskfile tf;
1329 int rc;
1330
1331 DPRINTK("ENTER\n");
1332
1333 ahci_stop_engine(ap);
1334
1335 /* clear D2H reception area to properly wait for D2H FIS */
1336 ata_tf_init(link->device, &tf);
1337 tf.command = 0x80;
1338 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1339
1340 rc = sata_std_hardreset(link, class, deadline);
1341
1342 ahci_start_engine(ap);
1343
1344 if (rc == 0 && ata_link_online(link))
1345 *class = ahci_dev_classify(ap);
1346 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1347 *class = ATA_DEV_NONE;
1348
1349 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1350 return rc;
1351 }
1352
1353 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1354 unsigned long deadline)
1355 {
1356 struct ata_port *ap = link->ap;
1357 u32 serror;
1358 int rc;
1359
1360 DPRINTK("ENTER\n");
1361
1362 ahci_stop_engine(ap);
1363
1364 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1365 deadline);
1366
1367 /* vt8251 needs SError cleared for the port to operate */
1368 ahci_scr_read(ap, SCR_ERROR, &serror);
1369 ahci_scr_write(ap, SCR_ERROR, serror);
1370
1371 ahci_start_engine(ap);
1372
1373 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1374
1375 /* vt8251 doesn't clear BSY on signature FIS reception,
1376 * request follow-up softreset.
1377 */
1378 return rc ?: -EAGAIN;
1379 }
1380
1381 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1382 unsigned long deadline)
1383 {
1384 struct ata_port *ap = link->ap;
1385 struct ahci_port_priv *pp = ap->private_data;
1386 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1387 struct ata_taskfile tf;
1388 int rc;
1389
1390 ahci_stop_engine(ap);
1391
1392 /* clear D2H reception area to properly wait for D2H FIS */
1393 ata_tf_init(link->device, &tf);
1394 tf.command = 0x80;
1395 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1396
1397 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1398 deadline);
1399
1400 ahci_start_engine(ap);
1401
1402 if (rc || ata_link_offline(link))
1403 return rc;
1404
1405 /* spec mandates ">= 2ms" before checking status */
1406 msleep(150);
1407
1408 /* The pseudo configuration device on SIMG4726 attached to
1409 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1410 * hardreset if no device is attached to the first downstream
1411 * port && the pseudo device locks up on SRST w/ PMP==0. To
1412 * work around this, wait for !BSY only briefly. If BSY isn't
1413 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1414 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1415 *
1416 * Wait for two seconds. Devices attached to downstream port
1417 * which can't process the following IDENTIFY after this will
1418 * have to be reset again. For most cases, this should
1419 * suffice while making probing snappish enough.
1420 */
1421 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1422 if (rc)
1423 ahci_kick_engine(ap, 0);
1424
1425 return 0;
1426 }
1427
1428 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1429 {
1430 struct ata_port *ap = link->ap;
1431 void __iomem *port_mmio = ahci_port_base(ap);
1432 u32 new_tmp, tmp;
1433
1434 ata_std_postreset(link, class);
1435
1436 /* Make sure port's ATAPI bit is set appropriately */
1437 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1438 if (*class == ATA_DEV_ATAPI)
1439 new_tmp |= PORT_CMD_ATAPI;
1440 else
1441 new_tmp &= ~PORT_CMD_ATAPI;
1442 if (new_tmp != tmp) {
1443 writel(new_tmp, port_mmio + PORT_CMD);
1444 readl(port_mmio + PORT_CMD); /* flush */
1445 }
1446 }
1447
1448 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1449 unsigned long deadline)
1450 {
1451 return ahci_do_softreset(link, class, link->pmp, deadline);
1452 }
1453
1454 static u8 ahci_check_status(struct ata_port *ap)
1455 {
1456 void __iomem *mmio = ap->ioaddr.cmd_addr;
1457
1458 return readl(mmio + PORT_TFDATA) & 0xFF;
1459 }
1460
1461 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1462 {
1463 struct ahci_port_priv *pp = ap->private_data;
1464 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1465
1466 ata_tf_from_fis(d2h_fis, tf);
1467 }
1468
1469 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1470 {
1471 struct scatterlist *sg;
1472 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1473 unsigned int si;
1474
1475 VPRINTK("ENTER\n");
1476
1477 /*
1478 * Next, the S/G list.
1479 */
1480 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1481 dma_addr_t addr = sg_dma_address(sg);
1482 u32 sg_len = sg_dma_len(sg);
1483
1484 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1485 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1486 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1487 }
1488
1489 return si;
1490 }
1491
1492 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1493 {
1494 struct ata_port *ap = qc->ap;
1495 struct ahci_port_priv *pp = ap->private_data;
1496 int is_atapi = ata_is_atapi(qc->tf.protocol);
1497 void *cmd_tbl;
1498 u32 opts;
1499 const u32 cmd_fis_len = 5; /* five dwords */
1500 unsigned int n_elem;
1501
1502 /*
1503 * Fill in command table information. First, the header,
1504 * a SATA Register - Host to Device command FIS.
1505 */
1506 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1507
1508 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1509 if (is_atapi) {
1510 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1511 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1512 }
1513
1514 n_elem = 0;
1515 if (qc->flags & ATA_QCFLAG_DMAMAP)
1516 n_elem = ahci_fill_sg(qc, cmd_tbl);
1517
1518 /*
1519 * Fill in command slot information.
1520 */
1521 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1522 if (qc->tf.flags & ATA_TFLAG_WRITE)
1523 opts |= AHCI_CMD_WRITE;
1524 if (is_atapi)
1525 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1526
1527 ahci_fill_cmd_slot(pp, qc->tag, opts);
1528 }
1529
1530 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1531 {
1532 struct ahci_host_priv *hpriv = ap->host->private_data;
1533 struct ahci_port_priv *pp = ap->private_data;
1534 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1535 struct ata_link *link = NULL;
1536 struct ata_queued_cmd *active_qc;
1537 struct ata_eh_info *active_ehi;
1538 u32 serror;
1539
1540 /* determine active link */
1541 ata_port_for_each_link(link, ap)
1542 if (ata_link_active(link))
1543 break;
1544 if (!link)
1545 link = &ap->link;
1546
1547 active_qc = ata_qc_from_tag(ap, link->active_tag);
1548 active_ehi = &link->eh_info;
1549
1550 /* record irq stat */
1551 ata_ehi_clear_desc(host_ehi);
1552 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1553
1554 /* AHCI needs SError cleared; otherwise, it might lock up */
1555 ahci_scr_read(ap, SCR_ERROR, &serror);
1556 ahci_scr_write(ap, SCR_ERROR, serror);
1557 host_ehi->serror |= serror;
1558
1559 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1560 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1561 irq_stat &= ~PORT_IRQ_IF_ERR;
1562
1563 if (irq_stat & PORT_IRQ_TF_ERR) {
1564 /* If qc is active, charge it; otherwise, the active
1565 * link. There's no active qc on NCQ errors. It will
1566 * be determined by EH by reading log page 10h.
1567 */
1568 if (active_qc)
1569 active_qc->err_mask |= AC_ERR_DEV;
1570 else
1571 active_ehi->err_mask |= AC_ERR_DEV;
1572
1573 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1574 host_ehi->serror &= ~SERR_INTERNAL;
1575 }
1576
1577 if (irq_stat & PORT_IRQ_UNK_FIS) {
1578 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1579
1580 active_ehi->err_mask |= AC_ERR_HSM;
1581 active_ehi->action |= ATA_EH_RESET;
1582 ata_ehi_push_desc(active_ehi,
1583 "unknown FIS %08x %08x %08x %08x" ,
1584 unk[0], unk[1], unk[2], unk[3]);
1585 }
1586
1587 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1588 active_ehi->err_mask |= AC_ERR_HSM;
1589 active_ehi->action |= ATA_EH_RESET;
1590 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1591 }
1592
1593 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1594 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1595 host_ehi->action |= ATA_EH_RESET;
1596 ata_ehi_push_desc(host_ehi, "host bus error");
1597 }
1598
1599 if (irq_stat & PORT_IRQ_IF_ERR) {
1600 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1601 host_ehi->action |= ATA_EH_RESET;
1602 ata_ehi_push_desc(host_ehi, "interface fatal error");
1603 }
1604
1605 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1606 ata_ehi_hotplugged(host_ehi);
1607 ata_ehi_push_desc(host_ehi, "%s",
1608 irq_stat & PORT_IRQ_CONNECT ?
1609 "connection status changed" : "PHY RDY changed");
1610 }
1611
1612 /* okay, let's hand over to EH */
1613
1614 if (irq_stat & PORT_IRQ_FREEZE)
1615 ata_port_freeze(ap);
1616 else
1617 ata_port_abort(ap);
1618 }
1619
1620 static void ahci_port_intr(struct ata_port *ap)
1621 {
1622 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1623 struct ata_eh_info *ehi = &ap->link.eh_info;
1624 struct ahci_port_priv *pp = ap->private_data;
1625 struct ahci_host_priv *hpriv = ap->host->private_data;
1626 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1627 u32 status, qc_active;
1628 int rc;
1629
1630 status = readl(port_mmio + PORT_IRQ_STAT);
1631 writel(status, port_mmio + PORT_IRQ_STAT);
1632
1633 /* ignore BAD_PMP while resetting */
1634 if (unlikely(resetting))
1635 status &= ~PORT_IRQ_BAD_PMP;
1636
1637 /* If we are getting PhyRdy, this is
1638 * just a power state change, we should
1639 * clear out this, plus the PhyRdy/Comm
1640 * Wake bits from Serror
1641 */
1642 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1643 (status & PORT_IRQ_PHYRDY)) {
1644 status &= ~PORT_IRQ_PHYRDY;
1645 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1646 }
1647
1648 if (unlikely(status & PORT_IRQ_ERROR)) {
1649 ahci_error_intr(ap, status);
1650 return;
1651 }
1652
1653 if (status & PORT_IRQ_SDB_FIS) {
1654 /* If SNotification is available, leave notification
1655 * handling to sata_async_notification(). If not,
1656 * emulate it by snooping SDB FIS RX area.
1657 *
1658 * Snooping FIS RX area is probably cheaper than
1659 * poking SNotification but some constrollers which
1660 * implement SNotification, ICH9 for example, don't
1661 * store AN SDB FIS into receive area.
1662 */
1663 if (hpriv->cap & HOST_CAP_SNTF)
1664 sata_async_notification(ap);
1665 else {
1666 /* If the 'N' bit in word 0 of the FIS is set,
1667 * we just received asynchronous notification.
1668 * Tell libata about it.
1669 */
1670 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1671 u32 f0 = le32_to_cpu(f[0]);
1672
1673 if (f0 & (1 << 15))
1674 sata_async_notification(ap);
1675 }
1676 }
1677
1678 /* pp->active_link is valid iff any command is in flight */
1679 if (ap->qc_active && pp->active_link->sactive)
1680 qc_active = readl(port_mmio + PORT_SCR_ACT);
1681 else
1682 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1683
1684 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1685
1686 /* while resetting, invalid completions are expected */
1687 if (unlikely(rc < 0 && !resetting)) {
1688 ehi->err_mask |= AC_ERR_HSM;
1689 ehi->action |= ATA_EH_RESET;
1690 ata_port_freeze(ap);
1691 }
1692 }
1693
1694 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1695 {
1696 struct ata_host *host = dev_instance;
1697 struct ahci_host_priv *hpriv;
1698 unsigned int i, handled = 0;
1699 void __iomem *mmio;
1700 u32 irq_stat, irq_ack = 0;
1701
1702 VPRINTK("ENTER\n");
1703
1704 hpriv = host->private_data;
1705 mmio = host->iomap[AHCI_PCI_BAR];
1706
1707 /* sigh. 0xffffffff is a valid return from h/w */
1708 irq_stat = readl(mmio + HOST_IRQ_STAT);
1709 irq_stat &= hpriv->port_map;
1710 if (!irq_stat)
1711 return IRQ_NONE;
1712
1713 spin_lock(&host->lock);
1714
1715 for (i = 0; i < host->n_ports; i++) {
1716 struct ata_port *ap;
1717
1718 if (!(irq_stat & (1 << i)))
1719 continue;
1720
1721 ap = host->ports[i];
1722 if (ap) {
1723 ahci_port_intr(ap);
1724 VPRINTK("port %u\n", i);
1725 } else {
1726 VPRINTK("port %u (no irq)\n", i);
1727 if (ata_ratelimit())
1728 dev_printk(KERN_WARNING, host->dev,
1729 "interrupt on disabled port %u\n", i);
1730 }
1731
1732 irq_ack |= (1 << i);
1733 }
1734
1735 if (irq_ack) {
1736 writel(irq_ack, mmio + HOST_IRQ_STAT);
1737 handled = 1;
1738 }
1739
1740 spin_unlock(&host->lock);
1741
1742 VPRINTK("EXIT\n");
1743
1744 return IRQ_RETVAL(handled);
1745 }
1746
1747 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1748 {
1749 struct ata_port *ap = qc->ap;
1750 void __iomem *port_mmio = ahci_port_base(ap);
1751 struct ahci_port_priv *pp = ap->private_data;
1752
1753 /* Keep track of the currently active link. It will be used
1754 * in completion path to determine whether NCQ phase is in
1755 * progress.
1756 */
1757 pp->active_link = qc->dev->link;
1758
1759 if (qc->tf.protocol == ATA_PROT_NCQ)
1760 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1761 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1762 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1763
1764 return 0;
1765 }
1766
1767 static void ahci_freeze(struct ata_port *ap)
1768 {
1769 void __iomem *port_mmio = ahci_port_base(ap);
1770
1771 /* turn IRQ off */
1772 writel(0, port_mmio + PORT_IRQ_MASK);
1773 }
1774
1775 static void ahci_thaw(struct ata_port *ap)
1776 {
1777 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1778 void __iomem *port_mmio = ahci_port_base(ap);
1779 u32 tmp;
1780 struct ahci_port_priv *pp = ap->private_data;
1781
1782 /* clear IRQ */
1783 tmp = readl(port_mmio + PORT_IRQ_STAT);
1784 writel(tmp, port_mmio + PORT_IRQ_STAT);
1785 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1786
1787 /* turn IRQ back on */
1788 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1789 }
1790
1791 static void ahci_error_handler(struct ata_port *ap)
1792 {
1793 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1794 /* restart engine */
1795 ahci_stop_engine(ap);
1796 ahci_start_engine(ap);
1797 }
1798
1799 /* perform recovery */
1800 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1801 ahci_hardreset, ahci_postreset,
1802 sata_pmp_std_prereset, ahci_pmp_softreset,
1803 sata_pmp_std_hardreset, sata_pmp_std_postreset);
1804 }
1805
1806 static void ahci_vt8251_error_handler(struct ata_port *ap)
1807 {
1808 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1809 /* restart engine */
1810 ahci_stop_engine(ap);
1811 ahci_start_engine(ap);
1812 }
1813
1814 /* perform recovery */
1815 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1816 ahci_postreset);
1817 }
1818
1819 static void ahci_p5wdh_error_handler(struct ata_port *ap)
1820 {
1821 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1822 /* restart engine */
1823 ahci_stop_engine(ap);
1824 ahci_start_engine(ap);
1825 }
1826
1827 /* perform recovery */
1828 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1829 ahci_postreset);
1830 }
1831
1832 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1833 {
1834 struct ata_port *ap = qc->ap;
1835
1836 /* make DMA engine forget about the failed command */
1837 if (qc->flags & ATA_QCFLAG_FAILED)
1838 ahci_kick_engine(ap, 1);
1839 }
1840
1841 static void ahci_pmp_attach(struct ata_port *ap)
1842 {
1843 void __iomem *port_mmio = ahci_port_base(ap);
1844 struct ahci_port_priv *pp = ap->private_data;
1845 u32 cmd;
1846
1847 cmd = readl(port_mmio + PORT_CMD);
1848 cmd |= PORT_CMD_PMP;
1849 writel(cmd, port_mmio + PORT_CMD);
1850
1851 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1852 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1853 }
1854
1855 static void ahci_pmp_detach(struct ata_port *ap)
1856 {
1857 void __iomem *port_mmio = ahci_port_base(ap);
1858 struct ahci_port_priv *pp = ap->private_data;
1859 u32 cmd;
1860
1861 cmd = readl(port_mmio + PORT_CMD);
1862 cmd &= ~PORT_CMD_PMP;
1863 writel(cmd, port_mmio + PORT_CMD);
1864
1865 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1866 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1867 }
1868
1869 static int ahci_port_resume(struct ata_port *ap)
1870 {
1871 ahci_power_up(ap);
1872 ahci_start_port(ap);
1873
1874 if (ap->nr_pmp_links)
1875 ahci_pmp_attach(ap);
1876 else
1877 ahci_pmp_detach(ap);
1878
1879 return 0;
1880 }
1881
1882 #ifdef CONFIG_PM
1883 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1884 {
1885 const char *emsg = NULL;
1886 int rc;
1887
1888 rc = ahci_deinit_port(ap, &emsg);
1889 if (rc == 0)
1890 ahci_power_down(ap);
1891 else {
1892 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1893 ahci_start_port(ap);
1894 }
1895
1896 return rc;
1897 }
1898
1899 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1900 {
1901 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1902 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1903 u32 ctl;
1904
1905 if (mesg.event & PM_EVENT_SLEEP) {
1906 /* AHCI spec rev1.1 section 8.3.3:
1907 * Software must disable interrupts prior to requesting a
1908 * transition of the HBA to D3 state.
1909 */
1910 ctl = readl(mmio + HOST_CTL);
1911 ctl &= ~HOST_IRQ_EN;
1912 writel(ctl, mmio + HOST_CTL);
1913 readl(mmio + HOST_CTL); /* flush */
1914 }
1915
1916 return ata_pci_device_suspend(pdev, mesg);
1917 }
1918
1919 static int ahci_pci_device_resume(struct pci_dev *pdev)
1920 {
1921 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1922 int rc;
1923
1924 rc = ata_pci_device_do_resume(pdev);
1925 if (rc)
1926 return rc;
1927
1928 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1929 rc = ahci_reset_controller(host);
1930 if (rc)
1931 return rc;
1932
1933 ahci_init_controller(host);
1934 }
1935
1936 ata_host_resume(host);
1937
1938 return 0;
1939 }
1940 #endif
1941
1942 static int ahci_port_start(struct ata_port *ap)
1943 {
1944 struct device *dev = ap->host->dev;
1945 struct ahci_port_priv *pp;
1946 void *mem;
1947 dma_addr_t mem_dma;
1948
1949 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1950 if (!pp)
1951 return -ENOMEM;
1952
1953 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1954 GFP_KERNEL);
1955 if (!mem)
1956 return -ENOMEM;
1957 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1958
1959 /*
1960 * First item in chunk of DMA memory: 32-slot command table,
1961 * 32 bytes each in size
1962 */
1963 pp->cmd_slot = mem;
1964 pp->cmd_slot_dma = mem_dma;
1965
1966 mem += AHCI_CMD_SLOT_SZ;
1967 mem_dma += AHCI_CMD_SLOT_SZ;
1968
1969 /*
1970 * Second item: Received-FIS area
1971 */
1972 pp->rx_fis = mem;
1973 pp->rx_fis_dma = mem_dma;
1974
1975 mem += AHCI_RX_FIS_SZ;
1976 mem_dma += AHCI_RX_FIS_SZ;
1977
1978 /*
1979 * Third item: data area for storing a single command
1980 * and its scatter-gather table
1981 */
1982 pp->cmd_tbl = mem;
1983 pp->cmd_tbl_dma = mem_dma;
1984
1985 /*
1986 * Save off initial list of interrupts to be enabled.
1987 * This could be changed later
1988 */
1989 pp->intr_mask = DEF_PORT_IRQ;
1990
1991 ap->private_data = pp;
1992
1993 /* engage engines, captain */
1994 return ahci_port_resume(ap);
1995 }
1996
1997 static void ahci_port_stop(struct ata_port *ap)
1998 {
1999 const char *emsg = NULL;
2000 int rc;
2001
2002 /* de-initialize port */
2003 rc = ahci_deinit_port(ap, &emsg);
2004 if (rc)
2005 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2006 }
2007
2008 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2009 {
2010 int rc;
2011
2012 if (using_dac &&
2013 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2014 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2015 if (rc) {
2016 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2017 if (rc) {
2018 dev_printk(KERN_ERR, &pdev->dev,
2019 "64-bit DMA enable failed\n");
2020 return rc;
2021 }
2022 }
2023 } else {
2024 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2025 if (rc) {
2026 dev_printk(KERN_ERR, &pdev->dev,
2027 "32-bit DMA enable failed\n");
2028 return rc;
2029 }
2030 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2031 if (rc) {
2032 dev_printk(KERN_ERR, &pdev->dev,
2033 "32-bit consistent DMA enable failed\n");
2034 return rc;
2035 }
2036 }
2037 return 0;
2038 }
2039
2040 static void ahci_print_info(struct ata_host *host)
2041 {
2042 struct ahci_host_priv *hpriv = host->private_data;
2043 struct pci_dev *pdev = to_pci_dev(host->dev);
2044 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2045 u32 vers, cap, impl, speed;
2046 const char *speed_s;
2047 u16 cc;
2048 const char *scc_s;
2049
2050 vers = readl(mmio + HOST_VERSION);
2051 cap = hpriv->cap;
2052 impl = hpriv->port_map;
2053
2054 speed = (cap >> 20) & 0xf;
2055 if (speed == 1)
2056 speed_s = "1.5";
2057 else if (speed == 2)
2058 speed_s = "3";
2059 else
2060 speed_s = "?";
2061
2062 pci_read_config_word(pdev, 0x0a, &cc);
2063 if (cc == PCI_CLASS_STORAGE_IDE)
2064 scc_s = "IDE";
2065 else if (cc == PCI_CLASS_STORAGE_SATA)
2066 scc_s = "SATA";
2067 else if (cc == PCI_CLASS_STORAGE_RAID)
2068 scc_s = "RAID";
2069 else
2070 scc_s = "unknown";
2071
2072 dev_printk(KERN_INFO, &pdev->dev,
2073 "AHCI %02x%02x.%02x%02x "
2074 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2075 ,
2076
2077 (vers >> 24) & 0xff,
2078 (vers >> 16) & 0xff,
2079 (vers >> 8) & 0xff,
2080 vers & 0xff,
2081
2082 ((cap >> 8) & 0x1f) + 1,
2083 (cap & 0x1f) + 1,
2084 speed_s,
2085 impl,
2086 scc_s);
2087
2088 dev_printk(KERN_INFO, &pdev->dev,
2089 "flags: "
2090 "%s%s%s%s%s%s%s"
2091 "%s%s%s%s%s%s%s\n"
2092 ,
2093
2094 cap & (1 << 31) ? "64bit " : "",
2095 cap & (1 << 30) ? "ncq " : "",
2096 cap & (1 << 29) ? "sntf " : "",
2097 cap & (1 << 28) ? "ilck " : "",
2098 cap & (1 << 27) ? "stag " : "",
2099 cap & (1 << 26) ? "pm " : "",
2100 cap & (1 << 25) ? "led " : "",
2101
2102 cap & (1 << 24) ? "clo " : "",
2103 cap & (1 << 19) ? "nz " : "",
2104 cap & (1 << 18) ? "only " : "",
2105 cap & (1 << 17) ? "pmp " : "",
2106 cap & (1 << 15) ? "pio " : "",
2107 cap & (1 << 14) ? "slum " : "",
2108 cap & (1 << 13) ? "part " : ""
2109 );
2110 }
2111
2112 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2113 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2114 * support PMP and the 4726 either directly exports the device
2115 * attached to the first downstream port or acts as a hardware storage
2116 * controller and emulate a single ATA device (can be RAID 0/1 or some
2117 * other configuration).
2118 *
2119 * When there's no device attached to the first downstream port of the
2120 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2121 * configure the 4726. However, ATA emulation of the device is very
2122 * lame. It doesn't send signature D2H Reg FIS after the initial
2123 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2124 *
2125 * The following function works around the problem by always using
2126 * hardreset on the port and not depending on receiving signature FIS
2127 * afterward. If signature FIS isn't received soon, ATA class is
2128 * assumed without follow-up softreset.
2129 */
2130 static void ahci_p5wdh_workaround(struct ata_host *host)
2131 {
2132 static struct dmi_system_id sysids[] = {
2133 {
2134 .ident = "P5W DH Deluxe",
2135 .matches = {
2136 DMI_MATCH(DMI_SYS_VENDOR,
2137 "ASUSTEK COMPUTER INC"),
2138 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2139 },
2140 },
2141 { }
2142 };
2143 struct pci_dev *pdev = to_pci_dev(host->dev);
2144
2145 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2146 dmi_check_system(sysids)) {
2147 struct ata_port *ap = host->ports[1];
2148
2149 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2150 "Deluxe on-board SIMG4726 workaround\n");
2151
2152 ap->ops = &ahci_p5wdh_ops;
2153 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2154 }
2155 }
2156
2157 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2158 {
2159 static int printed_version;
2160 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2161 const struct ata_port_info *ppi[] = { &pi, NULL };
2162 struct device *dev = &pdev->dev;
2163 struct ahci_host_priv *hpriv;
2164 struct ata_host *host;
2165 int n_ports, i, rc;
2166
2167 VPRINTK("ENTER\n");
2168
2169 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2170
2171 if (!printed_version++)
2172 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2173
2174 /* acquire resources */
2175 rc = pcim_enable_device(pdev);
2176 if (rc)
2177 return rc;
2178
2179 /* AHCI controllers often implement SFF compatible interface.
2180 * Grab all PCI BARs just in case.
2181 */
2182 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2183 if (rc == -EBUSY)
2184 pcim_pin_device(pdev);
2185 if (rc)
2186 return rc;
2187
2188 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2189 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2190 u8 map;
2191
2192 /* ICH6s share the same PCI ID for both piix and ahci
2193 * modes. Enabling ahci mode while MAP indicates
2194 * combined mode is a bad idea. Yield to ata_piix.
2195 */
2196 pci_read_config_byte(pdev, ICH_MAP, &map);
2197 if (map & 0x3) {
2198 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2199 "combined mode, can't enable AHCI mode\n");
2200 return -ENODEV;
2201 }
2202 }
2203
2204 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2205 if (!hpriv)
2206 return -ENOMEM;
2207 hpriv->flags |= (unsigned long)pi.private_data;
2208
2209 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2210 pci_intx(pdev, 1);
2211
2212 /* save initial config */
2213 ahci_save_initial_config(pdev, hpriv);
2214
2215 /* prepare host */
2216 if (hpriv->cap & HOST_CAP_NCQ)
2217 pi.flags |= ATA_FLAG_NCQ;
2218
2219 if (hpriv->cap & HOST_CAP_PMP)
2220 pi.flags |= ATA_FLAG_PMP;
2221
2222 /* CAP.NP sometimes indicate the index of the last enabled
2223 * port, at other times, that of the last possible port, so
2224 * determining the maximum port number requires looking at
2225 * both CAP.NP and port_map.
2226 */
2227 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2228
2229 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2230 if (!host)
2231 return -ENOMEM;
2232 host->iomap = pcim_iomap_table(pdev);
2233 host->private_data = hpriv;
2234
2235 for (i = 0; i < host->n_ports; i++) {
2236 struct ata_port *ap = host->ports[i];
2237 void __iomem *port_mmio = ahci_port_base(ap);
2238
2239 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2240 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2241 0x100 + ap->port_no * 0x80, "port");
2242
2243 /* set initial link pm policy */
2244 ap->pm_policy = NOT_AVAILABLE;
2245
2246 /* standard SATA port setup */
2247 if (hpriv->port_map & (1 << i))
2248 ap->ioaddr.cmd_addr = port_mmio;
2249
2250 /* disabled/not-implemented port */
2251 else
2252 ap->ops = &ata_dummy_port_ops;
2253 }
2254
2255 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2256 ahci_p5wdh_workaround(host);
2257
2258 /* initialize adapter */
2259 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2260 if (rc)
2261 return rc;
2262
2263 rc = ahci_reset_controller(host);
2264 if (rc)
2265 return rc;
2266
2267 ahci_init_controller(host);
2268 ahci_print_info(host);
2269
2270 pci_set_master(pdev);
2271 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2272 &ahci_sht);
2273 }
2274
2275 static int __init ahci_init(void)
2276 {
2277 return pci_register_driver(&ahci_pci_driver);
2278 }
2279
2280 static void __exit ahci_exit(void)
2281 {
2282 pci_unregister_driver(&ahci_pci_driver);
2283 }
2284
2285
2286 MODULE_AUTHOR("Jeff Garzik");
2287 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2288 MODULE_LICENSE("GPL");
2289 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2290 MODULE_VERSION(DRV_VERSION);
2291
2292 module_init(ahci_init);
2293 module_exit(ahci_exit);
Linux kernel - Deliverables
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