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drm/i915: Cancel vdd off work before suspend
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include "ahci.h"
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "3.0"
52
53 enum {
54 AHCI_PCI_BAR_STA2X11 = 0,
55 AHCI_PCI_BAR_ENMOTUS = 2,
56 AHCI_PCI_BAR_STANDARD = 5,
57 };
58
59 enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nomsi,
64 board_ahci_noncq,
65 board_ahci_nosntf,
66 board_ahci_yes_fbs,
67
68 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_mcp65,
70 board_ahci_mcp77,
71 board_ahci_mcp89,
72 board_ahci_mv,
73 board_ahci_sb600,
74 board_ahci_sb700, /* for SB700 and SB800 */
75 board_ahci_vt8251,
76
77 /* aliases */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
82 };
83
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
88 static bool is_mcp89_apple(struct pci_dev *pdev);
89 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 #ifdef CONFIG_PM
92 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
93 static int ahci_pci_device_resume(struct pci_dev *pdev);
94 #endif
95
96 static struct scsi_host_template ahci_sht = {
97 AHCI_SHT("ahci"),
98 };
99
100 static struct ata_port_operations ahci_vt8251_ops = {
101 .inherits = &ahci_ops,
102 .hardreset = ahci_vt8251_hardreset,
103 };
104
105 static struct ata_port_operations ahci_p5wdh_ops = {
106 .inherits = &ahci_ops,
107 .hardreset = ahci_p5wdh_hardreset,
108 };
109
110 static const struct ata_port_info ahci_port_info[] = {
111 /* by features */
112 [board_ahci] = {
113 .flags = AHCI_FLAG_COMMON,
114 .pio_mask = ATA_PIO4,
115 .udma_mask = ATA_UDMA6,
116 .port_ops = &ahci_ops,
117 },
118 [board_ahci_ign_iferr] = {
119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
120 .flags = AHCI_FLAG_COMMON,
121 .pio_mask = ATA_PIO4,
122 .udma_mask = ATA_UDMA6,
123 .port_ops = &ahci_ops,
124 },
125 [board_ahci_nomsi] = {
126 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_noncq] = {
133 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
139 [board_ahci_nosntf] = {
140 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
141 .flags = AHCI_FLAG_COMMON,
142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
145 },
146 [board_ahci_yes_fbs] = {
147 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
153 /* by chipsets */
154 [board_ahci_mcp65] = {
155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
156 AHCI_HFLAG_YES_NCQ),
157 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
161 },
162 [board_ahci_mcp77] = {
163 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
168 },
169 [board_ahci_mcp89] = {
170 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
176 [board_ahci_mv] = {
177 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
178 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
179 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
183 },
184 [board_ahci_sb600] = {
185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_pmp_retry_srst_ops,
192 },
193 [board_ahci_sb700] = { /* for SB700 and SB800 */
194 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_pmp_retry_srst_ops,
199 },
200 [board_ahci_vt8251] = {
201 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
202 .flags = AHCI_FLAG_COMMON,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_vt8251_ops,
206 },
207 };
208
209 static const struct pci_device_id ahci_pci_tbl[] = {
210 /* Intel */
211 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
212 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
213 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
214 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
215 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
216 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
217 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
218 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
221 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
222 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
223 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
224 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
225 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
226 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
237 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
239 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
240 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
241 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
242 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
243 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
245 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
246 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
247 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
248 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
250 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
251 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
252 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
253 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
254 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
255 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
258 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
259 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
260 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
261 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
262 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
265 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
266 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
267 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
268 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
270 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
271 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
272 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
273 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
274 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
275 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
276 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
277 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
278 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
279 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
280 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
281 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
282 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
283 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
284 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
285 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
294 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
295 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
298 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
299 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
300 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
301 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
304 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
305 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
306 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
307 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
308 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
309 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
310 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
311 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
312 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
313 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
314 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
315 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
316 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
317 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
318 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
319 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
320 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
321 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
322 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
323 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
324 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
325 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H RAID */
326 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
327 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
328 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
329
330 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
331 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
332 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
333 /* JMicron 362B and 362C have an AHCI function with IDE class code */
334 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
335 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
336
337 /* ATI */
338 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
339 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
340 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
341 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
342 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
343 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
344 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
345
346 /* AMD */
347 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
348 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
349 /* AMD is using RAID class only for ahci controllers */
350 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
351 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
352
353 /* VIA */
354 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
355 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
356
357 /* NVIDIA */
358 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
359 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
360 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
361 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
362 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
363 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
364 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
365 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
366 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
367 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
368 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
369 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
370 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
371 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
372 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
373 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
374 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
375 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
376 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
377 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
378 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
379 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
380 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
381 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
382 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
383 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
384 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
385 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
386 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
387 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
388 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
389 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
390 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
391 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
392 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
393 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
394 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
395 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
396 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
397 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
398 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
399 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
400 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
401 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
402 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
403 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
404 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
405 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
406 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
407 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
408 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
409 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
410 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
411 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
412 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
413 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
414 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
415 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
416 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
417 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
418 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
419 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
420 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
421 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
422 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
423 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
424 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
425 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
426 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
427 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
428 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
429 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
430 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
431 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
432 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
433 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
434 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
435 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
436 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
437 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
438 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
439 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
440 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
441 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
442
443 /* SiS */
444 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
445 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
446 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
447
448 /* ST Microelectronics */
449 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
450
451 /* Marvell */
452 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
453 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
454 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
455 .class = PCI_CLASS_STORAGE_SATA_AHCI,
456 .class_mask = 0xffffff,
457 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
458 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
459 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
460 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
461 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
462 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
463 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
464 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
465 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
466 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
467 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
468 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
469 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
470 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
471 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
472 .driver_data = board_ahci_yes_fbs },
473 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
474 .driver_data = board_ahci_yes_fbs },
475 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
476 .driver_data = board_ahci_yes_fbs },
477 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
478 .driver_data = board_ahci_yes_fbs },
479
480 /* Promise */
481 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
482 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
483
484 /* Asmedia */
485 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
486 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
487 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
488 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
489
490 /*
491 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
492 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
493 */
494 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
495
496 /* Enmotus */
497 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
498
499 /* Generic, PCI class code for AHCI */
500 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
501 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
502
503 { } /* terminate list */
504 };
505
506
507 static struct pci_driver ahci_pci_driver = {
508 .name = DRV_NAME,
509 .id_table = ahci_pci_tbl,
510 .probe = ahci_init_one,
511 .remove = ata_pci_remove_one,
512 #ifdef CONFIG_PM
513 .suspend = ahci_pci_device_suspend,
514 .resume = ahci_pci_device_resume,
515 #endif
516 };
517
518 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
519 static int marvell_enable;
520 #else
521 static int marvell_enable = 1;
522 #endif
523 module_param(marvell_enable, int, 0644);
524 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
525
526
527 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
528 struct ahci_host_priv *hpriv)
529 {
530 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
531 dev_info(&pdev->dev, "JMB361 has only one port\n");
532 hpriv->force_port_map = 1;
533 }
534
535 /*
536 * Temporary Marvell 6145 hack: PATA port presence
537 * is asserted through the standard AHCI port
538 * presence register, as bit 4 (counting from 0)
539 */
540 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
541 if (pdev->device == 0x6121)
542 hpriv->mask_port_map = 0x3;
543 else
544 hpriv->mask_port_map = 0xf;
545 dev_info(&pdev->dev,
546 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
547 }
548
549 ahci_save_initial_config(&pdev->dev, hpriv);
550 }
551
552 static int ahci_pci_reset_controller(struct ata_host *host)
553 {
554 struct pci_dev *pdev = to_pci_dev(host->dev);
555
556 ahci_reset_controller(host);
557
558 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
559 struct ahci_host_priv *hpriv = host->private_data;
560 u16 tmp16;
561
562 /* configure PCS */
563 pci_read_config_word(pdev, 0x92, &tmp16);
564 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
565 tmp16 |= hpriv->port_map;
566 pci_write_config_word(pdev, 0x92, tmp16);
567 }
568 }
569
570 return 0;
571 }
572
573 static void ahci_pci_init_controller(struct ata_host *host)
574 {
575 struct ahci_host_priv *hpriv = host->private_data;
576 struct pci_dev *pdev = to_pci_dev(host->dev);
577 void __iomem *port_mmio;
578 u32 tmp;
579 int mv;
580
581 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
582 if (pdev->device == 0x6121)
583 mv = 2;
584 else
585 mv = 4;
586 port_mmio = __ahci_port_base(host, mv);
587
588 writel(0, port_mmio + PORT_IRQ_MASK);
589
590 /* clear port IRQ */
591 tmp = readl(port_mmio + PORT_IRQ_STAT);
592 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
593 if (tmp)
594 writel(tmp, port_mmio + PORT_IRQ_STAT);
595 }
596
597 ahci_init_controller(host);
598 }
599
600 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
601 unsigned long deadline)
602 {
603 struct ata_port *ap = link->ap;
604 struct ahci_host_priv *hpriv = ap->host->private_data;
605 bool online;
606 int rc;
607
608 DPRINTK("ENTER\n");
609
610 ahci_stop_engine(ap);
611
612 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
613 deadline, &online, NULL);
614
615 hpriv->start_engine(ap);
616
617 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
618
619 /* vt8251 doesn't clear BSY on signature FIS reception,
620 * request follow-up softreset.
621 */
622 return online ? -EAGAIN : rc;
623 }
624
625 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
626 unsigned long deadline)
627 {
628 struct ata_port *ap = link->ap;
629 struct ahci_port_priv *pp = ap->private_data;
630 struct ahci_host_priv *hpriv = ap->host->private_data;
631 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
632 struct ata_taskfile tf;
633 bool online;
634 int rc;
635
636 ahci_stop_engine(ap);
637
638 /* clear D2H reception area to properly wait for D2H FIS */
639 ata_tf_init(link->device, &tf);
640 tf.command = ATA_BUSY;
641 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
642
643 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
644 deadline, &online, NULL);
645
646 hpriv->start_engine(ap);
647
648 /* The pseudo configuration device on SIMG4726 attached to
649 * ASUS P5W-DH Deluxe doesn't send signature FIS after
650 * hardreset if no device is attached to the first downstream
651 * port && the pseudo device locks up on SRST w/ PMP==0. To
652 * work around this, wait for !BSY only briefly. If BSY isn't
653 * cleared, perform CLO and proceed to IDENTIFY (achieved by
654 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
655 *
656 * Wait for two seconds. Devices attached to downstream port
657 * which can't process the following IDENTIFY after this will
658 * have to be reset again. For most cases, this should
659 * suffice while making probing snappish enough.
660 */
661 if (online) {
662 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
663 ahci_check_ready);
664 if (rc)
665 ahci_kick_engine(ap);
666 }
667 return rc;
668 }
669
670 #ifdef CONFIG_PM
671 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
672 {
673 struct ata_host *host = pci_get_drvdata(pdev);
674 struct ahci_host_priv *hpriv = host->private_data;
675 void __iomem *mmio = hpriv->mmio;
676 u32 ctl;
677
678 if (mesg.event & PM_EVENT_SUSPEND &&
679 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
680 dev_err(&pdev->dev,
681 "BIOS update required for suspend/resume\n");
682 return -EIO;
683 }
684
685 if (mesg.event & PM_EVENT_SLEEP) {
686 /* AHCI spec rev1.1 section 8.3.3:
687 * Software must disable interrupts prior to requesting a
688 * transition of the HBA to D3 state.
689 */
690 ctl = readl(mmio + HOST_CTL);
691 ctl &= ~HOST_IRQ_EN;
692 writel(ctl, mmio + HOST_CTL);
693 readl(mmio + HOST_CTL); /* flush */
694 }
695
696 return ata_pci_device_suspend(pdev, mesg);
697 }
698
699 static int ahci_pci_device_resume(struct pci_dev *pdev)
700 {
701 struct ata_host *host = pci_get_drvdata(pdev);
702 int rc;
703
704 rc = ata_pci_device_do_resume(pdev);
705 if (rc)
706 return rc;
707
708 /* Apple BIOS helpfully mangles the registers on resume */
709 if (is_mcp89_apple(pdev))
710 ahci_mcp89_apple_enable(pdev);
711
712 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
713 rc = ahci_pci_reset_controller(host);
714 if (rc)
715 return rc;
716
717 ahci_pci_init_controller(host);
718 }
719
720 ata_host_resume(host);
721
722 return 0;
723 }
724 #endif
725
726 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
727 {
728 int rc;
729
730 /*
731 * If the device fixup already set the dma_mask to some non-standard
732 * value, don't extend it here. This happens on STA2X11, for example.
733 */
734 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
735 return 0;
736
737 if (using_dac &&
738 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
739 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
740 if (rc) {
741 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
742 if (rc) {
743 dev_err(&pdev->dev,
744 "64-bit DMA enable failed\n");
745 return rc;
746 }
747 }
748 } else {
749 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
750 if (rc) {
751 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
752 return rc;
753 }
754 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
755 if (rc) {
756 dev_err(&pdev->dev,
757 "32-bit consistent DMA enable failed\n");
758 return rc;
759 }
760 }
761 return 0;
762 }
763
764 static void ahci_pci_print_info(struct ata_host *host)
765 {
766 struct pci_dev *pdev = to_pci_dev(host->dev);
767 u16 cc;
768 const char *scc_s;
769
770 pci_read_config_word(pdev, 0x0a, &cc);
771 if (cc == PCI_CLASS_STORAGE_IDE)
772 scc_s = "IDE";
773 else if (cc == PCI_CLASS_STORAGE_SATA)
774 scc_s = "SATA";
775 else if (cc == PCI_CLASS_STORAGE_RAID)
776 scc_s = "RAID";
777 else
778 scc_s = "unknown";
779
780 ahci_print_info(host, scc_s);
781 }
782
783 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
784 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
785 * support PMP and the 4726 either directly exports the device
786 * attached to the first downstream port or acts as a hardware storage
787 * controller and emulate a single ATA device (can be RAID 0/1 or some
788 * other configuration).
789 *
790 * When there's no device attached to the first downstream port of the
791 * 4726, "Config Disk" appears, which is a pseudo ATA device to
792 * configure the 4726. However, ATA emulation of the device is very
793 * lame. It doesn't send signature D2H Reg FIS after the initial
794 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
795 *
796 * The following function works around the problem by always using
797 * hardreset on the port and not depending on receiving signature FIS
798 * afterward. If signature FIS isn't received soon, ATA class is
799 * assumed without follow-up softreset.
800 */
801 static void ahci_p5wdh_workaround(struct ata_host *host)
802 {
803 static const struct dmi_system_id sysids[] = {
804 {
805 .ident = "P5W DH Deluxe",
806 .matches = {
807 DMI_MATCH(DMI_SYS_VENDOR,
808 "ASUSTEK COMPUTER INC"),
809 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
810 },
811 },
812 { }
813 };
814 struct pci_dev *pdev = to_pci_dev(host->dev);
815
816 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
817 dmi_check_system(sysids)) {
818 struct ata_port *ap = host->ports[1];
819
820 dev_info(&pdev->dev,
821 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
822
823 ap->ops = &ahci_p5wdh_ops;
824 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
825 }
826 }
827
828 /*
829 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
830 * booting in BIOS compatibility mode. We restore the registers but not ID.
831 */
832 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
833 {
834 u32 val;
835
836 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
837
838 pci_read_config_dword(pdev, 0xf8, &val);
839 val |= 1 << 0x1b;
840 /* the following changes the device ID, but appears not to affect function */
841 /* val = (val & ~0xf0000000) | 0x80000000; */
842 pci_write_config_dword(pdev, 0xf8, val);
843
844 pci_read_config_dword(pdev, 0x54c, &val);
845 val |= 1 << 0xc;
846 pci_write_config_dword(pdev, 0x54c, val);
847
848 pci_read_config_dword(pdev, 0x4a4, &val);
849 val &= 0xff;
850 val |= 0x01060100;
851 pci_write_config_dword(pdev, 0x4a4, val);
852
853 pci_read_config_dword(pdev, 0x54c, &val);
854 val &= ~(1 << 0xc);
855 pci_write_config_dword(pdev, 0x54c, val);
856
857 pci_read_config_dword(pdev, 0xf8, &val);
858 val &= ~(1 << 0x1b);
859 pci_write_config_dword(pdev, 0xf8, val);
860 }
861
862 static bool is_mcp89_apple(struct pci_dev *pdev)
863 {
864 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
865 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
866 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
867 pdev->subsystem_device == 0xcb89;
868 }
869
870 /* only some SB600 ahci controllers can do 64bit DMA */
871 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
872 {
873 static const struct dmi_system_id sysids[] = {
874 /*
875 * The oldest version known to be broken is 0901 and
876 * working is 1501 which was released on 2007-10-26.
877 * Enable 64bit DMA on 1501 and anything newer.
878 *
879 * Please read bko#9412 for more info.
880 */
881 {
882 .ident = "ASUS M2A-VM",
883 .matches = {
884 DMI_MATCH(DMI_BOARD_VENDOR,
885 "ASUSTeK Computer INC."),
886 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
887 },
888 .driver_data = "20071026", /* yyyymmdd */
889 },
890 /*
891 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
892 * support 64bit DMA.
893 *
894 * BIOS versions earlier than 1.5 had the Manufacturer DMI
895 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
896 * This spelling mistake was fixed in BIOS version 1.5, so
897 * 1.5 and later have the Manufacturer as
898 * "MICRO-STAR INTERNATIONAL CO.,LTD".
899 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
900 *
901 * BIOS versions earlier than 1.9 had a Board Product Name
902 * DMI field of "MS-7376". This was changed to be
903 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
904 * match on DMI_BOARD_NAME of "MS-7376".
905 */
906 {
907 .ident = "MSI K9A2 Platinum",
908 .matches = {
909 DMI_MATCH(DMI_BOARD_VENDOR,
910 "MICRO-STAR INTER"),
911 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
912 },
913 },
914 /*
915 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
916 * 64bit DMA.
917 *
918 * This board also had the typo mentioned above in the
919 * Manufacturer DMI field (fixed in BIOS version 1.5), so
920 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
921 */
922 {
923 .ident = "MSI K9AGM2",
924 .matches = {
925 DMI_MATCH(DMI_BOARD_VENDOR,
926 "MICRO-STAR INTER"),
927 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
928 },
929 },
930 /*
931 * All BIOS versions for the Asus M3A support 64bit DMA.
932 * (all release versions from 0301 to 1206 were tested)
933 */
934 {
935 .ident = "ASUS M3A",
936 .matches = {
937 DMI_MATCH(DMI_BOARD_VENDOR,
938 "ASUSTeK Computer INC."),
939 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
940 },
941 },
942 { }
943 };
944 const struct dmi_system_id *match;
945 int year, month, date;
946 char buf[9];
947
948 match = dmi_first_match(sysids);
949 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
950 !match)
951 return false;
952
953 if (!match->driver_data)
954 goto enable_64bit;
955
956 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
957 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
958
959 if (strcmp(buf, match->driver_data) >= 0)
960 goto enable_64bit;
961 else {
962 dev_warn(&pdev->dev,
963 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
964 match->ident);
965 return false;
966 }
967
968 enable_64bit:
969 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
970 return true;
971 }
972
973 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
974 {
975 static const struct dmi_system_id broken_systems[] = {
976 {
977 .ident = "HP Compaq nx6310",
978 .matches = {
979 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
980 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
981 },
982 /* PCI slot number of the controller */
983 .driver_data = (void *)0x1FUL,
984 },
985 {
986 .ident = "HP Compaq 6720s",
987 .matches = {
988 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
989 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
990 },
991 /* PCI slot number of the controller */
992 .driver_data = (void *)0x1FUL,
993 },
994
995 { } /* terminate list */
996 };
997 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
998
999 if (dmi) {
1000 unsigned long slot = (unsigned long)dmi->driver_data;
1001 /* apply the quirk only to on-board controllers */
1002 return slot == PCI_SLOT(pdev->devfn);
1003 }
1004
1005 return false;
1006 }
1007
1008 static bool ahci_broken_suspend(struct pci_dev *pdev)
1009 {
1010 static const struct dmi_system_id sysids[] = {
1011 /*
1012 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1013 * to the harddisk doesn't become online after
1014 * resuming from STR. Warn and fail suspend.
1015 *
1016 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1017 *
1018 * Use dates instead of versions to match as HP is
1019 * apparently recycling both product and version
1020 * strings.
1021 *
1022 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1023 */
1024 {
1025 .ident = "dv4",
1026 .matches = {
1027 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1028 DMI_MATCH(DMI_PRODUCT_NAME,
1029 "HP Pavilion dv4 Notebook PC"),
1030 },
1031 .driver_data = "20090105", /* F.30 */
1032 },
1033 {
1034 .ident = "dv5",
1035 .matches = {
1036 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1037 DMI_MATCH(DMI_PRODUCT_NAME,
1038 "HP Pavilion dv5 Notebook PC"),
1039 },
1040 .driver_data = "20090506", /* F.16 */
1041 },
1042 {
1043 .ident = "dv6",
1044 .matches = {
1045 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1046 DMI_MATCH(DMI_PRODUCT_NAME,
1047 "HP Pavilion dv6 Notebook PC"),
1048 },
1049 .driver_data = "20090423", /* F.21 */
1050 },
1051 {
1052 .ident = "HDX18",
1053 .matches = {
1054 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1055 DMI_MATCH(DMI_PRODUCT_NAME,
1056 "HP HDX18 Notebook PC"),
1057 },
1058 .driver_data = "20090430", /* F.23 */
1059 },
1060 /*
1061 * Acer eMachines G725 has the same problem. BIOS
1062 * V1.03 is known to be broken. V3.04 is known to
1063 * work. Between, there are V1.06, V2.06 and V3.03
1064 * that we don't have much idea about. For now,
1065 * blacklist anything older than V3.04.
1066 *
1067 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1068 */
1069 {
1070 .ident = "G725",
1071 .matches = {
1072 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1073 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1074 },
1075 .driver_data = "20091216", /* V3.04 */
1076 },
1077 { } /* terminate list */
1078 };
1079 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1080 int year, month, date;
1081 char buf[9];
1082
1083 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1084 return false;
1085
1086 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1087 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1088
1089 return strcmp(buf, dmi->driver_data) < 0;
1090 }
1091
1092 static bool ahci_broken_online(struct pci_dev *pdev)
1093 {
1094 #define ENCODE_BUSDEVFN(bus, slot, func) \
1095 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1096 static const struct dmi_system_id sysids[] = {
1097 /*
1098 * There are several gigabyte boards which use
1099 * SIMG5723s configured as hardware RAID. Certain
1100 * 5723 firmware revisions shipped there keep the link
1101 * online but fail to answer properly to SRST or
1102 * IDENTIFY when no device is attached downstream
1103 * causing libata to retry quite a few times leading
1104 * to excessive detection delay.
1105 *
1106 * As these firmwares respond to the second reset try
1107 * with invalid device signature, considering unknown
1108 * sig as offline works around the problem acceptably.
1109 */
1110 {
1111 .ident = "EP45-DQ6",
1112 .matches = {
1113 DMI_MATCH(DMI_BOARD_VENDOR,
1114 "Gigabyte Technology Co., Ltd."),
1115 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1116 },
1117 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1118 },
1119 {
1120 .ident = "EP45-DS5",
1121 .matches = {
1122 DMI_MATCH(DMI_BOARD_VENDOR,
1123 "Gigabyte Technology Co., Ltd."),
1124 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1125 },
1126 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1127 },
1128 { } /* terminate list */
1129 };
1130 #undef ENCODE_BUSDEVFN
1131 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1132 unsigned int val;
1133
1134 if (!dmi)
1135 return false;
1136
1137 val = (unsigned long)dmi->driver_data;
1138
1139 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1140 }
1141
1142 static bool ahci_broken_devslp(struct pci_dev *pdev)
1143 {
1144 /* device with broken DEVSLP but still showing SDS capability */
1145 static const struct pci_device_id ids[] = {
1146 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1147 {}
1148 };
1149
1150 return pci_match_id(ids, pdev);
1151 }
1152
1153 #ifdef CONFIG_ATA_ACPI
1154 static void ahci_gtf_filter_workaround(struct ata_host *host)
1155 {
1156 static const struct dmi_system_id sysids[] = {
1157 /*
1158 * Aspire 3810T issues a bunch of SATA enable commands
1159 * via _GTF including an invalid one and one which is
1160 * rejected by the device. Among the successful ones
1161 * is FPDMA non-zero offset enable which when enabled
1162 * only on the drive side leads to NCQ command
1163 * failures. Filter it out.
1164 */
1165 {
1166 .ident = "Aspire 3810T",
1167 .matches = {
1168 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1169 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1170 },
1171 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1172 },
1173 { }
1174 };
1175 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1176 unsigned int filter;
1177 int i;
1178
1179 if (!dmi)
1180 return;
1181
1182 filter = (unsigned long)dmi->driver_data;
1183 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1184 filter, dmi->ident);
1185
1186 for (i = 0; i < host->n_ports; i++) {
1187 struct ata_port *ap = host->ports[i];
1188 struct ata_link *link;
1189 struct ata_device *dev;
1190
1191 ata_for_each_link(link, ap, EDGE)
1192 ata_for_each_dev(dev, link, ALL)
1193 dev->gtf_filter |= filter;
1194 }
1195 }
1196 #else
1197 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1198 {}
1199 #endif
1200
1201 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1202 struct ahci_host_priv *hpriv)
1203 {
1204 int rc, nvec;
1205
1206 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1207 goto intx;
1208
1209 nvec = pci_msi_vec_count(pdev);
1210 if (nvec < 0)
1211 goto intx;
1212
1213 /*
1214 * If number of MSIs is less than number of ports then Sharing Last
1215 * Message mode could be enforced. In this case assume that advantage
1216 * of multipe MSIs is negated and use single MSI mode instead.
1217 */
1218 if (nvec < n_ports)
1219 goto single_msi;
1220
1221 rc = pci_enable_msi_exact(pdev, nvec);
1222 if (rc == -ENOSPC)
1223 goto single_msi;
1224 else if (rc < 0)
1225 goto intx;
1226
1227 /* fallback to single MSI mode if the controller enforced MRSM mode */
1228 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1229 pci_disable_msi(pdev);
1230 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1231 goto single_msi;
1232 }
1233
1234 if (nvec > 1)
1235 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1236
1237 return nvec;
1238
1239 single_msi:
1240 if (pci_enable_msi(pdev))
1241 goto intx;
1242 return 1;
1243
1244 intx:
1245 pci_intx(pdev, 1);
1246 return 0;
1247 }
1248
1249 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1250 {
1251 unsigned int board_id = ent->driver_data;
1252 struct ata_port_info pi = ahci_port_info[board_id];
1253 const struct ata_port_info *ppi[] = { &pi, NULL };
1254 struct device *dev = &pdev->dev;
1255 struct ahci_host_priv *hpriv;
1256 struct ata_host *host;
1257 int n_ports, i, rc;
1258 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1259
1260 VPRINTK("ENTER\n");
1261
1262 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1263
1264 ata_print_version_once(&pdev->dev, DRV_VERSION);
1265
1266 /* The AHCI driver can only drive the SATA ports, the PATA driver
1267 can drive them all so if both drivers are selected make sure
1268 AHCI stays out of the way */
1269 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1270 return -ENODEV;
1271
1272 /* Apple BIOS on MCP89 prevents us using AHCI */
1273 if (is_mcp89_apple(pdev))
1274 ahci_mcp89_apple_enable(pdev);
1275
1276 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1277 * At the moment, we can only use the AHCI mode. Let the users know
1278 * that for SAS drives they're out of luck.
1279 */
1280 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1281 dev_info(&pdev->dev,
1282 "PDC42819 can only drive SATA devices with this driver\n");
1283
1284 /* Both Connext and Enmotus devices use non-standard BARs */
1285 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1286 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1287 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1288 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1289
1290 /*
1291 * The JMicron chip 361/363 contains one SATA controller and one
1292 * PATA controller,for powering on these both controllers, we must
1293 * follow the sequence one by one, otherwise one of them can not be
1294 * powered on successfully, so here we disable the async suspend
1295 * method for these chips.
1296 */
1297 if (pdev->vendor == PCI_VENDOR_ID_JMICRON &&
1298 (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 ||
1299 pdev->device == PCI_DEVICE_ID_JMICRON_JMB361))
1300 device_disable_async_suspend(&pdev->dev);
1301
1302 /* acquire resources */
1303 rc = pcim_enable_device(pdev);
1304 if (rc)
1305 return rc;
1306
1307 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1308 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1309 u8 map;
1310
1311 /* ICH6s share the same PCI ID for both piix and ahci
1312 * modes. Enabling ahci mode while MAP indicates
1313 * combined mode is a bad idea. Yield to ata_piix.
1314 */
1315 pci_read_config_byte(pdev, ICH_MAP, &map);
1316 if (map & 0x3) {
1317 dev_info(&pdev->dev,
1318 "controller is in combined mode, can't enable AHCI mode\n");
1319 return -ENODEV;
1320 }
1321 }
1322
1323 /* AHCI controllers often implement SFF compatible interface.
1324 * Grab all PCI BARs just in case.
1325 */
1326 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1327 if (rc == -EBUSY)
1328 pcim_pin_device(pdev);
1329 if (rc)
1330 return rc;
1331
1332 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1333 if (!hpriv)
1334 return -ENOMEM;
1335 hpriv->flags |= (unsigned long)pi.private_data;
1336
1337 /* MCP65 revision A1 and A2 can't do MSI */
1338 if (board_id == board_ahci_mcp65 &&
1339 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1340 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1341
1342 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1343 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1344 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1345
1346 /* only some SB600s can do 64bit DMA */
1347 if (ahci_sb600_enable_64bit(pdev))
1348 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1349
1350 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1351
1352 /* must set flag prior to save config in order to take effect */
1353 if (ahci_broken_devslp(pdev))
1354 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1355
1356 /* save initial config */
1357 ahci_pci_save_initial_config(pdev, hpriv);
1358
1359 /* prepare host */
1360 if (hpriv->cap & HOST_CAP_NCQ) {
1361 pi.flags |= ATA_FLAG_NCQ;
1362 /*
1363 * Auto-activate optimization is supposed to be
1364 * supported on all AHCI controllers indicating NCQ
1365 * capability, but it seems to be broken on some
1366 * chipsets including NVIDIAs.
1367 */
1368 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1369 pi.flags |= ATA_FLAG_FPDMA_AA;
1370
1371 /*
1372 * All AHCI controllers should be forward-compatible
1373 * with the new auxiliary field. This code should be
1374 * conditionalized if any buggy AHCI controllers are
1375 * encountered.
1376 */
1377 pi.flags |= ATA_FLAG_FPDMA_AUX;
1378 }
1379
1380 if (hpriv->cap & HOST_CAP_PMP)
1381 pi.flags |= ATA_FLAG_PMP;
1382
1383 ahci_set_em_messages(hpriv, &pi);
1384
1385 if (ahci_broken_system_poweroff(pdev)) {
1386 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1387 dev_info(&pdev->dev,
1388 "quirky BIOS, skipping spindown on poweroff\n");
1389 }
1390
1391 if (ahci_broken_suspend(pdev)) {
1392 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1393 dev_warn(&pdev->dev,
1394 "BIOS update required for suspend/resume\n");
1395 }
1396
1397 if (ahci_broken_online(pdev)) {
1398 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1399 dev_info(&pdev->dev,
1400 "online status unreliable, applying workaround\n");
1401 }
1402
1403 /* CAP.NP sometimes indicate the index of the last enabled
1404 * port, at other times, that of the last possible port, so
1405 * determining the maximum port number requires looking at
1406 * both CAP.NP and port_map.
1407 */
1408 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1409
1410 ahci_init_interrupts(pdev, n_ports, hpriv);
1411
1412 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1413 if (!host)
1414 return -ENOMEM;
1415 host->private_data = hpriv;
1416
1417 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1418 host->flags |= ATA_HOST_PARALLEL_SCAN;
1419 else
1420 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1421
1422 if (pi.flags & ATA_FLAG_EM)
1423 ahci_reset_em(host);
1424
1425 for (i = 0; i < host->n_ports; i++) {
1426 struct ata_port *ap = host->ports[i];
1427
1428 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1429 ata_port_pbar_desc(ap, ahci_pci_bar,
1430 0x100 + ap->port_no * 0x80, "port");
1431
1432 /* set enclosure management message type */
1433 if (ap->flags & ATA_FLAG_EM)
1434 ap->em_message_type = hpriv->em_msg_type;
1435
1436
1437 /* disabled/not-implemented port */
1438 if (!(hpriv->port_map & (1 << i)))
1439 ap->ops = &ata_dummy_port_ops;
1440 }
1441
1442 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1443 ahci_p5wdh_workaround(host);
1444
1445 /* apply gtf filter quirk */
1446 ahci_gtf_filter_workaround(host);
1447
1448 /* initialize adapter */
1449 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1450 if (rc)
1451 return rc;
1452
1453 rc = ahci_pci_reset_controller(host);
1454 if (rc)
1455 return rc;
1456
1457 ahci_pci_init_controller(host);
1458 ahci_pci_print_info(host);
1459
1460 pci_set_master(pdev);
1461
1462 return ahci_host_activate(host, pdev->irq, &ahci_sht);
1463 }
1464
1465 module_pci_driver(ahci_pci_driver);
1466
1467 MODULE_AUTHOR("Jeff Garzik");
1468 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1469 MODULE_LICENSE("GPL");
1470 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1471 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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