2 * drivers/ata/ahci_tegra.c
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
7 * Mikko Perttunen <mperttunen@nvidia.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/ahci_platform.h>
21 #include <linux/reset.h>
22 #include <linux/errno.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/regulator/consumer.h>
28 #include <soc/tegra/pmc.h>
31 #define SATA_CONFIGURATION_0 0x180
32 #define SATA_CONFIGURATION_EN_FPCI BIT(0)
34 #define SCFG_OFFSET 0x1000
36 #define T_SATA0_CFG_1 0x04
37 #define T_SATA0_CFG_1_IO_SPACE BIT(0)
38 #define T_SATA0_CFG_1_MEMORY_SPACE BIT(1)
39 #define T_SATA0_CFG_1_BUS_MASTER BIT(2)
40 #define T_SATA0_CFG_1_SERR BIT(8)
42 #define T_SATA0_CFG_9 0x24
43 #define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13
45 #define SATA_FPCI_BAR5 0x94
46 #define SATA_FPCI_BAR5_START_SHIFT 4
48 #define SATA_INTR_MASK 0x188
49 #define SATA_INTR_MASK_IP_INT_MASK BIT(16)
51 #define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
53 #define T_SATA0_BKDOOR_CC 0x4a4
55 #define T_SATA0_CFG_SATA 0x54c
56 #define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
58 #define T_SATA0_CFG_MISC 0x550
60 #define T_SATA0_INDEX 0x680
62 #define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690
63 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff
64 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
65 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
66 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
68 #define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694
69 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff
70 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
71 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
72 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
74 #define T_SATA0_CHX_PHY_CTRL2 0x69c
75 #define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23
77 #define T_SATA0_CHX_PHY_CTRL11 0x6d0
78 #define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
80 #define FUSE_SATA_CALIB 0x124
81 #define FUSE_SATA_CALIB_MASK 0x3
83 struct sata_pad_calibration
{
90 static const struct sata_pad_calibration tegra124_pad_calibration
[] = {
91 {0x18, 0x04, 0x18, 0x0a},
92 {0x0e, 0x04, 0x14, 0x0a},
93 {0x0e, 0x07, 0x1a, 0x0e},
94 {0x14, 0x0e, 0x1a, 0x0e},
97 struct tegra_ahci_priv
{
98 struct platform_device
*pdev
;
99 void __iomem
*sata_regs
;
100 struct reset_control
*sata_rst
;
101 struct reset_control
*sata_oob_rst
;
102 struct reset_control
*sata_cold_rst
;
103 /* Needs special handling, cannot use ahci_platform */
104 struct clk
*sata_clk
;
105 struct regulator_bulk_data supplies
[5];
108 static int tegra_ahci_power_on(struct ahci_host_priv
*hpriv
)
110 struct tegra_ahci_priv
*tegra
= hpriv
->plat_data
;
113 ret
= regulator_bulk_enable(ARRAY_SIZE(tegra
->supplies
),
118 ret
= tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA
,
122 goto disable_regulators
;
124 reset_control_assert(tegra
->sata_oob_rst
);
125 reset_control_assert(tegra
->sata_cold_rst
);
127 ret
= ahci_platform_enable_resources(hpriv
);
131 reset_control_deassert(tegra
->sata_cold_rst
);
132 reset_control_deassert(tegra
->sata_oob_rst
);
137 clk_disable_unprepare(tegra
->sata_clk
);
139 tegra_powergate_power_off(TEGRA_POWERGATE_SATA
);
142 regulator_bulk_disable(ARRAY_SIZE(tegra
->supplies
), tegra
->supplies
);
147 static void tegra_ahci_power_off(struct ahci_host_priv
*hpriv
)
149 struct tegra_ahci_priv
*tegra
= hpriv
->plat_data
;
151 ahci_platform_disable_resources(hpriv
);
153 reset_control_assert(tegra
->sata_rst
);
154 reset_control_assert(tegra
->sata_oob_rst
);
155 reset_control_assert(tegra
->sata_cold_rst
);
157 clk_disable_unprepare(tegra
->sata_clk
);
158 tegra_powergate_power_off(TEGRA_POWERGATE_SATA
);
160 regulator_bulk_disable(ARRAY_SIZE(tegra
->supplies
), tegra
->supplies
);
163 static int tegra_ahci_controller_init(struct ahci_host_priv
*hpriv
)
165 struct tegra_ahci_priv
*tegra
= hpriv
->plat_data
;
168 struct sata_pad_calibration calib
;
170 ret
= tegra_ahci_power_on(hpriv
);
172 dev_err(&tegra
->pdev
->dev
,
173 "failed to power on AHCI controller: %d\n", ret
);
177 val
= readl(tegra
->sata_regs
+ SATA_CONFIGURATION_0
);
178 val
|= SATA_CONFIGURATION_EN_FPCI
;
179 writel(val
, tegra
->sata_regs
+ SATA_CONFIGURATION_0
);
181 /* Pad calibration */
183 /* FIXME Always use calibration 0. Change this to read the calibration
184 * fuse once the fuse driver has landed. */
187 calib
= tegra124_pad_calibration
[val
& FUSE_SATA_CALIB_MASK
];
189 writel(BIT(0), tegra
->sata_regs
+ SCFG_OFFSET
+ T_SATA0_INDEX
);
191 val
= readl(tegra
->sata_regs
+
192 SCFG_OFFSET
+ T_SATA0_CHX_PHY_CTRL1_GEN1
);
193 val
&= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK
;
194 val
&= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK
;
195 val
|= calib
.gen1_tx_amp
<<
196 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT
;
197 val
|= calib
.gen1_tx_peak
<<
198 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT
;
199 writel(val
, tegra
->sata_regs
+ SCFG_OFFSET
+
200 T_SATA0_CHX_PHY_CTRL1_GEN1
);
202 val
= readl(tegra
->sata_regs
+
203 SCFG_OFFSET
+ T_SATA0_CHX_PHY_CTRL1_GEN2
);
204 val
&= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK
;
205 val
&= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK
;
206 val
|= calib
.gen2_tx_amp
<<
207 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT
;
208 val
|= calib
.gen2_tx_peak
<<
209 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT
;
210 writel(val
, tegra
->sata_regs
+ SCFG_OFFSET
+
211 T_SATA0_CHX_PHY_CTRL1_GEN2
);
213 writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ
,
214 tegra
->sata_regs
+ SCFG_OFFSET
+ T_SATA0_CHX_PHY_CTRL11
);
215 writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1
,
216 tegra
->sata_regs
+ SCFG_OFFSET
+ T_SATA0_CHX_PHY_CTRL2
);
218 writel(0, tegra
->sata_regs
+ SCFG_OFFSET
+ T_SATA0_INDEX
);
220 /* Program controller device ID */
222 val
= readl(tegra
->sata_regs
+ SCFG_OFFSET
+ T_SATA0_CFG_SATA
);
223 val
|= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN
;
224 writel(val
, tegra
->sata_regs
+ SCFG_OFFSET
+ T_SATA0_CFG_SATA
);
226 writel(0x01060100, tegra
->sata_regs
+ SCFG_OFFSET
+ T_SATA0_BKDOOR_CC
);
228 val
= readl(tegra
->sata_regs
+ SCFG_OFFSET
+ T_SATA0_CFG_SATA
);
229 val
&= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN
;
230 writel(val
, tegra
->sata_regs
+ SCFG_OFFSET
+ T_SATA0_CFG_SATA
);
232 /* Enable IO & memory access, bus master mode */
234 val
= readl(tegra
->sata_regs
+ SCFG_OFFSET
+ T_SATA0_CFG_1
);
235 val
|= T_SATA0_CFG_1_IO_SPACE
| T_SATA0_CFG_1_MEMORY_SPACE
|
236 T_SATA0_CFG_1_BUS_MASTER
| T_SATA0_CFG_1_SERR
;
237 writel(val
, tegra
->sata_regs
+ SCFG_OFFSET
+ T_SATA0_CFG_1
);
239 /* Program SATA MMIO */
241 writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT
,
242 tegra
->sata_regs
+ SATA_FPCI_BAR5
);
244 writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT
,
245 tegra
->sata_regs
+ SCFG_OFFSET
+ T_SATA0_CFG_9
);
247 /* Unmask SATA interrupts */
249 val
= readl(tegra
->sata_regs
+ SATA_INTR_MASK
);
250 val
|= SATA_INTR_MASK_IP_INT_MASK
;
251 writel(val
, tegra
->sata_regs
+ SATA_INTR_MASK
);
256 static void tegra_ahci_controller_deinit(struct ahci_host_priv
*hpriv
)
258 tegra_ahci_power_off(hpriv
);
261 static void tegra_ahci_host_stop(struct ata_host
*host
)
263 struct ahci_host_priv
*hpriv
= host
->private_data
;
265 tegra_ahci_controller_deinit(hpriv
);
268 static struct ata_port_operations ahci_tegra_port_ops
= {
269 .inherits
= &ahci_ops
,
270 .host_stop
= tegra_ahci_host_stop
,
273 static const struct ata_port_info ahci_tegra_port_info
= {
274 .flags
= AHCI_FLAG_COMMON
,
275 .pio_mask
= ATA_PIO4
,
276 .udma_mask
= ATA_UDMA6
,
277 .port_ops
= &ahci_tegra_port_ops
,
280 static const struct of_device_id tegra_ahci_of_match
[] = {
281 { .compatible
= "nvidia,tegra124-ahci" },
284 MODULE_DEVICE_TABLE(of
, tegra_ahci_of_match
);
286 static int tegra_ahci_probe(struct platform_device
*pdev
)
288 struct ahci_host_priv
*hpriv
;
289 struct tegra_ahci_priv
*tegra
;
290 struct resource
*res
;
293 hpriv
= ahci_platform_get_resources(pdev
);
295 return PTR_ERR(hpriv
);
297 tegra
= devm_kzalloc(&pdev
->dev
, sizeof(*tegra
), GFP_KERNEL
);
301 hpriv
->plat_data
= tegra
;
305 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
306 tegra
->sata_regs
= devm_ioremap_resource(&pdev
->dev
, res
);
307 if (IS_ERR(tegra
->sata_regs
))
308 return PTR_ERR(tegra
->sata_regs
);
310 tegra
->sata_rst
= devm_reset_control_get(&pdev
->dev
, "sata");
311 if (IS_ERR(tegra
->sata_rst
)) {
312 dev_err(&pdev
->dev
, "Failed to get sata reset\n");
313 return PTR_ERR(tegra
->sata_rst
);
316 tegra
->sata_oob_rst
= devm_reset_control_get(&pdev
->dev
, "sata-oob");
317 if (IS_ERR(tegra
->sata_oob_rst
)) {
318 dev_err(&pdev
->dev
, "Failed to get sata-oob reset\n");
319 return PTR_ERR(tegra
->sata_oob_rst
);
322 tegra
->sata_cold_rst
= devm_reset_control_get(&pdev
->dev
, "sata-cold");
323 if (IS_ERR(tegra
->sata_cold_rst
)) {
324 dev_err(&pdev
->dev
, "Failed to get sata-cold reset\n");
325 return PTR_ERR(tegra
->sata_cold_rst
);
328 tegra
->sata_clk
= devm_clk_get(&pdev
->dev
, "sata");
329 if (IS_ERR(tegra
->sata_clk
)) {
330 dev_err(&pdev
->dev
, "Failed to get sata clock\n");
331 return PTR_ERR(tegra
->sata_clk
);
334 tegra
->supplies
[0].supply
= "avdd";
335 tegra
->supplies
[1].supply
= "hvdd";
336 tegra
->supplies
[2].supply
= "vddio";
337 tegra
->supplies
[3].supply
= "target-5v";
338 tegra
->supplies
[4].supply
= "target-12v";
340 ret
= devm_regulator_bulk_get(&pdev
->dev
, ARRAY_SIZE(tegra
->supplies
),
343 dev_err(&pdev
->dev
, "Failed to get regulators\n");
347 ret
= tegra_ahci_controller_init(hpriv
);
351 ret
= ahci_platform_init_host(pdev
, hpriv
, &ahci_tegra_port_info
);
353 goto deinit_controller
;
358 tegra_ahci_controller_deinit(hpriv
);
363 static struct platform_driver tegra_ahci_driver
= {
364 .probe
= tegra_ahci_probe
,
365 .remove
= ata_platform_remove_one
,
367 .name
= "tegra-ahci",
368 .of_match_table
= tegra_ahci_of_match
,
370 /* LP0 suspend support not implemented */
372 module_platform_driver(tegra_ahci_driver
);
374 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
375 MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
376 MODULE_LICENSE("GPL v2");