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2cfc1ae366ea1405fe4bcb031e1da917a232cfd1
[deliverable/linux.git] / drivers / ata / ata_piix.c
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The original Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
76 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <linux/gfp.h>
94 #include <scsi/scsi_host.h>
95 #include <linux/libata.h>
96 #include <linux/dmi.h>
97
98 #define DRV_NAME "ata_piix"
99 #define DRV_VERSION "2.13"
100
101 enum {
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
105 PIIX_SIDPR_BAR = 5,
106 PIIX_SIDPR_LEN = 16,
107 PIIX_SIDPR_IDX = 0,
108 PIIX_SIDPR_DATA = 4,
109
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
112
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
115
116 PIIX_80C_PRI = (1 << 5) | (1 << 4),
117 PIIX_80C_SEC = (1 << 7) | (1 << 6),
118
119 /* constants for mapping table */
120 P0 = 0, /* port 0 */
121 P1 = 1, /* port 1 */
122 P2 = 2, /* port 2 */
123 P3 = 3, /* port 3 */
124 IDE = -1, /* IDE */
125 NA = -2, /* not avaliable */
126 RV = -3, /* reserved */
127
128 PIIX_AHCI_DEVICE = 6,
129
130 /* host->flags bits */
131 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
132 };
133
134 enum piix_controller_ids {
135 /* controller IDs */
136 piix_pata_mwdma, /* PIIX3 MWDMA only */
137 piix_pata_33, /* PIIX4 at 33Mhz */
138 ich_pata_33, /* ICH up to UDMA 33 only */
139 ich_pata_66, /* ICH up to 66 Mhz */
140 ich_pata_100, /* ICH up to UDMA 100 */
141 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
142 ich5_sata,
143 ich6_sata,
144 ich6m_sata,
145 ich8_sata,
146 ich8_2port_sata,
147 ich8m_apple_sata, /* locks up on second port enable */
148 tolapai_sata,
149 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
150 };
151
152 struct piix_map_db {
153 const u32 mask;
154 const u16 port_enable;
155 const int map[][4];
156 };
157
158 struct piix_host_priv {
159 const int *map;
160 u32 saved_iocfg;
161 void __iomem *sidpr;
162 };
163
164 static int piix_init_one(struct pci_dev *pdev,
165 const struct pci_device_id *ent);
166 static void piix_remove_one(struct pci_dev *pdev);
167 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
168 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
169 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
170 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
171 static int ich_pata_cable_detect(struct ata_port *ap);
172 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
173 static int piix_sidpr_scr_read(struct ata_link *link,
174 unsigned int reg, u32 *val);
175 static int piix_sidpr_scr_write(struct ata_link *link,
176 unsigned int reg, u32 val);
177 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
178 unsigned hints);
179 static bool piix_irq_check(struct ata_port *ap);
180 #ifdef CONFIG_PM
181 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
182 static int piix_pci_device_resume(struct pci_dev *pdev);
183 #endif
184
185 static unsigned int in_module_init = 1;
186
187 static const struct pci_device_id piix_pci_tbl[] = {
188 /* Intel PIIX3 for the 430HX etc */
189 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
190 /* VMware ICH4 */
191 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
192 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
193 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
194 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
195 /* Intel PIIX4 */
196 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
197 /* Intel PIIX4 */
198 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
199 /* Intel PIIX */
200 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
201 /* Intel ICH (i810, i815, i840) UDMA 66*/
202 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
203 /* Intel ICH0 : UDMA 33*/
204 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
205 /* Intel ICH2M */
206 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
208 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 /* Intel ICH3M */
210 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
211 /* Intel ICH3 (E7500/1) UDMA 100 */
212 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
214 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
215 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 /* Intel ICH5 */
217 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 /* C-ICH (i810E2) */
219 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
220 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
221 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
222 /* ICH6 (and 6) (i915) UDMA 100 */
223 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
224 /* ICH7/7-R (i945, i975) UDMA 100*/
225 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
226 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
227 /* ICH8 Mobile PATA Controller */
228 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
229
230 /* SATA ports */
231
232 /* 82801EB (ICH5) */
233 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
234 /* 82801EB (ICH5) */
235 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
236 /* 6300ESB (ICH5 variant with broken PCS present bits) */
237 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
238 /* 6300ESB pretending RAID */
239 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
240 /* 82801FB/FW (ICH6/ICH6W) */
241 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
242 /* 82801FR/FRW (ICH6R/ICH6RW) */
243 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
244 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
245 * Attach iff the controller is in IDE mode. */
246 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
247 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
248 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
249 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
250 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
251 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
252 /* Enterprise Southbridge 2 (631xESB/632xESB) */
253 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
254 /* SATA Controller 1 IDE (ICH8) */
255 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
256 /* SATA Controller 2 IDE (ICH8) */
257 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
258 /* Mobile SATA Controller IDE (ICH8M), Apple */
259 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
260 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
261 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
262 /* Mobile SATA Controller IDE (ICH8M) */
263 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
264 /* SATA Controller IDE (ICH9) */
265 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
266 /* SATA Controller IDE (ICH9) */
267 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
268 /* SATA Controller IDE (ICH9) */
269 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
270 /* SATA Controller IDE (ICH9M) */
271 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
272 /* SATA Controller IDE (ICH9M) */
273 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
274 /* SATA Controller IDE (ICH9M) */
275 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
276 /* SATA Controller IDE (Tolapai) */
277 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
278 /* SATA Controller IDE (ICH10) */
279 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
280 /* SATA Controller IDE (ICH10) */
281 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
282 /* SATA Controller IDE (ICH10) */
283 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
284 /* SATA Controller IDE (ICH10) */
285 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
286 /* SATA Controller IDE (PCH) */
287 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
288 /* SATA Controller IDE (PCH) */
289 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
290 /* SATA Controller IDE (PCH) */
291 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
292 /* SATA Controller IDE (PCH) */
293 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
294 /* SATA Controller IDE (PCH) */
295 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
296 /* SATA Controller IDE (PCH) */
297 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
298 /* SATA Controller IDE (CPT) */
299 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
300 /* SATA Controller IDE (CPT) */
301 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
302 /* SATA Controller IDE (CPT) */
303 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
304 /* SATA Controller IDE (CPT) */
305 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
306 /* SATA Controller IDE (PBG) */
307 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
308 /* SATA Controller IDE (PBG) */
309 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
310 { } /* terminate list */
311 };
312
313 static struct pci_driver piix_pci_driver = {
314 .name = DRV_NAME,
315 .id_table = piix_pci_tbl,
316 .probe = piix_init_one,
317 .remove = piix_remove_one,
318 #ifdef CONFIG_PM
319 .suspend = piix_pci_device_suspend,
320 .resume = piix_pci_device_resume,
321 #endif
322 };
323
324 static struct scsi_host_template piix_sht = {
325 ATA_BMDMA_SHT(DRV_NAME),
326 };
327
328 static struct ata_port_operations piix_sata_ops = {
329 .inherits = &ata_bmdma32_port_ops,
330 .sff_irq_check = piix_irq_check,
331 };
332
333 static struct ata_port_operations piix_pata_ops = {
334 .inherits = &piix_sata_ops,
335 .cable_detect = ata_cable_40wire,
336 .set_piomode = piix_set_piomode,
337 .set_dmamode = piix_set_dmamode,
338 .prereset = piix_pata_prereset,
339 };
340
341 static struct ata_port_operations piix_vmw_ops = {
342 .inherits = &piix_pata_ops,
343 .bmdma_status = piix_vmw_bmdma_status,
344 };
345
346 static struct ata_port_operations ich_pata_ops = {
347 .inherits = &piix_pata_ops,
348 .cable_detect = ich_pata_cable_detect,
349 .set_dmamode = ich_set_dmamode,
350 };
351
352 static struct device_attribute *piix_sidpr_shost_attrs[] = {
353 &dev_attr_link_power_management_policy,
354 NULL
355 };
356
357 static struct scsi_host_template piix_sidpr_sht = {
358 ATA_BMDMA_SHT(DRV_NAME),
359 .shost_attrs = piix_sidpr_shost_attrs,
360 };
361
362 static struct ata_port_operations piix_sidpr_sata_ops = {
363 .inherits = &piix_sata_ops,
364 .hardreset = sata_std_hardreset,
365 .scr_read = piix_sidpr_scr_read,
366 .scr_write = piix_sidpr_scr_write,
367 .set_lpm = piix_sidpr_set_lpm,
368 };
369
370 static const struct piix_map_db ich5_map_db = {
371 .mask = 0x7,
372 .port_enable = 0x3,
373 .map = {
374 /* PM PS SM SS MAP */
375 { P0, NA, P1, NA }, /* 000b */
376 { P1, NA, P0, NA }, /* 001b */
377 { RV, RV, RV, RV },
378 { RV, RV, RV, RV },
379 { P0, P1, IDE, IDE }, /* 100b */
380 { P1, P0, IDE, IDE }, /* 101b */
381 { IDE, IDE, P0, P1 }, /* 110b */
382 { IDE, IDE, P1, P0 }, /* 111b */
383 },
384 };
385
386 static const struct piix_map_db ich6_map_db = {
387 .mask = 0x3,
388 .port_enable = 0xf,
389 .map = {
390 /* PM PS SM SS MAP */
391 { P0, P2, P1, P3 }, /* 00b */
392 { IDE, IDE, P1, P3 }, /* 01b */
393 { P0, P2, IDE, IDE }, /* 10b */
394 { RV, RV, RV, RV },
395 },
396 };
397
398 static const struct piix_map_db ich6m_map_db = {
399 .mask = 0x3,
400 .port_enable = 0x5,
401
402 /* Map 01b isn't specified in the doc but some notebooks use
403 * it anyway. MAP 01b have been spotted on both ICH6M and
404 * ICH7M.
405 */
406 .map = {
407 /* PM PS SM SS MAP */
408 { P0, P2, NA, NA }, /* 00b */
409 { IDE, IDE, P1, P3 }, /* 01b */
410 { P0, P2, IDE, IDE }, /* 10b */
411 { RV, RV, RV, RV },
412 },
413 };
414
415 static const struct piix_map_db ich8_map_db = {
416 .mask = 0x3,
417 .port_enable = 0xf,
418 .map = {
419 /* PM PS SM SS MAP */
420 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
421 { RV, RV, RV, RV },
422 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
423 { RV, RV, RV, RV },
424 },
425 };
426
427 static const struct piix_map_db ich8_2port_map_db = {
428 .mask = 0x3,
429 .port_enable = 0x3,
430 .map = {
431 /* PM PS SM SS MAP */
432 { P0, NA, P1, NA }, /* 00b */
433 { RV, RV, RV, RV }, /* 01b */
434 { RV, RV, RV, RV }, /* 10b */
435 { RV, RV, RV, RV },
436 },
437 };
438
439 static const struct piix_map_db ich8m_apple_map_db = {
440 .mask = 0x3,
441 .port_enable = 0x1,
442 .map = {
443 /* PM PS SM SS MAP */
444 { P0, NA, NA, NA }, /* 00b */
445 { RV, RV, RV, RV },
446 { P0, P2, IDE, IDE }, /* 10b */
447 { RV, RV, RV, RV },
448 },
449 };
450
451 static const struct piix_map_db tolapai_map_db = {
452 .mask = 0x3,
453 .port_enable = 0x3,
454 .map = {
455 /* PM PS SM SS MAP */
456 { P0, NA, P1, NA }, /* 00b */
457 { RV, RV, RV, RV }, /* 01b */
458 { RV, RV, RV, RV }, /* 10b */
459 { RV, RV, RV, RV },
460 },
461 };
462
463 static const struct piix_map_db *piix_map_db_table[] = {
464 [ich5_sata] = &ich5_map_db,
465 [ich6_sata] = &ich6_map_db,
466 [ich6m_sata] = &ich6m_map_db,
467 [ich8_sata] = &ich8_map_db,
468 [ich8_2port_sata] = &ich8_2port_map_db,
469 [ich8m_apple_sata] = &ich8m_apple_map_db,
470 [tolapai_sata] = &tolapai_map_db,
471 };
472
473 static struct ata_port_info piix_port_info[] = {
474 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
475 {
476 .flags = PIIX_PATA_FLAGS,
477 .pio_mask = ATA_PIO4,
478 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
479 .port_ops = &piix_pata_ops,
480 },
481
482 [piix_pata_33] = /* PIIX4 at 33MHz */
483 {
484 .flags = PIIX_PATA_FLAGS,
485 .pio_mask = ATA_PIO4,
486 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
487 .udma_mask = ATA_UDMA2,
488 .port_ops = &piix_pata_ops,
489 },
490
491 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
492 {
493 .flags = PIIX_PATA_FLAGS,
494 .pio_mask = ATA_PIO4,
495 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
496 .udma_mask = ATA_UDMA2,
497 .port_ops = &ich_pata_ops,
498 },
499
500 [ich_pata_66] = /* ICH controllers up to 66MHz */
501 {
502 .flags = PIIX_PATA_FLAGS,
503 .pio_mask = ATA_PIO4,
504 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
505 .udma_mask = ATA_UDMA4,
506 .port_ops = &ich_pata_ops,
507 },
508
509 [ich_pata_100] =
510 {
511 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
512 .pio_mask = ATA_PIO4,
513 .mwdma_mask = ATA_MWDMA12_ONLY,
514 .udma_mask = ATA_UDMA5,
515 .port_ops = &ich_pata_ops,
516 },
517
518 [ich_pata_100_nomwdma1] =
519 {
520 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
521 .pio_mask = ATA_PIO4,
522 .mwdma_mask = ATA_MWDMA2_ONLY,
523 .udma_mask = ATA_UDMA5,
524 .port_ops = &ich_pata_ops,
525 },
526
527 [ich5_sata] =
528 {
529 .flags = PIIX_SATA_FLAGS,
530 .pio_mask = ATA_PIO4,
531 .mwdma_mask = ATA_MWDMA2,
532 .udma_mask = ATA_UDMA6,
533 .port_ops = &piix_sata_ops,
534 },
535
536 [ich6_sata] =
537 {
538 .flags = PIIX_SATA_FLAGS,
539 .pio_mask = ATA_PIO4,
540 .mwdma_mask = ATA_MWDMA2,
541 .udma_mask = ATA_UDMA6,
542 .port_ops = &piix_sata_ops,
543 },
544
545 [ich6m_sata] =
546 {
547 .flags = PIIX_SATA_FLAGS,
548 .pio_mask = ATA_PIO4,
549 .mwdma_mask = ATA_MWDMA2,
550 .udma_mask = ATA_UDMA6,
551 .port_ops = &piix_sata_ops,
552 },
553
554 [ich8_sata] =
555 {
556 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
557 .pio_mask = ATA_PIO4,
558 .mwdma_mask = ATA_MWDMA2,
559 .udma_mask = ATA_UDMA6,
560 .port_ops = &piix_sata_ops,
561 },
562
563 [ich8_2port_sata] =
564 {
565 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
566 .pio_mask = ATA_PIO4,
567 .mwdma_mask = ATA_MWDMA2,
568 .udma_mask = ATA_UDMA6,
569 .port_ops = &piix_sata_ops,
570 },
571
572 [tolapai_sata] =
573 {
574 .flags = PIIX_SATA_FLAGS,
575 .pio_mask = ATA_PIO4,
576 .mwdma_mask = ATA_MWDMA2,
577 .udma_mask = ATA_UDMA6,
578 .port_ops = &piix_sata_ops,
579 },
580
581 [ich8m_apple_sata] =
582 {
583 .flags = PIIX_SATA_FLAGS,
584 .pio_mask = ATA_PIO4,
585 .mwdma_mask = ATA_MWDMA2,
586 .udma_mask = ATA_UDMA6,
587 .port_ops = &piix_sata_ops,
588 },
589
590 [piix_pata_vmw] =
591 {
592 .flags = PIIX_PATA_FLAGS,
593 .pio_mask = ATA_PIO4,
594 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
595 .udma_mask = ATA_UDMA2,
596 .port_ops = &piix_vmw_ops,
597 },
598
599 };
600
601 static struct pci_bits piix_enable_bits[] = {
602 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
603 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
604 };
605
606 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
607 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
608 MODULE_LICENSE("GPL");
609 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
610 MODULE_VERSION(DRV_VERSION);
611
612 struct ich_laptop {
613 u16 device;
614 u16 subvendor;
615 u16 subdevice;
616 };
617
618 /*
619 * List of laptops that use short cables rather than 80 wire
620 */
621
622 static const struct ich_laptop ich_laptop[] = {
623 /* devid, subvendor, subdev */
624 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
625 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
626 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
627 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
628 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
629 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
630 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
631 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
632 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
633 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
634 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
635 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
636 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
637 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
638 /* end marker */
639 { 0, }
640 };
641
642 /**
643 * ich_pata_cable_detect - Probe host controller cable detect info
644 * @ap: Port for which cable detect info is desired
645 *
646 * Read 80c cable indicator from ATA PCI device's PCI config
647 * register. This register is normally set by firmware (BIOS).
648 *
649 * LOCKING:
650 * None (inherited from caller).
651 */
652
653 static int ich_pata_cable_detect(struct ata_port *ap)
654 {
655 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
656 struct piix_host_priv *hpriv = ap->host->private_data;
657 const struct ich_laptop *lap = &ich_laptop[0];
658 u8 mask;
659
660 /* Check for specials - Acer Aspire 5602WLMi */
661 while (lap->device) {
662 if (lap->device == pdev->device &&
663 lap->subvendor == pdev->subsystem_vendor &&
664 lap->subdevice == pdev->subsystem_device)
665 return ATA_CBL_PATA40_SHORT;
666
667 lap++;
668 }
669
670 /* check BIOS cable detect results */
671 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
672 if ((hpriv->saved_iocfg & mask) == 0)
673 return ATA_CBL_PATA40;
674 return ATA_CBL_PATA80;
675 }
676
677 /**
678 * piix_pata_prereset - prereset for PATA host controller
679 * @link: Target link
680 * @deadline: deadline jiffies for the operation
681 *
682 * LOCKING:
683 * None (inherited from caller).
684 */
685 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
686 {
687 struct ata_port *ap = link->ap;
688 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
689
690 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
691 return -ENOENT;
692 return ata_sff_prereset(link, deadline);
693 }
694
695 static DEFINE_SPINLOCK(piix_lock);
696
697 /**
698 * piix_set_piomode - Initialize host controller PATA PIO timings
699 * @ap: Port whose timings we are configuring
700 * @adev: um
701 *
702 * Set PIO mode for device, in host controller PCI config space.
703 *
704 * LOCKING:
705 * None (inherited from caller).
706 */
707
708 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
709 {
710 struct pci_dev *dev = to_pci_dev(ap->host->dev);
711 unsigned long flags;
712 unsigned int pio = adev->pio_mode - XFER_PIO_0;
713 unsigned int is_slave = (adev->devno != 0);
714 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
715 unsigned int slave_port = 0x44;
716 u16 master_data;
717 u8 slave_data;
718 u8 udma_enable;
719 int control = 0;
720
721 /*
722 * See Intel Document 298600-004 for the timing programing rules
723 * for ICH controllers.
724 */
725
726 static const /* ISP RTC */
727 u8 timings[][2] = { { 0, 0 },
728 { 0, 0 },
729 { 1, 0 },
730 { 2, 1 },
731 { 2, 3 }, };
732
733 if (pio >= 2)
734 control |= 1; /* TIME1 enable */
735 if (ata_pio_need_iordy(adev))
736 control |= 2; /* IE enable */
737
738 /* Intel specifies that the PPE functionality is for disk only */
739 if (adev->class == ATA_DEV_ATA)
740 control |= 4; /* PPE enable */
741
742 spin_lock_irqsave(&piix_lock, flags);
743
744 /* PIO configuration clears DTE unconditionally. It will be
745 * programmed in set_dmamode which is guaranteed to be called
746 * after set_piomode if any DMA mode is available.
747 */
748 pci_read_config_word(dev, master_port, &master_data);
749 if (is_slave) {
750 /* clear TIME1|IE1|PPE1|DTE1 */
751 master_data &= 0xff0f;
752 /* Enable SITRE (separate slave timing register) */
753 master_data |= 0x4000;
754 /* enable PPE1, IE1 and TIME1 as needed */
755 master_data |= (control << 4);
756 pci_read_config_byte(dev, slave_port, &slave_data);
757 slave_data &= (ap->port_no ? 0x0f : 0xf0);
758 /* Load the timing nibble for this slave */
759 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
760 << (ap->port_no ? 4 : 0);
761 } else {
762 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
763 master_data &= 0xccf0;
764 /* Enable PPE, IE and TIME as appropriate */
765 master_data |= control;
766 /* load ISP and RCT */
767 master_data |=
768 (timings[pio][0] << 12) |
769 (timings[pio][1] << 8);
770 }
771 pci_write_config_word(dev, master_port, master_data);
772 if (is_slave)
773 pci_write_config_byte(dev, slave_port, slave_data);
774
775 /* Ensure the UDMA bit is off - it will be turned back on if
776 UDMA is selected */
777
778 if (ap->udma_mask) {
779 pci_read_config_byte(dev, 0x48, &udma_enable);
780 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
781 pci_write_config_byte(dev, 0x48, udma_enable);
782 }
783
784 spin_unlock_irqrestore(&piix_lock, flags);
785 }
786
787 /**
788 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
789 * @ap: Port whose timings we are configuring
790 * @adev: Drive in question
791 * @isich: set if the chip is an ICH device
792 *
793 * Set UDMA mode for device, in host controller PCI config space.
794 *
795 * LOCKING:
796 * None (inherited from caller).
797 */
798
799 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
800 {
801 struct pci_dev *dev = to_pci_dev(ap->host->dev);
802 unsigned long flags;
803 u8 master_port = ap->port_no ? 0x42 : 0x40;
804 u16 master_data;
805 u8 speed = adev->dma_mode;
806 int devid = adev->devno + 2 * ap->port_no;
807 u8 udma_enable = 0;
808
809 static const /* ISP RTC */
810 u8 timings[][2] = { { 0, 0 },
811 { 0, 0 },
812 { 1, 0 },
813 { 2, 1 },
814 { 2, 3 }, };
815
816 spin_lock_irqsave(&piix_lock, flags);
817
818 pci_read_config_word(dev, master_port, &master_data);
819 if (ap->udma_mask)
820 pci_read_config_byte(dev, 0x48, &udma_enable);
821
822 if (speed >= XFER_UDMA_0) {
823 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
824 u16 udma_timing;
825 u16 ideconf;
826 int u_clock, u_speed;
827
828 /*
829 * UDMA is handled by a combination of clock switching and
830 * selection of dividers
831 *
832 * Handy rule: Odd modes are UDMATIMx 01, even are 02
833 * except UDMA0 which is 00
834 */
835 u_speed = min(2 - (udma & 1), udma);
836 if (udma == 5)
837 u_clock = 0x1000; /* 100Mhz */
838 else if (udma > 2)
839 u_clock = 1; /* 66Mhz */
840 else
841 u_clock = 0; /* 33Mhz */
842
843 udma_enable |= (1 << devid);
844
845 /* Load the CT/RP selection */
846 pci_read_config_word(dev, 0x4A, &udma_timing);
847 udma_timing &= ~(3 << (4 * devid));
848 udma_timing |= u_speed << (4 * devid);
849 pci_write_config_word(dev, 0x4A, udma_timing);
850
851 if (isich) {
852 /* Select a 33/66/100Mhz clock */
853 pci_read_config_word(dev, 0x54, &ideconf);
854 ideconf &= ~(0x1001 << devid);
855 ideconf |= u_clock << devid;
856 /* For ICH or later we should set bit 10 for better
857 performance (WR_PingPong_En) */
858 pci_write_config_word(dev, 0x54, ideconf);
859 }
860 } else {
861 /*
862 * MWDMA is driven by the PIO timings. We must also enable
863 * IORDY unconditionally along with TIME1. PPE has already
864 * been set when the PIO timing was set.
865 */
866 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
867 unsigned int control;
868 u8 slave_data;
869 const unsigned int needed_pio[3] = {
870 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
871 };
872 int pio = needed_pio[mwdma] - XFER_PIO_0;
873
874 control = 3; /* IORDY|TIME1 */
875
876 /* If the drive MWDMA is faster than it can do PIO then
877 we must force PIO into PIO0 */
878
879 if (adev->pio_mode < needed_pio[mwdma])
880 /* Enable DMA timing only */
881 control |= 8; /* PIO cycles in PIO0 */
882
883 if (adev->devno) { /* Slave */
884 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
885 master_data |= control << 4;
886 pci_read_config_byte(dev, 0x44, &slave_data);
887 slave_data &= (ap->port_no ? 0x0f : 0xf0);
888 /* Load the matching timing */
889 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
890 pci_write_config_byte(dev, 0x44, slave_data);
891 } else { /* Master */
892 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
893 and master timing bits */
894 master_data |= control;
895 master_data |=
896 (timings[pio][0] << 12) |
897 (timings[pio][1] << 8);
898 }
899
900 if (ap->udma_mask)
901 udma_enable &= ~(1 << devid);
902
903 pci_write_config_word(dev, master_port, master_data);
904 }
905 /* Don't scribble on 0x48 if the controller does not support UDMA */
906 if (ap->udma_mask)
907 pci_write_config_byte(dev, 0x48, udma_enable);
908
909 spin_unlock_irqrestore(&piix_lock, flags);
910 }
911
912 /**
913 * piix_set_dmamode - Initialize host controller PATA DMA timings
914 * @ap: Port whose timings we are configuring
915 * @adev: um
916 *
917 * Set MW/UDMA mode for device, in host controller PCI config space.
918 *
919 * LOCKING:
920 * None (inherited from caller).
921 */
922
923 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
924 {
925 do_pata_set_dmamode(ap, adev, 0);
926 }
927
928 /**
929 * ich_set_dmamode - Initialize host controller PATA DMA timings
930 * @ap: Port whose timings we are configuring
931 * @adev: um
932 *
933 * Set MW/UDMA mode for device, in host controller PCI config space.
934 *
935 * LOCKING:
936 * None (inherited from caller).
937 */
938
939 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
940 {
941 do_pata_set_dmamode(ap, adev, 1);
942 }
943
944 /*
945 * Serial ATA Index/Data Pair Superset Registers access
946 *
947 * Beginning from ICH8, there's a sane way to access SCRs using index
948 * and data register pair located at BAR5 which means that we have
949 * separate SCRs for master and slave. This is handled using libata
950 * slave_link facility.
951 */
952 static const int piix_sidx_map[] = {
953 [SCR_STATUS] = 0,
954 [SCR_ERROR] = 2,
955 [SCR_CONTROL] = 1,
956 };
957
958 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
959 {
960 struct ata_port *ap = link->ap;
961 struct piix_host_priv *hpriv = ap->host->private_data;
962
963 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
964 hpriv->sidpr + PIIX_SIDPR_IDX);
965 }
966
967 static int piix_sidpr_scr_read(struct ata_link *link,
968 unsigned int reg, u32 *val)
969 {
970 struct piix_host_priv *hpriv = link->ap->host->private_data;
971
972 if (reg >= ARRAY_SIZE(piix_sidx_map))
973 return -EINVAL;
974
975 piix_sidpr_sel(link, reg);
976 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
977 return 0;
978 }
979
980 static int piix_sidpr_scr_write(struct ata_link *link,
981 unsigned int reg, u32 val)
982 {
983 struct piix_host_priv *hpriv = link->ap->host->private_data;
984
985 if (reg >= ARRAY_SIZE(piix_sidx_map))
986 return -EINVAL;
987
988 piix_sidpr_sel(link, reg);
989 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
990 return 0;
991 }
992
993 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
994 unsigned hints)
995 {
996 return sata_link_scr_lpm(link, policy, false);
997 }
998
999 static bool piix_irq_check(struct ata_port *ap)
1000 {
1001 if (unlikely(!ap->ioaddr.bmdma_addr))
1002 return false;
1003
1004 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
1005 }
1006
1007 #ifdef CONFIG_PM
1008 static int piix_broken_suspend(void)
1009 {
1010 static const struct dmi_system_id sysids[] = {
1011 {
1012 .ident = "TECRA M3",
1013 .matches = {
1014 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1015 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1016 },
1017 },
1018 {
1019 .ident = "TECRA M3",
1020 .matches = {
1021 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1022 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1023 },
1024 },
1025 {
1026 .ident = "TECRA M4",
1027 .matches = {
1028 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1029 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1030 },
1031 },
1032 {
1033 .ident = "TECRA M4",
1034 .matches = {
1035 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1036 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1037 },
1038 },
1039 {
1040 .ident = "TECRA M5",
1041 .matches = {
1042 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1043 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1044 },
1045 },
1046 {
1047 .ident = "TECRA M6",
1048 .matches = {
1049 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1050 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1051 },
1052 },
1053 {
1054 .ident = "TECRA M7",
1055 .matches = {
1056 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1057 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1058 },
1059 },
1060 {
1061 .ident = "TECRA A8",
1062 .matches = {
1063 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1064 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1065 },
1066 },
1067 {
1068 .ident = "Satellite R20",
1069 .matches = {
1070 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1071 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1072 },
1073 },
1074 {
1075 .ident = "Satellite R25",
1076 .matches = {
1077 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1078 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1079 },
1080 },
1081 {
1082 .ident = "Satellite U200",
1083 .matches = {
1084 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1085 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1086 },
1087 },
1088 {
1089 .ident = "Satellite U200",
1090 .matches = {
1091 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1092 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1093 },
1094 },
1095 {
1096 .ident = "Satellite Pro U200",
1097 .matches = {
1098 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1099 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1100 },
1101 },
1102 {
1103 .ident = "Satellite U205",
1104 .matches = {
1105 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1106 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1107 },
1108 },
1109 {
1110 .ident = "SATELLITE U205",
1111 .matches = {
1112 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1113 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1114 },
1115 },
1116 {
1117 .ident = "Portege M500",
1118 .matches = {
1119 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1120 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1121 },
1122 },
1123 {
1124 .ident = "VGN-BX297XP",
1125 .matches = {
1126 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1127 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1128 },
1129 },
1130
1131 { } /* terminate list */
1132 };
1133 static const char *oemstrs[] = {
1134 "Tecra M3,",
1135 };
1136 int i;
1137
1138 if (dmi_check_system(sysids))
1139 return 1;
1140
1141 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1142 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1143 return 1;
1144
1145 /* TECRA M4 sometimes forgets its identify and reports bogus
1146 * DMI information. As the bogus information is a bit
1147 * generic, match as many entries as possible. This manual
1148 * matching is necessary because dmi_system_id.matches is
1149 * limited to four entries.
1150 */
1151 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1152 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1153 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1154 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1155 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1156 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1157 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1158 return 1;
1159
1160 return 0;
1161 }
1162
1163 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1164 {
1165 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1166 unsigned long flags;
1167 int rc = 0;
1168
1169 rc = ata_host_suspend(host, mesg);
1170 if (rc)
1171 return rc;
1172
1173 /* Some braindamaged ACPI suspend implementations expect the
1174 * controller to be awake on entry; otherwise, it burns cpu
1175 * cycles and power trying to do something to the sleeping
1176 * beauty.
1177 */
1178 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1179 pci_save_state(pdev);
1180
1181 /* mark its power state as "unknown", since we don't
1182 * know if e.g. the BIOS will change its device state
1183 * when we suspend.
1184 */
1185 if (pdev->current_state == PCI_D0)
1186 pdev->current_state = PCI_UNKNOWN;
1187
1188 /* tell resume that it's waking up from broken suspend */
1189 spin_lock_irqsave(&host->lock, flags);
1190 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1191 spin_unlock_irqrestore(&host->lock, flags);
1192 } else
1193 ata_pci_device_do_suspend(pdev, mesg);
1194
1195 return 0;
1196 }
1197
1198 static int piix_pci_device_resume(struct pci_dev *pdev)
1199 {
1200 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1201 unsigned long flags;
1202 int rc;
1203
1204 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1205 spin_lock_irqsave(&host->lock, flags);
1206 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1207 spin_unlock_irqrestore(&host->lock, flags);
1208
1209 pci_set_power_state(pdev, PCI_D0);
1210 pci_restore_state(pdev);
1211
1212 /* PCI device wasn't disabled during suspend. Use
1213 * pci_reenable_device() to avoid affecting the enable
1214 * count.
1215 */
1216 rc = pci_reenable_device(pdev);
1217 if (rc)
1218 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1219 "device after resume (%d)\n", rc);
1220 } else
1221 rc = ata_pci_device_do_resume(pdev);
1222
1223 if (rc == 0)
1224 ata_host_resume(host);
1225
1226 return rc;
1227 }
1228 #endif
1229
1230 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1231 {
1232 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1233 }
1234
1235 #define AHCI_PCI_BAR 5
1236 #define AHCI_GLOBAL_CTL 0x04
1237 #define AHCI_ENABLE (1 << 31)
1238 static int piix_disable_ahci(struct pci_dev *pdev)
1239 {
1240 void __iomem *mmio;
1241 u32 tmp;
1242 int rc = 0;
1243
1244 /* BUG: pci_enable_device has not yet been called. This
1245 * works because this device is usually set up by BIOS.
1246 */
1247
1248 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1249 !pci_resource_len(pdev, AHCI_PCI_BAR))
1250 return 0;
1251
1252 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1253 if (!mmio)
1254 return -ENOMEM;
1255
1256 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1257 if (tmp & AHCI_ENABLE) {
1258 tmp &= ~AHCI_ENABLE;
1259 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1260
1261 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1262 if (tmp & AHCI_ENABLE)
1263 rc = -EIO;
1264 }
1265
1266 pci_iounmap(pdev, mmio);
1267 return rc;
1268 }
1269
1270 /**
1271 * piix_check_450nx_errata - Check for problem 450NX setup
1272 * @ata_dev: the PCI device to check
1273 *
1274 * Check for the present of 450NX errata #19 and errata #25. If
1275 * they are found return an error code so we can turn off DMA
1276 */
1277
1278 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1279 {
1280 struct pci_dev *pdev = NULL;
1281 u16 cfg;
1282 int no_piix_dma = 0;
1283
1284 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1285 /* Look for 450NX PXB. Check for problem configurations
1286 A PCI quirk checks bit 6 already */
1287 pci_read_config_word(pdev, 0x41, &cfg);
1288 /* Only on the original revision: IDE DMA can hang */
1289 if (pdev->revision == 0x00)
1290 no_piix_dma = 1;
1291 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1292 else if (cfg & (1<<14) && pdev->revision < 5)
1293 no_piix_dma = 2;
1294 }
1295 if (no_piix_dma)
1296 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1297 if (no_piix_dma == 2)
1298 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1299 return no_piix_dma;
1300 }
1301
1302 static void __devinit piix_init_pcs(struct ata_host *host,
1303 const struct piix_map_db *map_db)
1304 {
1305 struct pci_dev *pdev = to_pci_dev(host->dev);
1306 u16 pcs, new_pcs;
1307
1308 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1309
1310 new_pcs = pcs | map_db->port_enable;
1311
1312 if (new_pcs != pcs) {
1313 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1314 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1315 msleep(150);
1316 }
1317 }
1318
1319 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1320 struct ata_port_info *pinfo,
1321 const struct piix_map_db *map_db)
1322 {
1323 const int *map;
1324 int i, invalid_map = 0;
1325 u8 map_value;
1326
1327 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1328
1329 map = map_db->map[map_value & map_db->mask];
1330
1331 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1332 for (i = 0; i < 4; i++) {
1333 switch (map[i]) {
1334 case RV:
1335 invalid_map = 1;
1336 printk(" XX");
1337 break;
1338
1339 case NA:
1340 printk(" --");
1341 break;
1342
1343 case IDE:
1344 WARN_ON((i & 1) || map[i + 1] != IDE);
1345 pinfo[i / 2] = piix_port_info[ich_pata_100];
1346 i++;
1347 printk(" IDE IDE");
1348 break;
1349
1350 default:
1351 printk(" P%d", map[i]);
1352 if (i & 1)
1353 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1354 break;
1355 }
1356 }
1357 printk(" ]\n");
1358
1359 if (invalid_map)
1360 dev_printk(KERN_ERR, &pdev->dev,
1361 "invalid MAP value %u\n", map_value);
1362
1363 return map;
1364 }
1365
1366 static bool piix_no_sidpr(struct ata_host *host)
1367 {
1368 struct pci_dev *pdev = to_pci_dev(host->dev);
1369
1370 /*
1371 * Samsung DB-P70 only has three ATA ports exposed and
1372 * curiously the unconnected first port reports link online
1373 * while not responding to SRST protocol causing excessive
1374 * detection delay.
1375 *
1376 * Unfortunately, the system doesn't carry enough DMI
1377 * information to identify the machine but does have subsystem
1378 * vendor and device set. As it's unclear whether the
1379 * subsystem vendor/device is used only for this specific
1380 * board, the port can't be disabled solely with the
1381 * information; however, turning off SIDPR access works around
1382 * the problem. Turn it off.
1383 *
1384 * This problem is reported in bnc#441240.
1385 *
1386 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1387 */
1388 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1389 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1390 pdev->subsystem_device == 0xb049) {
1391 dev_printk(KERN_WARNING, host->dev,
1392 "Samsung DB-P70 detected, disabling SIDPR\n");
1393 return true;
1394 }
1395
1396 return false;
1397 }
1398
1399 static int __devinit piix_init_sidpr(struct ata_host *host)
1400 {
1401 struct pci_dev *pdev = to_pci_dev(host->dev);
1402 struct piix_host_priv *hpriv = host->private_data;
1403 struct ata_link *link0 = &host->ports[0]->link;
1404 u32 scontrol;
1405 int i, rc;
1406
1407 /* check for availability */
1408 for (i = 0; i < 4; i++)
1409 if (hpriv->map[i] == IDE)
1410 return 0;
1411
1412 /* is it blacklisted? */
1413 if (piix_no_sidpr(host))
1414 return 0;
1415
1416 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1417 return 0;
1418
1419 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1420 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1421 return 0;
1422
1423 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1424 return 0;
1425
1426 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1427
1428 /* SCR access via SIDPR doesn't work on some configurations.
1429 * Give it a test drive by inhibiting power save modes which
1430 * we'll do anyway.
1431 */
1432 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1433
1434 /* if IPM is already 3, SCR access is probably working. Don't
1435 * un-inhibit power save modes as BIOS might have inhibited
1436 * them for a reason.
1437 */
1438 if ((scontrol & 0xf00) != 0x300) {
1439 scontrol |= 0x300;
1440 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1441 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1442
1443 if ((scontrol & 0xf00) != 0x300) {
1444 dev_printk(KERN_INFO, host->dev, "SCR access via "
1445 "SIDPR is available but doesn't work\n");
1446 return 0;
1447 }
1448 }
1449
1450 /* okay, SCRs available, set ops and ask libata for slave_link */
1451 for (i = 0; i < 2; i++) {
1452 struct ata_port *ap = host->ports[i];
1453
1454 ap->ops = &piix_sidpr_sata_ops;
1455
1456 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1457 rc = ata_slave_link_init(ap);
1458 if (rc)
1459 return rc;
1460 }
1461 }
1462
1463 return 0;
1464 }
1465
1466 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1467 {
1468 static const struct dmi_system_id sysids[] = {
1469 {
1470 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1471 * isn't used to boot the system which
1472 * disables the channel.
1473 */
1474 .ident = "M570U",
1475 .matches = {
1476 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1477 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1478 },
1479 },
1480
1481 { } /* terminate list */
1482 };
1483 struct pci_dev *pdev = to_pci_dev(host->dev);
1484 struct piix_host_priv *hpriv = host->private_data;
1485
1486 if (!dmi_check_system(sysids))
1487 return;
1488
1489 /* The datasheet says that bit 18 is NOOP but certain systems
1490 * seem to use it to disable a channel. Clear the bit on the
1491 * affected systems.
1492 */
1493 if (hpriv->saved_iocfg & (1 << 18)) {
1494 dev_printk(KERN_INFO, &pdev->dev,
1495 "applying IOCFG bit18 quirk\n");
1496 pci_write_config_dword(pdev, PIIX_IOCFG,
1497 hpriv->saved_iocfg & ~(1 << 18));
1498 }
1499 }
1500
1501 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1502 {
1503 static const struct dmi_system_id broken_systems[] = {
1504 {
1505 .ident = "HP Compaq 2510p",
1506 .matches = {
1507 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1508 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1509 },
1510 /* PCI slot number of the controller */
1511 .driver_data = (void *)0x1FUL,
1512 },
1513 {
1514 .ident = "HP Compaq nc6000",
1515 .matches = {
1516 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1517 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1518 },
1519 /* PCI slot number of the controller */
1520 .driver_data = (void *)0x1FUL,
1521 },
1522
1523 { } /* terminate list */
1524 };
1525 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1526
1527 if (dmi) {
1528 unsigned long slot = (unsigned long)dmi->driver_data;
1529 /* apply the quirk only to on-board controllers */
1530 return slot == PCI_SLOT(pdev->devfn);
1531 }
1532
1533 return false;
1534 }
1535
1536 /**
1537 * piix_init_one - Register PIIX ATA PCI device with kernel services
1538 * @pdev: PCI device to register
1539 * @ent: Entry in piix_pci_tbl matching with @pdev
1540 *
1541 * Called from kernel PCI layer. We probe for combined mode (sigh),
1542 * and then hand over control to libata, for it to do the rest.
1543 *
1544 * LOCKING:
1545 * Inherited from PCI layer (may sleep).
1546 *
1547 * RETURNS:
1548 * Zero on success, or -ERRNO value.
1549 */
1550
1551 static int __devinit piix_init_one(struct pci_dev *pdev,
1552 const struct pci_device_id *ent)
1553 {
1554 static int printed_version;
1555 struct device *dev = &pdev->dev;
1556 struct ata_port_info port_info[2];
1557 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1558 struct scsi_host_template *sht = &piix_sht;
1559 unsigned long port_flags;
1560 struct ata_host *host;
1561 struct piix_host_priv *hpriv;
1562 int rc;
1563
1564 if (!printed_version++)
1565 dev_printk(KERN_DEBUG, &pdev->dev,
1566 "version " DRV_VERSION "\n");
1567
1568 /* no hotplugging support for later devices (FIXME) */
1569 if (!in_module_init && ent->driver_data >= ich5_sata)
1570 return -ENODEV;
1571
1572 if (piix_broken_system_poweroff(pdev)) {
1573 piix_port_info[ent->driver_data].flags |=
1574 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1575 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1576 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1577 "on poweroff and hibernation\n");
1578 }
1579
1580 port_info[0] = piix_port_info[ent->driver_data];
1581 port_info[1] = piix_port_info[ent->driver_data];
1582
1583 port_flags = port_info[0].flags;
1584
1585 /* enable device and prepare host */
1586 rc = pcim_enable_device(pdev);
1587 if (rc)
1588 return rc;
1589
1590 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1591 if (!hpriv)
1592 return -ENOMEM;
1593
1594 /* Save IOCFG, this will be used for cable detection, quirk
1595 * detection and restoration on detach. This is necessary
1596 * because some ACPI implementations mess up cable related
1597 * bits on _STM. Reported on kernel bz#11879.
1598 */
1599 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1600
1601 /* ICH6R may be driven by either ata_piix or ahci driver
1602 * regardless of BIOS configuration. Make sure AHCI mode is
1603 * off.
1604 */
1605 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1606 rc = piix_disable_ahci(pdev);
1607 if (rc)
1608 return rc;
1609 }
1610
1611 /* SATA map init can change port_info, do it before prepping host */
1612 if (port_flags & ATA_FLAG_SATA)
1613 hpriv->map = piix_init_sata_map(pdev, port_info,
1614 piix_map_db_table[ent->driver_data]);
1615
1616 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1617 if (rc)
1618 return rc;
1619 host->private_data = hpriv;
1620
1621 /* initialize controller */
1622 if (port_flags & ATA_FLAG_SATA) {
1623 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1624 rc = piix_init_sidpr(host);
1625 if (rc)
1626 return rc;
1627 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1628 sht = &piix_sidpr_sht;
1629 }
1630
1631 /* apply IOCFG bit18 quirk */
1632 piix_iocfg_bit18_quirk(host);
1633
1634 /* On ICH5, some BIOSen disable the interrupt using the
1635 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1636 * On ICH6, this bit has the same effect, but only when
1637 * MSI is disabled (and it is disabled, as we don't use
1638 * message-signalled interrupts currently).
1639 */
1640 if (port_flags & PIIX_FLAG_CHECKINTR)
1641 pci_intx(pdev, 1);
1642
1643 if (piix_check_450nx_errata(pdev)) {
1644 /* This writes into the master table but it does not
1645 really matter for this errata as we will apply it to
1646 all the PIIX devices on the board */
1647 host->ports[0]->mwdma_mask = 0;
1648 host->ports[0]->udma_mask = 0;
1649 host->ports[1]->mwdma_mask = 0;
1650 host->ports[1]->udma_mask = 0;
1651 }
1652 host->flags |= ATA_HOST_PARALLEL_SCAN;
1653
1654 pci_set_master(pdev);
1655 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1656 }
1657
1658 static void piix_remove_one(struct pci_dev *pdev)
1659 {
1660 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1661 struct piix_host_priv *hpriv = host->private_data;
1662
1663 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1664
1665 ata_pci_remove_one(pdev);
1666 }
1667
1668 static int __init piix_init(void)
1669 {
1670 int rc;
1671
1672 DPRINTK("pci_register_driver\n");
1673 rc = pci_register_driver(&piix_pci_driver);
1674 if (rc)
1675 return rc;
1676
1677 in_module_init = 0;
1678
1679 DPRINTK("done\n");
1680 return 0;
1681 }
1682
1683 static void __exit piix_exit(void)
1684 {
1685 pci_unregister_driver(&piix_pci_driver);
1686 }
1687
1688 module_init(piix_init);
1689 module_exit(piix_exit);
Linux kernel - Deliverables
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