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libata: make SCR access ops per-link
[deliverable/linux.git] / drivers / ata / ata_piix.c
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
95
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
98
99 enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
103 PIIX_SIDPR_BAR = 5,
104 PIIX_SIDPR_LEN = 16,
105 PIIX_SIDPR_IDX = 0,
106 PIIX_SIDPR_DATA = 4,
107
108 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
109 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
110
111 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
112 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
113
114 PIIX_80C_PRI = (1 << 5) | (1 << 4),
115 PIIX_80C_SEC = (1 << 7) | (1 << 6),
116
117 /* constants for mapping table */
118 P0 = 0, /* port 0 */
119 P1 = 1, /* port 1 */
120 P2 = 2, /* port 2 */
121 P3 = 3, /* port 3 */
122 IDE = -1, /* IDE */
123 NA = -2, /* not avaliable */
124 RV = -3, /* reserved */
125
126 PIIX_AHCI_DEVICE = 6,
127
128 /* host->flags bits */
129 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
130 };
131
132 enum piix_controller_ids {
133 /* controller IDs */
134 piix_pata_mwdma, /* PIIX3 MWDMA only */
135 piix_pata_33, /* PIIX4 at 33Mhz */
136 ich_pata_33, /* ICH up to UDMA 33 only */
137 ich_pata_66, /* ICH up to 66 Mhz */
138 ich_pata_100, /* ICH up to UDMA 100 */
139 ich5_sata,
140 ich6_sata,
141 ich6m_sata,
142 ich8_sata,
143 ich8_2port_sata,
144 ich8m_apple_sata, /* locks up on second port enable */
145 tolapai_sata,
146 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
147 };
148
149 struct piix_map_db {
150 const u32 mask;
151 const u16 port_enable;
152 const int map[][4];
153 };
154
155 struct piix_host_priv {
156 const int *map;
157 void __iomem *sidpr;
158 };
159
160 static int piix_init_one(struct pci_dev *pdev,
161 const struct pci_device_id *ent);
162 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
163 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
164 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
165 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
166 static int ich_pata_cable_detect(struct ata_port *ap);
167 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
168 static int piix_sidpr_scr_read(struct ata_link *link,
169 unsigned int reg, u32 *val);
170 static int piix_sidpr_scr_write(struct ata_link *link,
171 unsigned int reg, u32 val);
172 #ifdef CONFIG_PM
173 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
174 static int piix_pci_device_resume(struct pci_dev *pdev);
175 #endif
176
177 static unsigned int in_module_init = 1;
178
179 static const struct pci_device_id piix_pci_tbl[] = {
180 /* Intel PIIX3 for the 430HX etc */
181 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
182 /* VMware ICH4 */
183 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
184 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
185 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
186 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
187 /* Intel PIIX4 */
188 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
189 /* Intel PIIX4 */
190 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
191 /* Intel PIIX */
192 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
193 /* Intel ICH (i810, i815, i840) UDMA 66*/
194 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
195 /* Intel ICH0 : UDMA 33*/
196 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
197 /* Intel ICH2M */
198 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
200 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH3M */
202 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* Intel ICH3 (E7500/1) UDMA 100 */
204 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
206 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* Intel ICH5 */
209 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* C-ICH (i810E2) */
211 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
213 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 /* ICH6 (and 6) (i915) UDMA 100 */
215 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 /* ICH7/7-R (i945, i975) UDMA 100*/
217 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
219 /* ICH8 Mobile PATA Controller */
220 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221
222 /* NOTE: The following PCI ids must be kept in sync with the
223 * list in drivers/pci/quirks.c.
224 */
225
226 /* 82801EB (ICH5) */
227 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
228 /* 82801EB (ICH5) */
229 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
230 /* 6300ESB (ICH5 variant with broken PCS present bits) */
231 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
232 /* 6300ESB pretending RAID */
233 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
234 /* 82801FB/FW (ICH6/ICH6W) */
235 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
236 /* 82801FR/FRW (ICH6R/ICH6RW) */
237 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
238 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
239 * Attach iff the controller is in IDE mode. */
240 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
241 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
242 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
243 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
244 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
245 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
246 /* Enterprise Southbridge 2 (631xESB/632xESB) */
247 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
248 /* SATA Controller 1 IDE (ICH8) */
249 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
250 /* SATA Controller 2 IDE (ICH8) */
251 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
252 /* Mobile SATA Controller IDE (ICH8M), Apple */
253 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
254 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
255 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
256 /* Mobile SATA Controller IDE (ICH8M) */
257 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
258 /* SATA Controller IDE (ICH9) */
259 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
260 /* SATA Controller IDE (ICH9) */
261 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
262 /* SATA Controller IDE (ICH9) */
263 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
264 /* SATA Controller IDE (ICH9M) */
265 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* SATA Controller IDE (ICH9M) */
267 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
268 /* SATA Controller IDE (ICH9M) */
269 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
270 /* SATA Controller IDE (Tolapai) */
271 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
272 /* SATA Controller IDE (ICH10) */
273 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
274 /* SATA Controller IDE (ICH10) */
275 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
276 /* SATA Controller IDE (ICH10) */
277 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
278 /* SATA Controller IDE (ICH10) */
279 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
280 /* SATA Controller IDE (PCH) */
281 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
282 /* SATA Controller IDE (PCH) */
283 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
284 /* SATA Controller IDE (PCH) */
285 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
286 /* SATA Controller IDE (PCH) */
287 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
288
289 { } /* terminate list */
290 };
291
292 static struct pci_driver piix_pci_driver = {
293 .name = DRV_NAME,
294 .id_table = piix_pci_tbl,
295 .probe = piix_init_one,
296 .remove = ata_pci_remove_one,
297 #ifdef CONFIG_PM
298 .suspend = piix_pci_device_suspend,
299 .resume = piix_pci_device_resume,
300 #endif
301 };
302
303 static struct scsi_host_template piix_sht = {
304 ATA_BMDMA_SHT(DRV_NAME),
305 };
306
307 static struct ata_port_operations piix_pata_ops = {
308 .inherits = &ata_bmdma_port_ops,
309 .cable_detect = ata_cable_40wire,
310 .set_piomode = piix_set_piomode,
311 .set_dmamode = piix_set_dmamode,
312 .prereset = piix_pata_prereset,
313 };
314
315 static struct ata_port_operations piix_vmw_ops = {
316 .inherits = &piix_pata_ops,
317 .bmdma_status = piix_vmw_bmdma_status,
318 };
319
320 static struct ata_port_operations ich_pata_ops = {
321 .inherits = &piix_pata_ops,
322 .cable_detect = ich_pata_cable_detect,
323 .set_dmamode = ich_set_dmamode,
324 };
325
326 static struct ata_port_operations piix_sata_ops = {
327 .inherits = &ata_bmdma_port_ops,
328 };
329
330 static struct ata_port_operations piix_sidpr_sata_ops = {
331 .inherits = &piix_sata_ops,
332 .hardreset = sata_std_hardreset,
333 .scr_read = piix_sidpr_scr_read,
334 .scr_write = piix_sidpr_scr_write,
335 };
336
337 static const struct piix_map_db ich5_map_db = {
338 .mask = 0x7,
339 .port_enable = 0x3,
340 .map = {
341 /* PM PS SM SS MAP */
342 { P0, NA, P1, NA }, /* 000b */
343 { P1, NA, P0, NA }, /* 001b */
344 { RV, RV, RV, RV },
345 { RV, RV, RV, RV },
346 { P0, P1, IDE, IDE }, /* 100b */
347 { P1, P0, IDE, IDE }, /* 101b */
348 { IDE, IDE, P0, P1 }, /* 110b */
349 { IDE, IDE, P1, P0 }, /* 111b */
350 },
351 };
352
353 static const struct piix_map_db ich6_map_db = {
354 .mask = 0x3,
355 .port_enable = 0xf,
356 .map = {
357 /* PM PS SM SS MAP */
358 { P0, P2, P1, P3 }, /* 00b */
359 { IDE, IDE, P1, P3 }, /* 01b */
360 { P0, P2, IDE, IDE }, /* 10b */
361 { RV, RV, RV, RV },
362 },
363 };
364
365 static const struct piix_map_db ich6m_map_db = {
366 .mask = 0x3,
367 .port_enable = 0x5,
368
369 /* Map 01b isn't specified in the doc but some notebooks use
370 * it anyway. MAP 01b have been spotted on both ICH6M and
371 * ICH7M.
372 */
373 .map = {
374 /* PM PS SM SS MAP */
375 { P0, P2, NA, NA }, /* 00b */
376 { IDE, IDE, P1, P3 }, /* 01b */
377 { P0, P2, IDE, IDE }, /* 10b */
378 { RV, RV, RV, RV },
379 },
380 };
381
382 static const struct piix_map_db ich8_map_db = {
383 .mask = 0x3,
384 .port_enable = 0xf,
385 .map = {
386 /* PM PS SM SS MAP */
387 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
388 { RV, RV, RV, RV },
389 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
390 { RV, RV, RV, RV },
391 },
392 };
393
394 static const struct piix_map_db ich8_2port_map_db = {
395 .mask = 0x3,
396 .port_enable = 0x3,
397 .map = {
398 /* PM PS SM SS MAP */
399 { P0, NA, P1, NA }, /* 00b */
400 { RV, RV, RV, RV }, /* 01b */
401 { RV, RV, RV, RV }, /* 10b */
402 { RV, RV, RV, RV },
403 },
404 };
405
406 static const struct piix_map_db ich8m_apple_map_db = {
407 .mask = 0x3,
408 .port_enable = 0x1,
409 .map = {
410 /* PM PS SM SS MAP */
411 { P0, NA, NA, NA }, /* 00b */
412 { RV, RV, RV, RV },
413 { P0, P2, IDE, IDE }, /* 10b */
414 { RV, RV, RV, RV },
415 },
416 };
417
418 static const struct piix_map_db tolapai_map_db = {
419 .mask = 0x3,
420 .port_enable = 0x3,
421 .map = {
422 /* PM PS SM SS MAP */
423 { P0, NA, P1, NA }, /* 00b */
424 { RV, RV, RV, RV }, /* 01b */
425 { RV, RV, RV, RV }, /* 10b */
426 { RV, RV, RV, RV },
427 },
428 };
429
430 static const struct piix_map_db *piix_map_db_table[] = {
431 [ich5_sata] = &ich5_map_db,
432 [ich6_sata] = &ich6_map_db,
433 [ich6m_sata] = &ich6m_map_db,
434 [ich8_sata] = &ich8_map_db,
435 [ich8_2port_sata] = &ich8_2port_map_db,
436 [ich8m_apple_sata] = &ich8m_apple_map_db,
437 [tolapai_sata] = &tolapai_map_db,
438 };
439
440 static struct ata_port_info piix_port_info[] = {
441 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
442 {
443 .flags = PIIX_PATA_FLAGS,
444 .pio_mask = 0x1f, /* pio0-4 */
445 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
446 .port_ops = &piix_pata_ops,
447 },
448
449 [piix_pata_33] = /* PIIX4 at 33MHz */
450 {
451 .flags = PIIX_PATA_FLAGS,
452 .pio_mask = 0x1f, /* pio0-4 */
453 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
454 .udma_mask = ATA_UDMA_MASK_40C,
455 .port_ops = &piix_pata_ops,
456 },
457
458 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
459 {
460 .flags = PIIX_PATA_FLAGS,
461 .pio_mask = 0x1f, /* pio 0-4 */
462 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
463 .udma_mask = ATA_UDMA2, /* UDMA33 */
464 .port_ops = &ich_pata_ops,
465 },
466
467 [ich_pata_66] = /* ICH controllers up to 66MHz */
468 {
469 .flags = PIIX_PATA_FLAGS,
470 .pio_mask = 0x1f, /* pio 0-4 */
471 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
472 .udma_mask = ATA_UDMA4,
473 .port_ops = &ich_pata_ops,
474 },
475
476 [ich_pata_100] =
477 {
478 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
479 .pio_mask = 0x1f, /* pio0-4 */
480 .mwdma_mask = 0x06, /* mwdma1-2 */
481 .udma_mask = ATA_UDMA5, /* udma0-5 */
482 .port_ops = &ich_pata_ops,
483 },
484
485 [ich5_sata] =
486 {
487 .flags = PIIX_SATA_FLAGS,
488 .pio_mask = 0x1f, /* pio0-4 */
489 .mwdma_mask = 0x07, /* mwdma0-2 */
490 .udma_mask = ATA_UDMA6,
491 .port_ops = &piix_sata_ops,
492 },
493
494 [ich6_sata] =
495 {
496 .flags = PIIX_SATA_FLAGS,
497 .pio_mask = 0x1f, /* pio0-4 */
498 .mwdma_mask = 0x07, /* mwdma0-2 */
499 .udma_mask = ATA_UDMA6,
500 .port_ops = &piix_sata_ops,
501 },
502
503 [ich6m_sata] =
504 {
505 .flags = PIIX_SATA_FLAGS,
506 .pio_mask = 0x1f, /* pio0-4 */
507 .mwdma_mask = 0x07, /* mwdma0-2 */
508 .udma_mask = ATA_UDMA6,
509 .port_ops = &piix_sata_ops,
510 },
511
512 [ich8_sata] =
513 {
514 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
515 .pio_mask = 0x1f, /* pio0-4 */
516 .mwdma_mask = 0x07, /* mwdma0-2 */
517 .udma_mask = ATA_UDMA6,
518 .port_ops = &piix_sata_ops,
519 },
520
521 [ich8_2port_sata] =
522 {
523 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
524 .pio_mask = 0x1f, /* pio0-4 */
525 .mwdma_mask = 0x07, /* mwdma0-2 */
526 .udma_mask = ATA_UDMA6,
527 .port_ops = &piix_sata_ops,
528 },
529
530 [tolapai_sata] =
531 {
532 .flags = PIIX_SATA_FLAGS,
533 .pio_mask = 0x1f, /* pio0-4 */
534 .mwdma_mask = 0x07, /* mwdma0-2 */
535 .udma_mask = ATA_UDMA6,
536 .port_ops = &piix_sata_ops,
537 },
538
539 [ich8m_apple_sata] =
540 {
541 .flags = PIIX_SATA_FLAGS,
542 .pio_mask = 0x1f, /* pio0-4 */
543 .mwdma_mask = 0x07, /* mwdma0-2 */
544 .udma_mask = ATA_UDMA6,
545 .port_ops = &piix_sata_ops,
546 },
547
548 [piix_pata_vmw] =
549 {
550 .flags = PIIX_PATA_FLAGS,
551 .pio_mask = 0x1f, /* pio0-4 */
552 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
553 .udma_mask = ATA_UDMA_MASK_40C,
554 .port_ops = &piix_vmw_ops,
555 },
556
557 };
558
559 static struct pci_bits piix_enable_bits[] = {
560 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
561 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
562 };
563
564 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
565 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
566 MODULE_LICENSE("GPL");
567 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
568 MODULE_VERSION(DRV_VERSION);
569
570 struct ich_laptop {
571 u16 device;
572 u16 subvendor;
573 u16 subdevice;
574 };
575
576 /*
577 * List of laptops that use short cables rather than 80 wire
578 */
579
580 static const struct ich_laptop ich_laptop[] = {
581 /* devid, subvendor, subdev */
582 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
583 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
584 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
585 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
586 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
587 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
588 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
589 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
590 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
591 /* end marker */
592 { 0, }
593 };
594
595 /**
596 * ich_pata_cable_detect - Probe host controller cable detect info
597 * @ap: Port for which cable detect info is desired
598 *
599 * Read 80c cable indicator from ATA PCI device's PCI config
600 * register. This register is normally set by firmware (BIOS).
601 *
602 * LOCKING:
603 * None (inherited from caller).
604 */
605
606 static int ich_pata_cable_detect(struct ata_port *ap)
607 {
608 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
609 const struct ich_laptop *lap = &ich_laptop[0];
610 u8 tmp, mask;
611
612 /* Check for specials - Acer Aspire 5602WLMi */
613 while (lap->device) {
614 if (lap->device == pdev->device &&
615 lap->subvendor == pdev->subsystem_vendor &&
616 lap->subdevice == pdev->subsystem_device)
617 return ATA_CBL_PATA40_SHORT;
618
619 lap++;
620 }
621
622 /* check BIOS cable detect results */
623 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
624 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
625 if ((tmp & mask) == 0)
626 return ATA_CBL_PATA40;
627 return ATA_CBL_PATA80;
628 }
629
630 /**
631 * piix_pata_prereset - prereset for PATA host controller
632 * @link: Target link
633 * @deadline: deadline jiffies for the operation
634 *
635 * LOCKING:
636 * None (inherited from caller).
637 */
638 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
639 {
640 struct ata_port *ap = link->ap;
641 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
642
643 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
644 return -ENOENT;
645 return ata_sff_prereset(link, deadline);
646 }
647
648 /**
649 * piix_set_piomode - Initialize host controller PATA PIO timings
650 * @ap: Port whose timings we are configuring
651 * @adev: um
652 *
653 * Set PIO mode for device, in host controller PCI config space.
654 *
655 * LOCKING:
656 * None (inherited from caller).
657 */
658
659 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
660 {
661 unsigned int pio = adev->pio_mode - XFER_PIO_0;
662 struct pci_dev *dev = to_pci_dev(ap->host->dev);
663 unsigned int is_slave = (adev->devno != 0);
664 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
665 unsigned int slave_port = 0x44;
666 u16 master_data;
667 u8 slave_data;
668 u8 udma_enable;
669 int control = 0;
670
671 /*
672 * See Intel Document 298600-004 for the timing programing rules
673 * for ICH controllers.
674 */
675
676 static const /* ISP RTC */
677 u8 timings[][2] = { { 0, 0 },
678 { 0, 0 },
679 { 1, 0 },
680 { 2, 1 },
681 { 2, 3 }, };
682
683 if (pio >= 2)
684 control |= 1; /* TIME1 enable */
685 if (ata_pio_need_iordy(adev))
686 control |= 2; /* IE enable */
687
688 /* Intel specifies that the PPE functionality is for disk only */
689 if (adev->class == ATA_DEV_ATA)
690 control |= 4; /* PPE enable */
691
692 /* PIO configuration clears DTE unconditionally. It will be
693 * programmed in set_dmamode which is guaranteed to be called
694 * after set_piomode if any DMA mode is available.
695 */
696 pci_read_config_word(dev, master_port, &master_data);
697 if (is_slave) {
698 /* clear TIME1|IE1|PPE1|DTE1 */
699 master_data &= 0xff0f;
700 /* Enable SITRE (separate slave timing register) */
701 master_data |= 0x4000;
702 /* enable PPE1, IE1 and TIME1 as needed */
703 master_data |= (control << 4);
704 pci_read_config_byte(dev, slave_port, &slave_data);
705 slave_data &= (ap->port_no ? 0x0f : 0xf0);
706 /* Load the timing nibble for this slave */
707 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
708 << (ap->port_no ? 4 : 0);
709 } else {
710 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
711 master_data &= 0xccf0;
712 /* Enable PPE, IE and TIME as appropriate */
713 master_data |= control;
714 /* load ISP and RCT */
715 master_data |=
716 (timings[pio][0] << 12) |
717 (timings[pio][1] << 8);
718 }
719 pci_write_config_word(dev, master_port, master_data);
720 if (is_slave)
721 pci_write_config_byte(dev, slave_port, slave_data);
722
723 /* Ensure the UDMA bit is off - it will be turned back on if
724 UDMA is selected */
725
726 if (ap->udma_mask) {
727 pci_read_config_byte(dev, 0x48, &udma_enable);
728 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
729 pci_write_config_byte(dev, 0x48, udma_enable);
730 }
731 }
732
733 /**
734 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
735 * @ap: Port whose timings we are configuring
736 * @adev: Drive in question
737 * @udma: udma mode, 0 - 6
738 * @isich: set if the chip is an ICH device
739 *
740 * Set UDMA mode for device, in host controller PCI config space.
741 *
742 * LOCKING:
743 * None (inherited from caller).
744 */
745
746 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
747 {
748 struct pci_dev *dev = to_pci_dev(ap->host->dev);
749 u8 master_port = ap->port_no ? 0x42 : 0x40;
750 u16 master_data;
751 u8 speed = adev->dma_mode;
752 int devid = adev->devno + 2 * ap->port_no;
753 u8 udma_enable = 0;
754
755 static const /* ISP RTC */
756 u8 timings[][2] = { { 0, 0 },
757 { 0, 0 },
758 { 1, 0 },
759 { 2, 1 },
760 { 2, 3 }, };
761
762 pci_read_config_word(dev, master_port, &master_data);
763 if (ap->udma_mask)
764 pci_read_config_byte(dev, 0x48, &udma_enable);
765
766 if (speed >= XFER_UDMA_0) {
767 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
768 u16 udma_timing;
769 u16 ideconf;
770 int u_clock, u_speed;
771
772 /*
773 * UDMA is handled by a combination of clock switching and
774 * selection of dividers
775 *
776 * Handy rule: Odd modes are UDMATIMx 01, even are 02
777 * except UDMA0 which is 00
778 */
779 u_speed = min(2 - (udma & 1), udma);
780 if (udma == 5)
781 u_clock = 0x1000; /* 100Mhz */
782 else if (udma > 2)
783 u_clock = 1; /* 66Mhz */
784 else
785 u_clock = 0; /* 33Mhz */
786
787 udma_enable |= (1 << devid);
788
789 /* Load the CT/RP selection */
790 pci_read_config_word(dev, 0x4A, &udma_timing);
791 udma_timing &= ~(3 << (4 * devid));
792 udma_timing |= u_speed << (4 * devid);
793 pci_write_config_word(dev, 0x4A, udma_timing);
794
795 if (isich) {
796 /* Select a 33/66/100Mhz clock */
797 pci_read_config_word(dev, 0x54, &ideconf);
798 ideconf &= ~(0x1001 << devid);
799 ideconf |= u_clock << devid;
800 /* For ICH or later we should set bit 10 for better
801 performance (WR_PingPong_En) */
802 pci_write_config_word(dev, 0x54, ideconf);
803 }
804 } else {
805 /*
806 * MWDMA is driven by the PIO timings. We must also enable
807 * IORDY unconditionally along with TIME1. PPE has already
808 * been set when the PIO timing was set.
809 */
810 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
811 unsigned int control;
812 u8 slave_data;
813 const unsigned int needed_pio[3] = {
814 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
815 };
816 int pio = needed_pio[mwdma] - XFER_PIO_0;
817
818 control = 3; /* IORDY|TIME1 */
819
820 /* If the drive MWDMA is faster than it can do PIO then
821 we must force PIO into PIO0 */
822
823 if (adev->pio_mode < needed_pio[mwdma])
824 /* Enable DMA timing only */
825 control |= 8; /* PIO cycles in PIO0 */
826
827 if (adev->devno) { /* Slave */
828 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
829 master_data |= control << 4;
830 pci_read_config_byte(dev, 0x44, &slave_data);
831 slave_data &= (ap->port_no ? 0x0f : 0xf0);
832 /* Load the matching timing */
833 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
834 pci_write_config_byte(dev, 0x44, slave_data);
835 } else { /* Master */
836 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
837 and master timing bits */
838 master_data |= control;
839 master_data |=
840 (timings[pio][0] << 12) |
841 (timings[pio][1] << 8);
842 }
843
844 if (ap->udma_mask) {
845 udma_enable &= ~(1 << devid);
846 pci_write_config_word(dev, master_port, master_data);
847 }
848 }
849 /* Don't scribble on 0x48 if the controller does not support UDMA */
850 if (ap->udma_mask)
851 pci_write_config_byte(dev, 0x48, udma_enable);
852 }
853
854 /**
855 * piix_set_dmamode - Initialize host controller PATA DMA timings
856 * @ap: Port whose timings we are configuring
857 * @adev: um
858 *
859 * Set MW/UDMA mode for device, in host controller PCI config space.
860 *
861 * LOCKING:
862 * None (inherited from caller).
863 */
864
865 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
866 {
867 do_pata_set_dmamode(ap, adev, 0);
868 }
869
870 /**
871 * ich_set_dmamode - Initialize host controller PATA DMA timings
872 * @ap: Port whose timings we are configuring
873 * @adev: um
874 *
875 * Set MW/UDMA mode for device, in host controller PCI config space.
876 *
877 * LOCKING:
878 * None (inherited from caller).
879 */
880
881 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
882 {
883 do_pata_set_dmamode(ap, adev, 1);
884 }
885
886 /*
887 * Serial ATA Index/Data Pair Superset Registers access
888 *
889 * Beginning from ICH8, there's a sane way to access SCRs using index
890 * and data register pair located at BAR5. This creates an
891 * interesting problem of mapping two SCRs to one port.
892 *
893 * Although they have separate SCRs, the master and slave aren't
894 * independent enough to be treated as separate links - e.g. softreset
895 * resets both. Also, there's no protocol defined for hard resetting
896 * singled device sharing the virtual port (no defined way to acquire
897 * device signature). This is worked around by merging the SCR values
898 * into one sensible value and requesting follow-up SRST after
899 * hardreset.
900 *
901 * SCR merging is perfomed in nibbles which is the unit contents in
902 * SCRs are organized. If two values are equal, the value is used.
903 * When they differ, merge table which lists precedence of possible
904 * values is consulted and the first match or the last entry when
905 * nothing matches is used. When there's no merge table for the
906 * specific nibble, value from the first port is used.
907 */
908 static const int piix_sidx_map[] = {
909 [SCR_STATUS] = 0,
910 [SCR_ERROR] = 2,
911 [SCR_CONTROL] = 1,
912 };
913
914 static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg)
915 {
916 struct ata_port *ap = dev->link->ap;
917 struct piix_host_priv *hpriv = ap->host->private_data;
918
919 iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg],
920 hpriv->sidpr + PIIX_SIDPR_IDX);
921 }
922
923 static int piix_sidpr_read(struct ata_device *dev, unsigned int reg)
924 {
925 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
926
927 piix_sidpr_sel(dev, reg);
928 return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
929 }
930
931 static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val)
932 {
933 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
934
935 piix_sidpr_sel(dev, reg);
936 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
937 }
938
939 static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl)
940 {
941 u32 val = 0;
942 int i, mi;
943
944 for (i = 0, mi = 0; i < 32 / 4; i++) {
945 u8 c0 = (val0 >> (i * 4)) & 0xf;
946 u8 c1 = (val1 >> (i * 4)) & 0xf;
947 u8 merged = c0;
948 const int *cur;
949
950 /* if no merge preference, assume the first value */
951 cur = merge_tbl[mi];
952 if (!cur)
953 goto done;
954 mi++;
955
956 /* if two values equal, use it */
957 if (c0 == c1)
958 goto done;
959
960 /* choose the first match or the last from the merge table */
961 while (*cur != -1) {
962 if (c0 == *cur || c1 == *cur)
963 break;
964 cur++;
965 }
966 if (*cur == -1)
967 cur--;
968 merged = *cur;
969 done:
970 val |= merged << (i * 4);
971 }
972
973 return val;
974 }
975
976 static int piix_sidpr_scr_read(struct ata_link *link,
977 unsigned int reg, u32 *val)
978 {
979 struct ata_port *ap = link->ap;
980 const int * const sstatus_merge_tbl[] = {
981 /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 },
982 /* SPD */ (const int []){ 2, 1, 0, -1 },
983 /* IPM */ (const int []){ 6, 2, 1, 0, -1 },
984 NULL,
985 };
986 const int * const scontrol_merge_tbl[] = {
987 /* DET */ (const int []){ 1, 0, 4, 0, -1 },
988 /* SPD */ (const int []){ 0, 2, 1, 0, -1 },
989 /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 },
990 NULL,
991 };
992 u32 v0, v1;
993
994 if (reg >= ARRAY_SIZE(piix_sidx_map))
995 return -EINVAL;
996
997 if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) {
998 *val = piix_sidpr_read(&ap->link.device[0], reg);
999 return 0;
1000 }
1001
1002 v0 = piix_sidpr_read(&ap->link.device[0], reg);
1003 v1 = piix_sidpr_read(&ap->link.device[1], reg);
1004
1005 switch (reg) {
1006 case SCR_STATUS:
1007 *val = piix_merge_scr(v0, v1, sstatus_merge_tbl);
1008 break;
1009 case SCR_ERROR:
1010 *val = v0 | v1;
1011 break;
1012 case SCR_CONTROL:
1013 *val = piix_merge_scr(v0, v1, scontrol_merge_tbl);
1014 break;
1015 }
1016
1017 return 0;
1018 }
1019
1020 static int piix_sidpr_scr_write(struct ata_link *link,
1021 unsigned int reg, u32 val)
1022 {
1023 struct ata_port *ap = link->ap;
1024
1025 if (reg >= ARRAY_SIZE(piix_sidx_map))
1026 return -EINVAL;
1027
1028 piix_sidpr_write(&ap->link.device[0], reg, val);
1029
1030 if (ap->flags & ATA_FLAG_SLAVE_POSS)
1031 piix_sidpr_write(&ap->link.device[1], reg, val);
1032
1033 return 0;
1034 }
1035
1036 #ifdef CONFIG_PM
1037 static int piix_broken_suspend(void)
1038 {
1039 static const struct dmi_system_id sysids[] = {
1040 {
1041 .ident = "TECRA M3",
1042 .matches = {
1043 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1044 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1045 },
1046 },
1047 {
1048 .ident = "TECRA M3",
1049 .matches = {
1050 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1051 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1052 },
1053 },
1054 {
1055 .ident = "TECRA M4",
1056 .matches = {
1057 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1058 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1059 },
1060 },
1061 {
1062 .ident = "TECRA M4",
1063 .matches = {
1064 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1065 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1066 },
1067 },
1068 {
1069 .ident = "TECRA M5",
1070 .matches = {
1071 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1072 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1073 },
1074 },
1075 {
1076 .ident = "TECRA M6",
1077 .matches = {
1078 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1079 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1080 },
1081 },
1082 {
1083 .ident = "TECRA M7",
1084 .matches = {
1085 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1086 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1087 },
1088 },
1089 {
1090 .ident = "TECRA A8",
1091 .matches = {
1092 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1093 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1094 },
1095 },
1096 {
1097 .ident = "Satellite R20",
1098 .matches = {
1099 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1100 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1101 },
1102 },
1103 {
1104 .ident = "Satellite R25",
1105 .matches = {
1106 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1107 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1108 },
1109 },
1110 {
1111 .ident = "Satellite U200",
1112 .matches = {
1113 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1114 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1115 },
1116 },
1117 {
1118 .ident = "Satellite U200",
1119 .matches = {
1120 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1121 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1122 },
1123 },
1124 {
1125 .ident = "Satellite Pro U200",
1126 .matches = {
1127 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1128 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1129 },
1130 },
1131 {
1132 .ident = "Satellite U205",
1133 .matches = {
1134 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1135 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1136 },
1137 },
1138 {
1139 .ident = "SATELLITE U205",
1140 .matches = {
1141 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1142 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1143 },
1144 },
1145 {
1146 .ident = "Portege M500",
1147 .matches = {
1148 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1149 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1150 },
1151 },
1152
1153 { } /* terminate list */
1154 };
1155 static const char *oemstrs[] = {
1156 "Tecra M3,",
1157 };
1158 int i;
1159
1160 if (dmi_check_system(sysids))
1161 return 1;
1162
1163 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1164 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1165 return 1;
1166
1167 return 0;
1168 }
1169
1170 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1171 {
1172 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1173 unsigned long flags;
1174 int rc = 0;
1175
1176 rc = ata_host_suspend(host, mesg);
1177 if (rc)
1178 return rc;
1179
1180 /* Some braindamaged ACPI suspend implementations expect the
1181 * controller to be awake on entry; otherwise, it burns cpu
1182 * cycles and power trying to do something to the sleeping
1183 * beauty.
1184 */
1185 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1186 pci_save_state(pdev);
1187
1188 /* mark its power state as "unknown", since we don't
1189 * know if e.g. the BIOS will change its device state
1190 * when we suspend.
1191 */
1192 if (pdev->current_state == PCI_D0)
1193 pdev->current_state = PCI_UNKNOWN;
1194
1195 /* tell resume that it's waking up from broken suspend */
1196 spin_lock_irqsave(&host->lock, flags);
1197 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1198 spin_unlock_irqrestore(&host->lock, flags);
1199 } else
1200 ata_pci_device_do_suspend(pdev, mesg);
1201
1202 return 0;
1203 }
1204
1205 static int piix_pci_device_resume(struct pci_dev *pdev)
1206 {
1207 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1208 unsigned long flags;
1209 int rc;
1210
1211 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1212 spin_lock_irqsave(&host->lock, flags);
1213 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1214 spin_unlock_irqrestore(&host->lock, flags);
1215
1216 pci_set_power_state(pdev, PCI_D0);
1217 pci_restore_state(pdev);
1218
1219 /* PCI device wasn't disabled during suspend. Use
1220 * pci_reenable_device() to avoid affecting the enable
1221 * count.
1222 */
1223 rc = pci_reenable_device(pdev);
1224 if (rc)
1225 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1226 "device after resume (%d)\n", rc);
1227 } else
1228 rc = ata_pci_device_do_resume(pdev);
1229
1230 if (rc == 0)
1231 ata_host_resume(host);
1232
1233 return rc;
1234 }
1235 #endif
1236
1237 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1238 {
1239 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1240 }
1241
1242 #define AHCI_PCI_BAR 5
1243 #define AHCI_GLOBAL_CTL 0x04
1244 #define AHCI_ENABLE (1 << 31)
1245 static int piix_disable_ahci(struct pci_dev *pdev)
1246 {
1247 void __iomem *mmio;
1248 u32 tmp;
1249 int rc = 0;
1250
1251 /* BUG: pci_enable_device has not yet been called. This
1252 * works because this device is usually set up by BIOS.
1253 */
1254
1255 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1256 !pci_resource_len(pdev, AHCI_PCI_BAR))
1257 return 0;
1258
1259 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1260 if (!mmio)
1261 return -ENOMEM;
1262
1263 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1264 if (tmp & AHCI_ENABLE) {
1265 tmp &= ~AHCI_ENABLE;
1266 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1267
1268 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1269 if (tmp & AHCI_ENABLE)
1270 rc = -EIO;
1271 }
1272
1273 pci_iounmap(pdev, mmio);
1274 return rc;
1275 }
1276
1277 /**
1278 * piix_check_450nx_errata - Check for problem 450NX setup
1279 * @ata_dev: the PCI device to check
1280 *
1281 * Check for the present of 450NX errata #19 and errata #25. If
1282 * they are found return an error code so we can turn off DMA
1283 */
1284
1285 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1286 {
1287 struct pci_dev *pdev = NULL;
1288 u16 cfg;
1289 int no_piix_dma = 0;
1290
1291 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1292 /* Look for 450NX PXB. Check for problem configurations
1293 A PCI quirk checks bit 6 already */
1294 pci_read_config_word(pdev, 0x41, &cfg);
1295 /* Only on the original revision: IDE DMA can hang */
1296 if (pdev->revision == 0x00)
1297 no_piix_dma = 1;
1298 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1299 else if (cfg & (1<<14) && pdev->revision < 5)
1300 no_piix_dma = 2;
1301 }
1302 if (no_piix_dma)
1303 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1304 if (no_piix_dma == 2)
1305 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1306 return no_piix_dma;
1307 }
1308
1309 static void __devinit piix_init_pcs(struct ata_host *host,
1310 const struct piix_map_db *map_db)
1311 {
1312 struct pci_dev *pdev = to_pci_dev(host->dev);
1313 u16 pcs, new_pcs;
1314
1315 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1316
1317 new_pcs = pcs | map_db->port_enable;
1318
1319 if (new_pcs != pcs) {
1320 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1321 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1322 msleep(150);
1323 }
1324 }
1325
1326 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1327 struct ata_port_info *pinfo,
1328 const struct piix_map_db *map_db)
1329 {
1330 const int *map;
1331 int i, invalid_map = 0;
1332 u8 map_value;
1333
1334 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1335
1336 map = map_db->map[map_value & map_db->mask];
1337
1338 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1339 for (i = 0; i < 4; i++) {
1340 switch (map[i]) {
1341 case RV:
1342 invalid_map = 1;
1343 printk(" XX");
1344 break;
1345
1346 case NA:
1347 printk(" --");
1348 break;
1349
1350 case IDE:
1351 WARN_ON((i & 1) || map[i + 1] != IDE);
1352 pinfo[i / 2] = piix_port_info[ich_pata_100];
1353 i++;
1354 printk(" IDE IDE");
1355 break;
1356
1357 default:
1358 printk(" P%d", map[i]);
1359 if (i & 1)
1360 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1361 break;
1362 }
1363 }
1364 printk(" ]\n");
1365
1366 if (invalid_map)
1367 dev_printk(KERN_ERR, &pdev->dev,
1368 "invalid MAP value %u\n", map_value);
1369
1370 return map;
1371 }
1372
1373 static void __devinit piix_init_sidpr(struct ata_host *host)
1374 {
1375 struct pci_dev *pdev = to_pci_dev(host->dev);
1376 struct piix_host_priv *hpriv = host->private_data;
1377 struct ata_device *dev0 = &host->ports[0]->link.device[0];
1378 u32 scontrol;
1379 int i;
1380
1381 /* check for availability */
1382 for (i = 0; i < 4; i++)
1383 if (hpriv->map[i] == IDE)
1384 return;
1385
1386 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1387 return;
1388
1389 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1390 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1391 return;
1392
1393 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1394 return;
1395
1396 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1397
1398 /* SCR access via SIDPR doesn't work on some configurations.
1399 * Give it a test drive by inhibiting power save modes which
1400 * we'll do anyway.
1401 */
1402 scontrol = piix_sidpr_read(dev0, SCR_CONTROL);
1403
1404 /* if IPM is already 3, SCR access is probably working. Don't
1405 * un-inhibit power save modes as BIOS might have inhibited
1406 * them for a reason.
1407 */
1408 if ((scontrol & 0xf00) != 0x300) {
1409 scontrol |= 0x300;
1410 piix_sidpr_write(dev0, SCR_CONTROL, scontrol);
1411 scontrol = piix_sidpr_read(dev0, SCR_CONTROL);
1412
1413 if ((scontrol & 0xf00) != 0x300) {
1414 dev_printk(KERN_INFO, host->dev, "SCR access via "
1415 "SIDPR is available but doesn't work\n");
1416 return;
1417 }
1418 }
1419
1420 host->ports[0]->ops = &piix_sidpr_sata_ops;
1421 host->ports[1]->ops = &piix_sidpr_sata_ops;
1422 }
1423
1424 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1425 {
1426 static const struct dmi_system_id sysids[] = {
1427 {
1428 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1429 * isn't used to boot the system which
1430 * disables the channel.
1431 */
1432 .ident = "M570U",
1433 .matches = {
1434 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1435 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1436 },
1437 },
1438
1439 { } /* terminate list */
1440 };
1441 u32 iocfg;
1442
1443 if (!dmi_check_system(sysids))
1444 return;
1445
1446 /* The datasheet says that bit 18 is NOOP but certain systems
1447 * seem to use it to disable a channel. Clear the bit on the
1448 * affected systems.
1449 */
1450 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1451 if (iocfg & (1 << 18)) {
1452 dev_printk(KERN_INFO, &pdev->dev,
1453 "applying IOCFG bit18 quirk\n");
1454 iocfg &= ~(1 << 18);
1455 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1456 }
1457 }
1458
1459 /**
1460 * piix_init_one - Register PIIX ATA PCI device with kernel services
1461 * @pdev: PCI device to register
1462 * @ent: Entry in piix_pci_tbl matching with @pdev
1463 *
1464 * Called from kernel PCI layer. We probe for combined mode (sigh),
1465 * and then hand over control to libata, for it to do the rest.
1466 *
1467 * LOCKING:
1468 * Inherited from PCI layer (may sleep).
1469 *
1470 * RETURNS:
1471 * Zero on success, or -ERRNO value.
1472 */
1473
1474 static int __devinit piix_init_one(struct pci_dev *pdev,
1475 const struct pci_device_id *ent)
1476 {
1477 static int printed_version;
1478 struct device *dev = &pdev->dev;
1479 struct ata_port_info port_info[2];
1480 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1481 unsigned long port_flags;
1482 struct ata_host *host;
1483 struct piix_host_priv *hpriv;
1484 int rc;
1485
1486 if (!printed_version++)
1487 dev_printk(KERN_DEBUG, &pdev->dev,
1488 "version " DRV_VERSION "\n");
1489
1490 /* no hotplugging support (FIXME) */
1491 if (!in_module_init)
1492 return -ENODEV;
1493
1494 port_info[0] = piix_port_info[ent->driver_data];
1495 port_info[1] = piix_port_info[ent->driver_data];
1496
1497 port_flags = port_info[0].flags;
1498
1499 /* enable device and prepare host */
1500 rc = pcim_enable_device(pdev);
1501 if (rc)
1502 return rc;
1503
1504 /* ICH6R may be driven by either ata_piix or ahci driver
1505 * regardless of BIOS configuration. Make sure AHCI mode is
1506 * off.
1507 */
1508 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1509 rc = piix_disable_ahci(pdev);
1510 if (rc)
1511 return rc;
1512 }
1513
1514 /* SATA map init can change port_info, do it before prepping host */
1515 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1516 if (!hpriv)
1517 return -ENOMEM;
1518
1519 if (port_flags & ATA_FLAG_SATA)
1520 hpriv->map = piix_init_sata_map(pdev, port_info,
1521 piix_map_db_table[ent->driver_data]);
1522
1523 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
1524 if (rc)
1525 return rc;
1526 host->private_data = hpriv;
1527
1528 /* initialize controller */
1529 if (port_flags & ATA_FLAG_SATA) {
1530 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1531 piix_init_sidpr(host);
1532 }
1533
1534 /* apply IOCFG bit18 quirk */
1535 piix_iocfg_bit18_quirk(pdev);
1536
1537 /* On ICH5, some BIOSen disable the interrupt using the
1538 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1539 * On ICH6, this bit has the same effect, but only when
1540 * MSI is disabled (and it is disabled, as we don't use
1541 * message-signalled interrupts currently).
1542 */
1543 if (port_flags & PIIX_FLAG_CHECKINTR)
1544 pci_intx(pdev, 1);
1545
1546 if (piix_check_450nx_errata(pdev)) {
1547 /* This writes into the master table but it does not
1548 really matter for this errata as we will apply it to
1549 all the PIIX devices on the board */
1550 host->ports[0]->mwdma_mask = 0;
1551 host->ports[0]->udma_mask = 0;
1552 host->ports[1]->mwdma_mask = 0;
1553 host->ports[1]->udma_mask = 0;
1554 }
1555
1556 pci_set_master(pdev);
1557 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht);
1558 }
1559
1560 static int __init piix_init(void)
1561 {
1562 int rc;
1563
1564 DPRINTK("pci_register_driver\n");
1565 rc = pci_register_driver(&piix_pci_driver);
1566 if (rc)
1567 return rc;
1568
1569 in_module_init = 0;
1570
1571 DPRINTK("done\n");
1572 return 0;
1573 }
1574
1575 static void __exit piix_exit(void)
1576 {
1577 pci_unregister_driver(&piix_pci_driver);
1578 }
1579
1580 module_init(piix_init);
1581 module_exit(piix_exit);
Linux kernel - Deliverables
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