projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
more trivial signedness fixes in drivers
[deliverable/linux.git] / drivers / ata / ata_piix.c
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
95
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
98
99 enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
103 PIIX_SCC = 0x0A, /* sub-class code register */
104
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108
109 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
110 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
111
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121 /* controller IDs */
122 piix_pata_33 = 0, /* PIIX4 at 33Mhz */
123 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
124 ich_pata_66 = 2, /* ICH up to 66 Mhz */
125 ich_pata_100 = 3, /* ICH up to UDMA 100 */
126 ich5_sata = 5,
127 ich6_sata = 6,
128 ich6_sata_ahci = 7,
129 ich6m_sata_ahci = 8,
130 ich8_sata_ahci = 9,
131 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
132 tolapai_sata_ahci = 11,
133
134 /* constants for mapping table */
135 P0 = 0, /* port 0 */
136 P1 = 1, /* port 1 */
137 P2 = 2, /* port 2 */
138 P3 = 3, /* port 3 */
139 IDE = -1, /* IDE */
140 NA = -2, /* not avaliable */
141 RV = -3, /* reserved */
142
143 PIIX_AHCI_DEVICE = 6,
144
145 /* host->flags bits */
146 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
147 };
148
149 struct piix_map_db {
150 const u32 mask;
151 const u16 port_enable;
152 const int map[][4];
153 };
154
155 struct piix_host_priv {
156 const int *map;
157 };
158
159 static int piix_init_one (struct pci_dev *pdev,
160 const struct pci_device_id *ent);
161 static void piix_pata_error_handler(struct ata_port *ap);
162 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
163 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
164 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
165 static int ich_pata_cable_detect(struct ata_port *ap);
166 #ifdef CONFIG_PM
167 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
168 static int piix_pci_device_resume(struct pci_dev *pdev);
169 #endif
170
171 static unsigned int in_module_init = 1;
172
173 static const struct pci_device_id piix_pci_tbl[] = {
174 /* Intel PIIX3 for the 430HX etc */
175 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
176 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
177 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
178 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
179 /* Intel PIIX4 */
180 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
181 /* Intel PIIX4 */
182 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
183 /* Intel PIIX */
184 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
185 /* Intel ICH (i810, i815, i840) UDMA 66*/
186 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
187 /* Intel ICH0 : UDMA 33*/
188 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
189 /* Intel ICH2M */
190 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
192 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 /* Intel ICH3M */
194 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
195 /* Intel ICH3 (E7500/1) UDMA 100 */
196 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
197 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
198 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 /* Intel ICH5 */
201 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
202 /* C-ICH (i810E2) */
203 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
204 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
205 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* ICH6 (and 6) (i915) UDMA 100 */
207 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* ICH7/7-R (i945, i975) UDMA 100*/
209 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
211 /* ICH8 Mobile PATA Controller */
212 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213
214 /* NOTE: The following PCI ids must be kept in sync with the
215 * list in drivers/pci/quirks.c.
216 */
217
218 /* 82801EB (ICH5) */
219 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
220 /* 82801EB (ICH5) */
221 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
222 /* 6300ESB (ICH5 variant with broken PCS present bits) */
223 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
224 /* 6300ESB pretending RAID */
225 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
226 /* 82801FB/FW (ICH6/ICH6W) */
227 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
228 /* 82801FR/FRW (ICH6R/ICH6RW) */
229 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
230 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
231 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
232 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
233 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
234 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
235 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
236 /* Enterprise Southbridge 2 (631xESB/632xESB) */
237 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
238 /* SATA Controller 1 IDE (ICH8) */
239 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
240 /* SATA Controller 2 IDE (ICH8) */
241 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
242 /* Mobile SATA Controller IDE (ICH8M) */
243 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
244 /* SATA Controller IDE (ICH9) */
245 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
246 /* SATA Controller IDE (ICH9) */
247 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
248 /* SATA Controller IDE (ICH9) */
249 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
250 /* SATA Controller IDE (ICH9M) */
251 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
252 /* SATA Controller IDE (ICH9M) */
253 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
254 /* SATA Controller IDE (ICH9M) */
255 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
256 /* SATA Controller IDE (Tolapai) */
257 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
258
259 { } /* terminate list */
260 };
261
262 static struct pci_driver piix_pci_driver = {
263 .name = DRV_NAME,
264 .id_table = piix_pci_tbl,
265 .probe = piix_init_one,
266 .remove = ata_pci_remove_one,
267 #ifdef CONFIG_PM
268 .suspend = piix_pci_device_suspend,
269 .resume = piix_pci_device_resume,
270 #endif
271 };
272
273 static struct scsi_host_template piix_sht = {
274 .module = THIS_MODULE,
275 .name = DRV_NAME,
276 .ioctl = ata_scsi_ioctl,
277 .queuecommand = ata_scsi_queuecmd,
278 .can_queue = ATA_DEF_QUEUE,
279 .this_id = ATA_SHT_THIS_ID,
280 .sg_tablesize = LIBATA_MAX_PRD,
281 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
282 .emulated = ATA_SHT_EMULATED,
283 .use_clustering = ATA_SHT_USE_CLUSTERING,
284 .proc_name = DRV_NAME,
285 .dma_boundary = ATA_DMA_BOUNDARY,
286 .slave_configure = ata_scsi_slave_config,
287 .slave_destroy = ata_scsi_slave_destroy,
288 .bios_param = ata_std_bios_param,
289 };
290
291 static const struct ata_port_operations piix_pata_ops = {
292 .set_piomode = piix_set_piomode,
293 .set_dmamode = piix_set_dmamode,
294 .mode_filter = ata_pci_default_filter,
295
296 .tf_load = ata_tf_load,
297 .tf_read = ata_tf_read,
298 .check_status = ata_check_status,
299 .exec_command = ata_exec_command,
300 .dev_select = ata_std_dev_select,
301
302 .bmdma_setup = ata_bmdma_setup,
303 .bmdma_start = ata_bmdma_start,
304 .bmdma_stop = ata_bmdma_stop,
305 .bmdma_status = ata_bmdma_status,
306 .qc_prep = ata_qc_prep,
307 .qc_issue = ata_qc_issue_prot,
308 .data_xfer = ata_data_xfer,
309
310 .freeze = ata_bmdma_freeze,
311 .thaw = ata_bmdma_thaw,
312 .error_handler = piix_pata_error_handler,
313 .post_internal_cmd = ata_bmdma_post_internal_cmd,
314 .cable_detect = ata_cable_40wire,
315
316 .irq_handler = ata_interrupt,
317 .irq_clear = ata_bmdma_irq_clear,
318 .irq_on = ata_irq_on,
319
320 .port_start = ata_port_start,
321 };
322
323 static const struct ata_port_operations ich_pata_ops = {
324 .set_piomode = piix_set_piomode,
325 .set_dmamode = ich_set_dmamode,
326 .mode_filter = ata_pci_default_filter,
327
328 .tf_load = ata_tf_load,
329 .tf_read = ata_tf_read,
330 .check_status = ata_check_status,
331 .exec_command = ata_exec_command,
332 .dev_select = ata_std_dev_select,
333
334 .bmdma_setup = ata_bmdma_setup,
335 .bmdma_start = ata_bmdma_start,
336 .bmdma_stop = ata_bmdma_stop,
337 .bmdma_status = ata_bmdma_status,
338 .qc_prep = ata_qc_prep,
339 .qc_issue = ata_qc_issue_prot,
340 .data_xfer = ata_data_xfer,
341
342 .freeze = ata_bmdma_freeze,
343 .thaw = ata_bmdma_thaw,
344 .error_handler = piix_pata_error_handler,
345 .post_internal_cmd = ata_bmdma_post_internal_cmd,
346 .cable_detect = ich_pata_cable_detect,
347
348 .irq_handler = ata_interrupt,
349 .irq_clear = ata_bmdma_irq_clear,
350 .irq_on = ata_irq_on,
351
352 .port_start = ata_port_start,
353 };
354
355 static const struct ata_port_operations piix_sata_ops = {
356 .tf_load = ata_tf_load,
357 .tf_read = ata_tf_read,
358 .check_status = ata_check_status,
359 .exec_command = ata_exec_command,
360 .dev_select = ata_std_dev_select,
361
362 .bmdma_setup = ata_bmdma_setup,
363 .bmdma_start = ata_bmdma_start,
364 .bmdma_stop = ata_bmdma_stop,
365 .bmdma_status = ata_bmdma_status,
366 .qc_prep = ata_qc_prep,
367 .qc_issue = ata_qc_issue_prot,
368 .data_xfer = ata_data_xfer,
369
370 .freeze = ata_bmdma_freeze,
371 .thaw = ata_bmdma_thaw,
372 .error_handler = ata_bmdma_error_handler,
373 .post_internal_cmd = ata_bmdma_post_internal_cmd,
374
375 .irq_handler = ata_interrupt,
376 .irq_clear = ata_bmdma_irq_clear,
377 .irq_on = ata_irq_on,
378
379 .port_start = ata_port_start,
380 };
381
382 static const struct piix_map_db ich5_map_db = {
383 .mask = 0x7,
384 .port_enable = 0x3,
385 .map = {
386 /* PM PS SM SS MAP */
387 { P0, NA, P1, NA }, /* 000b */
388 { P1, NA, P0, NA }, /* 001b */
389 { RV, RV, RV, RV },
390 { RV, RV, RV, RV },
391 { P0, P1, IDE, IDE }, /* 100b */
392 { P1, P0, IDE, IDE }, /* 101b */
393 { IDE, IDE, P0, P1 }, /* 110b */
394 { IDE, IDE, P1, P0 }, /* 111b */
395 },
396 };
397
398 static const struct piix_map_db ich6_map_db = {
399 .mask = 0x3,
400 .port_enable = 0xf,
401 .map = {
402 /* PM PS SM SS MAP */
403 { P0, P2, P1, P3 }, /* 00b */
404 { IDE, IDE, P1, P3 }, /* 01b */
405 { P0, P2, IDE, IDE }, /* 10b */
406 { RV, RV, RV, RV },
407 },
408 };
409
410 static const struct piix_map_db ich6m_map_db = {
411 .mask = 0x3,
412 .port_enable = 0x5,
413
414 /* Map 01b isn't specified in the doc but some notebooks use
415 * it anyway. MAP 01b have been spotted on both ICH6M and
416 * ICH7M.
417 */
418 .map = {
419 /* PM PS SM SS MAP */
420 { P0, P2, NA, NA }, /* 00b */
421 { IDE, IDE, P1, P3 }, /* 01b */
422 { P0, P2, IDE, IDE }, /* 10b */
423 { RV, RV, RV, RV },
424 },
425 };
426
427 static const struct piix_map_db ich8_map_db = {
428 .mask = 0x3,
429 .port_enable = 0x3,
430 .map = {
431 /* PM PS SM SS MAP */
432 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
433 { RV, RV, RV, RV },
434 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
435 { RV, RV, RV, RV },
436 },
437 };
438
439 static const struct piix_map_db tolapai_map_db = {
440 .mask = 0x3,
441 .port_enable = 0x3,
442 .map = {
443 /* PM PS SM SS MAP */
444 { P0, NA, P1, NA }, /* 00b */
445 { RV, RV, RV, RV }, /* 01b */
446 { RV, RV, RV, RV }, /* 10b */
447 { RV, RV, RV, RV },
448 },
449 };
450
451 static const struct piix_map_db *piix_map_db_table[] = {
452 [ich5_sata] = &ich5_map_db,
453 [ich6_sata] = &ich6_map_db,
454 [ich6_sata_ahci] = &ich6_map_db,
455 [ich6m_sata_ahci] = &ich6m_map_db,
456 [ich8_sata_ahci] = &ich8_map_db,
457 [tolapai_sata_ahci] = &tolapai_map_db,
458 };
459
460 static struct ata_port_info piix_port_info[] = {
461 [piix_pata_33] = /* PIIX4 at 33MHz */
462 {
463 .sht = &piix_sht,
464 .flags = PIIX_PATA_FLAGS,
465 .pio_mask = 0x1f, /* pio0-4 */
466 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
467 .udma_mask = ATA_UDMA_MASK_40C,
468 .port_ops = &piix_pata_ops,
469 },
470
471 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
472 {
473 .sht = &piix_sht,
474 .flags = PIIX_PATA_FLAGS,
475 .pio_mask = 0x1f, /* pio 0-4 */
476 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
477 .udma_mask = ATA_UDMA2, /* UDMA33 */
478 .port_ops = &ich_pata_ops,
479 },
480
481 [ich_pata_66] = /* ICH controllers up to 66MHz */
482 {
483 .sht = &piix_sht,
484 .flags = PIIX_PATA_FLAGS,
485 .pio_mask = 0x1f, /* pio 0-4 */
486 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
487 .udma_mask = ATA_UDMA4,
488 .port_ops = &ich_pata_ops,
489 },
490
491 [ich_pata_100] =
492 {
493 .sht = &piix_sht,
494 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
495 .pio_mask = 0x1f, /* pio0-4 */
496 .mwdma_mask = 0x06, /* mwdma1-2 */
497 .udma_mask = ATA_UDMA5, /* udma0-5 */
498 .port_ops = &ich_pata_ops,
499 },
500
501 [ich5_sata] =
502 {
503 .sht = &piix_sht,
504 .flags = PIIX_SATA_FLAGS,
505 .pio_mask = 0x1f, /* pio0-4 */
506 .mwdma_mask = 0x07, /* mwdma0-2 */
507 .udma_mask = ATA_UDMA6,
508 .port_ops = &piix_sata_ops,
509 },
510
511 [ich6_sata] =
512 {
513 .sht = &piix_sht,
514 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
515 .pio_mask = 0x1f, /* pio0-4 */
516 .mwdma_mask = 0x07, /* mwdma0-2 */
517 .udma_mask = ATA_UDMA6,
518 .port_ops = &piix_sata_ops,
519 },
520
521 [ich6_sata_ahci] =
522 {
523 .sht = &piix_sht,
524 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
525 PIIX_FLAG_AHCI,
526 .pio_mask = 0x1f, /* pio0-4 */
527 .mwdma_mask = 0x07, /* mwdma0-2 */
528 .udma_mask = ATA_UDMA6,
529 .port_ops = &piix_sata_ops,
530 },
531
532 [ich6m_sata_ahci] =
533 {
534 .sht = &piix_sht,
535 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
536 PIIX_FLAG_AHCI,
537 .pio_mask = 0x1f, /* pio0-4 */
538 .mwdma_mask = 0x07, /* mwdma0-2 */
539 .udma_mask = ATA_UDMA6,
540 .port_ops = &piix_sata_ops,
541 },
542
543 [ich8_sata_ahci] =
544 {
545 .sht = &piix_sht,
546 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
547 PIIX_FLAG_AHCI,
548 .pio_mask = 0x1f, /* pio0-4 */
549 .mwdma_mask = 0x07, /* mwdma0-2 */
550 .udma_mask = ATA_UDMA6,
551 .port_ops = &piix_sata_ops,
552 },
553
554 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
555 {
556 .sht = &piix_sht,
557 .flags = PIIX_PATA_FLAGS,
558 .pio_mask = 0x1f, /* pio0-4 */
559 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
560 .port_ops = &piix_pata_ops,
561 },
562
563 [tolapai_sata_ahci] =
564 {
565 .sht = &piix_sht,
566 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
567 PIIX_FLAG_AHCI,
568 .pio_mask = 0x1f, /* pio0-4 */
569 .mwdma_mask = 0x07, /* mwdma0-2 */
570 .udma_mask = ATA_UDMA6,
571 .port_ops = &piix_sata_ops,
572 },
573 };
574
575 static struct pci_bits piix_enable_bits[] = {
576 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
577 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
578 };
579
580 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
581 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
582 MODULE_LICENSE("GPL");
583 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
584 MODULE_VERSION(DRV_VERSION);
585
586 struct ich_laptop {
587 u16 device;
588 u16 subvendor;
589 u16 subdevice;
590 };
591
592 /*
593 * List of laptops that use short cables rather than 80 wire
594 */
595
596 static const struct ich_laptop ich_laptop[] = {
597 /* devid, subvendor, subdev */
598 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
599 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
600 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
601 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
602 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
603 /* end marker */
604 { 0, }
605 };
606
607 /**
608 * ich_pata_cable_detect - Probe host controller cable detect info
609 * @ap: Port for which cable detect info is desired
610 *
611 * Read 80c cable indicator from ATA PCI device's PCI config
612 * register. This register is normally set by firmware (BIOS).
613 *
614 * LOCKING:
615 * None (inherited from caller).
616 */
617
618 static int ich_pata_cable_detect(struct ata_port *ap)
619 {
620 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
621 const struct ich_laptop *lap = &ich_laptop[0];
622 u8 tmp, mask;
623
624 /* Check for specials - Acer Aspire 5602WLMi */
625 while (lap->device) {
626 if (lap->device == pdev->device &&
627 lap->subvendor == pdev->subsystem_vendor &&
628 lap->subdevice == pdev->subsystem_device) {
629 return ATA_CBL_PATA40_SHORT;
630 }
631 lap++;
632 }
633
634 /* check BIOS cable detect results */
635 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
636 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
637 if ((tmp & mask) == 0)
638 return ATA_CBL_PATA40;
639 return ATA_CBL_PATA80;
640 }
641
642 /**
643 * piix_pata_prereset - prereset for PATA host controller
644 * @link: Target link
645 * @deadline: deadline jiffies for the operation
646 *
647 * LOCKING:
648 * None (inherited from caller).
649 */
650 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
651 {
652 struct ata_port *ap = link->ap;
653 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
654
655 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
656 return -ENOENT;
657 return ata_std_prereset(link, deadline);
658 }
659
660 static void piix_pata_error_handler(struct ata_port *ap)
661 {
662 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
663 ata_std_postreset);
664 }
665
666 /**
667 * piix_set_piomode - Initialize host controller PATA PIO timings
668 * @ap: Port whose timings we are configuring
669 * @adev: um
670 *
671 * Set PIO mode for device, in host controller PCI config space.
672 *
673 * LOCKING:
674 * None (inherited from caller).
675 */
676
677 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
678 {
679 unsigned int pio = adev->pio_mode - XFER_PIO_0;
680 struct pci_dev *dev = to_pci_dev(ap->host->dev);
681 unsigned int is_slave = (adev->devno != 0);
682 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
683 unsigned int slave_port = 0x44;
684 u16 master_data;
685 u8 slave_data;
686 u8 udma_enable;
687 int control = 0;
688
689 /*
690 * See Intel Document 298600-004 for the timing programing rules
691 * for ICH controllers.
692 */
693
694 static const /* ISP RTC */
695 u8 timings[][2] = { { 0, 0 },
696 { 0, 0 },
697 { 1, 0 },
698 { 2, 1 },
699 { 2, 3 }, };
700
701 if (pio >= 2)
702 control |= 1; /* TIME1 enable */
703 if (ata_pio_need_iordy(adev))
704 control |= 2; /* IE enable */
705
706 /* Intel specifies that the PPE functionality is for disk only */
707 if (adev->class == ATA_DEV_ATA)
708 control |= 4; /* PPE enable */
709
710 /* PIO configuration clears DTE unconditionally. It will be
711 * programmed in set_dmamode which is guaranteed to be called
712 * after set_piomode if any DMA mode is available.
713 */
714 pci_read_config_word(dev, master_port, &master_data);
715 if (is_slave) {
716 /* clear TIME1|IE1|PPE1|DTE1 */
717 master_data &= 0xff0f;
718 /* Enable SITRE (seperate slave timing register) */
719 master_data |= 0x4000;
720 /* enable PPE1, IE1 and TIME1 as needed */
721 master_data |= (control << 4);
722 pci_read_config_byte(dev, slave_port, &slave_data);
723 slave_data &= (ap->port_no ? 0x0f : 0xf0);
724 /* Load the timing nibble for this slave */
725 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
726 << (ap->port_no ? 4 : 0);
727 } else {
728 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
729 master_data &= 0xccf0;
730 /* Enable PPE, IE and TIME as appropriate */
731 master_data |= control;
732 /* load ISP and RCT */
733 master_data |=
734 (timings[pio][0] << 12) |
735 (timings[pio][1] << 8);
736 }
737 pci_write_config_word(dev, master_port, master_data);
738 if (is_slave)
739 pci_write_config_byte(dev, slave_port, slave_data);
740
741 /* Ensure the UDMA bit is off - it will be turned back on if
742 UDMA is selected */
743
744 if (ap->udma_mask) {
745 pci_read_config_byte(dev, 0x48, &udma_enable);
746 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
747 pci_write_config_byte(dev, 0x48, udma_enable);
748 }
749 }
750
751 /**
752 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
753 * @ap: Port whose timings we are configuring
754 * @adev: Drive in question
755 * @udma: udma mode, 0 - 6
756 * @isich: set if the chip is an ICH device
757 *
758 * Set UDMA mode for device, in host controller PCI config space.
759 *
760 * LOCKING:
761 * None (inherited from caller).
762 */
763
764 static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
765 {
766 struct pci_dev *dev = to_pci_dev(ap->host->dev);
767 u8 master_port = ap->port_no ? 0x42 : 0x40;
768 u16 master_data;
769 u8 speed = adev->dma_mode;
770 int devid = adev->devno + 2 * ap->port_no;
771 u8 udma_enable = 0;
772
773 static const /* ISP RTC */
774 u8 timings[][2] = { { 0, 0 },
775 { 0, 0 },
776 { 1, 0 },
777 { 2, 1 },
778 { 2, 3 }, };
779
780 pci_read_config_word(dev, master_port, &master_data);
781 if (ap->udma_mask)
782 pci_read_config_byte(dev, 0x48, &udma_enable);
783
784 if (speed >= XFER_UDMA_0) {
785 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
786 u16 udma_timing;
787 u16 ideconf;
788 int u_clock, u_speed;
789
790 /*
791 * UDMA is handled by a combination of clock switching and
792 * selection of dividers
793 *
794 * Handy rule: Odd modes are UDMATIMx 01, even are 02
795 * except UDMA0 which is 00
796 */
797 u_speed = min(2 - (udma & 1), udma);
798 if (udma == 5)
799 u_clock = 0x1000; /* 100Mhz */
800 else if (udma > 2)
801 u_clock = 1; /* 66Mhz */
802 else
803 u_clock = 0; /* 33Mhz */
804
805 udma_enable |= (1 << devid);
806
807 /* Load the CT/RP selection */
808 pci_read_config_word(dev, 0x4A, &udma_timing);
809 udma_timing &= ~(3 << (4 * devid));
810 udma_timing |= u_speed << (4 * devid);
811 pci_write_config_word(dev, 0x4A, udma_timing);
812
813 if (isich) {
814 /* Select a 33/66/100Mhz clock */
815 pci_read_config_word(dev, 0x54, &ideconf);
816 ideconf &= ~(0x1001 << devid);
817 ideconf |= u_clock << devid;
818 /* For ICH or later we should set bit 10 for better
819 performance (WR_PingPong_En) */
820 pci_write_config_word(dev, 0x54, ideconf);
821 }
822 } else {
823 /*
824 * MWDMA is driven by the PIO timings. We must also enable
825 * IORDY unconditionally along with TIME1. PPE has already
826 * been set when the PIO timing was set.
827 */
828 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
829 unsigned int control;
830 u8 slave_data;
831 const unsigned int needed_pio[3] = {
832 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
833 };
834 int pio = needed_pio[mwdma] - XFER_PIO_0;
835
836 control = 3; /* IORDY|TIME1 */
837
838 /* If the drive MWDMA is faster than it can do PIO then
839 we must force PIO into PIO0 */
840
841 if (adev->pio_mode < needed_pio[mwdma])
842 /* Enable DMA timing only */
843 control |= 8; /* PIO cycles in PIO0 */
844
845 if (adev->devno) { /* Slave */
846 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
847 master_data |= control << 4;
848 pci_read_config_byte(dev, 0x44, &slave_data);
849 slave_data &= (ap->port_no ? 0x0f : 0xf0);
850 /* Load the matching timing */
851 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
852 pci_write_config_byte(dev, 0x44, slave_data);
853 } else { /* Master */
854 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
855 and master timing bits */
856 master_data |= control;
857 master_data |=
858 (timings[pio][0] << 12) |
859 (timings[pio][1] << 8);
860 }
861
862 if (ap->udma_mask) {
863 udma_enable &= ~(1 << devid);
864 pci_write_config_word(dev, master_port, master_data);
865 }
866 }
867 /* Don't scribble on 0x48 if the controller does not support UDMA */
868 if (ap->udma_mask)
869 pci_write_config_byte(dev, 0x48, udma_enable);
870 }
871
872 /**
873 * piix_set_dmamode - Initialize host controller PATA DMA timings
874 * @ap: Port whose timings we are configuring
875 * @adev: um
876 *
877 * Set MW/UDMA mode for device, in host controller PCI config space.
878 *
879 * LOCKING:
880 * None (inherited from caller).
881 */
882
883 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
884 {
885 do_pata_set_dmamode(ap, adev, 0);
886 }
887
888 /**
889 * ich_set_dmamode - Initialize host controller PATA DMA timings
890 * @ap: Port whose timings we are configuring
891 * @adev: um
892 *
893 * Set MW/UDMA mode for device, in host controller PCI config space.
894 *
895 * LOCKING:
896 * None (inherited from caller).
897 */
898
899 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
900 {
901 do_pata_set_dmamode(ap, adev, 1);
902 }
903
904 #ifdef CONFIG_PM
905 static int piix_broken_suspend(void)
906 {
907 static const struct dmi_system_id sysids[] = {
908 {
909 .ident = "TECRA M3",
910 .matches = {
911 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
912 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
913 },
914 },
915 {
916 .ident = "TECRA M5",
917 .matches = {
918 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
919 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
920 },
921 },
922 {
923 .ident = "TECRA M7",
924 .matches = {
925 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
926 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
927 },
928 },
929 {
930 .ident = "Satellite U200",
931 .matches = {
932 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
933 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
934 },
935 },
936 {
937 .ident = "Satellite U205",
938 .matches = {
939 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
940 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
941 },
942 },
943 {
944 .ident = "Portege M500",
945 .matches = {
946 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
947 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
948 },
949 },
950
951 { } /* terminate list */
952 };
953 static const char *oemstrs[] = {
954 "Tecra M3,",
955 };
956 int i;
957
958 if (dmi_check_system(sysids))
959 return 1;
960
961 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
962 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
963 return 1;
964
965 return 0;
966 }
967
968 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
969 {
970 struct ata_host *host = dev_get_drvdata(&pdev->dev);
971 unsigned long flags;
972 int rc = 0;
973
974 rc = ata_host_suspend(host, mesg);
975 if (rc)
976 return rc;
977
978 /* Some braindamaged ACPI suspend implementations expect the
979 * controller to be awake on entry; otherwise, it burns cpu
980 * cycles and power trying to do something to the sleeping
981 * beauty.
982 */
983 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
984 pci_save_state(pdev);
985
986 /* mark its power state as "unknown", since we don't
987 * know if e.g. the BIOS will change its device state
988 * when we suspend.
989 */
990 if (pdev->current_state == PCI_D0)
991 pdev->current_state = PCI_UNKNOWN;
992
993 /* tell resume that it's waking up from broken suspend */
994 spin_lock_irqsave(&host->lock, flags);
995 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
996 spin_unlock_irqrestore(&host->lock, flags);
997 } else
998 ata_pci_device_do_suspend(pdev, mesg);
999
1000 return 0;
1001 }
1002
1003 static int piix_pci_device_resume(struct pci_dev *pdev)
1004 {
1005 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1006 unsigned long flags;
1007 int rc;
1008
1009 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1010 spin_lock_irqsave(&host->lock, flags);
1011 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1012 spin_unlock_irqrestore(&host->lock, flags);
1013
1014 pci_set_power_state(pdev, PCI_D0);
1015 pci_restore_state(pdev);
1016
1017 /* PCI device wasn't disabled during suspend. Use
1018 * pci_reenable_device() to avoid affecting the enable
1019 * count.
1020 */
1021 rc = pci_reenable_device(pdev);
1022 if (rc)
1023 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1024 "device after resume (%d)\n", rc);
1025 } else
1026 rc = ata_pci_device_do_resume(pdev);
1027
1028 if (rc == 0)
1029 ata_host_resume(host);
1030
1031 return rc;
1032 }
1033 #endif
1034
1035 #define AHCI_PCI_BAR 5
1036 #define AHCI_GLOBAL_CTL 0x04
1037 #define AHCI_ENABLE (1 << 31)
1038 static int piix_disable_ahci(struct pci_dev *pdev)
1039 {
1040 void __iomem *mmio;
1041 u32 tmp;
1042 int rc = 0;
1043
1044 /* BUG: pci_enable_device has not yet been called. This
1045 * works because this device is usually set up by BIOS.
1046 */
1047
1048 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1049 !pci_resource_len(pdev, AHCI_PCI_BAR))
1050 return 0;
1051
1052 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1053 if (!mmio)
1054 return -ENOMEM;
1055
1056 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1057 if (tmp & AHCI_ENABLE) {
1058 tmp &= ~AHCI_ENABLE;
1059 writel(tmp, mmio + AHCI_GLOBAL_CTL);
1060
1061 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1062 if (tmp & AHCI_ENABLE)
1063 rc = -EIO;
1064 }
1065
1066 pci_iounmap(pdev, mmio);
1067 return rc;
1068 }
1069
1070 /**
1071 * piix_check_450nx_errata - Check for problem 450NX setup
1072 * @ata_dev: the PCI device to check
1073 *
1074 * Check for the present of 450NX errata #19 and errata #25. If
1075 * they are found return an error code so we can turn off DMA
1076 */
1077
1078 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1079 {
1080 struct pci_dev *pdev = NULL;
1081 u16 cfg;
1082 int no_piix_dma = 0;
1083
1084 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
1085 {
1086 /* Look for 450NX PXB. Check for problem configurations
1087 A PCI quirk checks bit 6 already */
1088 pci_read_config_word(pdev, 0x41, &cfg);
1089 /* Only on the original revision: IDE DMA can hang */
1090 if (pdev->revision == 0x00)
1091 no_piix_dma = 1;
1092 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1093 else if (cfg & (1<<14) && pdev->revision < 5)
1094 no_piix_dma = 2;
1095 }
1096 if (no_piix_dma)
1097 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1098 if (no_piix_dma == 2)
1099 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1100 return no_piix_dma;
1101 }
1102
1103 static void __devinit piix_init_pcs(struct pci_dev *pdev,
1104 struct ata_port_info *pinfo,
1105 const struct piix_map_db *map_db)
1106 {
1107 u16 pcs, new_pcs;
1108
1109 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1110
1111 new_pcs = pcs | map_db->port_enable;
1112
1113 if (new_pcs != pcs) {
1114 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1115 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1116 msleep(150);
1117 }
1118 }
1119
1120 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
1121 struct ata_port_info *pinfo,
1122 const struct piix_map_db *map_db)
1123 {
1124 struct piix_host_priv *hpriv = pinfo[0].private_data;
1125 const int *map;
1126 int i, invalid_map = 0;
1127 u8 map_value;
1128
1129 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1130
1131 map = map_db->map[map_value & map_db->mask];
1132
1133 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1134 for (i = 0; i < 4; i++) {
1135 switch (map[i]) {
1136 case RV:
1137 invalid_map = 1;
1138 printk(" XX");
1139 break;
1140
1141 case NA:
1142 printk(" --");
1143 break;
1144
1145 case IDE:
1146 WARN_ON((i & 1) || map[i + 1] != IDE);
1147 pinfo[i / 2] = piix_port_info[ich_pata_100];
1148 pinfo[i / 2].private_data = hpriv;
1149 i++;
1150 printk(" IDE IDE");
1151 break;
1152
1153 default:
1154 printk(" P%d", map[i]);
1155 if (i & 1)
1156 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1157 break;
1158 }
1159 }
1160 printk(" ]\n");
1161
1162 if (invalid_map)
1163 dev_printk(KERN_ERR, &pdev->dev,
1164 "invalid MAP value %u\n", map_value);
1165
1166 hpriv->map = map;
1167 }
1168
1169 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1170 {
1171 static const struct dmi_system_id sysids[] = {
1172 {
1173 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1174 * isn't used to boot the system which
1175 * disables the channel.
1176 */
1177 .ident = "M570U",
1178 .matches = {
1179 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1180 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1181 },
1182 },
1183
1184 { } /* terminate list */
1185 };
1186 u32 iocfg;
1187
1188 if (!dmi_check_system(sysids))
1189 return;
1190
1191 /* The datasheet says that bit 18 is NOOP but certain systems
1192 * seem to use it to disable a channel. Clear the bit on the
1193 * affected systems.
1194 */
1195 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1196 if (iocfg & (1 << 18)) {
1197 dev_printk(KERN_INFO, &pdev->dev,
1198 "applying IOCFG bit18 quirk\n");
1199 iocfg &= ~(1 << 18);
1200 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1201 }
1202 }
1203
1204 /**
1205 * piix_init_one - Register PIIX ATA PCI device with kernel services
1206 * @pdev: PCI device to register
1207 * @ent: Entry in piix_pci_tbl matching with @pdev
1208 *
1209 * Called from kernel PCI layer. We probe for combined mode (sigh),
1210 * and then hand over control to libata, for it to do the rest.
1211 *
1212 * LOCKING:
1213 * Inherited from PCI layer (may sleep).
1214 *
1215 * RETURNS:
1216 * Zero on success, or -ERRNO value.
1217 */
1218
1219 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1220 {
1221 static int printed_version;
1222 struct device *dev = &pdev->dev;
1223 struct ata_port_info port_info[2];
1224 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1225 struct piix_host_priv *hpriv;
1226 unsigned long port_flags;
1227
1228 if (!printed_version++)
1229 dev_printk(KERN_DEBUG, &pdev->dev,
1230 "version " DRV_VERSION "\n");
1231
1232 /* no hotplugging support (FIXME) */
1233 if (!in_module_init)
1234 return -ENODEV;
1235
1236 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1237 if (!hpriv)
1238 return -ENOMEM;
1239
1240 port_info[0] = piix_port_info[ent->driver_data];
1241 port_info[1] = piix_port_info[ent->driver_data];
1242 port_info[0].private_data = hpriv;
1243 port_info[1].private_data = hpriv;
1244
1245 port_flags = port_info[0].flags;
1246
1247 if (port_flags & PIIX_FLAG_AHCI) {
1248 u8 tmp;
1249 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1250 if (tmp == PIIX_AHCI_DEVICE) {
1251 int rc = piix_disable_ahci(pdev);
1252 if (rc)
1253 return rc;
1254 }
1255 }
1256
1257 /* Initialize SATA map */
1258 if (port_flags & ATA_FLAG_SATA) {
1259 piix_init_sata_map(pdev, port_info,
1260 piix_map_db_table[ent->driver_data]);
1261 piix_init_pcs(pdev, port_info,
1262 piix_map_db_table[ent->driver_data]);
1263 }
1264
1265 /* apply IOCFG bit18 quirk */
1266 piix_iocfg_bit18_quirk(pdev);
1267
1268 /* On ICH5, some BIOSen disable the interrupt using the
1269 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1270 * On ICH6, this bit has the same effect, but only when
1271 * MSI is disabled (and it is disabled, as we don't use
1272 * message-signalled interrupts currently).
1273 */
1274 if (port_flags & PIIX_FLAG_CHECKINTR)
1275 pci_intx(pdev, 1);
1276
1277 if (piix_check_450nx_errata(pdev)) {
1278 /* This writes into the master table but it does not
1279 really matter for this errata as we will apply it to
1280 all the PIIX devices on the board */
1281 port_info[0].mwdma_mask = 0;
1282 port_info[0].udma_mask = 0;
1283 port_info[1].mwdma_mask = 0;
1284 port_info[1].udma_mask = 0;
1285 }
1286 return ata_pci_init_one(pdev, ppi);
1287 }
1288
1289 static int __init piix_init(void)
1290 {
1291 int rc;
1292
1293 DPRINTK("pci_register_driver\n");
1294 rc = pci_register_driver(&piix_pci_driver);
1295 if (rc)
1296 return rc;
1297
1298 in_module_init = 0;
1299
1300 DPRINTK("done\n");
1301 return 0;
1302 }
1303
1304 static void __exit piix_exit(void)
1305 {
1306 pci_unregister_driver(&piix_pci_driver);
1307 }
1308
1309 module_init(piix_init);
1310 module_exit(piix_exit);
Linux kernel - Deliverables
This page took 0.062069 seconds and 5 git commands to generate.