2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
100 PIIX_IOCFG
= 0x54, /* IDE I/O configuration register */
101 ICH5_PMR
= 0x90, /* port mapping register */
102 ICH5_PCS
= 0x92, /* port control and status */
108 PIIX_FLAG_CHECKINTR
= (1 << 28), /* make sure PCI INTx enabled */
109 PIIX_FLAG_SIDPR
= (1 << 29), /* SATA idx/data pair regs */
111 PIIX_PATA_FLAGS
= ATA_FLAG_SLAVE_POSS
,
112 PIIX_SATA_FLAGS
= ATA_FLAG_SATA
| PIIX_FLAG_CHECKINTR
,
114 PIIX_80C_PRI
= (1 << 5) | (1 << 4),
115 PIIX_80C_SEC
= (1 << 7) | (1 << 6),
117 /* constants for mapping table */
123 NA
= -2, /* not avaliable */
124 RV
= -3, /* reserved */
126 PIIX_AHCI_DEVICE
= 6,
128 /* host->flags bits */
129 PIIX_HOST_BROKEN_SUSPEND
= (1 << 24),
132 enum piix_controller_ids
{
134 piix_pata_mwdma
, /* PIIX3 MWDMA only */
135 piix_pata_33
, /* PIIX4 at 33Mhz */
136 ich_pata_33
, /* ICH up to UDMA 33 only */
137 ich_pata_66
, /* ICH up to 66 Mhz */
138 ich_pata_100
, /* ICH up to UDMA 100 */
144 ich8m_apple_sata
, /* locks up on second port enable */
146 piix_pata_vmw
, /* PIIX4 for VMware, spurious DMA_ERR */
151 const u16 port_enable
;
155 struct piix_host_priv
{
160 static int piix_init_one(struct pci_dev
*pdev
,
161 const struct pci_device_id
*ent
);
162 static int piix_pata_prereset(struct ata_link
*link
, unsigned long deadline
);
163 static void piix_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
);
164 static void piix_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
);
165 static void ich_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
);
166 static int ich_pata_cable_detect(struct ata_port
*ap
);
167 static u8
piix_vmw_bmdma_status(struct ata_port
*ap
);
168 static int piix_sidpr_hardreset(struct ata_link
*link
, unsigned int *class,
169 unsigned long deadline
);
170 static int piix_sidpr_scr_read(struct ata_port
*ap
, unsigned int reg
, u32
*val
);
171 static int piix_sidpr_scr_write(struct ata_port
*ap
, unsigned int reg
, u32 val
);
173 static int piix_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
);
174 static int piix_pci_device_resume(struct pci_dev
*pdev
);
177 static unsigned int in_module_init
= 1;
179 static const struct pci_device_id piix_pci_tbl
[] = {
180 /* Intel PIIX3 for the 430HX etc */
181 { 0x8086, 0x7010, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_mwdma
},
183 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw
},
184 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
185 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
186 { 0x8086, 0x7111, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
188 { 0x8086, 0x7199, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
190 { 0x8086, 0x7601, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
192 { 0x8086, 0x84CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
193 /* Intel ICH (i810, i815, i840) UDMA 66*/
194 { 0x8086, 0x2411, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_66
},
195 /* Intel ICH0 : UDMA 33*/
196 { 0x8086, 0x2421, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_33
},
198 { 0x8086, 0x244A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
199 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
200 { 0x8086, 0x244B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
202 { 0x8086, 0x248A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
203 /* Intel ICH3 (E7500/1) UDMA 100 */
204 { 0x8086, 0x248B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
205 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
206 { 0x8086, 0x24CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
207 { 0x8086, 0x24CB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
209 { 0x8086, 0x24DB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
211 { 0x8086, 0x245B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
212 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
213 { 0x8086, 0x25A2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
214 /* ICH6 (and 6) (i915) UDMA 100 */
215 { 0x8086, 0x266F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
216 /* ICH7/7-R (i945, i975) UDMA 100*/
217 { 0x8086, 0x27DF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
218 { 0x8086, 0x269E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
219 /* ICH8 Mobile PATA Controller */
220 { 0x8086, 0x2850, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
222 /* NOTE: The following PCI ids must be kept in sync with the
223 * list in drivers/pci/quirks.c.
227 { 0x8086, 0x24d1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
229 { 0x8086, 0x24df, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
230 /* 6300ESB (ICH5 variant with broken PCS present bits) */
231 { 0x8086, 0x25a3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
232 /* 6300ESB pretending RAID */
233 { 0x8086, 0x25b0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
234 /* 82801FB/FW (ICH6/ICH6W) */
235 { 0x8086, 0x2651, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
236 /* 82801FR/FRW (ICH6R/ICH6RW) */
237 { 0x8086, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
238 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
239 * Attach iff the controller is in IDE mode. */
240 { 0x8086, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
,
241 PCI_CLASS_STORAGE_IDE
<< 8, 0xffff00, ich6m_sata
},
242 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
243 { 0x8086, 0x27c0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
244 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
245 { 0x8086, 0x27c4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6m_sata
},
246 /* Enterprise Southbridge 2 (631xESB/632xESB) */
247 { 0x8086, 0x2680, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
248 /* SATA Controller 1 IDE (ICH8) */
249 { 0x8086, 0x2820, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
250 /* SATA Controller 2 IDE (ICH8) */
251 { 0x8086, 0x2825, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
252 /* Mobile SATA Controller IDE (ICH8M) */
253 { 0x8086, 0x2828, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
254 /* Mobile SATA Controller IDE (ICH8M), Apple */
255 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata
},
256 /* SATA Controller IDE (ICH9) */
257 { 0x8086, 0x2920, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
258 /* SATA Controller IDE (ICH9) */
259 { 0x8086, 0x2921, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
260 /* SATA Controller IDE (ICH9) */
261 { 0x8086, 0x2926, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
262 /* SATA Controller IDE (ICH9M) */
263 { 0x8086, 0x2928, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
264 /* SATA Controller IDE (ICH9M) */
265 { 0x8086, 0x292d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
266 /* SATA Controller IDE (ICH9M) */
267 { 0x8086, 0x292e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
268 /* SATA Controller IDE (Tolapai) */
269 { 0x8086, 0x5028, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, tolapai_sata
},
270 /* SATA Controller IDE (ICH10) */
271 { 0x8086, 0x3a00, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
272 /* SATA Controller IDE (ICH10) */
273 { 0x8086, 0x3a06, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
274 /* SATA Controller IDE (ICH10) */
275 { 0x8086, 0x3a20, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata
},
276 /* SATA Controller IDE (ICH10) */
277 { 0x8086, 0x3a26, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
279 { } /* terminate list */
282 static struct pci_driver piix_pci_driver
= {
284 .id_table
= piix_pci_tbl
,
285 .probe
= piix_init_one
,
286 .remove
= ata_pci_remove_one
,
288 .suspend
= piix_pci_device_suspend
,
289 .resume
= piix_pci_device_resume
,
293 static struct scsi_host_template piix_sht
= {
294 ATA_BMDMA_SHT(DRV_NAME
),
297 static struct ata_port_operations piix_pata_ops
= {
298 .inherits
= &ata_bmdma_port_ops
,
299 .cable_detect
= ata_cable_40wire
,
300 .set_piomode
= piix_set_piomode
,
301 .set_dmamode
= piix_set_dmamode
,
302 .prereset
= piix_pata_prereset
,
305 static struct ata_port_operations piix_vmw_ops
= {
306 .inherits
= &piix_pata_ops
,
307 .bmdma_status
= piix_vmw_bmdma_status
,
310 static struct ata_port_operations ich_pata_ops
= {
311 .inherits
= &piix_pata_ops
,
312 .cable_detect
= ich_pata_cable_detect
,
313 .set_dmamode
= ich_set_dmamode
,
316 static struct ata_port_operations piix_sata_ops
= {
317 .inherits
= &ata_bmdma_port_ops
,
320 static struct ata_port_operations piix_sidpr_sata_ops
= {
321 .inherits
= &piix_sata_ops
,
322 .hardreset
= piix_sidpr_hardreset
,
323 .scr_read
= piix_sidpr_scr_read
,
324 .scr_write
= piix_sidpr_scr_write
,
327 static const struct piix_map_db ich5_map_db
= {
331 /* PM PS SM SS MAP */
332 { P0
, NA
, P1
, NA
}, /* 000b */
333 { P1
, NA
, P0
, NA
}, /* 001b */
336 { P0
, P1
, IDE
, IDE
}, /* 100b */
337 { P1
, P0
, IDE
, IDE
}, /* 101b */
338 { IDE
, IDE
, P0
, P1
}, /* 110b */
339 { IDE
, IDE
, P1
, P0
}, /* 111b */
343 static const struct piix_map_db ich6_map_db
= {
347 /* PM PS SM SS MAP */
348 { P0
, P2
, P1
, P3
}, /* 00b */
349 { IDE
, IDE
, P1
, P3
}, /* 01b */
350 { P0
, P2
, IDE
, IDE
}, /* 10b */
355 static const struct piix_map_db ich6m_map_db
= {
359 /* Map 01b isn't specified in the doc but some notebooks use
360 * it anyway. MAP 01b have been spotted on both ICH6M and
364 /* PM PS SM SS MAP */
365 { P0
, P2
, NA
, NA
}, /* 00b */
366 { IDE
, IDE
, P1
, P3
}, /* 01b */
367 { P0
, P2
, IDE
, IDE
}, /* 10b */
372 static const struct piix_map_db ich8_map_db
= {
376 /* PM PS SM SS MAP */
377 { P0
, P2
, P1
, P3
}, /* 00b (hardwired when in AHCI) */
379 { P0
, P2
, IDE
, IDE
}, /* 10b (IDE mode) */
384 static const struct piix_map_db ich8_2port_map_db
= {
388 /* PM PS SM SS MAP */
389 { P0
, NA
, P1
, NA
}, /* 00b */
390 { RV
, RV
, RV
, RV
}, /* 01b */
391 { RV
, RV
, RV
, RV
}, /* 10b */
396 static const struct piix_map_db ich8m_apple_map_db
= {
400 /* PM PS SM SS MAP */
401 { P0
, NA
, NA
, NA
}, /* 00b */
403 { P0
, P2
, IDE
, IDE
}, /* 10b */
408 static const struct piix_map_db tolapai_map_db
= {
412 /* PM PS SM SS MAP */
413 { P0
, NA
, P1
, NA
}, /* 00b */
414 { RV
, RV
, RV
, RV
}, /* 01b */
415 { RV
, RV
, RV
, RV
}, /* 10b */
420 static const struct piix_map_db
*piix_map_db_table
[] = {
421 [ich5_sata
] = &ich5_map_db
,
422 [ich6_sata
] = &ich6_map_db
,
423 [ich6m_sata
] = &ich6m_map_db
,
424 [ich8_sata
] = &ich8_map_db
,
425 [ich8_2port_sata
] = &ich8_2port_map_db
,
426 [ich8m_apple_sata
] = &ich8m_apple_map_db
,
427 [tolapai_sata
] = &tolapai_map_db
,
430 static struct ata_port_info piix_port_info
[] = {
431 [piix_pata_mwdma
] = /* PIIX3 MWDMA only */
433 .flags
= PIIX_PATA_FLAGS
,
434 .pio_mask
= 0x1f, /* pio0-4 */
435 .mwdma_mask
= 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
436 .port_ops
= &piix_pata_ops
,
439 [piix_pata_33
] = /* PIIX4 at 33MHz */
441 .flags
= PIIX_PATA_FLAGS
,
442 .pio_mask
= 0x1f, /* pio0-4 */
443 .mwdma_mask
= 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
444 .udma_mask
= ATA_UDMA_MASK_40C
,
445 .port_ops
= &piix_pata_ops
,
448 [ich_pata_33
] = /* ICH0 - ICH at 33Mhz*/
450 .flags
= PIIX_PATA_FLAGS
,
451 .pio_mask
= 0x1f, /* pio 0-4 */
452 .mwdma_mask
= 0x06, /* Check: maybe 0x07 */
453 .udma_mask
= ATA_UDMA2
, /* UDMA33 */
454 .port_ops
= &ich_pata_ops
,
457 [ich_pata_66
] = /* ICH controllers up to 66MHz */
459 .flags
= PIIX_PATA_FLAGS
,
460 .pio_mask
= 0x1f, /* pio 0-4 */
461 .mwdma_mask
= 0x06, /* MWDMA0 is broken on chip */
462 .udma_mask
= ATA_UDMA4
,
463 .port_ops
= &ich_pata_ops
,
468 .flags
= PIIX_PATA_FLAGS
| PIIX_FLAG_CHECKINTR
,
469 .pio_mask
= 0x1f, /* pio0-4 */
470 .mwdma_mask
= 0x06, /* mwdma1-2 */
471 .udma_mask
= ATA_UDMA5
, /* udma0-5 */
472 .port_ops
= &ich_pata_ops
,
477 .flags
= PIIX_SATA_FLAGS
,
478 .pio_mask
= 0x1f, /* pio0-4 */
479 .mwdma_mask
= 0x07, /* mwdma0-2 */
480 .udma_mask
= ATA_UDMA6
,
481 .port_ops
= &piix_sata_ops
,
486 .flags
= PIIX_SATA_FLAGS
,
487 .pio_mask
= 0x1f, /* pio0-4 */
488 .mwdma_mask
= 0x07, /* mwdma0-2 */
489 .udma_mask
= ATA_UDMA6
,
490 .port_ops
= &piix_sata_ops
,
495 .flags
= PIIX_SATA_FLAGS
,
496 .pio_mask
= 0x1f, /* pio0-4 */
497 .mwdma_mask
= 0x07, /* mwdma0-2 */
498 .udma_mask
= ATA_UDMA6
,
499 .port_ops
= &piix_sata_ops
,
504 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SIDPR
,
505 .pio_mask
= 0x1f, /* pio0-4 */
506 .mwdma_mask
= 0x07, /* mwdma0-2 */
507 .udma_mask
= ATA_UDMA6
,
508 .port_ops
= &piix_sata_ops
,
513 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SIDPR
,
514 .pio_mask
= 0x1f, /* pio0-4 */
515 .mwdma_mask
= 0x07, /* mwdma0-2 */
516 .udma_mask
= ATA_UDMA6
,
517 .port_ops
= &piix_sata_ops
,
522 .flags
= PIIX_SATA_FLAGS
,
523 .pio_mask
= 0x1f, /* pio0-4 */
524 .mwdma_mask
= 0x07, /* mwdma0-2 */
525 .udma_mask
= ATA_UDMA6
,
526 .port_ops
= &piix_sata_ops
,
531 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SIDPR
,
532 .pio_mask
= 0x1f, /* pio0-4 */
533 .mwdma_mask
= 0x07, /* mwdma0-2 */
534 .udma_mask
= ATA_UDMA6
,
535 .port_ops
= &piix_sata_ops
,
540 .flags
= PIIX_PATA_FLAGS
,
541 .pio_mask
= 0x1f, /* pio0-4 */
542 .mwdma_mask
= 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
543 .udma_mask
= ATA_UDMA_MASK_40C
,
544 .port_ops
= &piix_vmw_ops
,
549 static struct pci_bits piix_enable_bits
[] = {
550 { 0x41U
, 1U, 0x80UL
, 0x80UL
}, /* port 0 */
551 { 0x43U
, 1U, 0x80UL
, 0x80UL
}, /* port 1 */
554 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
555 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
556 MODULE_LICENSE("GPL");
557 MODULE_DEVICE_TABLE(pci
, piix_pci_tbl
);
558 MODULE_VERSION(DRV_VERSION
);
567 * List of laptops that use short cables rather than 80 wire
570 static const struct ich_laptop ich_laptop
[] = {
571 /* devid, subvendor, subdev */
572 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
573 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
574 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
575 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
576 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
577 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
583 * ich_pata_cable_detect - Probe host controller cable detect info
584 * @ap: Port for which cable detect info is desired
586 * Read 80c cable indicator from ATA PCI device's PCI config
587 * register. This register is normally set by firmware (BIOS).
590 * None (inherited from caller).
593 static int ich_pata_cable_detect(struct ata_port
*ap
)
595 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
596 const struct ich_laptop
*lap
= &ich_laptop
[0];
599 /* Check for specials - Acer Aspire 5602WLMi */
600 while (lap
->device
) {
601 if (lap
->device
== pdev
->device
&&
602 lap
->subvendor
== pdev
->subsystem_vendor
&&
603 lap
->subdevice
== pdev
->subsystem_device
)
604 return ATA_CBL_PATA40_SHORT
;
609 /* check BIOS cable detect results */
610 mask
= ap
->port_no
== 0 ? PIIX_80C_PRI
: PIIX_80C_SEC
;
611 pci_read_config_byte(pdev
, PIIX_IOCFG
, &tmp
);
612 if ((tmp
& mask
) == 0)
613 return ATA_CBL_PATA40
;
614 return ATA_CBL_PATA80
;
618 * piix_pata_prereset - prereset for PATA host controller
620 * @deadline: deadline jiffies for the operation
623 * None (inherited from caller).
625 static int piix_pata_prereset(struct ata_link
*link
, unsigned long deadline
)
627 struct ata_port
*ap
= link
->ap
;
628 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
630 if (!pci_test_config_bits(pdev
, &piix_enable_bits
[ap
->port_no
]))
632 return ata_std_prereset(link
, deadline
);
636 * piix_set_piomode - Initialize host controller PATA PIO timings
637 * @ap: Port whose timings we are configuring
640 * Set PIO mode for device, in host controller PCI config space.
643 * None (inherited from caller).
646 static void piix_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
648 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
649 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
650 unsigned int is_slave
= (adev
->devno
!= 0);
651 unsigned int master_port
= ap
->port_no
? 0x42 : 0x40;
652 unsigned int slave_port
= 0x44;
659 * See Intel Document 298600-004 for the timing programing rules
660 * for ICH controllers.
663 static const /* ISP RTC */
664 u8 timings
[][2] = { { 0, 0 },
671 control
|= 1; /* TIME1 enable */
672 if (ata_pio_need_iordy(adev
))
673 control
|= 2; /* IE enable */
675 /* Intel specifies that the PPE functionality is for disk only */
676 if (adev
->class == ATA_DEV_ATA
)
677 control
|= 4; /* PPE enable */
679 /* PIO configuration clears DTE unconditionally. It will be
680 * programmed in set_dmamode which is guaranteed to be called
681 * after set_piomode if any DMA mode is available.
683 pci_read_config_word(dev
, master_port
, &master_data
);
685 /* clear TIME1|IE1|PPE1|DTE1 */
686 master_data
&= 0xff0f;
687 /* Enable SITRE (separate slave timing register) */
688 master_data
|= 0x4000;
689 /* enable PPE1, IE1 and TIME1 as needed */
690 master_data
|= (control
<< 4);
691 pci_read_config_byte(dev
, slave_port
, &slave_data
);
692 slave_data
&= (ap
->port_no
? 0x0f : 0xf0);
693 /* Load the timing nibble for this slave */
694 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1])
695 << (ap
->port_no
? 4 : 0);
697 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
698 master_data
&= 0xccf0;
699 /* Enable PPE, IE and TIME as appropriate */
700 master_data
|= control
;
701 /* load ISP and RCT */
703 (timings
[pio
][0] << 12) |
704 (timings
[pio
][1] << 8);
706 pci_write_config_word(dev
, master_port
, master_data
);
708 pci_write_config_byte(dev
, slave_port
, slave_data
);
710 /* Ensure the UDMA bit is off - it will be turned back on if
714 pci_read_config_byte(dev
, 0x48, &udma_enable
);
715 udma_enable
&= ~(1 << (2 * ap
->port_no
+ adev
->devno
));
716 pci_write_config_byte(dev
, 0x48, udma_enable
);
721 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
722 * @ap: Port whose timings we are configuring
723 * @adev: Drive in question
724 * @udma: udma mode, 0 - 6
725 * @isich: set if the chip is an ICH device
727 * Set UDMA mode for device, in host controller PCI config space.
730 * None (inherited from caller).
733 static void do_pata_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
, int isich
)
735 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
736 u8 master_port
= ap
->port_no
? 0x42 : 0x40;
738 u8 speed
= adev
->dma_mode
;
739 int devid
= adev
->devno
+ 2 * ap
->port_no
;
742 static const /* ISP RTC */
743 u8 timings
[][2] = { { 0, 0 },
749 pci_read_config_word(dev
, master_port
, &master_data
);
751 pci_read_config_byte(dev
, 0x48, &udma_enable
);
753 if (speed
>= XFER_UDMA_0
) {
754 unsigned int udma
= adev
->dma_mode
- XFER_UDMA_0
;
757 int u_clock
, u_speed
;
760 * UDMA is handled by a combination of clock switching and
761 * selection of dividers
763 * Handy rule: Odd modes are UDMATIMx 01, even are 02
764 * except UDMA0 which is 00
766 u_speed
= min(2 - (udma
& 1), udma
);
768 u_clock
= 0x1000; /* 100Mhz */
770 u_clock
= 1; /* 66Mhz */
772 u_clock
= 0; /* 33Mhz */
774 udma_enable
|= (1 << devid
);
776 /* Load the CT/RP selection */
777 pci_read_config_word(dev
, 0x4A, &udma_timing
);
778 udma_timing
&= ~(3 << (4 * devid
));
779 udma_timing
|= u_speed
<< (4 * devid
);
780 pci_write_config_word(dev
, 0x4A, udma_timing
);
783 /* Select a 33/66/100Mhz clock */
784 pci_read_config_word(dev
, 0x54, &ideconf
);
785 ideconf
&= ~(0x1001 << devid
);
786 ideconf
|= u_clock
<< devid
;
787 /* For ICH or later we should set bit 10 for better
788 performance (WR_PingPong_En) */
789 pci_write_config_word(dev
, 0x54, ideconf
);
793 * MWDMA is driven by the PIO timings. We must also enable
794 * IORDY unconditionally along with TIME1. PPE has already
795 * been set when the PIO timing was set.
797 unsigned int mwdma
= adev
->dma_mode
- XFER_MW_DMA_0
;
798 unsigned int control
;
800 const unsigned int needed_pio
[3] = {
801 XFER_PIO_0
, XFER_PIO_3
, XFER_PIO_4
803 int pio
= needed_pio
[mwdma
] - XFER_PIO_0
;
805 control
= 3; /* IORDY|TIME1 */
807 /* If the drive MWDMA is faster than it can do PIO then
808 we must force PIO into PIO0 */
810 if (adev
->pio_mode
< needed_pio
[mwdma
])
811 /* Enable DMA timing only */
812 control
|= 8; /* PIO cycles in PIO0 */
814 if (adev
->devno
) { /* Slave */
815 master_data
&= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
816 master_data
|= control
<< 4;
817 pci_read_config_byte(dev
, 0x44, &slave_data
);
818 slave_data
&= (ap
->port_no
? 0x0f : 0xf0);
819 /* Load the matching timing */
820 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) << (ap
->port_no
? 4 : 0);
821 pci_write_config_byte(dev
, 0x44, slave_data
);
822 } else { /* Master */
823 master_data
&= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
824 and master timing bits */
825 master_data
|= control
;
827 (timings
[pio
][0] << 12) |
828 (timings
[pio
][1] << 8);
832 udma_enable
&= ~(1 << devid
);
833 pci_write_config_word(dev
, master_port
, master_data
);
836 /* Don't scribble on 0x48 if the controller does not support UDMA */
838 pci_write_config_byte(dev
, 0x48, udma_enable
);
842 * piix_set_dmamode - Initialize host controller PATA DMA timings
843 * @ap: Port whose timings we are configuring
846 * Set MW/UDMA mode for device, in host controller PCI config space.
849 * None (inherited from caller).
852 static void piix_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
854 do_pata_set_dmamode(ap
, adev
, 0);
858 * ich_set_dmamode - Initialize host controller PATA DMA timings
859 * @ap: Port whose timings we are configuring
862 * Set MW/UDMA mode for device, in host controller PCI config space.
865 * None (inherited from caller).
868 static void ich_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
870 do_pata_set_dmamode(ap
, adev
, 1);
874 * Serial ATA Index/Data Pair Superset Registers access
876 * Beginning from ICH8, there's a sane way to access SCRs using index
877 * and data register pair located at BAR5. This creates an
878 * interesting problem of mapping two SCRs to one port.
880 * Although they have separate SCRs, the master and slave aren't
881 * independent enough to be treated as separate links - e.g. softreset
882 * resets both. Also, there's no protocol defined for hard resetting
883 * singled device sharing the virtual port (no defined way to acquire
884 * device signature). This is worked around by merging the SCR values
885 * into one sensible value and requesting follow-up SRST after
888 * SCR merging is perfomed in nibbles which is the unit contents in
889 * SCRs are organized. If two values are equal, the value is used.
890 * When they differ, merge table which lists precedence of possible
891 * values is consulted and the first match or the last entry when
892 * nothing matches is used. When there's no merge table for the
893 * specific nibble, value from the first port is used.
895 static const int piix_sidx_map
[] = {
901 static void piix_sidpr_sel(struct ata_device
*dev
, unsigned int reg
)
903 struct ata_port
*ap
= dev
->link
->ap
;
904 struct piix_host_priv
*hpriv
= ap
->host
->private_data
;
906 iowrite32(((ap
->port_no
* 2 + dev
->devno
) << 8) | piix_sidx_map
[reg
],
907 hpriv
->sidpr
+ PIIX_SIDPR_IDX
);
910 static int piix_sidpr_read(struct ata_device
*dev
, unsigned int reg
)
912 struct piix_host_priv
*hpriv
= dev
->link
->ap
->host
->private_data
;
914 piix_sidpr_sel(dev
, reg
);
915 return ioread32(hpriv
->sidpr
+ PIIX_SIDPR_DATA
);
918 static void piix_sidpr_write(struct ata_device
*dev
, unsigned int reg
, u32 val
)
920 struct piix_host_priv
*hpriv
= dev
->link
->ap
->host
->private_data
;
922 piix_sidpr_sel(dev
, reg
);
923 iowrite32(val
, hpriv
->sidpr
+ PIIX_SIDPR_DATA
);
926 static u32
piix_merge_scr(u32 val0
, u32 val1
, const int * const *merge_tbl
)
931 for (i
= 0, mi
= 0; i
< 32 / 4; i
++) {
932 u8 c0
= (val0
>> (i
* 4)) & 0xf;
933 u8 c1
= (val1
>> (i
* 4)) & 0xf;
937 /* if no merge preference, assume the first value */
943 /* if two values equal, use it */
947 /* choose the first match or the last from the merge table */
949 if (c0
== *cur
|| c1
== *cur
)
957 val
|= merged
<< (i
* 4);
963 static int piix_sidpr_scr_read(struct ata_port
*ap
, unsigned int reg
, u32
*val
)
965 const int * const sstatus_merge_tbl
[] = {
966 /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 },
967 /* SPD */ (const int []){ 2, 1, 0, -1 },
968 /* IPM */ (const int []){ 6, 2, 1, 0, -1 },
971 const int * const scontrol_merge_tbl
[] = {
972 /* DET */ (const int []){ 1, 0, 4, 0, -1 },
973 /* SPD */ (const int []){ 0, 2, 1, 0, -1 },
974 /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 },
979 if (reg
>= ARRAY_SIZE(piix_sidx_map
))
982 if (!(ap
->flags
& ATA_FLAG_SLAVE_POSS
)) {
983 *val
= piix_sidpr_read(&ap
->link
.device
[0], reg
);
987 v0
= piix_sidpr_read(&ap
->link
.device
[0], reg
);
988 v1
= piix_sidpr_read(&ap
->link
.device
[1], reg
);
992 *val
= piix_merge_scr(v0
, v1
, sstatus_merge_tbl
);
998 *val
= piix_merge_scr(v0
, v1
, scontrol_merge_tbl
);
1005 static int piix_sidpr_scr_write(struct ata_port
*ap
, unsigned int reg
, u32 val
)
1007 if (reg
>= ARRAY_SIZE(piix_sidx_map
))
1010 piix_sidpr_write(&ap
->link
.device
[0], reg
, val
);
1012 if (ap
->flags
& ATA_FLAG_SLAVE_POSS
)
1013 piix_sidpr_write(&ap
->link
.device
[1], reg
, val
);
1018 static int piix_sidpr_hardreset(struct ata_link
*link
, unsigned int *class,
1019 unsigned long deadline
)
1021 const unsigned long *timing
= sata_ehc_deb_timing(&link
->eh_context
);
1025 rc
= sata_link_hardreset(link
, timing
, deadline
);
1027 ata_link_printk(link
, KERN_ERR
,
1028 "COMRESET failed (errno=%d)\n", rc
);
1032 /* TODO: phy layer with polling, timeouts, etc. */
1033 if (ata_link_offline(link
)) {
1034 *class = ATA_DEV_NONE
;
1042 static int piix_broken_suspend(void)
1044 static const struct dmi_system_id sysids
[] = {
1046 .ident
= "TECRA M3",
1048 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1049 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M3"),
1053 .ident
= "TECRA M3",
1055 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1056 DMI_MATCH(DMI_PRODUCT_NAME
, "Tecra M3"),
1060 .ident
= "TECRA M4",
1062 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1063 DMI_MATCH(DMI_PRODUCT_NAME
, "Tecra M4"),
1067 .ident
= "TECRA M5",
1069 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1070 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M5"),
1074 .ident
= "TECRA M6",
1076 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1077 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M6"),
1081 .ident
= "TECRA M7",
1083 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1084 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M7"),
1088 .ident
= "TECRA A8",
1090 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1091 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA A8"),
1095 .ident
= "Satellite R20",
1097 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1098 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite R20"),
1102 .ident
= "Satellite R25",
1104 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1105 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite R25"),
1109 .ident
= "Satellite U200",
1111 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1112 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite U200"),
1116 .ident
= "Satellite U200",
1118 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1119 DMI_MATCH(DMI_PRODUCT_NAME
, "SATELLITE U200"),
1123 .ident
= "Satellite Pro U200",
1125 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1126 DMI_MATCH(DMI_PRODUCT_NAME
, "SATELLITE PRO U200"),
1130 .ident
= "Satellite U205",
1132 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1133 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite U205"),
1137 .ident
= "SATELLITE U205",
1139 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1140 DMI_MATCH(DMI_PRODUCT_NAME
, "SATELLITE U205"),
1144 .ident
= "Portege M500",
1146 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1147 DMI_MATCH(DMI_PRODUCT_NAME
, "PORTEGE M500"),
1151 { } /* terminate list */
1153 static const char *oemstrs
[] = {
1158 if (dmi_check_system(sysids
))
1161 for (i
= 0; i
< ARRAY_SIZE(oemstrs
); i
++)
1162 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING
, oemstrs
[i
], NULL
))
1168 static int piix_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1170 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1171 unsigned long flags
;
1174 rc
= ata_host_suspend(host
, mesg
);
1178 /* Some braindamaged ACPI suspend implementations expect the
1179 * controller to be awake on entry; otherwise, it burns cpu
1180 * cycles and power trying to do something to the sleeping
1183 if (piix_broken_suspend() && (mesg
.event
& PM_EVENT_SLEEP
)) {
1184 pci_save_state(pdev
);
1186 /* mark its power state as "unknown", since we don't
1187 * know if e.g. the BIOS will change its device state
1190 if (pdev
->current_state
== PCI_D0
)
1191 pdev
->current_state
= PCI_UNKNOWN
;
1193 /* tell resume that it's waking up from broken suspend */
1194 spin_lock_irqsave(&host
->lock
, flags
);
1195 host
->flags
|= PIIX_HOST_BROKEN_SUSPEND
;
1196 spin_unlock_irqrestore(&host
->lock
, flags
);
1198 ata_pci_device_do_suspend(pdev
, mesg
);
1203 static int piix_pci_device_resume(struct pci_dev
*pdev
)
1205 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1206 unsigned long flags
;
1209 if (host
->flags
& PIIX_HOST_BROKEN_SUSPEND
) {
1210 spin_lock_irqsave(&host
->lock
, flags
);
1211 host
->flags
&= ~PIIX_HOST_BROKEN_SUSPEND
;
1212 spin_unlock_irqrestore(&host
->lock
, flags
);
1214 pci_set_power_state(pdev
, PCI_D0
);
1215 pci_restore_state(pdev
);
1217 /* PCI device wasn't disabled during suspend. Use
1218 * pci_reenable_device() to avoid affecting the enable
1221 rc
= pci_reenable_device(pdev
);
1223 dev_printk(KERN_ERR
, &pdev
->dev
, "failed to enable "
1224 "device after resume (%d)\n", rc
);
1226 rc
= ata_pci_device_do_resume(pdev
);
1229 ata_host_resume(host
);
1235 static u8
piix_vmw_bmdma_status(struct ata_port
*ap
)
1237 return ata_bmdma_status(ap
) & ~ATA_DMA_ERR
;
1240 #define AHCI_PCI_BAR 5
1241 #define AHCI_GLOBAL_CTL 0x04
1242 #define AHCI_ENABLE (1 << 31)
1243 static int piix_disable_ahci(struct pci_dev
*pdev
)
1249 /* BUG: pci_enable_device has not yet been called. This
1250 * works because this device is usually set up by BIOS.
1253 if (!pci_resource_start(pdev
, AHCI_PCI_BAR
) ||
1254 !pci_resource_len(pdev
, AHCI_PCI_BAR
))
1257 mmio
= pci_iomap(pdev
, AHCI_PCI_BAR
, 64);
1261 tmp
= ioread32(mmio
+ AHCI_GLOBAL_CTL
);
1262 if (tmp
& AHCI_ENABLE
) {
1263 tmp
&= ~AHCI_ENABLE
;
1264 iowrite32(tmp
, mmio
+ AHCI_GLOBAL_CTL
);
1266 tmp
= ioread32(mmio
+ AHCI_GLOBAL_CTL
);
1267 if (tmp
& AHCI_ENABLE
)
1271 pci_iounmap(pdev
, mmio
);
1276 * piix_check_450nx_errata - Check for problem 450NX setup
1277 * @ata_dev: the PCI device to check
1279 * Check for the present of 450NX errata #19 and errata #25. If
1280 * they are found return an error code so we can turn off DMA
1283 static int __devinit
piix_check_450nx_errata(struct pci_dev
*ata_dev
)
1285 struct pci_dev
*pdev
= NULL
;
1287 int no_piix_dma
= 0;
1289 while ((pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, pdev
)) != NULL
) {
1290 /* Look for 450NX PXB. Check for problem configurations
1291 A PCI quirk checks bit 6 already */
1292 pci_read_config_word(pdev
, 0x41, &cfg
);
1293 /* Only on the original revision: IDE DMA can hang */
1294 if (pdev
->revision
== 0x00)
1296 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1297 else if (cfg
& (1<<14) && pdev
->revision
< 5)
1301 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "450NX errata present, disabling IDE DMA.\n");
1302 if (no_piix_dma
== 2)
1303 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "A BIOS update may resolve this.\n");
1307 static void __devinit
piix_init_pcs(struct ata_host
*host
,
1308 const struct piix_map_db
*map_db
)
1310 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1313 pci_read_config_word(pdev
, ICH5_PCS
, &pcs
);
1315 new_pcs
= pcs
| map_db
->port_enable
;
1317 if (new_pcs
!= pcs
) {
1318 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs
, new_pcs
);
1319 pci_write_config_word(pdev
, ICH5_PCS
, new_pcs
);
1324 static const int *__devinit
piix_init_sata_map(struct pci_dev
*pdev
,
1325 struct ata_port_info
*pinfo
,
1326 const struct piix_map_db
*map_db
)
1329 int i
, invalid_map
= 0;
1332 pci_read_config_byte(pdev
, ICH5_PMR
, &map_value
);
1334 map
= map_db
->map
[map_value
& map_db
->mask
];
1336 dev_printk(KERN_INFO
, &pdev
->dev
, "MAP [");
1337 for (i
= 0; i
< 4; i
++) {
1349 WARN_ON((i
& 1) || map
[i
+ 1] != IDE
);
1350 pinfo
[i
/ 2] = piix_port_info
[ich_pata_100
];
1356 printk(" P%d", map
[i
]);
1358 pinfo
[i
/ 2].flags
|= ATA_FLAG_SLAVE_POSS
;
1365 dev_printk(KERN_ERR
, &pdev
->dev
,
1366 "invalid MAP value %u\n", map_value
);
1371 static void __devinit
piix_init_sidpr(struct ata_host
*host
)
1373 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1374 struct piix_host_priv
*hpriv
= host
->private_data
;
1377 /* check for availability */
1378 for (i
= 0; i
< 4; i
++)
1379 if (hpriv
->map
[i
] == IDE
)
1382 if (!(host
->ports
[0]->flags
& PIIX_FLAG_SIDPR
))
1385 if (pci_resource_start(pdev
, PIIX_SIDPR_BAR
) == 0 ||
1386 pci_resource_len(pdev
, PIIX_SIDPR_BAR
) != PIIX_SIDPR_LEN
)
1389 if (pcim_iomap_regions(pdev
, 1 << PIIX_SIDPR_BAR
, DRV_NAME
))
1392 hpriv
->sidpr
= pcim_iomap_table(pdev
)[PIIX_SIDPR_BAR
];
1393 host
->ports
[0]->ops
= &piix_sidpr_sata_ops
;
1394 host
->ports
[1]->ops
= &piix_sidpr_sata_ops
;
1397 static void piix_iocfg_bit18_quirk(struct pci_dev
*pdev
)
1399 static const struct dmi_system_id sysids
[] = {
1401 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1402 * isn't used to boot the system which
1403 * disables the channel.
1407 DMI_MATCH(DMI_SYS_VENDOR
, "Clevo Co."),
1408 DMI_MATCH(DMI_PRODUCT_NAME
, "M570U"),
1412 { } /* terminate list */
1416 if (!dmi_check_system(sysids
))
1419 /* The datasheet says that bit 18 is NOOP but certain systems
1420 * seem to use it to disable a channel. Clear the bit on the
1423 pci_read_config_dword(pdev
, PIIX_IOCFG
, &iocfg
);
1424 if (iocfg
& (1 << 18)) {
1425 dev_printk(KERN_INFO
, &pdev
->dev
,
1426 "applying IOCFG bit18 quirk\n");
1427 iocfg
&= ~(1 << 18);
1428 pci_write_config_dword(pdev
, PIIX_IOCFG
, iocfg
);
1433 * piix_init_one - Register PIIX ATA PCI device with kernel services
1434 * @pdev: PCI device to register
1435 * @ent: Entry in piix_pci_tbl matching with @pdev
1437 * Called from kernel PCI layer. We probe for combined mode (sigh),
1438 * and then hand over control to libata, for it to do the rest.
1441 * Inherited from PCI layer (may sleep).
1444 * Zero on success, or -ERRNO value.
1447 static int __devinit
piix_init_one(struct pci_dev
*pdev
,
1448 const struct pci_device_id
*ent
)
1450 static int printed_version
;
1451 struct device
*dev
= &pdev
->dev
;
1452 struct ata_port_info port_info
[2];
1453 const struct ata_port_info
*ppi
[] = { &port_info
[0], &port_info
[1] };
1454 unsigned long port_flags
;
1455 struct ata_host
*host
;
1456 struct piix_host_priv
*hpriv
;
1459 if (!printed_version
++)
1460 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1461 "version " DRV_VERSION
"\n");
1463 /* no hotplugging support (FIXME) */
1464 if (!in_module_init
)
1467 port_info
[0] = piix_port_info
[ent
->driver_data
];
1468 port_info
[1] = piix_port_info
[ent
->driver_data
];
1470 port_flags
= port_info
[0].flags
;
1472 /* enable device and prepare host */
1473 rc
= pcim_enable_device(pdev
);
1477 /* ICH6R may be driven by either ata_piix or ahci driver
1478 * regardless of BIOS configuration. Make sure AHCI mode is
1481 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
&& pdev
->device
== 0x2652) {
1482 int rc
= piix_disable_ahci(pdev
);
1487 /* SATA map init can change port_info, do it before prepping host */
1488 hpriv
= devm_kzalloc(dev
, sizeof(*hpriv
), GFP_KERNEL
);
1492 if (port_flags
& ATA_FLAG_SATA
)
1493 hpriv
->map
= piix_init_sata_map(pdev
, port_info
,
1494 piix_map_db_table
[ent
->driver_data
]);
1496 rc
= ata_pci_prepare_sff_host(pdev
, ppi
, &host
);
1499 host
->private_data
= hpriv
;
1501 /* initialize controller */
1502 if (port_flags
& ATA_FLAG_SATA
) {
1503 piix_init_pcs(host
, piix_map_db_table
[ent
->driver_data
]);
1504 piix_init_sidpr(host
);
1507 /* apply IOCFG bit18 quirk */
1508 piix_iocfg_bit18_quirk(pdev
);
1510 /* On ICH5, some BIOSen disable the interrupt using the
1511 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1512 * On ICH6, this bit has the same effect, but only when
1513 * MSI is disabled (and it is disabled, as we don't use
1514 * message-signalled interrupts currently).
1516 if (port_flags
& PIIX_FLAG_CHECKINTR
)
1519 if (piix_check_450nx_errata(pdev
)) {
1520 /* This writes into the master table but it does not
1521 really matter for this errata as we will apply it to
1522 all the PIIX devices on the board */
1523 host
->ports
[0]->mwdma_mask
= 0;
1524 host
->ports
[0]->udma_mask
= 0;
1525 host
->ports
[1]->mwdma_mask
= 0;
1526 host
->ports
[1]->udma_mask
= 0;
1529 pci_set_master(pdev
);
1530 return ata_pci_activate_sff_host(host
, ata_interrupt
, &piix_sht
);
1533 static int __init
piix_init(void)
1537 DPRINTK("pci_register_driver\n");
1538 rc
= pci_register_driver(&piix_pci_driver
);
1548 static void __exit
piix_exit(void)
1550 pci_unregister_driver(&piix_pci_driver
);
1553 module_init(piix_init
);
1554 module_exit(piix_exit
);