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[libata] Bump driver versions
[deliverable/linux.git] / drivers / ata / ata_piix.c
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
95
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
98
99 enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
103 PIIX_SCC = 0x0A, /* sub-class code register */
104
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108
109 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
110 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
111
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121 /* controller IDs */
122 piix_pata_33 = 0, /* PIIX4 at 33Mhz */
123 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
124 ich_pata_66 = 2, /* ICH up to 66 Mhz */
125 ich_pata_100 = 3, /* ICH up to UDMA 100 */
126 ich_pata_133 = 4, /* ICH up to UDMA 133 */
127 ich5_sata = 5,
128 ich6_sata = 6,
129 ich6_sata_ahci = 7,
130 ich6m_sata_ahci = 8,
131 ich8_sata_ahci = 9,
132 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
133 tolapai_sata_ahci = 11,
134
135 /* constants for mapping table */
136 P0 = 0, /* port 0 */
137 P1 = 1, /* port 1 */
138 P2 = 2, /* port 2 */
139 P3 = 3, /* port 3 */
140 IDE = -1, /* IDE */
141 NA = -2, /* not avaliable */
142 RV = -3, /* reserved */
143
144 PIIX_AHCI_DEVICE = 6,
145
146 /* host->flags bits */
147 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
148 };
149
150 struct piix_map_db {
151 const u32 mask;
152 const u16 port_enable;
153 const int map[][4];
154 };
155
156 struct piix_host_priv {
157 const int *map;
158 };
159
160 static int piix_init_one (struct pci_dev *pdev,
161 const struct pci_device_id *ent);
162 static void piix_pata_error_handler(struct ata_port *ap);
163 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
164 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
165 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
166 static int ich_pata_cable_detect(struct ata_port *ap);
167 #ifdef CONFIG_PM
168 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
169 static int piix_pci_device_resume(struct pci_dev *pdev);
170 #endif
171
172 static unsigned int in_module_init = 1;
173
174 static const struct pci_device_id piix_pci_tbl[] = {
175 /* Intel PIIX3 for the 430HX etc */
176 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
177 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
178 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
179 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
180 /* Intel PIIX4 */
181 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
182 /* Intel PIIX4 */
183 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
184 /* Intel PIIX */
185 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
186 /* Intel ICH (i810, i815, i840) UDMA 66*/
187 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
188 /* Intel ICH0 : UDMA 33*/
189 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
190 /* Intel ICH2M */
191 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
193 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 /* Intel ICH3M */
195 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
196 /* Intel ICH3 (E7500/1) UDMA 100 */
197 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
198 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
199 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH5 */
202 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
203 /* C-ICH (i810E2) */
204 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
206 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* ICH6 (and 6) (i915) UDMA 100 */
208 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 /* ICH7/7-R (i945, i975) UDMA 100*/
210 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
211 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 /* ICH8 Mobile PATA Controller */
213 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214
215 /* NOTE: The following PCI ids must be kept in sync with the
216 * list in drivers/pci/quirks.c.
217 */
218
219 /* 82801EB (ICH5) */
220 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
221 /* 82801EB (ICH5) */
222 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
223 /* 6300ESB (ICH5 variant with broken PCS present bits) */
224 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
225 /* 6300ESB pretending RAID */
226 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
227 /* 82801FB/FW (ICH6/ICH6W) */
228 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
229 /* 82801FR/FRW (ICH6R/ICH6RW) */
230 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
231 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
232 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
233 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
234 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
235 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
236 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
237 /* Enterprise Southbridge 2 (631xESB/632xESB) */
238 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
239 /* SATA Controller 1 IDE (ICH8) */
240 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
241 /* SATA Controller 2 IDE (ICH8) */
242 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
243 /* Mobile SATA Controller IDE (ICH8M) */
244 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
245 /* SATA Controller IDE (ICH9) */
246 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
247 /* SATA Controller IDE (ICH9) */
248 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
249 /* SATA Controller IDE (ICH9) */
250 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
251 /* SATA Controller IDE (ICH9M) */
252 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
253 /* SATA Controller IDE (ICH9M) */
254 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
255 /* SATA Controller IDE (ICH9M) */
256 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
257 /* SATA Controller IDE (Tolapai) */
258 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
259
260 { } /* terminate list */
261 };
262
263 static struct pci_driver piix_pci_driver = {
264 .name = DRV_NAME,
265 .id_table = piix_pci_tbl,
266 .probe = piix_init_one,
267 .remove = ata_pci_remove_one,
268 #ifdef CONFIG_PM
269 .suspend = piix_pci_device_suspend,
270 .resume = piix_pci_device_resume,
271 #endif
272 };
273
274 static struct scsi_host_template piix_sht = {
275 .module = THIS_MODULE,
276 .name = DRV_NAME,
277 .ioctl = ata_scsi_ioctl,
278 .queuecommand = ata_scsi_queuecmd,
279 .can_queue = ATA_DEF_QUEUE,
280 .this_id = ATA_SHT_THIS_ID,
281 .sg_tablesize = LIBATA_MAX_PRD,
282 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
283 .emulated = ATA_SHT_EMULATED,
284 .use_clustering = ATA_SHT_USE_CLUSTERING,
285 .proc_name = DRV_NAME,
286 .dma_boundary = ATA_DMA_BOUNDARY,
287 .slave_configure = ata_scsi_slave_config,
288 .slave_destroy = ata_scsi_slave_destroy,
289 .bios_param = ata_std_bios_param,
290 };
291
292 static const struct ata_port_operations piix_pata_ops = {
293 .port_disable = ata_port_disable,
294 .set_piomode = piix_set_piomode,
295 .set_dmamode = piix_set_dmamode,
296 .mode_filter = ata_pci_default_filter,
297
298 .tf_load = ata_tf_load,
299 .tf_read = ata_tf_read,
300 .check_status = ata_check_status,
301 .exec_command = ata_exec_command,
302 .dev_select = ata_std_dev_select,
303
304 .bmdma_setup = ata_bmdma_setup,
305 .bmdma_start = ata_bmdma_start,
306 .bmdma_stop = ata_bmdma_stop,
307 .bmdma_status = ata_bmdma_status,
308 .qc_prep = ata_qc_prep,
309 .qc_issue = ata_qc_issue_prot,
310 .data_xfer = ata_data_xfer,
311
312 .freeze = ata_bmdma_freeze,
313 .thaw = ata_bmdma_thaw,
314 .error_handler = piix_pata_error_handler,
315 .post_internal_cmd = ata_bmdma_post_internal_cmd,
316 .cable_detect = ata_cable_40wire,
317
318 .irq_handler = ata_interrupt,
319 .irq_clear = ata_bmdma_irq_clear,
320 .irq_on = ata_irq_on,
321 .irq_ack = ata_irq_ack,
322
323 .port_start = ata_port_start,
324 };
325
326 static const struct ata_port_operations ich_pata_ops = {
327 .port_disable = ata_port_disable,
328 .set_piomode = piix_set_piomode,
329 .set_dmamode = ich_set_dmamode,
330 .mode_filter = ata_pci_default_filter,
331
332 .tf_load = ata_tf_load,
333 .tf_read = ata_tf_read,
334 .check_status = ata_check_status,
335 .exec_command = ata_exec_command,
336 .dev_select = ata_std_dev_select,
337
338 .bmdma_setup = ata_bmdma_setup,
339 .bmdma_start = ata_bmdma_start,
340 .bmdma_stop = ata_bmdma_stop,
341 .bmdma_status = ata_bmdma_status,
342 .qc_prep = ata_qc_prep,
343 .qc_issue = ata_qc_issue_prot,
344 .data_xfer = ata_data_xfer,
345
346 .freeze = ata_bmdma_freeze,
347 .thaw = ata_bmdma_thaw,
348 .error_handler = piix_pata_error_handler,
349 .post_internal_cmd = ata_bmdma_post_internal_cmd,
350 .cable_detect = ich_pata_cable_detect,
351
352 .irq_handler = ata_interrupt,
353 .irq_clear = ata_bmdma_irq_clear,
354 .irq_on = ata_irq_on,
355 .irq_ack = ata_irq_ack,
356
357 .port_start = ata_port_start,
358 };
359
360 static const struct ata_port_operations piix_sata_ops = {
361 .port_disable = ata_port_disable,
362
363 .tf_load = ata_tf_load,
364 .tf_read = ata_tf_read,
365 .check_status = ata_check_status,
366 .exec_command = ata_exec_command,
367 .dev_select = ata_std_dev_select,
368
369 .bmdma_setup = ata_bmdma_setup,
370 .bmdma_start = ata_bmdma_start,
371 .bmdma_stop = ata_bmdma_stop,
372 .bmdma_status = ata_bmdma_status,
373 .qc_prep = ata_qc_prep,
374 .qc_issue = ata_qc_issue_prot,
375 .data_xfer = ata_data_xfer,
376
377 .freeze = ata_bmdma_freeze,
378 .thaw = ata_bmdma_thaw,
379 .error_handler = ata_bmdma_error_handler,
380 .post_internal_cmd = ata_bmdma_post_internal_cmd,
381
382 .irq_handler = ata_interrupt,
383 .irq_clear = ata_bmdma_irq_clear,
384 .irq_on = ata_irq_on,
385 .irq_ack = ata_irq_ack,
386
387 .port_start = ata_port_start,
388 };
389
390 static const struct piix_map_db ich5_map_db = {
391 .mask = 0x7,
392 .port_enable = 0x3,
393 .map = {
394 /* PM PS SM SS MAP */
395 { P0, NA, P1, NA }, /* 000b */
396 { P1, NA, P0, NA }, /* 001b */
397 { RV, RV, RV, RV },
398 { RV, RV, RV, RV },
399 { P0, P1, IDE, IDE }, /* 100b */
400 { P1, P0, IDE, IDE }, /* 101b */
401 { IDE, IDE, P0, P1 }, /* 110b */
402 { IDE, IDE, P1, P0 }, /* 111b */
403 },
404 };
405
406 static const struct piix_map_db ich6_map_db = {
407 .mask = 0x3,
408 .port_enable = 0xf,
409 .map = {
410 /* PM PS SM SS MAP */
411 { P0, P2, P1, P3 }, /* 00b */
412 { IDE, IDE, P1, P3 }, /* 01b */
413 { P0, P2, IDE, IDE }, /* 10b */
414 { RV, RV, RV, RV },
415 },
416 };
417
418 static const struct piix_map_db ich6m_map_db = {
419 .mask = 0x3,
420 .port_enable = 0x5,
421
422 /* Map 01b isn't specified in the doc but some notebooks use
423 * it anyway. MAP 01b have been spotted on both ICH6M and
424 * ICH7M.
425 */
426 .map = {
427 /* PM PS SM SS MAP */
428 { P0, P2, NA, NA }, /* 00b */
429 { IDE, IDE, P1, P3 }, /* 01b */
430 { P0, P2, IDE, IDE }, /* 10b */
431 { RV, RV, RV, RV },
432 },
433 };
434
435 static const struct piix_map_db ich8_map_db = {
436 .mask = 0x3,
437 .port_enable = 0x3,
438 .map = {
439 /* PM PS SM SS MAP */
440 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
441 { RV, RV, RV, RV },
442 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
443 { RV, RV, RV, RV },
444 },
445 };
446
447 static const struct piix_map_db tolapai_map_db = {
448 .mask = 0x3,
449 .port_enable = 0x3,
450 .map = {
451 /* PM PS SM SS MAP */
452 { P0, NA, P1, NA }, /* 00b */
453 { RV, RV, RV, RV }, /* 01b */
454 { RV, RV, RV, RV }, /* 10b */
455 { RV, RV, RV, RV },
456 },
457 };
458
459 static const struct piix_map_db *piix_map_db_table[] = {
460 [ich5_sata] = &ich5_map_db,
461 [ich6_sata] = &ich6_map_db,
462 [ich6_sata_ahci] = &ich6_map_db,
463 [ich6m_sata_ahci] = &ich6m_map_db,
464 [ich8_sata_ahci] = &ich8_map_db,
465 [tolapai_sata_ahci] = &tolapai_map_db,
466 };
467
468 static struct ata_port_info piix_port_info[] = {
469 /* piix_pata_33: 0: PIIX4 at 33MHz */
470 {
471 .sht = &piix_sht,
472 .flags = PIIX_PATA_FLAGS,
473 .pio_mask = 0x1f, /* pio0-4 */
474 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
475 .udma_mask = ATA_UDMA_MASK_40C,
476 .port_ops = &piix_pata_ops,
477 },
478
479 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
480 {
481 .sht = &piix_sht,
482 .flags = PIIX_PATA_FLAGS,
483 .pio_mask = 0x1f, /* pio 0-4 */
484 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
485 .udma_mask = ATA_UDMA2, /* UDMA33 */
486 .port_ops = &ich_pata_ops,
487 },
488 /* ich_pata_66: 2 ICH controllers up to 66MHz */
489 {
490 .sht = &piix_sht,
491 .flags = PIIX_PATA_FLAGS,
492 .pio_mask = 0x1f, /* pio 0-4 */
493 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
494 .udma_mask = ATA_UDMA4,
495 .port_ops = &ich_pata_ops,
496 },
497
498 /* ich_pata_100: 3 */
499 {
500 .sht = &piix_sht,
501 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
502 .pio_mask = 0x1f, /* pio0-4 */
503 .mwdma_mask = 0x06, /* mwdma1-2 */
504 .udma_mask = ATA_UDMA5, /* udma0-5 */
505 .port_ops = &ich_pata_ops,
506 },
507
508 /* ich_pata_133: 4 ICH with full UDMA6 */
509 {
510 .sht = &piix_sht,
511 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
512 .pio_mask = 0x1f, /* pio 0-4 */
513 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
514 .udma_mask = ATA_UDMA6, /* UDMA133 */
515 .port_ops = &ich_pata_ops,
516 },
517
518 /* ich5_sata: 5 */
519 {
520 .sht = &piix_sht,
521 .flags = PIIX_SATA_FLAGS,
522 .pio_mask = 0x1f, /* pio0-4 */
523 .mwdma_mask = 0x07, /* mwdma0-2 */
524 .udma_mask = ATA_UDMA6,
525 .port_ops = &piix_sata_ops,
526 },
527
528 /* ich6_sata: 6 */
529 {
530 .sht = &piix_sht,
531 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
532 .pio_mask = 0x1f, /* pio0-4 */
533 .mwdma_mask = 0x07, /* mwdma0-2 */
534 .udma_mask = ATA_UDMA6,
535 .port_ops = &piix_sata_ops,
536 },
537
538 /* ich6_sata_ahci: 7 */
539 {
540 .sht = &piix_sht,
541 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
542 PIIX_FLAG_AHCI,
543 .pio_mask = 0x1f, /* pio0-4 */
544 .mwdma_mask = 0x07, /* mwdma0-2 */
545 .udma_mask = ATA_UDMA6,
546 .port_ops = &piix_sata_ops,
547 },
548
549 /* ich6m_sata_ahci: 8 */
550 {
551 .sht = &piix_sht,
552 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
553 PIIX_FLAG_AHCI,
554 .pio_mask = 0x1f, /* pio0-4 */
555 .mwdma_mask = 0x07, /* mwdma0-2 */
556 .udma_mask = ATA_UDMA6,
557 .port_ops = &piix_sata_ops,
558 },
559
560 /* ich8_sata_ahci: 9 */
561 {
562 .sht = &piix_sht,
563 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
564 PIIX_FLAG_AHCI,
565 .pio_mask = 0x1f, /* pio0-4 */
566 .mwdma_mask = 0x07, /* mwdma0-2 */
567 .udma_mask = ATA_UDMA6,
568 .port_ops = &piix_sata_ops,
569 },
570
571 /* piix_pata_mwdma: 10: PIIX3 MWDMA only */
572 {
573 .sht = &piix_sht,
574 .flags = PIIX_PATA_FLAGS,
575 .pio_mask = 0x1f, /* pio0-4 */
576 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
577 .port_ops = &piix_pata_ops,
578 },
579
580 /* tolapai_sata_ahci: 11: */
581 {
582 .sht = &piix_sht,
583 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
584 PIIX_FLAG_AHCI,
585 .pio_mask = 0x1f, /* pio0-4 */
586 .mwdma_mask = 0x07, /* mwdma0-2 */
587 .udma_mask = ATA_UDMA6,
588 .port_ops = &piix_sata_ops,
589 },
590 };
591
592 static struct pci_bits piix_enable_bits[] = {
593 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
594 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
595 };
596
597 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
598 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
599 MODULE_LICENSE("GPL");
600 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
601 MODULE_VERSION(DRV_VERSION);
602
603 struct ich_laptop {
604 u16 device;
605 u16 subvendor;
606 u16 subdevice;
607 };
608
609 /*
610 * List of laptops that use short cables rather than 80 wire
611 */
612
613 static const struct ich_laptop ich_laptop[] = {
614 /* devid, subvendor, subdev */
615 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
616 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
617 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
618 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
619 /* end marker */
620 { 0, }
621 };
622
623 /**
624 * ich_pata_cable_detect - Probe host controller cable detect info
625 * @ap: Port for which cable detect info is desired
626 *
627 * Read 80c cable indicator from ATA PCI device's PCI config
628 * register. This register is normally set by firmware (BIOS).
629 *
630 * LOCKING:
631 * None (inherited from caller).
632 */
633
634 static int ich_pata_cable_detect(struct ata_port *ap)
635 {
636 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
637 const struct ich_laptop *lap = &ich_laptop[0];
638 u8 tmp, mask;
639
640 /* Check for specials - Acer Aspire 5602WLMi */
641 while (lap->device) {
642 if (lap->device == pdev->device &&
643 lap->subvendor == pdev->subsystem_vendor &&
644 lap->subdevice == pdev->subsystem_device) {
645 return ATA_CBL_PATA40_SHORT;
646 }
647 lap++;
648 }
649
650 /* check BIOS cable detect results */
651 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
652 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
653 if ((tmp & mask) == 0)
654 return ATA_CBL_PATA40;
655 return ATA_CBL_PATA80;
656 }
657
658 /**
659 * piix_pata_prereset - prereset for PATA host controller
660 * @ap: Target port
661 * @deadline: deadline jiffies for the operation
662 *
663 * LOCKING:
664 * None (inherited from caller).
665 */
666 static int piix_pata_prereset(struct ata_port *ap, unsigned long deadline)
667 {
668 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669
670 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
671 return -ENOENT;
672 return ata_std_prereset(ap, deadline);
673 }
674
675 static void piix_pata_error_handler(struct ata_port *ap)
676 {
677 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
678 ata_std_postreset);
679 }
680
681 /**
682 * piix_set_piomode - Initialize host controller PATA PIO timings
683 * @ap: Port whose timings we are configuring
684 * @adev: um
685 *
686 * Set PIO mode for device, in host controller PCI config space.
687 *
688 * LOCKING:
689 * None (inherited from caller).
690 */
691
692 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
693 {
694 unsigned int pio = adev->pio_mode - XFER_PIO_0;
695 struct pci_dev *dev = to_pci_dev(ap->host->dev);
696 unsigned int is_slave = (adev->devno != 0);
697 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
698 unsigned int slave_port = 0x44;
699 u16 master_data;
700 u8 slave_data;
701 u8 udma_enable;
702 int control = 0;
703
704 /*
705 * See Intel Document 298600-004 for the timing programing rules
706 * for ICH controllers.
707 */
708
709 static const /* ISP RTC */
710 u8 timings[][2] = { { 0, 0 },
711 { 0, 0 },
712 { 1, 0 },
713 { 2, 1 },
714 { 2, 3 }, };
715
716 if (pio >= 2)
717 control |= 1; /* TIME1 enable */
718 if (ata_pio_need_iordy(adev))
719 control |= 2; /* IE enable */
720
721 /* Intel specifies that the PPE functionality is for disk only */
722 if (adev->class == ATA_DEV_ATA)
723 control |= 4; /* PPE enable */
724
725 /* PIO configuration clears DTE unconditionally. It will be
726 * programmed in set_dmamode which is guaranteed to be called
727 * after set_piomode if any DMA mode is available.
728 */
729 pci_read_config_word(dev, master_port, &master_data);
730 if (is_slave) {
731 /* clear TIME1|IE1|PPE1|DTE1 */
732 master_data &= 0xff0f;
733 /* Enable SITRE (seperate slave timing register) */
734 master_data |= 0x4000;
735 /* enable PPE1, IE1 and TIME1 as needed */
736 master_data |= (control << 4);
737 pci_read_config_byte(dev, slave_port, &slave_data);
738 slave_data &= (ap->port_no ? 0x0f : 0xf0);
739 /* Load the timing nibble for this slave */
740 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
741 << (ap->port_no ? 4 : 0);
742 } else {
743 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
744 master_data &= 0xccf0;
745 /* Enable PPE, IE and TIME as appropriate */
746 master_data |= control;
747 /* load ISP and RCT */
748 master_data |=
749 (timings[pio][0] << 12) |
750 (timings[pio][1] << 8);
751 }
752 pci_write_config_word(dev, master_port, master_data);
753 if (is_slave)
754 pci_write_config_byte(dev, slave_port, slave_data);
755
756 /* Ensure the UDMA bit is off - it will be turned back on if
757 UDMA is selected */
758
759 if (ap->udma_mask) {
760 pci_read_config_byte(dev, 0x48, &udma_enable);
761 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
762 pci_write_config_byte(dev, 0x48, udma_enable);
763 }
764 }
765
766 /**
767 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
768 * @ap: Port whose timings we are configuring
769 * @adev: Drive in question
770 * @udma: udma mode, 0 - 6
771 * @isich: set if the chip is an ICH device
772 *
773 * Set UDMA mode for device, in host controller PCI config space.
774 *
775 * LOCKING:
776 * None (inherited from caller).
777 */
778
779 static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
780 {
781 struct pci_dev *dev = to_pci_dev(ap->host->dev);
782 u8 master_port = ap->port_no ? 0x42 : 0x40;
783 u16 master_data;
784 u8 speed = adev->dma_mode;
785 int devid = adev->devno + 2 * ap->port_no;
786 u8 udma_enable = 0;
787
788 static const /* ISP RTC */
789 u8 timings[][2] = { { 0, 0 },
790 { 0, 0 },
791 { 1, 0 },
792 { 2, 1 },
793 { 2, 3 }, };
794
795 pci_read_config_word(dev, master_port, &master_data);
796 if (ap->udma_mask)
797 pci_read_config_byte(dev, 0x48, &udma_enable);
798
799 if (speed >= XFER_UDMA_0) {
800 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
801 u16 udma_timing;
802 u16 ideconf;
803 int u_clock, u_speed;
804
805 /*
806 * UDMA is handled by a combination of clock switching and
807 * selection of dividers
808 *
809 * Handy rule: Odd modes are UDMATIMx 01, even are 02
810 * except UDMA0 which is 00
811 */
812 u_speed = min(2 - (udma & 1), udma);
813 if (udma == 5)
814 u_clock = 0x1000; /* 100Mhz */
815 else if (udma > 2)
816 u_clock = 1; /* 66Mhz */
817 else
818 u_clock = 0; /* 33Mhz */
819
820 udma_enable |= (1 << devid);
821
822 /* Load the CT/RP selection */
823 pci_read_config_word(dev, 0x4A, &udma_timing);
824 udma_timing &= ~(3 << (4 * devid));
825 udma_timing |= u_speed << (4 * devid);
826 pci_write_config_word(dev, 0x4A, udma_timing);
827
828 if (isich) {
829 /* Select a 33/66/100Mhz clock */
830 pci_read_config_word(dev, 0x54, &ideconf);
831 ideconf &= ~(0x1001 << devid);
832 ideconf |= u_clock << devid;
833 /* For ICH or later we should set bit 10 for better
834 performance (WR_PingPong_En) */
835 pci_write_config_word(dev, 0x54, ideconf);
836 }
837 } else {
838 /*
839 * MWDMA is driven by the PIO timings. We must also enable
840 * IORDY unconditionally along with TIME1. PPE has already
841 * been set when the PIO timing was set.
842 */
843 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
844 unsigned int control;
845 u8 slave_data;
846 const unsigned int needed_pio[3] = {
847 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
848 };
849 int pio = needed_pio[mwdma] - XFER_PIO_0;
850
851 control = 3; /* IORDY|TIME1 */
852
853 /* If the drive MWDMA is faster than it can do PIO then
854 we must force PIO into PIO0 */
855
856 if (adev->pio_mode < needed_pio[mwdma])
857 /* Enable DMA timing only */
858 control |= 8; /* PIO cycles in PIO0 */
859
860 if (adev->devno) { /* Slave */
861 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
862 master_data |= control << 4;
863 pci_read_config_byte(dev, 0x44, &slave_data);
864 slave_data &= (ap->port_no ? 0x0f : 0xf0);
865 /* Load the matching timing */
866 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
867 pci_write_config_byte(dev, 0x44, slave_data);
868 } else { /* Master */
869 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
870 and master timing bits */
871 master_data |= control;
872 master_data |=
873 (timings[pio][0] << 12) |
874 (timings[pio][1] << 8);
875 }
876
877 if (ap->udma_mask) {
878 udma_enable &= ~(1 << devid);
879 pci_write_config_word(dev, master_port, master_data);
880 }
881 }
882 /* Don't scribble on 0x48 if the controller does not support UDMA */
883 if (ap->udma_mask)
884 pci_write_config_byte(dev, 0x48, udma_enable);
885 }
886
887 /**
888 * piix_set_dmamode - Initialize host controller PATA DMA timings
889 * @ap: Port whose timings we are configuring
890 * @adev: um
891 *
892 * Set MW/UDMA mode for device, in host controller PCI config space.
893 *
894 * LOCKING:
895 * None (inherited from caller).
896 */
897
898 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
899 {
900 do_pata_set_dmamode(ap, adev, 0);
901 }
902
903 /**
904 * ich_set_dmamode - Initialize host controller PATA DMA timings
905 * @ap: Port whose timings we are configuring
906 * @adev: um
907 *
908 * Set MW/UDMA mode for device, in host controller PCI config space.
909 *
910 * LOCKING:
911 * None (inherited from caller).
912 */
913
914 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
915 {
916 do_pata_set_dmamode(ap, adev, 1);
917 }
918
919 #ifdef CONFIG_PM
920 static int piix_broken_suspend(void)
921 {
922 static struct dmi_system_id sysids[] = {
923 {
924 .ident = "TECRA M5",
925 .matches = {
926 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
927 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
928 },
929 },
930 {
931 .ident = "TECRA M7",
932 .matches = {
933 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
934 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
935 },
936 },
937 {
938 .ident = "Satellite U200",
939 .matches = {
940 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
941 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
942 },
943 },
944 {
945 .ident = "Satellite U205",
946 .matches = {
947 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
948 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
949 },
950 },
951 {
952 .ident = "Portege M500",
953 .matches = {
954 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
955 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
956 },
957 },
958 { }
959 };
960 static const char *oemstrs[] = {
961 "Tecra M3,",
962 };
963 int i;
964
965 if (dmi_check_system(sysids))
966 return 1;
967
968 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
969 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
970 return 1;
971
972 return 0;
973 }
974
975 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
976 {
977 struct ata_host *host = dev_get_drvdata(&pdev->dev);
978 unsigned long flags;
979 int rc = 0;
980
981 rc = ata_host_suspend(host, mesg);
982 if (rc)
983 return rc;
984
985 /* Some braindamaged ACPI suspend implementations expect the
986 * controller to be awake on entry; otherwise, it burns cpu
987 * cycles and power trying to do something to the sleeping
988 * beauty.
989 */
990 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
991 pci_save_state(pdev);
992
993 /* mark its power state as "unknown", since we don't
994 * know if e.g. the BIOS will change its device state
995 * when we suspend.
996 */
997 if (pdev->current_state == PCI_D0)
998 pdev->current_state = PCI_UNKNOWN;
999
1000 /* tell resume that it's waking up from broken suspend */
1001 spin_lock_irqsave(&host->lock, flags);
1002 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1003 spin_unlock_irqrestore(&host->lock, flags);
1004 } else
1005 ata_pci_device_do_suspend(pdev, mesg);
1006
1007 return 0;
1008 }
1009
1010 static int piix_pci_device_resume(struct pci_dev *pdev)
1011 {
1012 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1013 unsigned long flags;
1014 int rc;
1015
1016 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1017 spin_lock_irqsave(&host->lock, flags);
1018 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1019 spin_unlock_irqrestore(&host->lock, flags);
1020
1021 pci_set_power_state(pdev, PCI_D0);
1022 pci_restore_state(pdev);
1023
1024 /* PCI device wasn't disabled during suspend. Use
1025 * pci_reenable_device() to avoid affecting the enable
1026 * count.
1027 */
1028 rc = pci_reenable_device(pdev);
1029 if (rc)
1030 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1031 "device after resume (%d)\n", rc);
1032 } else
1033 rc = ata_pci_device_do_resume(pdev);
1034
1035 if (rc == 0)
1036 ata_host_resume(host);
1037
1038 return rc;
1039 }
1040 #endif
1041
1042 #define AHCI_PCI_BAR 5
1043 #define AHCI_GLOBAL_CTL 0x04
1044 #define AHCI_ENABLE (1 << 31)
1045 static int piix_disable_ahci(struct pci_dev *pdev)
1046 {
1047 void __iomem *mmio;
1048 u32 tmp;
1049 int rc = 0;
1050
1051 /* BUG: pci_enable_device has not yet been called. This
1052 * works because this device is usually set up by BIOS.
1053 */
1054
1055 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1056 !pci_resource_len(pdev, AHCI_PCI_BAR))
1057 return 0;
1058
1059 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1060 if (!mmio)
1061 return -ENOMEM;
1062
1063 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1064 if (tmp & AHCI_ENABLE) {
1065 tmp &= ~AHCI_ENABLE;
1066 writel(tmp, mmio + AHCI_GLOBAL_CTL);
1067
1068 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1069 if (tmp & AHCI_ENABLE)
1070 rc = -EIO;
1071 }
1072
1073 pci_iounmap(pdev, mmio);
1074 return rc;
1075 }
1076
1077 /**
1078 * piix_check_450nx_errata - Check for problem 450NX setup
1079 * @ata_dev: the PCI device to check
1080 *
1081 * Check for the present of 450NX errata #19 and errata #25. If
1082 * they are found return an error code so we can turn off DMA
1083 */
1084
1085 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1086 {
1087 struct pci_dev *pdev = NULL;
1088 u16 cfg;
1089 int no_piix_dma = 0;
1090
1091 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
1092 {
1093 /* Look for 450NX PXB. Check for problem configurations
1094 A PCI quirk checks bit 6 already */
1095 pci_read_config_word(pdev, 0x41, &cfg);
1096 /* Only on the original revision: IDE DMA can hang */
1097 if (pdev->revision == 0x00)
1098 no_piix_dma = 1;
1099 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1100 else if (cfg & (1<<14) && pdev->revision < 5)
1101 no_piix_dma = 2;
1102 }
1103 if (no_piix_dma)
1104 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1105 if (no_piix_dma == 2)
1106 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1107 return no_piix_dma;
1108 }
1109
1110 static void __devinit piix_init_pcs(struct pci_dev *pdev,
1111 struct ata_port_info *pinfo,
1112 const struct piix_map_db *map_db)
1113 {
1114 u16 pcs, new_pcs;
1115
1116 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1117
1118 new_pcs = pcs | map_db->port_enable;
1119
1120 if (new_pcs != pcs) {
1121 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1122 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1123 msleep(150);
1124 }
1125 }
1126
1127 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
1128 struct ata_port_info *pinfo,
1129 const struct piix_map_db *map_db)
1130 {
1131 struct piix_host_priv *hpriv = pinfo[0].private_data;
1132 const unsigned int *map;
1133 int i, invalid_map = 0;
1134 u8 map_value;
1135
1136 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1137
1138 map = map_db->map[map_value & map_db->mask];
1139
1140 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1141 for (i = 0; i < 4; i++) {
1142 switch (map[i]) {
1143 case RV:
1144 invalid_map = 1;
1145 printk(" XX");
1146 break;
1147
1148 case NA:
1149 printk(" --");
1150 break;
1151
1152 case IDE:
1153 WARN_ON((i & 1) || map[i + 1] != IDE);
1154 pinfo[i / 2] = piix_port_info[ich_pata_100];
1155 pinfo[i / 2].private_data = hpriv;
1156 i++;
1157 printk(" IDE IDE");
1158 break;
1159
1160 default:
1161 printk(" P%d", map[i]);
1162 if (i & 1)
1163 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1164 break;
1165 }
1166 }
1167 printk(" ]\n");
1168
1169 if (invalid_map)
1170 dev_printk(KERN_ERR, &pdev->dev,
1171 "invalid MAP value %u\n", map_value);
1172
1173 hpriv->map = map;
1174 }
1175
1176 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1177 {
1178 static struct dmi_system_id sysids[] = {
1179 {
1180 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1181 * isn't used to boot the system which
1182 * disables the channel.
1183 */
1184 .ident = "M570U",
1185 .matches = {
1186 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1187 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1188 },
1189 },
1190 };
1191 u32 iocfg;
1192
1193 if (!dmi_check_system(sysids))
1194 return;
1195
1196 /* The datasheet says that bit 18 is NOOP but certain systems
1197 * seem to use it to disable a channel. Clear the bit on the
1198 * affected systems.
1199 */
1200 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1201 if (iocfg & (1 << 18)) {
1202 dev_printk(KERN_INFO, &pdev->dev,
1203 "applying IOCFG bit18 quirk\n");
1204 iocfg &= ~(1 << 18);
1205 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1206 }
1207 }
1208
1209 /**
1210 * piix_init_one - Register PIIX ATA PCI device with kernel services
1211 * @pdev: PCI device to register
1212 * @ent: Entry in piix_pci_tbl matching with @pdev
1213 *
1214 * Called from kernel PCI layer. We probe for combined mode (sigh),
1215 * and then hand over control to libata, for it to do the rest.
1216 *
1217 * LOCKING:
1218 * Inherited from PCI layer (may sleep).
1219 *
1220 * RETURNS:
1221 * Zero on success, or -ERRNO value.
1222 */
1223
1224 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1225 {
1226 static int printed_version;
1227 struct device *dev = &pdev->dev;
1228 struct ata_port_info port_info[2];
1229 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1230 struct piix_host_priv *hpriv;
1231 unsigned long port_flags;
1232
1233 if (!printed_version++)
1234 dev_printk(KERN_DEBUG, &pdev->dev,
1235 "version " DRV_VERSION "\n");
1236
1237 /* no hotplugging support (FIXME) */
1238 if (!in_module_init)
1239 return -ENODEV;
1240
1241 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1242 if (!hpriv)
1243 return -ENOMEM;
1244
1245 port_info[0] = piix_port_info[ent->driver_data];
1246 port_info[1] = piix_port_info[ent->driver_data];
1247 port_info[0].private_data = hpriv;
1248 port_info[1].private_data = hpriv;
1249
1250 port_flags = port_info[0].flags;
1251
1252 if (port_flags & PIIX_FLAG_AHCI) {
1253 u8 tmp;
1254 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1255 if (tmp == PIIX_AHCI_DEVICE) {
1256 int rc = piix_disable_ahci(pdev);
1257 if (rc)
1258 return rc;
1259 }
1260 }
1261
1262 /* Initialize SATA map */
1263 if (port_flags & ATA_FLAG_SATA) {
1264 piix_init_sata_map(pdev, port_info,
1265 piix_map_db_table[ent->driver_data]);
1266 piix_init_pcs(pdev, port_info,
1267 piix_map_db_table[ent->driver_data]);
1268 }
1269
1270 /* apply IOCFG bit18 quirk */
1271 piix_iocfg_bit18_quirk(pdev);
1272
1273 /* On ICH5, some BIOSen disable the interrupt using the
1274 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1275 * On ICH6, this bit has the same effect, but only when
1276 * MSI is disabled (and it is disabled, as we don't use
1277 * message-signalled interrupts currently).
1278 */
1279 if (port_flags & PIIX_FLAG_CHECKINTR)
1280 pci_intx(pdev, 1);
1281
1282 if (piix_check_450nx_errata(pdev)) {
1283 /* This writes into the master table but it does not
1284 really matter for this errata as we will apply it to
1285 all the PIIX devices on the board */
1286 port_info[0].mwdma_mask = 0;
1287 port_info[0].udma_mask = 0;
1288 port_info[1].mwdma_mask = 0;
1289 port_info[1].udma_mask = 0;
1290 }
1291 return ata_pci_init_one(pdev, ppi);
1292 }
1293
1294 static int __init piix_init(void)
1295 {
1296 int rc;
1297
1298 DPRINTK("pci_register_driver\n");
1299 rc = pci_register_driver(&piix_pci_driver);
1300 if (rc)
1301 return rc;
1302
1303 in_module_init = 0;
1304
1305 DPRINTK("done\n");
1306 return 0;
1307 }
1308
1309 static void __exit piix_exit(void)
1310 {
1311 pci_unregister_driver(&piix_pci_driver);
1312 }
1313
1314 module_init(piix_init);
1315 module_exit(piix_exit);
Linux kernel - Deliverables
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