2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
100 PIIX_IOCFG
= 0x54, /* IDE I/O configuration register */
101 ICH5_PMR
= 0x90, /* port mapping register */
102 ICH5_PCS
= 0x92, /* port control and status */
108 PIIX_FLAG_CHECKINTR
= (1 << 28), /* make sure PCI INTx enabled */
109 PIIX_FLAG_SIDPR
= (1 << 29), /* SATA idx/data pair regs */
111 PIIX_PATA_FLAGS
= ATA_FLAG_SLAVE_POSS
,
112 PIIX_SATA_FLAGS
= ATA_FLAG_SATA
| PIIX_FLAG_CHECKINTR
,
114 PIIX_80C_PRI
= (1 << 5) | (1 << 4),
115 PIIX_80C_SEC
= (1 << 7) | (1 << 6),
117 /* constants for mapping table */
123 NA
= -2, /* not avaliable */
124 RV
= -3, /* reserved */
126 PIIX_AHCI_DEVICE
= 6,
128 /* host->flags bits */
129 PIIX_HOST_BROKEN_SUSPEND
= (1 << 24),
132 enum piix_controller_ids
{
134 piix_pata_mwdma
, /* PIIX3 MWDMA only */
135 piix_pata_33
, /* PIIX4 at 33Mhz */
136 ich_pata_33
, /* ICH up to UDMA 33 only */
137 ich_pata_66
, /* ICH up to 66 Mhz */
138 ich_pata_100
, /* ICH up to UDMA 100 */
145 ich8m_apple_sata_ahci
, /* locks up on second port enable */
147 piix_pata_vmw
, /* PIIX4 for VMware, spurious DMA_ERR */
152 const u16 port_enable
;
156 struct piix_host_priv
{
161 static int piix_init_one(struct pci_dev
*pdev
,
162 const struct pci_device_id
*ent
);
163 static int piix_pata_prereset(struct ata_link
*link
, unsigned long deadline
);
164 static void piix_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
);
165 static void piix_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
);
166 static void ich_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
);
167 static int ich_pata_cable_detect(struct ata_port
*ap
);
168 static u8
piix_vmw_bmdma_status(struct ata_port
*ap
);
169 static int piix_sidpr_hardreset(struct ata_link
*link
, unsigned int *class,
170 unsigned long deadline
);
171 static int piix_sidpr_scr_read(struct ata_port
*ap
, unsigned int reg
, u32
*val
);
172 static int piix_sidpr_scr_write(struct ata_port
*ap
, unsigned int reg
, u32 val
);
174 static int piix_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
);
175 static int piix_pci_device_resume(struct pci_dev
*pdev
);
178 static unsigned int in_module_init
= 1;
180 static const struct pci_device_id piix_pci_tbl
[] = {
181 /* Intel PIIX3 for the 430HX etc */
182 { 0x8086, 0x7010, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_mwdma
},
184 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw
},
185 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
186 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
187 { 0x8086, 0x7111, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
189 { 0x8086, 0x7199, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
191 { 0x8086, 0x7601, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
193 { 0x8086, 0x84CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix_pata_33
},
194 /* Intel ICH (i810, i815, i840) UDMA 66*/
195 { 0x8086, 0x2411, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_66
},
196 /* Intel ICH0 : UDMA 33*/
197 { 0x8086, 0x2421, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_33
},
199 { 0x8086, 0x244A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
200 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
201 { 0x8086, 0x244B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
203 { 0x8086, 0x248A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
204 /* Intel ICH3 (E7500/1) UDMA 100 */
205 { 0x8086, 0x248B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
206 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
207 { 0x8086, 0x24CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
208 { 0x8086, 0x24CB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
210 { 0x8086, 0x24DB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
212 { 0x8086, 0x245B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
213 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
214 { 0x8086, 0x25A2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
215 /* ICH6 (and 6) (i915) UDMA 100 */
216 { 0x8086, 0x266F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
217 /* ICH7/7-R (i945, i975) UDMA 100*/
218 { 0x8086, 0x27DF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
219 { 0x8086, 0x269E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
220 /* ICH8 Mobile PATA Controller */
221 { 0x8086, 0x2850, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich_pata_100
},
223 /* NOTE: The following PCI ids must be kept in sync with the
224 * list in drivers/pci/quirks.c.
228 { 0x8086, 0x24d1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
230 { 0x8086, 0x24df, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
231 /* 6300ESB (ICH5 variant with broken PCS present bits) */
232 { 0x8086, 0x25a3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
233 /* 6300ESB pretending RAID */
234 { 0x8086, 0x25b0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
235 /* 82801FB/FW (ICH6/ICH6W) */
236 { 0x8086, 0x2651, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
237 /* 82801FR/FRW (ICH6R/ICH6RW) */
238 { 0x8086, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
239 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
240 * Attach iff the controller is in IDE mode. */
241 { 0x8086, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
,
242 PCI_CLASS_STORAGE_IDE
<< 8, 0xffff00, ich6m_sata_ahci
},
243 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
244 { 0x8086, 0x27c0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
245 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
246 { 0x8086, 0x27c4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6m_sata_ahci
},
247 /* Enterprise Southbridge 2 (631xESB/632xESB) */
248 { 0x8086, 0x2680, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
249 /* SATA Controller 1 IDE (ICH8) */
250 { 0x8086, 0x2820, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
251 /* SATA Controller 2 IDE (ICH8) */
252 { 0x8086, 0x2825, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
253 /* Mobile SATA Controller IDE (ICH8M) */
254 { 0x8086, 0x2828, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
255 /* Mobile SATA Controller IDE (ICH8M), Apple */
256 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci
},
257 /* SATA Controller IDE (ICH9) */
258 { 0x8086, 0x2920, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
259 /* SATA Controller IDE (ICH9) */
260 { 0x8086, 0x2921, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
261 /* SATA Controller IDE (ICH9) */
262 { 0x8086, 0x2926, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
263 /* SATA Controller IDE (ICH9M) */
264 { 0x8086, 0x2928, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
265 /* SATA Controller IDE (ICH9M) */
266 { 0x8086, 0x292d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
267 /* SATA Controller IDE (ICH9M) */
268 { 0x8086, 0x292e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
269 /* SATA Controller IDE (Tolapai) */
270 { 0x8086, 0x5028, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, tolapai_sata_ahci
},
271 /* SATA Controller IDE (ICH10) */
272 { 0x8086, 0x3a00, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
273 /* SATA Controller IDE (ICH10) */
274 { 0x8086, 0x3a06, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
275 /* SATA Controller IDE (ICH10) */
276 { 0x8086, 0x3a20, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_sata_ahci
},
277 /* SATA Controller IDE (ICH10) */
278 { 0x8086, 0x3a26, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich8_2port_sata
},
280 { } /* terminate list */
283 static struct pci_driver piix_pci_driver
= {
285 .id_table
= piix_pci_tbl
,
286 .probe
= piix_init_one
,
287 .remove
= ata_pci_remove_one
,
289 .suspend
= piix_pci_device_suspend
,
290 .resume
= piix_pci_device_resume
,
294 static struct scsi_host_template piix_sht
= {
295 ATA_BMDMA_SHT(DRV_NAME
),
298 static struct ata_port_operations piix_pata_ops
= {
299 .inherits
= &ata_bmdma_port_ops
,
300 .cable_detect
= ata_cable_40wire
,
301 .set_piomode
= piix_set_piomode
,
302 .set_dmamode
= piix_set_dmamode
,
303 .prereset
= piix_pata_prereset
,
306 static struct ata_port_operations piix_vmw_ops
= {
307 .inherits
= &piix_pata_ops
,
308 .bmdma_status
= piix_vmw_bmdma_status
,
311 static struct ata_port_operations ich_pata_ops
= {
312 .inherits
= &piix_pata_ops
,
313 .cable_detect
= ich_pata_cable_detect
,
314 .set_dmamode
= ich_set_dmamode
,
317 static struct ata_port_operations piix_sata_ops
= {
318 .inherits
= &ata_bmdma_port_ops
,
321 static struct ata_port_operations piix_sidpr_sata_ops
= {
322 .inherits
= &piix_sata_ops
,
323 .hardreset
= piix_sidpr_hardreset
,
324 .scr_read
= piix_sidpr_scr_read
,
325 .scr_write
= piix_sidpr_scr_write
,
328 static const struct piix_map_db ich5_map_db
= {
332 /* PM PS SM SS MAP */
333 { P0
, NA
, P1
, NA
}, /* 000b */
334 { P1
, NA
, P0
, NA
}, /* 001b */
337 { P0
, P1
, IDE
, IDE
}, /* 100b */
338 { P1
, P0
, IDE
, IDE
}, /* 101b */
339 { IDE
, IDE
, P0
, P1
}, /* 110b */
340 { IDE
, IDE
, P1
, P0
}, /* 111b */
344 static const struct piix_map_db ich6_map_db
= {
348 /* PM PS SM SS MAP */
349 { P0
, P2
, P1
, P3
}, /* 00b */
350 { IDE
, IDE
, P1
, P3
}, /* 01b */
351 { P0
, P2
, IDE
, IDE
}, /* 10b */
356 static const struct piix_map_db ich6m_map_db
= {
360 /* Map 01b isn't specified in the doc but some notebooks use
361 * it anyway. MAP 01b have been spotted on both ICH6M and
365 /* PM PS SM SS MAP */
366 { P0
, P2
, NA
, NA
}, /* 00b */
367 { IDE
, IDE
, P1
, P3
}, /* 01b */
368 { P0
, P2
, IDE
, IDE
}, /* 10b */
373 static const struct piix_map_db ich8_map_db
= {
377 /* PM PS SM SS MAP */
378 { P0
, P2
, P1
, P3
}, /* 00b (hardwired when in AHCI) */
380 { P0
, P2
, IDE
, IDE
}, /* 10b (IDE mode) */
385 static const struct piix_map_db ich8_2port_map_db
= {
389 /* PM PS SM SS MAP */
390 { P0
, NA
, P1
, NA
}, /* 00b */
391 { RV
, RV
, RV
, RV
}, /* 01b */
392 { RV
, RV
, RV
, RV
}, /* 10b */
397 static const struct piix_map_db ich8m_apple_map_db
= {
401 /* PM PS SM SS MAP */
402 { P0
, NA
, NA
, NA
}, /* 00b */
404 { P0
, P2
, IDE
, IDE
}, /* 10b */
409 static const struct piix_map_db tolapai_map_db
= {
413 /* PM PS SM SS MAP */
414 { P0
, NA
, P1
, NA
}, /* 00b */
415 { RV
, RV
, RV
, RV
}, /* 01b */
416 { RV
, RV
, RV
, RV
}, /* 10b */
421 static const struct piix_map_db
*piix_map_db_table
[] = {
422 [ich5_sata
] = &ich5_map_db
,
423 [ich6_sata
] = &ich6_map_db
,
424 [ich6_sata_ahci
] = &ich6_map_db
,
425 [ich6m_sata_ahci
] = &ich6m_map_db
,
426 [ich8_sata_ahci
] = &ich8_map_db
,
427 [ich8_2port_sata
] = &ich8_2port_map_db
,
428 [ich8m_apple_sata_ahci
] = &ich8m_apple_map_db
,
429 [tolapai_sata_ahci
] = &tolapai_map_db
,
432 static struct ata_port_info piix_port_info
[] = {
433 [piix_pata_mwdma
] = /* PIIX3 MWDMA only */
435 .flags
= PIIX_PATA_FLAGS
,
436 .pio_mask
= 0x1f, /* pio0-4 */
437 .mwdma_mask
= 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
438 .port_ops
= &piix_pata_ops
,
441 [piix_pata_33
] = /* PIIX4 at 33MHz */
443 .flags
= PIIX_PATA_FLAGS
,
444 .pio_mask
= 0x1f, /* pio0-4 */
445 .mwdma_mask
= 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
446 .udma_mask
= ATA_UDMA_MASK_40C
,
447 .port_ops
= &piix_pata_ops
,
450 [ich_pata_33
] = /* ICH0 - ICH at 33Mhz*/
452 .flags
= PIIX_PATA_FLAGS
,
453 .pio_mask
= 0x1f, /* pio 0-4 */
454 .mwdma_mask
= 0x06, /* Check: maybe 0x07 */
455 .udma_mask
= ATA_UDMA2
, /* UDMA33 */
456 .port_ops
= &ich_pata_ops
,
459 [ich_pata_66
] = /* ICH controllers up to 66MHz */
461 .flags
= PIIX_PATA_FLAGS
,
462 .pio_mask
= 0x1f, /* pio 0-4 */
463 .mwdma_mask
= 0x06, /* MWDMA0 is broken on chip */
464 .udma_mask
= ATA_UDMA4
,
465 .port_ops
= &ich_pata_ops
,
470 .flags
= PIIX_PATA_FLAGS
| PIIX_FLAG_CHECKINTR
,
471 .pio_mask
= 0x1f, /* pio0-4 */
472 .mwdma_mask
= 0x06, /* mwdma1-2 */
473 .udma_mask
= ATA_UDMA5
, /* udma0-5 */
474 .port_ops
= &ich_pata_ops
,
479 .flags
= PIIX_SATA_FLAGS
,
480 .pio_mask
= 0x1f, /* pio0-4 */
481 .mwdma_mask
= 0x07, /* mwdma0-2 */
482 .udma_mask
= ATA_UDMA6
,
483 .port_ops
= &piix_sata_ops
,
488 .flags
= PIIX_SATA_FLAGS
,
489 .pio_mask
= 0x1f, /* pio0-4 */
490 .mwdma_mask
= 0x07, /* mwdma0-2 */
491 .udma_mask
= ATA_UDMA6
,
492 .port_ops
= &piix_sata_ops
,
497 .flags
= PIIX_SATA_FLAGS
,
498 .pio_mask
= 0x1f, /* pio0-4 */
499 .mwdma_mask
= 0x07, /* mwdma0-2 */
500 .udma_mask
= ATA_UDMA6
,
501 .port_ops
= &piix_sata_ops
,
506 .flags
= PIIX_SATA_FLAGS
,
507 .pio_mask
= 0x1f, /* pio0-4 */
508 .mwdma_mask
= 0x07, /* mwdma0-2 */
509 .udma_mask
= ATA_UDMA6
,
510 .port_ops
= &piix_sata_ops
,
515 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SIDPR
,
516 .pio_mask
= 0x1f, /* pio0-4 */
517 .mwdma_mask
= 0x07, /* mwdma0-2 */
518 .udma_mask
= ATA_UDMA6
,
519 .port_ops
= &piix_sata_ops
,
524 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SIDPR
,
525 .pio_mask
= 0x1f, /* pio0-4 */
526 .mwdma_mask
= 0x07, /* mwdma0-2 */
527 .udma_mask
= ATA_UDMA6
,
528 .port_ops
= &piix_sata_ops
,
531 [tolapai_sata_ahci
] =
533 .flags
= PIIX_SATA_FLAGS
,
534 .pio_mask
= 0x1f, /* pio0-4 */
535 .mwdma_mask
= 0x07, /* mwdma0-2 */
536 .udma_mask
= ATA_UDMA6
,
537 .port_ops
= &piix_sata_ops
,
540 [ich8m_apple_sata_ahci
] =
542 .flags
= PIIX_SATA_FLAGS
| PIIX_FLAG_SIDPR
,
543 .pio_mask
= 0x1f, /* pio0-4 */
544 .mwdma_mask
= 0x07, /* mwdma0-2 */
545 .udma_mask
= ATA_UDMA6
,
546 .port_ops
= &piix_sata_ops
,
551 .flags
= PIIX_PATA_FLAGS
,
552 .pio_mask
= 0x1f, /* pio0-4 */
553 .mwdma_mask
= 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
554 .udma_mask
= ATA_UDMA_MASK_40C
,
555 .port_ops
= &piix_vmw_ops
,
560 static struct pci_bits piix_enable_bits
[] = {
561 { 0x41U
, 1U, 0x80UL
, 0x80UL
}, /* port 0 */
562 { 0x43U
, 1U, 0x80UL
, 0x80UL
}, /* port 1 */
565 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
566 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
567 MODULE_LICENSE("GPL");
568 MODULE_DEVICE_TABLE(pci
, piix_pci_tbl
);
569 MODULE_VERSION(DRV_VERSION
);
578 * List of laptops that use short cables rather than 80 wire
581 static const struct ich_laptop ich_laptop
[] = {
582 /* devid, subvendor, subdev */
583 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
584 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
585 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
586 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
587 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
588 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
594 * ich_pata_cable_detect - Probe host controller cable detect info
595 * @ap: Port for which cable detect info is desired
597 * Read 80c cable indicator from ATA PCI device's PCI config
598 * register. This register is normally set by firmware (BIOS).
601 * None (inherited from caller).
604 static int ich_pata_cable_detect(struct ata_port
*ap
)
606 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
607 const struct ich_laptop
*lap
= &ich_laptop
[0];
610 /* Check for specials - Acer Aspire 5602WLMi */
611 while (lap
->device
) {
612 if (lap
->device
== pdev
->device
&&
613 lap
->subvendor
== pdev
->subsystem_vendor
&&
614 lap
->subdevice
== pdev
->subsystem_device
)
615 return ATA_CBL_PATA40_SHORT
;
620 /* check BIOS cable detect results */
621 mask
= ap
->port_no
== 0 ? PIIX_80C_PRI
: PIIX_80C_SEC
;
622 pci_read_config_byte(pdev
, PIIX_IOCFG
, &tmp
);
623 if ((tmp
& mask
) == 0)
624 return ATA_CBL_PATA40
;
625 return ATA_CBL_PATA80
;
629 * piix_pata_prereset - prereset for PATA host controller
631 * @deadline: deadline jiffies for the operation
634 * None (inherited from caller).
636 static int piix_pata_prereset(struct ata_link
*link
, unsigned long deadline
)
638 struct ata_port
*ap
= link
->ap
;
639 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
641 if (!pci_test_config_bits(pdev
, &piix_enable_bits
[ap
->port_no
]))
643 return ata_std_prereset(link
, deadline
);
647 * piix_set_piomode - Initialize host controller PATA PIO timings
648 * @ap: Port whose timings we are configuring
651 * Set PIO mode for device, in host controller PCI config space.
654 * None (inherited from caller).
657 static void piix_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
659 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
660 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
661 unsigned int is_slave
= (adev
->devno
!= 0);
662 unsigned int master_port
= ap
->port_no
? 0x42 : 0x40;
663 unsigned int slave_port
= 0x44;
670 * See Intel Document 298600-004 for the timing programing rules
671 * for ICH controllers.
674 static const /* ISP RTC */
675 u8 timings
[][2] = { { 0, 0 },
682 control
|= 1; /* TIME1 enable */
683 if (ata_pio_need_iordy(adev
))
684 control
|= 2; /* IE enable */
686 /* Intel specifies that the PPE functionality is for disk only */
687 if (adev
->class == ATA_DEV_ATA
)
688 control
|= 4; /* PPE enable */
690 /* PIO configuration clears DTE unconditionally. It will be
691 * programmed in set_dmamode which is guaranteed to be called
692 * after set_piomode if any DMA mode is available.
694 pci_read_config_word(dev
, master_port
, &master_data
);
696 /* clear TIME1|IE1|PPE1|DTE1 */
697 master_data
&= 0xff0f;
698 /* Enable SITRE (separate slave timing register) */
699 master_data
|= 0x4000;
700 /* enable PPE1, IE1 and TIME1 as needed */
701 master_data
|= (control
<< 4);
702 pci_read_config_byte(dev
, slave_port
, &slave_data
);
703 slave_data
&= (ap
->port_no
? 0x0f : 0xf0);
704 /* Load the timing nibble for this slave */
705 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1])
706 << (ap
->port_no
? 4 : 0);
708 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
709 master_data
&= 0xccf0;
710 /* Enable PPE, IE and TIME as appropriate */
711 master_data
|= control
;
712 /* load ISP and RCT */
714 (timings
[pio
][0] << 12) |
715 (timings
[pio
][1] << 8);
717 pci_write_config_word(dev
, master_port
, master_data
);
719 pci_write_config_byte(dev
, slave_port
, slave_data
);
721 /* Ensure the UDMA bit is off - it will be turned back on if
725 pci_read_config_byte(dev
, 0x48, &udma_enable
);
726 udma_enable
&= ~(1 << (2 * ap
->port_no
+ adev
->devno
));
727 pci_write_config_byte(dev
, 0x48, udma_enable
);
732 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
733 * @ap: Port whose timings we are configuring
734 * @adev: Drive in question
735 * @udma: udma mode, 0 - 6
736 * @isich: set if the chip is an ICH device
738 * Set UDMA mode for device, in host controller PCI config space.
741 * None (inherited from caller).
744 static void do_pata_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
, int isich
)
746 struct pci_dev
*dev
= to_pci_dev(ap
->host
->dev
);
747 u8 master_port
= ap
->port_no
? 0x42 : 0x40;
749 u8 speed
= adev
->dma_mode
;
750 int devid
= adev
->devno
+ 2 * ap
->port_no
;
753 static const /* ISP RTC */
754 u8 timings
[][2] = { { 0, 0 },
760 pci_read_config_word(dev
, master_port
, &master_data
);
762 pci_read_config_byte(dev
, 0x48, &udma_enable
);
764 if (speed
>= XFER_UDMA_0
) {
765 unsigned int udma
= adev
->dma_mode
- XFER_UDMA_0
;
768 int u_clock
, u_speed
;
771 * UDMA is handled by a combination of clock switching and
772 * selection of dividers
774 * Handy rule: Odd modes are UDMATIMx 01, even are 02
775 * except UDMA0 which is 00
777 u_speed
= min(2 - (udma
& 1), udma
);
779 u_clock
= 0x1000; /* 100Mhz */
781 u_clock
= 1; /* 66Mhz */
783 u_clock
= 0; /* 33Mhz */
785 udma_enable
|= (1 << devid
);
787 /* Load the CT/RP selection */
788 pci_read_config_word(dev
, 0x4A, &udma_timing
);
789 udma_timing
&= ~(3 << (4 * devid
));
790 udma_timing
|= u_speed
<< (4 * devid
);
791 pci_write_config_word(dev
, 0x4A, udma_timing
);
794 /* Select a 33/66/100Mhz clock */
795 pci_read_config_word(dev
, 0x54, &ideconf
);
796 ideconf
&= ~(0x1001 << devid
);
797 ideconf
|= u_clock
<< devid
;
798 /* For ICH or later we should set bit 10 for better
799 performance (WR_PingPong_En) */
800 pci_write_config_word(dev
, 0x54, ideconf
);
804 * MWDMA is driven by the PIO timings. We must also enable
805 * IORDY unconditionally along with TIME1. PPE has already
806 * been set when the PIO timing was set.
808 unsigned int mwdma
= adev
->dma_mode
- XFER_MW_DMA_0
;
809 unsigned int control
;
811 const unsigned int needed_pio
[3] = {
812 XFER_PIO_0
, XFER_PIO_3
, XFER_PIO_4
814 int pio
= needed_pio
[mwdma
] - XFER_PIO_0
;
816 control
= 3; /* IORDY|TIME1 */
818 /* If the drive MWDMA is faster than it can do PIO then
819 we must force PIO into PIO0 */
821 if (adev
->pio_mode
< needed_pio
[mwdma
])
822 /* Enable DMA timing only */
823 control
|= 8; /* PIO cycles in PIO0 */
825 if (adev
->devno
) { /* Slave */
826 master_data
&= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
827 master_data
|= control
<< 4;
828 pci_read_config_byte(dev
, 0x44, &slave_data
);
829 slave_data
&= (ap
->port_no
? 0x0f : 0xf0);
830 /* Load the matching timing */
831 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) << (ap
->port_no
? 4 : 0);
832 pci_write_config_byte(dev
, 0x44, slave_data
);
833 } else { /* Master */
834 master_data
&= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
835 and master timing bits */
836 master_data
|= control
;
838 (timings
[pio
][0] << 12) |
839 (timings
[pio
][1] << 8);
843 udma_enable
&= ~(1 << devid
);
844 pci_write_config_word(dev
, master_port
, master_data
);
847 /* Don't scribble on 0x48 if the controller does not support UDMA */
849 pci_write_config_byte(dev
, 0x48, udma_enable
);
853 * piix_set_dmamode - Initialize host controller PATA DMA timings
854 * @ap: Port whose timings we are configuring
857 * Set MW/UDMA mode for device, in host controller PCI config space.
860 * None (inherited from caller).
863 static void piix_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
865 do_pata_set_dmamode(ap
, adev
, 0);
869 * ich_set_dmamode - Initialize host controller PATA DMA timings
870 * @ap: Port whose timings we are configuring
873 * Set MW/UDMA mode for device, in host controller PCI config space.
876 * None (inherited from caller).
879 static void ich_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
881 do_pata_set_dmamode(ap
, adev
, 1);
885 * Serial ATA Index/Data Pair Superset Registers access
887 * Beginning from ICH8, there's a sane way to access SCRs using index
888 * and data register pair located at BAR5. This creates an
889 * interesting problem of mapping two SCRs to one port.
891 * Although they have separate SCRs, the master and slave aren't
892 * independent enough to be treated as separate links - e.g. softreset
893 * resets both. Also, there's no protocol defined for hard resetting
894 * singled device sharing the virtual port (no defined way to acquire
895 * device signature). This is worked around by merging the SCR values
896 * into one sensible value and requesting follow-up SRST after
899 * SCR merging is perfomed in nibbles which is the unit contents in
900 * SCRs are organized. If two values are equal, the value is used.
901 * When they differ, merge table which lists precedence of possible
902 * values is consulted and the first match or the last entry when
903 * nothing matches is used. When there's no merge table for the
904 * specific nibble, value from the first port is used.
906 static const int piix_sidx_map
[] = {
912 static void piix_sidpr_sel(struct ata_device
*dev
, unsigned int reg
)
914 struct ata_port
*ap
= dev
->link
->ap
;
915 struct piix_host_priv
*hpriv
= ap
->host
->private_data
;
917 iowrite32(((ap
->port_no
* 2 + dev
->devno
) << 8) | piix_sidx_map
[reg
],
918 hpriv
->sidpr
+ PIIX_SIDPR_IDX
);
921 static int piix_sidpr_read(struct ata_device
*dev
, unsigned int reg
)
923 struct piix_host_priv
*hpriv
= dev
->link
->ap
->host
->private_data
;
925 piix_sidpr_sel(dev
, reg
);
926 return ioread32(hpriv
->sidpr
+ PIIX_SIDPR_DATA
);
929 static void piix_sidpr_write(struct ata_device
*dev
, unsigned int reg
, u32 val
)
931 struct piix_host_priv
*hpriv
= dev
->link
->ap
->host
->private_data
;
933 piix_sidpr_sel(dev
, reg
);
934 iowrite32(val
, hpriv
->sidpr
+ PIIX_SIDPR_DATA
);
937 static u32
piix_merge_scr(u32 val0
, u32 val1
, const int * const *merge_tbl
)
942 for (i
= 0, mi
= 0; i
< 32 / 4; i
++) {
943 u8 c0
= (val0
>> (i
* 4)) & 0xf;
944 u8 c1
= (val1
>> (i
* 4)) & 0xf;
948 /* if no merge preference, assume the first value */
954 /* if two values equal, use it */
958 /* choose the first match or the last from the merge table */
960 if (c0
== *cur
|| c1
== *cur
)
968 val
|= merged
<< (i
* 4);
974 static int piix_sidpr_scr_read(struct ata_port
*ap
, unsigned int reg
, u32
*val
)
976 const int * const sstatus_merge_tbl
[] = {
977 /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 },
978 /* SPD */ (const int []){ 2, 1, 0, -1 },
979 /* IPM */ (const int []){ 6, 2, 1, 0, -1 },
982 const int * const scontrol_merge_tbl
[] = {
983 /* DET */ (const int []){ 1, 0, 4, 0, -1 },
984 /* SPD */ (const int []){ 0, 2, 1, 0, -1 },
985 /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 },
990 if (reg
>= ARRAY_SIZE(piix_sidx_map
))
993 if (!(ap
->flags
& ATA_FLAG_SLAVE_POSS
)) {
994 *val
= piix_sidpr_read(&ap
->link
.device
[0], reg
);
998 v0
= piix_sidpr_read(&ap
->link
.device
[0], reg
);
999 v1
= piix_sidpr_read(&ap
->link
.device
[1], reg
);
1003 *val
= piix_merge_scr(v0
, v1
, sstatus_merge_tbl
);
1009 *val
= piix_merge_scr(v0
, v1
, scontrol_merge_tbl
);
1016 static int piix_sidpr_scr_write(struct ata_port
*ap
, unsigned int reg
, u32 val
)
1018 if (reg
>= ARRAY_SIZE(piix_sidx_map
))
1021 piix_sidpr_write(&ap
->link
.device
[0], reg
, val
);
1023 if (ap
->flags
& ATA_FLAG_SLAVE_POSS
)
1024 piix_sidpr_write(&ap
->link
.device
[1], reg
, val
);
1029 static int piix_sidpr_hardreset(struct ata_link
*link
, unsigned int *class,
1030 unsigned long deadline
)
1032 const unsigned long *timing
= sata_ehc_deb_timing(&link
->eh_context
);
1036 rc
= sata_link_hardreset(link
, timing
, deadline
);
1038 ata_link_printk(link
, KERN_ERR
,
1039 "COMRESET failed (errno=%d)\n", rc
);
1043 /* TODO: phy layer with polling, timeouts, etc. */
1044 if (ata_link_offline(link
)) {
1045 *class = ATA_DEV_NONE
;
1053 static int piix_broken_suspend(void)
1055 static const struct dmi_system_id sysids
[] = {
1057 .ident
= "TECRA M3",
1059 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1060 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M3"),
1064 .ident
= "TECRA M3",
1066 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1067 DMI_MATCH(DMI_PRODUCT_NAME
, "Tecra M3"),
1071 .ident
= "TECRA M4",
1073 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1074 DMI_MATCH(DMI_PRODUCT_NAME
, "Tecra M4"),
1078 .ident
= "TECRA M5",
1080 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1081 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M5"),
1085 .ident
= "TECRA M6",
1087 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1088 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M6"),
1092 .ident
= "TECRA M7",
1094 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1095 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA M7"),
1099 .ident
= "TECRA A8",
1101 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1102 DMI_MATCH(DMI_PRODUCT_NAME
, "TECRA A8"),
1106 .ident
= "Satellite R20",
1108 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1109 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite R20"),
1113 .ident
= "Satellite R25",
1115 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1116 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite R25"),
1120 .ident
= "Satellite U200",
1122 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1123 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite U200"),
1127 .ident
= "Satellite U200",
1129 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1130 DMI_MATCH(DMI_PRODUCT_NAME
, "SATELLITE U200"),
1134 .ident
= "Satellite Pro U200",
1136 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1137 DMI_MATCH(DMI_PRODUCT_NAME
, "SATELLITE PRO U200"),
1141 .ident
= "Satellite U205",
1143 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1144 DMI_MATCH(DMI_PRODUCT_NAME
, "Satellite U205"),
1148 .ident
= "SATELLITE U205",
1150 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1151 DMI_MATCH(DMI_PRODUCT_NAME
, "SATELLITE U205"),
1155 .ident
= "Portege M500",
1157 DMI_MATCH(DMI_SYS_VENDOR
, "TOSHIBA"),
1158 DMI_MATCH(DMI_PRODUCT_NAME
, "PORTEGE M500"),
1162 { } /* terminate list */
1164 static const char *oemstrs
[] = {
1169 if (dmi_check_system(sysids
))
1172 for (i
= 0; i
< ARRAY_SIZE(oemstrs
); i
++)
1173 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING
, oemstrs
[i
], NULL
))
1179 static int piix_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1181 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1182 unsigned long flags
;
1185 rc
= ata_host_suspend(host
, mesg
);
1189 /* Some braindamaged ACPI suspend implementations expect the
1190 * controller to be awake on entry; otherwise, it burns cpu
1191 * cycles and power trying to do something to the sleeping
1194 if (piix_broken_suspend() && (mesg
.event
& PM_EVENT_SLEEP
)) {
1195 pci_save_state(pdev
);
1197 /* mark its power state as "unknown", since we don't
1198 * know if e.g. the BIOS will change its device state
1201 if (pdev
->current_state
== PCI_D0
)
1202 pdev
->current_state
= PCI_UNKNOWN
;
1204 /* tell resume that it's waking up from broken suspend */
1205 spin_lock_irqsave(&host
->lock
, flags
);
1206 host
->flags
|= PIIX_HOST_BROKEN_SUSPEND
;
1207 spin_unlock_irqrestore(&host
->lock
, flags
);
1209 ata_pci_device_do_suspend(pdev
, mesg
);
1214 static int piix_pci_device_resume(struct pci_dev
*pdev
)
1216 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1217 unsigned long flags
;
1220 if (host
->flags
& PIIX_HOST_BROKEN_SUSPEND
) {
1221 spin_lock_irqsave(&host
->lock
, flags
);
1222 host
->flags
&= ~PIIX_HOST_BROKEN_SUSPEND
;
1223 spin_unlock_irqrestore(&host
->lock
, flags
);
1225 pci_set_power_state(pdev
, PCI_D0
);
1226 pci_restore_state(pdev
);
1228 /* PCI device wasn't disabled during suspend. Use
1229 * pci_reenable_device() to avoid affecting the enable
1232 rc
= pci_reenable_device(pdev
);
1234 dev_printk(KERN_ERR
, &pdev
->dev
, "failed to enable "
1235 "device after resume (%d)\n", rc
);
1237 rc
= ata_pci_device_do_resume(pdev
);
1240 ata_host_resume(host
);
1246 static u8
piix_vmw_bmdma_status(struct ata_port
*ap
)
1248 return ata_bmdma_status(ap
) & ~ATA_DMA_ERR
;
1251 #define AHCI_PCI_BAR 5
1252 #define AHCI_GLOBAL_CTL 0x04
1253 #define AHCI_ENABLE (1 << 31)
1254 static int piix_disable_ahci(struct pci_dev
*pdev
)
1260 /* BUG: pci_enable_device has not yet been called. This
1261 * works because this device is usually set up by BIOS.
1264 if (!pci_resource_start(pdev
, AHCI_PCI_BAR
) ||
1265 !pci_resource_len(pdev
, AHCI_PCI_BAR
))
1268 mmio
= pci_iomap(pdev
, AHCI_PCI_BAR
, 64);
1272 tmp
= ioread32(mmio
+ AHCI_GLOBAL_CTL
);
1273 if (tmp
& AHCI_ENABLE
) {
1274 tmp
&= ~AHCI_ENABLE
;
1275 iowrite32(tmp
, mmio
+ AHCI_GLOBAL_CTL
);
1277 tmp
= ioread32(mmio
+ AHCI_GLOBAL_CTL
);
1278 if (tmp
& AHCI_ENABLE
)
1282 pci_iounmap(pdev
, mmio
);
1287 * piix_check_450nx_errata - Check for problem 450NX setup
1288 * @ata_dev: the PCI device to check
1290 * Check for the present of 450NX errata #19 and errata #25. If
1291 * they are found return an error code so we can turn off DMA
1294 static int __devinit
piix_check_450nx_errata(struct pci_dev
*ata_dev
)
1296 struct pci_dev
*pdev
= NULL
;
1298 int no_piix_dma
= 0;
1300 while ((pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, pdev
)) != NULL
) {
1301 /* Look for 450NX PXB. Check for problem configurations
1302 A PCI quirk checks bit 6 already */
1303 pci_read_config_word(pdev
, 0x41, &cfg
);
1304 /* Only on the original revision: IDE DMA can hang */
1305 if (pdev
->revision
== 0x00)
1307 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1308 else if (cfg
& (1<<14) && pdev
->revision
< 5)
1312 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "450NX errata present, disabling IDE DMA.\n");
1313 if (no_piix_dma
== 2)
1314 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "A BIOS update may resolve this.\n");
1318 static void __devinit
piix_init_pcs(struct ata_host
*host
,
1319 const struct piix_map_db
*map_db
)
1321 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1324 pci_read_config_word(pdev
, ICH5_PCS
, &pcs
);
1326 new_pcs
= pcs
| map_db
->port_enable
;
1328 if (new_pcs
!= pcs
) {
1329 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs
, new_pcs
);
1330 pci_write_config_word(pdev
, ICH5_PCS
, new_pcs
);
1335 static const int *__devinit
piix_init_sata_map(struct pci_dev
*pdev
,
1336 struct ata_port_info
*pinfo
,
1337 const struct piix_map_db
*map_db
)
1340 int i
, invalid_map
= 0;
1343 pci_read_config_byte(pdev
, ICH5_PMR
, &map_value
);
1345 map
= map_db
->map
[map_value
& map_db
->mask
];
1347 dev_printk(KERN_INFO
, &pdev
->dev
, "MAP [");
1348 for (i
= 0; i
< 4; i
++) {
1360 WARN_ON((i
& 1) || map
[i
+ 1] != IDE
);
1361 pinfo
[i
/ 2] = piix_port_info
[ich_pata_100
];
1367 printk(" P%d", map
[i
]);
1369 pinfo
[i
/ 2].flags
|= ATA_FLAG_SLAVE_POSS
;
1376 dev_printk(KERN_ERR
, &pdev
->dev
,
1377 "invalid MAP value %u\n", map_value
);
1382 static void __devinit
piix_init_sidpr(struct ata_host
*host
)
1384 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1385 struct piix_host_priv
*hpriv
= host
->private_data
;
1388 /* check for availability */
1389 for (i
= 0; i
< 4; i
++)
1390 if (hpriv
->map
[i
] == IDE
)
1393 if (!(host
->ports
[0]->flags
& PIIX_FLAG_SIDPR
))
1396 if (pci_resource_start(pdev
, PIIX_SIDPR_BAR
) == 0 ||
1397 pci_resource_len(pdev
, PIIX_SIDPR_BAR
) != PIIX_SIDPR_LEN
)
1400 if (pcim_iomap_regions(pdev
, 1 << PIIX_SIDPR_BAR
, DRV_NAME
))
1403 hpriv
->sidpr
= pcim_iomap_table(pdev
)[PIIX_SIDPR_BAR
];
1404 host
->ports
[0]->ops
= &piix_sidpr_sata_ops
;
1405 host
->ports
[1]->ops
= &piix_sidpr_sata_ops
;
1408 static void piix_iocfg_bit18_quirk(struct pci_dev
*pdev
)
1410 static const struct dmi_system_id sysids
[] = {
1412 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1413 * isn't used to boot the system which
1414 * disables the channel.
1418 DMI_MATCH(DMI_SYS_VENDOR
, "Clevo Co."),
1419 DMI_MATCH(DMI_PRODUCT_NAME
, "M570U"),
1423 { } /* terminate list */
1427 if (!dmi_check_system(sysids
))
1430 /* The datasheet says that bit 18 is NOOP but certain systems
1431 * seem to use it to disable a channel. Clear the bit on the
1434 pci_read_config_dword(pdev
, PIIX_IOCFG
, &iocfg
);
1435 if (iocfg
& (1 << 18)) {
1436 dev_printk(KERN_INFO
, &pdev
->dev
,
1437 "applying IOCFG bit18 quirk\n");
1438 iocfg
&= ~(1 << 18);
1439 pci_write_config_dword(pdev
, PIIX_IOCFG
, iocfg
);
1444 * piix_init_one - Register PIIX ATA PCI device with kernel services
1445 * @pdev: PCI device to register
1446 * @ent: Entry in piix_pci_tbl matching with @pdev
1448 * Called from kernel PCI layer. We probe for combined mode (sigh),
1449 * and then hand over control to libata, for it to do the rest.
1452 * Inherited from PCI layer (may sleep).
1455 * Zero on success, or -ERRNO value.
1458 static int __devinit
piix_init_one(struct pci_dev
*pdev
,
1459 const struct pci_device_id
*ent
)
1461 static int printed_version
;
1462 struct device
*dev
= &pdev
->dev
;
1463 struct ata_port_info port_info
[2];
1464 const struct ata_port_info
*ppi
[] = { &port_info
[0], &port_info
[1] };
1465 unsigned long port_flags
;
1466 struct ata_host
*host
;
1467 struct piix_host_priv
*hpriv
;
1470 if (!printed_version
++)
1471 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1472 "version " DRV_VERSION
"\n");
1474 /* no hotplugging support (FIXME) */
1475 if (!in_module_init
)
1478 port_info
[0] = piix_port_info
[ent
->driver_data
];
1479 port_info
[1] = piix_port_info
[ent
->driver_data
];
1481 port_flags
= port_info
[0].flags
;
1483 /* enable device and prepare host */
1484 rc
= pcim_enable_device(pdev
);
1488 /* ICH6R may be driven by either ata_piix or ahci driver
1489 * regardless of BIOS configuration. Make sure AHCI mode is
1492 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
&& pdev
->device
== 0x2652) {
1493 int rc
= piix_disable_ahci(pdev
);
1498 /* SATA map init can change port_info, do it before prepping host */
1499 hpriv
= devm_kzalloc(dev
, sizeof(*hpriv
), GFP_KERNEL
);
1503 if (port_flags
& ATA_FLAG_SATA
)
1504 hpriv
->map
= piix_init_sata_map(pdev
, port_info
,
1505 piix_map_db_table
[ent
->driver_data
]);
1507 rc
= ata_pci_prepare_sff_host(pdev
, ppi
, &host
);
1510 host
->private_data
= hpriv
;
1512 /* initialize controller */
1513 if (port_flags
& ATA_FLAG_SATA
) {
1514 piix_init_pcs(host
, piix_map_db_table
[ent
->driver_data
]);
1515 piix_init_sidpr(host
);
1518 /* apply IOCFG bit18 quirk */
1519 piix_iocfg_bit18_quirk(pdev
);
1521 /* On ICH5, some BIOSen disable the interrupt using the
1522 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1523 * On ICH6, this bit has the same effect, but only when
1524 * MSI is disabled (and it is disabled, as we don't use
1525 * message-signalled interrupts currently).
1527 if (port_flags
& PIIX_FLAG_CHECKINTR
)
1530 if (piix_check_450nx_errata(pdev
)) {
1531 /* This writes into the master table but it does not
1532 really matter for this errata as we will apply it to
1533 all the PIIX devices on the board */
1534 host
->ports
[0]->mwdma_mask
= 0;
1535 host
->ports
[0]->udma_mask
= 0;
1536 host
->ports
[1]->mwdma_mask
= 0;
1537 host
->ports
[1]->udma_mask
= 0;
1540 pci_set_master(pdev
);
1541 return ata_pci_activate_sff_host(host
, ata_interrupt
, &piix_sht
);
1544 static int __init
piix_init(void)
1548 DPRINTK("pci_register_driver\n");
1549 rc
= pci_register_driver(&piix_pci_driver
);
1559 static void __exit
piix_exit(void)
1561 pci_unregister_driver(&piix_pci_driver
);
1564 module_init(piix_init
);
1565 module_exit(piix_exit
);