2 * libahci.c - Common AHCI SATA low-level routines
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
50 static int ahci_skip_host_reset
;
52 EXPORT_SYMBOL_GPL(ahci_ignore_sss
);
54 module_param_named(skip_host_reset
, ahci_skip_host_reset
, int, 0444);
55 MODULE_PARM_DESC(skip_host_reset
, "skip global host reset (0=don't skip, 1=skip)");
57 module_param_named(ignore_sss
, ahci_ignore_sss
, int, 0444);
58 MODULE_PARM_DESC(ignore_sss
, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
60 static int ahci_set_lpm(struct ata_link
*link
, enum ata_lpm_policy policy
,
62 static ssize_t
ahci_led_show(struct ata_port
*ap
, char *buf
);
63 static ssize_t
ahci_led_store(struct ata_port
*ap
, const char *buf
,
65 static ssize_t
ahci_transmit_led_message(struct ata_port
*ap
, u32 state
,
70 static int ahci_scr_read(struct ata_link
*link
, unsigned int sc_reg
, u32
*val
);
71 static int ahci_scr_write(struct ata_link
*link
, unsigned int sc_reg
, u32 val
);
72 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
);
73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd
*qc
);
74 static int ahci_port_start(struct ata_port
*ap
);
75 static void ahci_port_stop(struct ata_port
*ap
);
76 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
77 static int ahci_pmp_qc_defer(struct ata_queued_cmd
*qc
);
78 static void ahci_freeze(struct ata_port
*ap
);
79 static void ahci_thaw(struct ata_port
*ap
);
80 static void ahci_set_aggressive_devslp(struct ata_port
*ap
, bool sleep
);
81 static void ahci_enable_fbs(struct ata_port
*ap
);
82 static void ahci_disable_fbs(struct ata_port
*ap
);
83 static void ahci_pmp_attach(struct ata_port
*ap
);
84 static void ahci_pmp_detach(struct ata_port
*ap
);
85 static int ahci_softreset(struct ata_link
*link
, unsigned int *class,
86 unsigned long deadline
);
87 static int ahci_pmp_retry_softreset(struct ata_link
*link
, unsigned int *class,
88 unsigned long deadline
);
89 static int ahci_hardreset(struct ata_link
*link
, unsigned int *class,
90 unsigned long deadline
);
91 static void ahci_postreset(struct ata_link
*link
, unsigned int *class);
92 static void ahci_error_handler(struct ata_port
*ap
);
93 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
);
94 static void ahci_dev_config(struct ata_device
*dev
);
96 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
);
98 static ssize_t
ahci_activity_show(struct ata_device
*dev
, char *buf
);
99 static ssize_t
ahci_activity_store(struct ata_device
*dev
,
100 enum sw_activity val
);
101 static void ahci_init_sw_activity(struct ata_link
*link
);
103 static ssize_t
ahci_show_host_caps(struct device
*dev
,
104 struct device_attribute
*attr
, char *buf
);
105 static ssize_t
ahci_show_host_cap2(struct device
*dev
,
106 struct device_attribute
*attr
, char *buf
);
107 static ssize_t
ahci_show_host_version(struct device
*dev
,
108 struct device_attribute
*attr
, char *buf
);
109 static ssize_t
ahci_show_port_cmd(struct device
*dev
,
110 struct device_attribute
*attr
, char *buf
);
111 static ssize_t
ahci_read_em_buffer(struct device
*dev
,
112 struct device_attribute
*attr
, char *buf
);
113 static ssize_t
ahci_store_em_buffer(struct device
*dev
,
114 struct device_attribute
*attr
,
115 const char *buf
, size_t size
);
116 static ssize_t
ahci_show_em_supported(struct device
*dev
,
117 struct device_attribute
*attr
, char *buf
);
119 static DEVICE_ATTR(ahci_host_caps
, S_IRUGO
, ahci_show_host_caps
, NULL
);
120 static DEVICE_ATTR(ahci_host_cap2
, S_IRUGO
, ahci_show_host_cap2
, NULL
);
121 static DEVICE_ATTR(ahci_host_version
, S_IRUGO
, ahci_show_host_version
, NULL
);
122 static DEVICE_ATTR(ahci_port_cmd
, S_IRUGO
, ahci_show_port_cmd
, NULL
);
123 static DEVICE_ATTR(em_buffer
, S_IWUSR
| S_IRUGO
,
124 ahci_read_em_buffer
, ahci_store_em_buffer
);
125 static DEVICE_ATTR(em_message_supported
, S_IRUGO
, ahci_show_em_supported
, NULL
);
127 struct device_attribute
*ahci_shost_attrs
[] = {
128 &dev_attr_link_power_management_policy
,
129 &dev_attr_em_message_type
,
130 &dev_attr_em_message
,
131 &dev_attr_ahci_host_caps
,
132 &dev_attr_ahci_host_cap2
,
133 &dev_attr_ahci_host_version
,
134 &dev_attr_ahci_port_cmd
,
136 &dev_attr_em_message_supported
,
139 EXPORT_SYMBOL_GPL(ahci_shost_attrs
);
141 struct device_attribute
*ahci_sdev_attrs
[] = {
142 &dev_attr_sw_activity
,
143 &dev_attr_unload_heads
,
146 EXPORT_SYMBOL_GPL(ahci_sdev_attrs
);
148 struct ata_port_operations ahci_ops
= {
149 .inherits
= &sata_pmp_port_ops
,
151 .qc_defer
= ahci_pmp_qc_defer
,
152 .qc_prep
= ahci_qc_prep
,
153 .qc_issue
= ahci_qc_issue
,
154 .qc_fill_rtf
= ahci_qc_fill_rtf
,
156 .freeze
= ahci_freeze
,
158 .softreset
= ahci_softreset
,
159 .hardreset
= ahci_hardreset
,
160 .postreset
= ahci_postreset
,
161 .pmp_softreset
= ahci_softreset
,
162 .error_handler
= ahci_error_handler
,
163 .post_internal_cmd
= ahci_post_internal_cmd
,
164 .dev_config
= ahci_dev_config
,
166 .scr_read
= ahci_scr_read
,
167 .scr_write
= ahci_scr_write
,
168 .pmp_attach
= ahci_pmp_attach
,
169 .pmp_detach
= ahci_pmp_detach
,
171 .set_lpm
= ahci_set_lpm
,
172 .em_show
= ahci_led_show
,
173 .em_store
= ahci_led_store
,
174 .sw_activity_show
= ahci_activity_show
,
175 .sw_activity_store
= ahci_activity_store
,
176 .transmit_led_message
= ahci_transmit_led_message
,
178 .port_suspend
= ahci_port_suspend
,
179 .port_resume
= ahci_port_resume
,
181 .port_start
= ahci_port_start
,
182 .port_stop
= ahci_port_stop
,
184 EXPORT_SYMBOL_GPL(ahci_ops
);
186 struct ata_port_operations ahci_pmp_retry_srst_ops
= {
187 .inherits
= &ahci_ops
,
188 .softreset
= ahci_pmp_retry_softreset
,
190 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops
);
192 int ahci_em_messages
= 1;
193 EXPORT_SYMBOL_GPL(ahci_em_messages
);
194 module_param(ahci_em_messages
, int, 0444);
195 /* add other LED protocol types when they become supported */
196 MODULE_PARM_DESC(ahci_em_messages
,
197 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
199 int devslp_idle_timeout
= 1000; /* device sleep idle timeout in ms */
200 module_param(devslp_idle_timeout
, int, 0644);
201 MODULE_PARM_DESC(devslp_idle_timeout
, "device sleep idle timeout");
203 static void ahci_enable_ahci(void __iomem
*mmio
)
208 /* turn on AHCI_EN */
209 tmp
= readl(mmio
+ HOST_CTL
);
210 if (tmp
& HOST_AHCI_EN
)
213 /* Some controllers need AHCI_EN to be written multiple times.
214 * Try a few times before giving up.
216 for (i
= 0; i
< 5; i
++) {
218 writel(tmp
, mmio
+ HOST_CTL
);
219 tmp
= readl(mmio
+ HOST_CTL
); /* flush && sanity check */
220 if (tmp
& HOST_AHCI_EN
)
228 static ssize_t
ahci_show_host_caps(struct device
*dev
,
229 struct device_attribute
*attr
, char *buf
)
231 struct Scsi_Host
*shost
= class_to_shost(dev
);
232 struct ata_port
*ap
= ata_shost_to_port(shost
);
233 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
235 return sprintf(buf
, "%x\n", hpriv
->cap
);
238 static ssize_t
ahci_show_host_cap2(struct device
*dev
,
239 struct device_attribute
*attr
, char *buf
)
241 struct Scsi_Host
*shost
= class_to_shost(dev
);
242 struct ata_port
*ap
= ata_shost_to_port(shost
);
243 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
245 return sprintf(buf
, "%x\n", hpriv
->cap2
);
248 static ssize_t
ahci_show_host_version(struct device
*dev
,
249 struct device_attribute
*attr
, char *buf
)
251 struct Scsi_Host
*shost
= class_to_shost(dev
);
252 struct ata_port
*ap
= ata_shost_to_port(shost
);
253 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
254 void __iomem
*mmio
= hpriv
->mmio
;
256 return sprintf(buf
, "%x\n", readl(mmio
+ HOST_VERSION
));
259 static ssize_t
ahci_show_port_cmd(struct device
*dev
,
260 struct device_attribute
*attr
, char *buf
)
262 struct Scsi_Host
*shost
= class_to_shost(dev
);
263 struct ata_port
*ap
= ata_shost_to_port(shost
);
264 void __iomem
*port_mmio
= ahci_port_base(ap
);
266 return sprintf(buf
, "%x\n", readl(port_mmio
+ PORT_CMD
));
269 static ssize_t
ahci_read_em_buffer(struct device
*dev
,
270 struct device_attribute
*attr
, char *buf
)
272 struct Scsi_Host
*shost
= class_to_shost(dev
);
273 struct ata_port
*ap
= ata_shost_to_port(shost
);
274 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
275 void __iomem
*mmio
= hpriv
->mmio
;
276 void __iomem
*em_mmio
= mmio
+ hpriv
->em_loc
;
282 spin_lock_irqsave(ap
->lock
, flags
);
284 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
285 if (!(ap
->flags
& ATA_FLAG_EM
) || em_ctl
& EM_CTL_XMT
||
286 !(hpriv
->em_msg_type
& EM_MSG_TYPE_SGPIO
)) {
287 spin_unlock_irqrestore(ap
->lock
, flags
);
291 if (!(em_ctl
& EM_CTL_MR
)) {
292 spin_unlock_irqrestore(ap
->lock
, flags
);
296 if (!(em_ctl
& EM_CTL_SMB
))
297 em_mmio
+= hpriv
->em_buf_sz
;
299 count
= hpriv
->em_buf_sz
;
301 /* the count should not be larger than PAGE_SIZE */
302 if (count
> PAGE_SIZE
) {
303 if (printk_ratelimit())
305 "EM read buffer size too large: "
306 "buffer size %u, page size %lu\n",
307 hpriv
->em_buf_sz
, PAGE_SIZE
);
311 for (i
= 0; i
< count
; i
+= 4) {
312 msg
= readl(em_mmio
+ i
);
314 buf
[i
+ 1] = (msg
>> 8) & 0xff;
315 buf
[i
+ 2] = (msg
>> 16) & 0xff;
316 buf
[i
+ 3] = (msg
>> 24) & 0xff;
319 spin_unlock_irqrestore(ap
->lock
, flags
);
324 static ssize_t
ahci_store_em_buffer(struct device
*dev
,
325 struct device_attribute
*attr
,
326 const char *buf
, size_t size
)
328 struct Scsi_Host
*shost
= class_to_shost(dev
);
329 struct ata_port
*ap
= ata_shost_to_port(shost
);
330 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
331 void __iomem
*mmio
= hpriv
->mmio
;
332 void __iomem
*em_mmio
= mmio
+ hpriv
->em_loc
;
333 const unsigned char *msg_buf
= buf
;
338 /* check size validity */
339 if (!(ap
->flags
& ATA_FLAG_EM
) ||
340 !(hpriv
->em_msg_type
& EM_MSG_TYPE_SGPIO
) ||
341 size
% 4 || size
> hpriv
->em_buf_sz
)
344 spin_lock_irqsave(ap
->lock
, flags
);
346 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
347 if (em_ctl
& EM_CTL_TM
) {
348 spin_unlock_irqrestore(ap
->lock
, flags
);
352 for (i
= 0; i
< size
; i
+= 4) {
353 msg
= msg_buf
[i
] | msg_buf
[i
+ 1] << 8 |
354 msg_buf
[i
+ 2] << 16 | msg_buf
[i
+ 3] << 24;
355 writel(msg
, em_mmio
+ i
);
358 writel(em_ctl
| EM_CTL_TM
, mmio
+ HOST_EM_CTL
);
360 spin_unlock_irqrestore(ap
->lock
, flags
);
365 static ssize_t
ahci_show_em_supported(struct device
*dev
,
366 struct device_attribute
*attr
, char *buf
)
368 struct Scsi_Host
*shost
= class_to_shost(dev
);
369 struct ata_port
*ap
= ata_shost_to_port(shost
);
370 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
371 void __iomem
*mmio
= hpriv
->mmio
;
374 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
376 return sprintf(buf
, "%s%s%s%s\n",
377 em_ctl
& EM_CTL_LED
? "led " : "",
378 em_ctl
& EM_CTL_SAFTE
? "saf-te " : "",
379 em_ctl
& EM_CTL_SES
? "ses-2 " : "",
380 em_ctl
& EM_CTL_SGPIO
? "sgpio " : "");
384 * ahci_save_initial_config - Save and fixup initial config values
385 * @dev: target AHCI device
386 * @hpriv: host private area to store config values
387 * @force_port_map: force port map to a specified value
388 * @mask_port_map: mask out particular bits from port map
390 * Some registers containing configuration info might be setup by
391 * BIOS and might be cleared on reset. This function saves the
392 * initial values of those registers into @hpriv such that they
393 * can be restored after controller reset.
395 * If inconsistent, config values are fixed up by this function.
400 void ahci_save_initial_config(struct device
*dev
,
401 struct ahci_host_priv
*hpriv
,
402 unsigned int force_port_map
,
403 unsigned int mask_port_map
)
405 void __iomem
*mmio
= hpriv
->mmio
;
406 u32 cap
, cap2
, vers
, port_map
;
409 /* make sure AHCI mode is enabled before accessing CAP */
410 ahci_enable_ahci(mmio
);
412 /* Values prefixed with saved_ are written back to host after
413 * reset. Values without are used for driver operation.
415 hpriv
->saved_cap
= cap
= readl(mmio
+ HOST_CAP
);
416 hpriv
->saved_port_map
= port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
418 /* CAP2 register is only defined for AHCI 1.2 and later */
419 vers
= readl(mmio
+ HOST_VERSION
);
420 if ((vers
>> 16) > 1 ||
421 ((vers
>> 16) == 1 && (vers
& 0xFFFF) >= 0x200))
422 hpriv
->saved_cap2
= cap2
= readl(mmio
+ HOST_CAP2
);
424 hpriv
->saved_cap2
= cap2
= 0;
426 /* some chips have errata preventing 64bit use */
427 if ((cap
& HOST_CAP_64
) && (hpriv
->flags
& AHCI_HFLAG_32BIT_ONLY
)) {
428 dev_info(dev
, "controller can't do 64bit DMA, forcing 32bit\n");
432 if ((cap
& HOST_CAP_NCQ
) && (hpriv
->flags
& AHCI_HFLAG_NO_NCQ
)) {
433 dev_info(dev
, "controller can't do NCQ, turning off CAP_NCQ\n");
434 cap
&= ~HOST_CAP_NCQ
;
437 if (!(cap
& HOST_CAP_NCQ
) && (hpriv
->flags
& AHCI_HFLAG_YES_NCQ
)) {
438 dev_info(dev
, "controller can do NCQ, turning on CAP_NCQ\n");
442 if ((cap
& HOST_CAP_PMP
) && (hpriv
->flags
& AHCI_HFLAG_NO_PMP
)) {
443 dev_info(dev
, "controller can't do PMP, turning off CAP_PMP\n");
444 cap
&= ~HOST_CAP_PMP
;
447 if ((cap
& HOST_CAP_SNTF
) && (hpriv
->flags
& AHCI_HFLAG_NO_SNTF
)) {
449 "controller can't do SNTF, turning off CAP_SNTF\n");
450 cap
&= ~HOST_CAP_SNTF
;
453 if (!(cap
& HOST_CAP_FBS
) && (hpriv
->flags
& AHCI_HFLAG_YES_FBS
)) {
454 dev_info(dev
, "controller can do FBS, turning on CAP_FBS\n");
458 if (force_port_map
&& port_map
!= force_port_map
) {
459 dev_info(dev
, "forcing port_map 0x%x -> 0x%x\n",
460 port_map
, force_port_map
);
461 port_map
= force_port_map
;
465 dev_warn(dev
, "masking port_map 0x%x -> 0x%x\n",
467 port_map
& mask_port_map
);
468 port_map
&= mask_port_map
;
471 /* cross check port_map and cap.n_ports */
475 for (i
= 0; i
< AHCI_MAX_PORTS
; i
++)
476 if (port_map
& (1 << i
))
479 /* If PI has more ports than n_ports, whine, clear
480 * port_map and let it be generated from n_ports.
482 if (map_ports
> ahci_nr_ports(cap
)) {
484 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
485 port_map
, ahci_nr_ports(cap
));
490 /* fabricate port_map from cap.nr_ports */
492 port_map
= (1 << ahci_nr_ports(cap
)) - 1;
493 dev_warn(dev
, "forcing PORTS_IMPL to 0x%x\n", port_map
);
495 /* write the fixed up value to the PI register */
496 hpriv
->saved_port_map
= port_map
;
499 /* record values to use during operation */
502 hpriv
->port_map
= port_map
;
504 EXPORT_SYMBOL_GPL(ahci_save_initial_config
);
507 * ahci_restore_initial_config - Restore initial config
508 * @host: target ATA host
510 * Restore initial config stored by ahci_save_initial_config().
515 static void ahci_restore_initial_config(struct ata_host
*host
)
517 struct ahci_host_priv
*hpriv
= host
->private_data
;
518 void __iomem
*mmio
= hpriv
->mmio
;
520 writel(hpriv
->saved_cap
, mmio
+ HOST_CAP
);
521 if (hpriv
->saved_cap2
)
522 writel(hpriv
->saved_cap2
, mmio
+ HOST_CAP2
);
523 writel(hpriv
->saved_port_map
, mmio
+ HOST_PORTS_IMPL
);
524 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
527 static unsigned ahci_scr_offset(struct ata_port
*ap
, unsigned int sc_reg
)
529 static const int offset
[] = {
530 [SCR_STATUS
] = PORT_SCR_STAT
,
531 [SCR_CONTROL
] = PORT_SCR_CTL
,
532 [SCR_ERROR
] = PORT_SCR_ERR
,
533 [SCR_ACTIVE
] = PORT_SCR_ACT
,
534 [SCR_NOTIFICATION
] = PORT_SCR_NTF
,
536 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
538 if (sc_reg
< ARRAY_SIZE(offset
) &&
539 (sc_reg
!= SCR_NOTIFICATION
|| (hpriv
->cap
& HOST_CAP_SNTF
)))
540 return offset
[sc_reg
];
544 static int ahci_scr_read(struct ata_link
*link
, unsigned int sc_reg
, u32
*val
)
546 void __iomem
*port_mmio
= ahci_port_base(link
->ap
);
547 int offset
= ahci_scr_offset(link
->ap
, sc_reg
);
550 *val
= readl(port_mmio
+ offset
);
556 static int ahci_scr_write(struct ata_link
*link
, unsigned int sc_reg
, u32 val
)
558 void __iomem
*port_mmio
= ahci_port_base(link
->ap
);
559 int offset
= ahci_scr_offset(link
->ap
, sc_reg
);
562 writel(val
, port_mmio
+ offset
);
568 void ahci_start_engine(struct ata_port
*ap
)
570 void __iomem
*port_mmio
= ahci_port_base(ap
);
574 tmp
= readl(port_mmio
+ PORT_CMD
);
575 tmp
|= PORT_CMD_START
;
576 writel(tmp
, port_mmio
+ PORT_CMD
);
577 readl(port_mmio
+ PORT_CMD
); /* flush */
579 EXPORT_SYMBOL_GPL(ahci_start_engine
);
581 int ahci_stop_engine(struct ata_port
*ap
)
583 void __iomem
*port_mmio
= ahci_port_base(ap
);
586 tmp
= readl(port_mmio
+ PORT_CMD
);
588 /* check if the HBA is idle */
589 if ((tmp
& (PORT_CMD_START
| PORT_CMD_LIST_ON
)) == 0)
592 /* setting HBA to idle */
593 tmp
&= ~PORT_CMD_START
;
594 writel(tmp
, port_mmio
+ PORT_CMD
);
596 /* wait for engine to stop. This could be as long as 500 msec */
597 tmp
= ata_wait_register(ap
, port_mmio
+ PORT_CMD
,
598 PORT_CMD_LIST_ON
, PORT_CMD_LIST_ON
, 1, 500);
599 if (tmp
& PORT_CMD_LIST_ON
)
604 EXPORT_SYMBOL_GPL(ahci_stop_engine
);
606 static void ahci_start_fis_rx(struct ata_port
*ap
)
608 void __iomem
*port_mmio
= ahci_port_base(ap
);
609 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
610 struct ahci_port_priv
*pp
= ap
->private_data
;
613 /* set FIS registers */
614 if (hpriv
->cap
& HOST_CAP_64
)
615 writel((pp
->cmd_slot_dma
>> 16) >> 16,
616 port_mmio
+ PORT_LST_ADDR_HI
);
617 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
619 if (hpriv
->cap
& HOST_CAP_64
)
620 writel((pp
->rx_fis_dma
>> 16) >> 16,
621 port_mmio
+ PORT_FIS_ADDR_HI
);
622 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
624 /* enable FIS reception */
625 tmp
= readl(port_mmio
+ PORT_CMD
);
626 tmp
|= PORT_CMD_FIS_RX
;
627 writel(tmp
, port_mmio
+ PORT_CMD
);
630 readl(port_mmio
+ PORT_CMD
);
633 static int ahci_stop_fis_rx(struct ata_port
*ap
)
635 void __iomem
*port_mmio
= ahci_port_base(ap
);
638 /* disable FIS reception */
639 tmp
= readl(port_mmio
+ PORT_CMD
);
640 tmp
&= ~PORT_CMD_FIS_RX
;
641 writel(tmp
, port_mmio
+ PORT_CMD
);
643 /* wait for completion, spec says 500ms, give it 1000 */
644 tmp
= ata_wait_register(ap
, port_mmio
+ PORT_CMD
, PORT_CMD_FIS_ON
,
645 PORT_CMD_FIS_ON
, 10, 1000);
646 if (tmp
& PORT_CMD_FIS_ON
)
652 static void ahci_power_up(struct ata_port
*ap
)
654 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
655 void __iomem
*port_mmio
= ahci_port_base(ap
);
658 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
661 if (hpriv
->cap
& HOST_CAP_SSS
) {
662 cmd
|= PORT_CMD_SPIN_UP
;
663 writel(cmd
, port_mmio
+ PORT_CMD
);
667 writel(cmd
| PORT_CMD_ICC_ACTIVE
, port_mmio
+ PORT_CMD
);
670 static int ahci_set_lpm(struct ata_link
*link
, enum ata_lpm_policy policy
,
673 struct ata_port
*ap
= link
->ap
;
674 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
675 struct ahci_port_priv
*pp
= ap
->private_data
;
676 void __iomem
*port_mmio
= ahci_port_base(ap
);
678 if (policy
!= ATA_LPM_MAX_POWER
) {
680 * Disable interrupts on Phy Ready. This keeps us from
681 * getting woken up due to spurious phy ready
684 pp
->intr_mask
&= ~PORT_IRQ_PHYRDY
;
685 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
687 sata_link_scr_lpm(link
, policy
, false);
690 if (hpriv
->cap
& HOST_CAP_ALPM
) {
691 u32 cmd
= readl(port_mmio
+ PORT_CMD
);
693 if (policy
== ATA_LPM_MAX_POWER
|| !(hints
& ATA_LPM_HIPM
)) {
694 cmd
&= ~(PORT_CMD_ASP
| PORT_CMD_ALPE
);
695 cmd
|= PORT_CMD_ICC_ACTIVE
;
697 writel(cmd
, port_mmio
+ PORT_CMD
);
698 readl(port_mmio
+ PORT_CMD
);
700 /* wait 10ms to be sure we've come out of LPM state */
703 cmd
|= PORT_CMD_ALPE
;
704 if (policy
== ATA_LPM_MIN_POWER
)
707 /* write out new cmd value */
708 writel(cmd
, port_mmio
+ PORT_CMD
);
712 /* set aggressive device sleep */
713 if ((hpriv
->cap2
& HOST_CAP2_SDS
) &&
714 (hpriv
->cap2
& HOST_CAP2_SADM
) &&
715 (link
->device
->flags
& ATA_DFLAG_DEVSLP
)) {
716 if (policy
== ATA_LPM_MIN_POWER
)
717 ahci_set_aggressive_devslp(ap
, true);
719 ahci_set_aggressive_devslp(ap
, false);
722 if (policy
== ATA_LPM_MAX_POWER
) {
723 sata_link_scr_lpm(link
, policy
, false);
725 /* turn PHYRDY IRQ back on */
726 pp
->intr_mask
|= PORT_IRQ_PHYRDY
;
727 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
734 static void ahci_power_down(struct ata_port
*ap
)
736 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
737 void __iomem
*port_mmio
= ahci_port_base(ap
);
740 if (!(hpriv
->cap
& HOST_CAP_SSS
))
743 /* put device into listen mode, first set PxSCTL.DET to 0 */
744 scontrol
= readl(port_mmio
+ PORT_SCR_CTL
);
746 writel(scontrol
, port_mmio
+ PORT_SCR_CTL
);
748 /* then set PxCMD.SUD to 0 */
749 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
750 cmd
&= ~PORT_CMD_SPIN_UP
;
751 writel(cmd
, port_mmio
+ PORT_CMD
);
755 static void ahci_start_port(struct ata_port
*ap
)
757 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
758 struct ahci_port_priv
*pp
= ap
->private_data
;
759 struct ata_link
*link
;
760 struct ahci_em_priv
*emp
;
764 /* enable FIS reception */
765 ahci_start_fis_rx(ap
);
768 if (!(hpriv
->flags
& AHCI_HFLAG_DELAY_ENGINE
))
769 ahci_start_engine(ap
);
772 if (ap
->flags
& ATA_FLAG_EM
) {
773 ata_for_each_link(link
, ap
, EDGE
) {
774 emp
= &pp
->em_priv
[link
->pmp
];
776 /* EM Transmit bit maybe busy during init */
777 for (i
= 0; i
< EM_MAX_RETRY
; i
++) {
778 rc
= ap
->ops
->transmit_led_message(ap
,
782 * If busy, give a breather but do not
783 * release EH ownership by using msleep()
784 * instead of ata_msleep(). EM Transmit
785 * bit is busy for the whole host and
786 * releasing ownership will cause other
787 * ports to fail the same way.
797 if (ap
->flags
& ATA_FLAG_SW_ACTIVITY
)
798 ata_for_each_link(link
, ap
, EDGE
)
799 ahci_init_sw_activity(link
);
803 static int ahci_deinit_port(struct ata_port
*ap
, const char **emsg
)
808 rc
= ahci_stop_engine(ap
);
810 *emsg
= "failed to stop engine";
814 /* disable FIS reception */
815 rc
= ahci_stop_fis_rx(ap
);
817 *emsg
= "failed stop FIS RX";
824 int ahci_reset_controller(struct ata_host
*host
)
826 struct ahci_host_priv
*hpriv
= host
->private_data
;
827 void __iomem
*mmio
= hpriv
->mmio
;
830 /* we must be in AHCI mode, before using anything
831 * AHCI-specific, such as HOST_RESET.
833 ahci_enable_ahci(mmio
);
835 /* global controller reset */
836 if (!ahci_skip_host_reset
) {
837 tmp
= readl(mmio
+ HOST_CTL
);
838 if ((tmp
& HOST_RESET
) == 0) {
839 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
840 readl(mmio
+ HOST_CTL
); /* flush */
844 * to perform host reset, OS should set HOST_RESET
845 * and poll until this bit is read to be "0".
846 * reset must complete within 1 second, or
847 * the hardware should be considered fried.
849 tmp
= ata_wait_register(NULL
, mmio
+ HOST_CTL
, HOST_RESET
,
850 HOST_RESET
, 10, 1000);
852 if (tmp
& HOST_RESET
) {
853 dev_err(host
->dev
, "controller reset failed (0x%x)\n",
858 /* turn on AHCI mode */
859 ahci_enable_ahci(mmio
);
861 /* Some registers might be cleared on reset. Restore
864 ahci_restore_initial_config(host
);
866 dev_info(host
->dev
, "skipping global host reset\n");
870 EXPORT_SYMBOL_GPL(ahci_reset_controller
);
872 static void ahci_sw_activity(struct ata_link
*link
)
874 struct ata_port
*ap
= link
->ap
;
875 struct ahci_port_priv
*pp
= ap
->private_data
;
876 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
878 if (!(link
->flags
& ATA_LFLAG_SW_ACTIVITY
))
882 if (!timer_pending(&emp
->timer
))
883 mod_timer(&emp
->timer
, jiffies
+ msecs_to_jiffies(10));
886 static void ahci_sw_activity_blink(unsigned long arg
)
888 struct ata_link
*link
= (struct ata_link
*)arg
;
889 struct ata_port
*ap
= link
->ap
;
890 struct ahci_port_priv
*pp
= ap
->private_data
;
891 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
892 unsigned long led_message
= emp
->led_state
;
893 u32 activity_led_state
;
896 led_message
&= EM_MSG_LED_VALUE
;
897 led_message
|= ap
->port_no
| (link
->pmp
<< 8);
899 /* check to see if we've had activity. If so,
900 * toggle state of LED and reset timer. If not,
901 * turn LED to desired idle state.
903 spin_lock_irqsave(ap
->lock
, flags
);
904 if (emp
->saved_activity
!= emp
->activity
) {
905 emp
->saved_activity
= emp
->activity
;
906 /* get the current LED state */
907 activity_led_state
= led_message
& EM_MSG_LED_VALUE_ON
;
909 if (activity_led_state
)
910 activity_led_state
= 0;
912 activity_led_state
= 1;
914 /* clear old state */
915 led_message
&= ~EM_MSG_LED_VALUE_ACTIVITY
;
918 led_message
|= (activity_led_state
<< 16);
919 mod_timer(&emp
->timer
, jiffies
+ msecs_to_jiffies(100));
922 led_message
&= ~EM_MSG_LED_VALUE_ACTIVITY
;
923 if (emp
->blink_policy
== BLINK_OFF
)
924 led_message
|= (1 << 16);
926 spin_unlock_irqrestore(ap
->lock
, flags
);
927 ap
->ops
->transmit_led_message(ap
, led_message
, 4);
930 static void ahci_init_sw_activity(struct ata_link
*link
)
932 struct ata_port
*ap
= link
->ap
;
933 struct ahci_port_priv
*pp
= ap
->private_data
;
934 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
936 /* init activity stats, setup timer */
937 emp
->saved_activity
= emp
->activity
= 0;
938 setup_timer(&emp
->timer
, ahci_sw_activity_blink
, (unsigned long)link
);
940 /* check our blink policy and set flag for link if it's enabled */
941 if (emp
->blink_policy
)
942 link
->flags
|= ATA_LFLAG_SW_ACTIVITY
;
945 int ahci_reset_em(struct ata_host
*host
)
947 struct ahci_host_priv
*hpriv
= host
->private_data
;
948 void __iomem
*mmio
= hpriv
->mmio
;
951 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
952 if ((em_ctl
& EM_CTL_TM
) || (em_ctl
& EM_CTL_RST
))
955 writel(em_ctl
| EM_CTL_RST
, mmio
+ HOST_EM_CTL
);
958 EXPORT_SYMBOL_GPL(ahci_reset_em
);
960 static ssize_t
ahci_transmit_led_message(struct ata_port
*ap
, u32 state
,
963 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
964 struct ahci_port_priv
*pp
= ap
->private_data
;
965 void __iomem
*mmio
= hpriv
->mmio
;
967 u32 message
[] = {0, 0};
970 struct ahci_em_priv
*emp
;
972 /* get the slot number from the message */
973 pmp
= (state
& EM_MSG_LED_PMP_SLOT
) >> 8;
974 if (pmp
< EM_MAX_SLOTS
)
975 emp
= &pp
->em_priv
[pmp
];
979 spin_lock_irqsave(ap
->lock
, flags
);
982 * if we are still busy transmitting a previous message,
985 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
986 if (em_ctl
& EM_CTL_TM
) {
987 spin_unlock_irqrestore(ap
->lock
, flags
);
991 if (hpriv
->em_msg_type
& EM_MSG_TYPE_LED
) {
993 * create message header - this is all zero except for
994 * the message size, which is 4 bytes.
996 message
[0] |= (4 << 8);
998 /* ignore 0:4 of byte zero, fill in port info yourself */
999 message
[1] = ((state
& ~EM_MSG_LED_HBA_PORT
) | ap
->port_no
);
1001 /* write message to EM_LOC */
1002 writel(message
[0], mmio
+ hpriv
->em_loc
);
1003 writel(message
[1], mmio
+ hpriv
->em_loc
+4);
1006 * tell hardware to transmit the message
1008 writel(em_ctl
| EM_CTL_TM
, mmio
+ HOST_EM_CTL
);
1011 /* save off new led state for port/slot */
1012 emp
->led_state
= state
;
1014 spin_unlock_irqrestore(ap
->lock
, flags
);
1018 static ssize_t
ahci_led_show(struct ata_port
*ap
, char *buf
)
1020 struct ahci_port_priv
*pp
= ap
->private_data
;
1021 struct ata_link
*link
;
1022 struct ahci_em_priv
*emp
;
1025 ata_for_each_link(link
, ap
, EDGE
) {
1026 emp
= &pp
->em_priv
[link
->pmp
];
1027 rc
+= sprintf(buf
, "%lx\n", emp
->led_state
);
1032 static ssize_t
ahci_led_store(struct ata_port
*ap
, const char *buf
,
1037 struct ahci_port_priv
*pp
= ap
->private_data
;
1038 struct ahci_em_priv
*emp
;
1040 state
= simple_strtoul(buf
, NULL
, 0);
1042 /* get the slot number from the message */
1043 pmp
= (state
& EM_MSG_LED_PMP_SLOT
) >> 8;
1044 if (pmp
< EM_MAX_SLOTS
)
1045 emp
= &pp
->em_priv
[pmp
];
1049 /* mask off the activity bits if we are in sw_activity
1050 * mode, user should turn off sw_activity before setting
1051 * activity led through em_message
1053 if (emp
->blink_policy
)
1054 state
&= ~EM_MSG_LED_VALUE_ACTIVITY
;
1056 return ap
->ops
->transmit_led_message(ap
, state
, size
);
1059 static ssize_t
ahci_activity_store(struct ata_device
*dev
, enum sw_activity val
)
1061 struct ata_link
*link
= dev
->link
;
1062 struct ata_port
*ap
= link
->ap
;
1063 struct ahci_port_priv
*pp
= ap
->private_data
;
1064 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
1065 u32 port_led_state
= emp
->led_state
;
1067 /* save the desired Activity LED behavior */
1070 link
->flags
&= ~(ATA_LFLAG_SW_ACTIVITY
);
1072 /* set the LED to OFF */
1073 port_led_state
&= EM_MSG_LED_VALUE_OFF
;
1074 port_led_state
|= (ap
->port_no
| (link
->pmp
<< 8));
1075 ap
->ops
->transmit_led_message(ap
, port_led_state
, 4);
1077 link
->flags
|= ATA_LFLAG_SW_ACTIVITY
;
1078 if (val
== BLINK_OFF
) {
1079 /* set LED to ON for idle */
1080 port_led_state
&= EM_MSG_LED_VALUE_OFF
;
1081 port_led_state
|= (ap
->port_no
| (link
->pmp
<< 8));
1082 port_led_state
|= EM_MSG_LED_VALUE_ON
; /* check this */
1083 ap
->ops
->transmit_led_message(ap
, port_led_state
, 4);
1086 emp
->blink_policy
= val
;
1090 static ssize_t
ahci_activity_show(struct ata_device
*dev
, char *buf
)
1092 struct ata_link
*link
= dev
->link
;
1093 struct ata_port
*ap
= link
->ap
;
1094 struct ahci_port_priv
*pp
= ap
->private_data
;
1095 struct ahci_em_priv
*emp
= &pp
->em_priv
[link
->pmp
];
1097 /* display the saved value of activity behavior for this
1100 return sprintf(buf
, "%d\n", emp
->blink_policy
);
1103 static void ahci_port_init(struct device
*dev
, struct ata_port
*ap
,
1104 int port_no
, void __iomem
*mmio
,
1105 void __iomem
*port_mmio
)
1107 const char *emsg
= NULL
;
1111 /* make sure port is not active */
1112 rc
= ahci_deinit_port(ap
, &emsg
);
1114 dev_warn(dev
, "%s (%d)\n", emsg
, rc
);
1117 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
1118 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
1119 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
1121 /* clear port IRQ */
1122 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1123 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
1125 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1127 writel(1 << port_no
, mmio
+ HOST_IRQ_STAT
);
1130 void ahci_init_controller(struct ata_host
*host
)
1132 struct ahci_host_priv
*hpriv
= host
->private_data
;
1133 void __iomem
*mmio
= hpriv
->mmio
;
1135 void __iomem
*port_mmio
;
1138 for (i
= 0; i
< host
->n_ports
; i
++) {
1139 struct ata_port
*ap
= host
->ports
[i
];
1141 port_mmio
= ahci_port_base(ap
);
1142 if (ata_port_is_dummy(ap
))
1145 ahci_port_init(host
->dev
, ap
, i
, mmio
, port_mmio
);
1148 tmp
= readl(mmio
+ HOST_CTL
);
1149 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1150 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
1151 tmp
= readl(mmio
+ HOST_CTL
);
1152 VPRINTK("HOST_CTL 0x%x\n", tmp
);
1154 EXPORT_SYMBOL_GPL(ahci_init_controller
);
1156 static void ahci_dev_config(struct ata_device
*dev
)
1158 struct ahci_host_priv
*hpriv
= dev
->link
->ap
->host
->private_data
;
1160 if (hpriv
->flags
& AHCI_HFLAG_SECT255
) {
1161 dev
->max_sectors
= 255;
1163 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1167 unsigned int ahci_dev_classify(struct ata_port
*ap
)
1169 void __iomem
*port_mmio
= ahci_port_base(ap
);
1170 struct ata_taskfile tf
;
1173 tmp
= readl(port_mmio
+ PORT_SIG
);
1174 tf
.lbah
= (tmp
>> 24) & 0xff;
1175 tf
.lbam
= (tmp
>> 16) & 0xff;
1176 tf
.lbal
= (tmp
>> 8) & 0xff;
1177 tf
.nsect
= (tmp
) & 0xff;
1179 return ata_dev_classify(&tf
);
1181 EXPORT_SYMBOL_GPL(ahci_dev_classify
);
1183 void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, unsigned int tag
,
1186 dma_addr_t cmd_tbl_dma
;
1188 cmd_tbl_dma
= pp
->cmd_tbl_dma
+ tag
* AHCI_CMD_TBL_SZ
;
1190 pp
->cmd_slot
[tag
].opts
= cpu_to_le32(opts
);
1191 pp
->cmd_slot
[tag
].status
= 0;
1192 pp
->cmd_slot
[tag
].tbl_addr
= cpu_to_le32(cmd_tbl_dma
& 0xffffffff);
1193 pp
->cmd_slot
[tag
].tbl_addr_hi
= cpu_to_le32((cmd_tbl_dma
>> 16) >> 16);
1195 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot
);
1197 int ahci_kick_engine(struct ata_port
*ap
)
1199 void __iomem
*port_mmio
= ahci_port_base(ap
);
1200 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1201 u8 status
= readl(port_mmio
+ PORT_TFDATA
) & 0xFF;
1206 rc
= ahci_stop_engine(ap
);
1211 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1213 busy
= status
& (ATA_BUSY
| ATA_DRQ
);
1214 if (!busy
&& !sata_pmp_attached(ap
)) {
1219 if (!(hpriv
->cap
& HOST_CAP_CLO
)) {
1225 tmp
= readl(port_mmio
+ PORT_CMD
);
1226 tmp
|= PORT_CMD_CLO
;
1227 writel(tmp
, port_mmio
+ PORT_CMD
);
1230 tmp
= ata_wait_register(ap
, port_mmio
+ PORT_CMD
,
1231 PORT_CMD_CLO
, PORT_CMD_CLO
, 1, 500);
1232 if (tmp
& PORT_CMD_CLO
)
1235 /* restart engine */
1237 ahci_start_engine(ap
);
1240 EXPORT_SYMBOL_GPL(ahci_kick_engine
);
1242 static int ahci_exec_polled_cmd(struct ata_port
*ap
, int pmp
,
1243 struct ata_taskfile
*tf
, int is_cmd
, u16 flags
,
1244 unsigned long timeout_msec
)
1246 const u32 cmd_fis_len
= 5; /* five dwords */
1247 struct ahci_port_priv
*pp
= ap
->private_data
;
1248 void __iomem
*port_mmio
= ahci_port_base(ap
);
1249 u8
*fis
= pp
->cmd_tbl
;
1252 /* prep the command */
1253 ata_tf_to_fis(tf
, pmp
, is_cmd
, fis
);
1254 ahci_fill_cmd_slot(pp
, 0, cmd_fis_len
| flags
| (pmp
<< 12));
1257 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
1260 tmp
= ata_wait_register(ap
, port_mmio
+ PORT_CMD_ISSUE
,
1261 0x1, 0x1, 1, timeout_msec
);
1263 ahci_kick_engine(ap
);
1267 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
1272 int ahci_do_softreset(struct ata_link
*link
, unsigned int *class,
1273 int pmp
, unsigned long deadline
,
1274 int (*check_ready
)(struct ata_link
*link
))
1276 struct ata_port
*ap
= link
->ap
;
1277 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1278 const char *reason
= NULL
;
1279 unsigned long now
, msecs
;
1280 struct ata_taskfile tf
;
1285 /* prepare for SRST (AHCI-1.1 10.4.1) */
1286 rc
= ahci_kick_engine(ap
);
1287 if (rc
&& rc
!= -EOPNOTSUPP
)
1288 ata_link_warn(link
, "failed to reset engine (errno=%d)\n", rc
);
1290 ata_tf_init(link
->device
, &tf
);
1292 /* issue the first D2H Register FIS */
1295 if (time_after(deadline
, now
))
1296 msecs
= jiffies_to_msecs(deadline
- now
);
1299 if (ahci_exec_polled_cmd(ap
, pmp
, &tf
, 0,
1300 AHCI_CMD_RESET
| AHCI_CMD_CLR_BUSY
, msecs
)) {
1302 reason
= "1st FIS failed";
1306 /* spec says at least 5us, but be generous and sleep for 1ms */
1309 /* issue the second D2H Register FIS */
1310 tf
.ctl
&= ~ATA_SRST
;
1311 ahci_exec_polled_cmd(ap
, pmp
, &tf
, 0, 0, 0);
1313 /* wait for link to become ready */
1314 rc
= ata_wait_after_reset(link
, deadline
, check_ready
);
1315 if (rc
== -EBUSY
&& hpriv
->flags
& AHCI_HFLAG_SRST_TOUT_IS_OFFLINE
) {
1317 * Workaround for cases where link online status can't
1318 * be trusted. Treat device readiness timeout as link
1321 ata_link_info(link
, "device not ready, treating as offline\n");
1322 *class = ATA_DEV_NONE
;
1324 /* link occupied, -ENODEV too is an error */
1325 reason
= "device not ready";
1328 *class = ahci_dev_classify(ap
);
1330 DPRINTK("EXIT, class=%u\n", *class);
1334 ata_link_err(link
, "softreset failed (%s)\n", reason
);
1338 int ahci_check_ready(struct ata_link
*link
)
1340 void __iomem
*port_mmio
= ahci_port_base(link
->ap
);
1341 u8 status
= readl(port_mmio
+ PORT_TFDATA
) & 0xFF;
1343 return ata_check_ready(status
);
1345 EXPORT_SYMBOL_GPL(ahci_check_ready
);
1347 static int ahci_softreset(struct ata_link
*link
, unsigned int *class,
1348 unsigned long deadline
)
1350 int pmp
= sata_srst_pmp(link
);
1354 return ahci_do_softreset(link
, class, pmp
, deadline
, ahci_check_ready
);
1356 EXPORT_SYMBOL_GPL(ahci_do_softreset
);
1358 static int ahci_bad_pmp_check_ready(struct ata_link
*link
)
1360 void __iomem
*port_mmio
= ahci_port_base(link
->ap
);
1361 u8 status
= readl(port_mmio
+ PORT_TFDATA
) & 0xFF;
1362 u32 irq_status
= readl(port_mmio
+ PORT_IRQ_STAT
);
1365 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1366 * which can save timeout delay.
1368 if (irq_status
& PORT_IRQ_BAD_PMP
)
1371 return ata_check_ready(status
);
1374 int ahci_pmp_retry_softreset(struct ata_link
*link
, unsigned int *class,
1375 unsigned long deadline
)
1377 struct ata_port
*ap
= link
->ap
;
1378 void __iomem
*port_mmio
= ahci_port_base(ap
);
1379 int pmp
= sata_srst_pmp(link
);
1385 rc
= ahci_do_softreset(link
, class, pmp
, deadline
,
1386 ahci_bad_pmp_check_ready
);
1389 * Soft reset fails with IPMS set when PMP is enabled but
1390 * SATA HDD/ODD is connected to SATA port, do soft reset
1394 irq_sts
= readl(port_mmio
+ PORT_IRQ_STAT
);
1395 if (irq_sts
& PORT_IRQ_BAD_PMP
) {
1397 "applying PMP SRST workaround "
1399 rc
= ahci_do_softreset(link
, class, 0, deadline
,
1407 static int ahci_hardreset(struct ata_link
*link
, unsigned int *class,
1408 unsigned long deadline
)
1410 const unsigned long *timing
= sata_ehc_deb_timing(&link
->eh_context
);
1411 struct ata_port
*ap
= link
->ap
;
1412 struct ahci_port_priv
*pp
= ap
->private_data
;
1413 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
1414 struct ata_taskfile tf
;
1420 ahci_stop_engine(ap
);
1422 /* clear D2H reception area to properly wait for D2H FIS */
1423 ata_tf_init(link
->device
, &tf
);
1424 tf
.command
= ATA_BUSY
;
1425 ata_tf_to_fis(&tf
, 0, 0, d2h_fis
);
1427 rc
= sata_link_hardreset(link
, timing
, deadline
, &online
,
1430 ahci_start_engine(ap
);
1433 *class = ahci_dev_classify(ap
);
1435 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
1439 static void ahci_postreset(struct ata_link
*link
, unsigned int *class)
1441 struct ata_port
*ap
= link
->ap
;
1442 void __iomem
*port_mmio
= ahci_port_base(ap
);
1445 ata_std_postreset(link
, class);
1447 /* Make sure port's ATAPI bit is set appropriately */
1448 new_tmp
= tmp
= readl(port_mmio
+ PORT_CMD
);
1449 if (*class == ATA_DEV_ATAPI
)
1450 new_tmp
|= PORT_CMD_ATAPI
;
1452 new_tmp
&= ~PORT_CMD_ATAPI
;
1453 if (new_tmp
!= tmp
) {
1454 writel(new_tmp
, port_mmio
+ PORT_CMD
);
1455 readl(port_mmio
+ PORT_CMD
); /* flush */
1459 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_tbl
)
1461 struct scatterlist
*sg
;
1462 struct ahci_sg
*ahci_sg
= cmd_tbl
+ AHCI_CMD_TBL_HDR_SZ
;
1468 * Next, the S/G list.
1470 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
1471 dma_addr_t addr
= sg_dma_address(sg
);
1472 u32 sg_len
= sg_dma_len(sg
);
1474 ahci_sg
[si
].addr
= cpu_to_le32(addr
& 0xffffffff);
1475 ahci_sg
[si
].addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
1476 ahci_sg
[si
].flags_size
= cpu_to_le32(sg_len
- 1);
1482 static int ahci_pmp_qc_defer(struct ata_queued_cmd
*qc
)
1484 struct ata_port
*ap
= qc
->ap
;
1485 struct ahci_port_priv
*pp
= ap
->private_data
;
1487 if (!sata_pmp_attached(ap
) || pp
->fbs_enabled
)
1488 return ata_std_qc_defer(qc
);
1490 return sata_pmp_qc_defer_cmd_switch(qc
);
1493 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
1495 struct ata_port
*ap
= qc
->ap
;
1496 struct ahci_port_priv
*pp
= ap
->private_data
;
1497 int is_atapi
= ata_is_atapi(qc
->tf
.protocol
);
1500 const u32 cmd_fis_len
= 5; /* five dwords */
1501 unsigned int n_elem
;
1504 * Fill in command table information. First, the header,
1505 * a SATA Register - Host to Device command FIS.
1507 cmd_tbl
= pp
->cmd_tbl
+ qc
->tag
* AHCI_CMD_TBL_SZ
;
1509 ata_tf_to_fis(&qc
->tf
, qc
->dev
->link
->pmp
, 1, cmd_tbl
);
1511 memset(cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
1512 memcpy(cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
, qc
->dev
->cdb_len
);
1516 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
1517 n_elem
= ahci_fill_sg(qc
, cmd_tbl
);
1520 * Fill in command slot information.
1522 opts
= cmd_fis_len
| n_elem
<< 16 | (qc
->dev
->link
->pmp
<< 12);
1523 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
1524 opts
|= AHCI_CMD_WRITE
;
1526 opts
|= AHCI_CMD_ATAPI
| AHCI_CMD_PREFETCH
;
1528 ahci_fill_cmd_slot(pp
, qc
->tag
, opts
);
1531 static void ahci_fbs_dec_intr(struct ata_port
*ap
)
1533 struct ahci_port_priv
*pp
= ap
->private_data
;
1534 void __iomem
*port_mmio
= ahci_port_base(ap
);
1535 u32 fbs
= readl(port_mmio
+ PORT_FBS
);
1539 BUG_ON(!pp
->fbs_enabled
);
1541 /* time to wait for DEC is not specified by AHCI spec,
1542 * add a retry loop for safety.
1544 writel(fbs
| PORT_FBS_DEC
, port_mmio
+ PORT_FBS
);
1545 fbs
= readl(port_mmio
+ PORT_FBS
);
1546 while ((fbs
& PORT_FBS_DEC
) && retries
--) {
1548 fbs
= readl(port_mmio
+ PORT_FBS
);
1551 if (fbs
& PORT_FBS_DEC
)
1552 dev_err(ap
->host
->dev
, "failed to clear device error\n");
1555 static void ahci_error_intr(struct ata_port
*ap
, u32 irq_stat
)
1557 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1558 struct ahci_port_priv
*pp
= ap
->private_data
;
1559 struct ata_eh_info
*host_ehi
= &ap
->link
.eh_info
;
1560 struct ata_link
*link
= NULL
;
1561 struct ata_queued_cmd
*active_qc
;
1562 struct ata_eh_info
*active_ehi
;
1563 bool fbs_need_dec
= false;
1566 /* determine active link with error */
1567 if (pp
->fbs_enabled
) {
1568 void __iomem
*port_mmio
= ahci_port_base(ap
);
1569 u32 fbs
= readl(port_mmio
+ PORT_FBS
);
1570 int pmp
= fbs
>> PORT_FBS_DWE_OFFSET
;
1572 if ((fbs
& PORT_FBS_SDE
) && (pmp
< ap
->nr_pmp_links
)) {
1573 link
= &ap
->pmp_link
[pmp
];
1574 fbs_need_dec
= true;
1578 ata_for_each_link(link
, ap
, EDGE
)
1579 if (ata_link_active(link
))
1585 active_qc
= ata_qc_from_tag(ap
, link
->active_tag
);
1586 active_ehi
= &link
->eh_info
;
1588 /* record irq stat */
1589 ata_ehi_clear_desc(host_ehi
);
1590 ata_ehi_push_desc(host_ehi
, "irq_stat 0x%08x", irq_stat
);
1592 /* AHCI needs SError cleared; otherwise, it might lock up */
1593 ahci_scr_read(&ap
->link
, SCR_ERROR
, &serror
);
1594 ahci_scr_write(&ap
->link
, SCR_ERROR
, serror
);
1595 host_ehi
->serror
|= serror
;
1597 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1598 if (hpriv
->flags
& AHCI_HFLAG_IGN_IRQ_IF_ERR
)
1599 irq_stat
&= ~PORT_IRQ_IF_ERR
;
1601 if (irq_stat
& PORT_IRQ_TF_ERR
) {
1602 /* If qc is active, charge it; otherwise, the active
1603 * link. There's no active qc on NCQ errors. It will
1604 * be determined by EH by reading log page 10h.
1607 active_qc
->err_mask
|= AC_ERR_DEV
;
1609 active_ehi
->err_mask
|= AC_ERR_DEV
;
1611 if (hpriv
->flags
& AHCI_HFLAG_IGN_SERR_INTERNAL
)
1612 host_ehi
->serror
&= ~SERR_INTERNAL
;
1615 if (irq_stat
& PORT_IRQ_UNK_FIS
) {
1616 u32
*unk
= (u32
*)(pp
->rx_fis
+ RX_FIS_UNK
);
1618 active_ehi
->err_mask
|= AC_ERR_HSM
;
1619 active_ehi
->action
|= ATA_EH_RESET
;
1620 ata_ehi_push_desc(active_ehi
,
1621 "unknown FIS %08x %08x %08x %08x" ,
1622 unk
[0], unk
[1], unk
[2], unk
[3]);
1625 if (sata_pmp_attached(ap
) && (irq_stat
& PORT_IRQ_BAD_PMP
)) {
1626 active_ehi
->err_mask
|= AC_ERR_HSM
;
1627 active_ehi
->action
|= ATA_EH_RESET
;
1628 ata_ehi_push_desc(active_ehi
, "incorrect PMP");
1631 if (irq_stat
& (PORT_IRQ_HBUS_ERR
| PORT_IRQ_HBUS_DATA_ERR
)) {
1632 host_ehi
->err_mask
|= AC_ERR_HOST_BUS
;
1633 host_ehi
->action
|= ATA_EH_RESET
;
1634 ata_ehi_push_desc(host_ehi
, "host bus error");
1637 if (irq_stat
& PORT_IRQ_IF_ERR
) {
1639 active_ehi
->err_mask
|= AC_ERR_DEV
;
1641 host_ehi
->err_mask
|= AC_ERR_ATA_BUS
;
1642 host_ehi
->action
|= ATA_EH_RESET
;
1645 ata_ehi_push_desc(host_ehi
, "interface fatal error");
1648 if (irq_stat
& (PORT_IRQ_CONNECT
| PORT_IRQ_PHYRDY
)) {
1649 ata_ehi_hotplugged(host_ehi
);
1650 ata_ehi_push_desc(host_ehi
, "%s",
1651 irq_stat
& PORT_IRQ_CONNECT
?
1652 "connection status changed" : "PHY RDY changed");
1655 /* okay, let's hand over to EH */
1657 if (irq_stat
& PORT_IRQ_FREEZE
)
1658 ata_port_freeze(ap
);
1659 else if (fbs_need_dec
) {
1660 ata_link_abort(link
);
1661 ahci_fbs_dec_intr(ap
);
1666 static void ahci_handle_port_interrupt(struct ata_port
*ap
,
1667 void __iomem
*port_mmio
, u32 status
)
1669 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
1670 struct ahci_port_priv
*pp
= ap
->private_data
;
1671 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1672 int resetting
= !!(ap
->pflags
& ATA_PFLAG_RESETTING
);
1676 /* ignore BAD_PMP while resetting */
1677 if (unlikely(resetting
))
1678 status
&= ~PORT_IRQ_BAD_PMP
;
1680 /* if LPM is enabled, PHYRDY doesn't mean anything */
1681 if (ap
->link
.lpm_policy
> ATA_LPM_MAX_POWER
) {
1682 status
&= ~PORT_IRQ_PHYRDY
;
1683 ahci_scr_write(&ap
->link
, SCR_ERROR
, SERR_PHYRDY_CHG
);
1686 if (unlikely(status
& PORT_IRQ_ERROR
)) {
1687 ahci_error_intr(ap
, status
);
1691 if (status
& PORT_IRQ_SDB_FIS
) {
1692 /* If SNotification is available, leave notification
1693 * handling to sata_async_notification(). If not,
1694 * emulate it by snooping SDB FIS RX area.
1696 * Snooping FIS RX area is probably cheaper than
1697 * poking SNotification but some constrollers which
1698 * implement SNotification, ICH9 for example, don't
1699 * store AN SDB FIS into receive area.
1701 if (hpriv
->cap
& HOST_CAP_SNTF
)
1702 sata_async_notification(ap
);
1704 /* If the 'N' bit in word 0 of the FIS is set,
1705 * we just received asynchronous notification.
1706 * Tell libata about it.
1708 * Lack of SNotification should not appear in
1709 * ahci 1.2, so the workaround is unnecessary
1710 * when FBS is enabled.
1712 if (pp
->fbs_enabled
)
1715 const __le32
*f
= pp
->rx_fis
+ RX_FIS_SDB
;
1716 u32 f0
= le32_to_cpu(f
[0]);
1718 sata_async_notification(ap
);
1723 /* pp->active_link is not reliable once FBS is enabled, both
1724 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1725 * NCQ and non-NCQ commands may be in flight at the same time.
1727 if (pp
->fbs_enabled
) {
1728 if (ap
->qc_active
) {
1729 qc_active
= readl(port_mmio
+ PORT_SCR_ACT
);
1730 qc_active
|= readl(port_mmio
+ PORT_CMD_ISSUE
);
1733 /* pp->active_link is valid iff any command is in flight */
1734 if (ap
->qc_active
&& pp
->active_link
->sactive
)
1735 qc_active
= readl(port_mmio
+ PORT_SCR_ACT
);
1737 qc_active
= readl(port_mmio
+ PORT_CMD_ISSUE
);
1741 rc
= ata_qc_complete_multiple(ap
, qc_active
);
1743 /* while resetting, invalid completions are expected */
1744 if (unlikely(rc
< 0 && !resetting
)) {
1745 ehi
->err_mask
|= AC_ERR_HSM
;
1746 ehi
->action
|= ATA_EH_RESET
;
1747 ata_port_freeze(ap
);
1751 void ahci_port_intr(struct ata_port
*ap
)
1753 void __iomem
*port_mmio
= ahci_port_base(ap
);
1756 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
1757 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
1759 ahci_handle_port_interrupt(ap
, port_mmio
, status
);
1762 irqreturn_t
ahci_thread_fn(int irq
, void *dev_instance
)
1764 struct ata_port
*ap
= dev_instance
;
1765 struct ahci_port_priv
*pp
= ap
->private_data
;
1766 void __iomem
*port_mmio
= ahci_port_base(ap
);
1767 unsigned long flags
;
1770 spin_lock_irqsave(&ap
->host
->lock
, flags
);
1771 status
= pp
->intr_status
;
1773 pp
->intr_status
= 0;
1774 spin_unlock_irqrestore(&ap
->host
->lock
, flags
);
1776 spin_lock_bh(ap
->lock
);
1777 ahci_handle_port_interrupt(ap
, port_mmio
, status
);
1778 spin_unlock_bh(ap
->lock
);
1782 EXPORT_SYMBOL_GPL(ahci_thread_fn
);
1784 void ahci_hw_port_interrupt(struct ata_port
*ap
)
1786 void __iomem
*port_mmio
= ahci_port_base(ap
);
1787 struct ahci_port_priv
*pp
= ap
->private_data
;
1790 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
1791 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
1793 pp
->intr_status
|= status
;
1796 irqreturn_t
ahci_hw_interrupt(int irq
, void *dev_instance
)
1798 struct ata_port
*ap_this
= dev_instance
;
1799 struct ahci_port_priv
*pp
= ap_this
->private_data
;
1800 struct ata_host
*host
= ap_this
->host
;
1801 struct ahci_host_priv
*hpriv
= host
->private_data
;
1802 void __iomem
*mmio
= hpriv
->mmio
;
1804 u32 irq_stat
, irq_masked
;
1808 spin_lock(&host
->lock
);
1810 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
1813 u32 status
= pp
->intr_status
;
1815 spin_unlock(&host
->lock
);
1819 return status
? IRQ_WAKE_THREAD
: IRQ_NONE
;
1822 irq_masked
= irq_stat
& hpriv
->port_map
;
1824 for (i
= 0; i
< host
->n_ports
; i
++) {
1825 struct ata_port
*ap
;
1827 if (!(irq_masked
& (1 << i
)))
1830 ap
= host
->ports
[i
];
1832 ahci_hw_port_interrupt(ap
);
1833 VPRINTK("port %u\n", i
);
1835 VPRINTK("port %u (no irq)\n", i
);
1836 if (ata_ratelimit())
1838 "interrupt on disabled port %u\n", i
);
1842 writel(irq_stat
, mmio
+ HOST_IRQ_STAT
);
1844 spin_unlock(&host
->lock
);
1848 return IRQ_WAKE_THREAD
;
1850 EXPORT_SYMBOL_GPL(ahci_hw_interrupt
);
1852 irqreturn_t
ahci_interrupt(int irq
, void *dev_instance
)
1854 struct ata_host
*host
= dev_instance
;
1855 struct ahci_host_priv
*hpriv
;
1856 unsigned int i
, handled
= 0;
1858 u32 irq_stat
, irq_masked
;
1862 hpriv
= host
->private_data
;
1865 /* sigh. 0xffffffff is a valid return from h/w */
1866 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
1870 irq_masked
= irq_stat
& hpriv
->port_map
;
1872 spin_lock(&host
->lock
);
1874 for (i
= 0; i
< host
->n_ports
; i
++) {
1875 struct ata_port
*ap
;
1877 if (!(irq_masked
& (1 << i
)))
1880 ap
= host
->ports
[i
];
1883 VPRINTK("port %u\n", i
);
1885 VPRINTK("port %u (no irq)\n", i
);
1886 if (ata_ratelimit())
1888 "interrupt on disabled port %u\n", i
);
1894 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1895 * it should be cleared after all the port events are cleared;
1896 * otherwise, it will raise a spurious interrupt after each
1897 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1900 * Also, use the unmasked value to clear interrupt as spurious
1901 * pending event on a dummy port might cause screaming IRQ.
1903 writel(irq_stat
, mmio
+ HOST_IRQ_STAT
);
1905 spin_unlock(&host
->lock
);
1909 return IRQ_RETVAL(handled
);
1911 EXPORT_SYMBOL_GPL(ahci_interrupt
);
1913 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
)
1915 struct ata_port
*ap
= qc
->ap
;
1916 void __iomem
*port_mmio
= ahci_port_base(ap
);
1917 struct ahci_port_priv
*pp
= ap
->private_data
;
1919 /* Keep track of the currently active link. It will be used
1920 * in completion path to determine whether NCQ phase is in
1923 pp
->active_link
= qc
->dev
->link
;
1925 if (qc
->tf
.protocol
== ATA_PROT_NCQ
)
1926 writel(1 << qc
->tag
, port_mmio
+ PORT_SCR_ACT
);
1928 if (pp
->fbs_enabled
&& pp
->fbs_last_dev
!= qc
->dev
->link
->pmp
) {
1929 u32 fbs
= readl(port_mmio
+ PORT_FBS
);
1930 fbs
&= ~(PORT_FBS_DEV_MASK
| PORT_FBS_DEC
);
1931 fbs
|= qc
->dev
->link
->pmp
<< PORT_FBS_DEV_OFFSET
;
1932 writel(fbs
, port_mmio
+ PORT_FBS
);
1933 pp
->fbs_last_dev
= qc
->dev
->link
->pmp
;
1936 writel(1 << qc
->tag
, port_mmio
+ PORT_CMD_ISSUE
);
1938 ahci_sw_activity(qc
->dev
->link
);
1943 static bool ahci_qc_fill_rtf(struct ata_queued_cmd
*qc
)
1945 struct ahci_port_priv
*pp
= qc
->ap
->private_data
;
1946 u8
*rx_fis
= pp
->rx_fis
;
1948 if (pp
->fbs_enabled
)
1949 rx_fis
+= qc
->dev
->link
->pmp
* AHCI_RX_FIS_SZ
;
1952 * After a successful execution of an ATA PIO data-in command,
1953 * the device doesn't send D2H Reg FIS to update the TF and
1954 * the host should take TF and E_Status from the preceding PIO
1957 if (qc
->tf
.protocol
== ATA_PROT_PIO
&& qc
->dma_dir
== DMA_FROM_DEVICE
&&
1958 !(qc
->flags
& ATA_QCFLAG_FAILED
)) {
1959 ata_tf_from_fis(rx_fis
+ RX_FIS_PIO_SETUP
, &qc
->result_tf
);
1960 qc
->result_tf
.command
= (rx_fis
+ RX_FIS_PIO_SETUP
)[15];
1962 ata_tf_from_fis(rx_fis
+ RX_FIS_D2H_REG
, &qc
->result_tf
);
1967 static void ahci_freeze(struct ata_port
*ap
)
1969 void __iomem
*port_mmio
= ahci_port_base(ap
);
1972 writel(0, port_mmio
+ PORT_IRQ_MASK
);
1975 static void ahci_thaw(struct ata_port
*ap
)
1977 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1978 void __iomem
*mmio
= hpriv
->mmio
;
1979 void __iomem
*port_mmio
= ahci_port_base(ap
);
1981 struct ahci_port_priv
*pp
= ap
->private_data
;
1984 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1985 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1986 writel(1 << ap
->port_no
, mmio
+ HOST_IRQ_STAT
);
1988 /* turn IRQ back on */
1989 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
1992 static void ahci_error_handler(struct ata_port
*ap
)
1994 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
)) {
1995 /* restart engine */
1996 ahci_stop_engine(ap
);
1997 ahci_start_engine(ap
);
2000 sata_pmp_error_handler(ap
);
2002 if (!ata_dev_enabled(ap
->link
.device
))
2003 ahci_stop_engine(ap
);
2006 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
)
2008 struct ata_port
*ap
= qc
->ap
;
2010 /* make DMA engine forget about the failed command */
2011 if (qc
->flags
& ATA_QCFLAG_FAILED
)
2012 ahci_kick_engine(ap
);
2015 static void ahci_set_aggressive_devslp(struct ata_port
*ap
, bool sleep
)
2017 void __iomem
*port_mmio
= ahci_port_base(ap
);
2018 struct ata_device
*dev
= ap
->link
.device
;
2019 u32 devslp
, dm
, dito
, mdat
, deto
;
2021 unsigned int err_mask
;
2023 devslp
= readl(port_mmio
+ PORT_DEVSLP
);
2024 if (!(devslp
& PORT_DEVSLP_DSP
)) {
2025 dev_err(ap
->host
->dev
, "port does not support device sleep\n");
2029 /* disable device sleep */
2031 if (devslp
& PORT_DEVSLP_ADSE
) {
2032 writel(devslp
& ~PORT_DEVSLP_ADSE
,
2033 port_mmio
+ PORT_DEVSLP
);
2034 err_mask
= ata_dev_set_feature(dev
,
2035 SETFEATURES_SATA_DISABLE
,
2037 if (err_mask
&& err_mask
!= AC_ERR_DEV
)
2038 ata_dev_warn(dev
, "failed to disable DEVSLP\n");
2043 /* device sleep was already enabled */
2044 if (devslp
& PORT_DEVSLP_ADSE
)
2047 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2048 rc
= ahci_stop_engine(ap
);
2052 dm
= (devslp
& PORT_DEVSLP_DM_MASK
) >> PORT_DEVSLP_DM_OFFSET
;
2053 dito
= devslp_idle_timeout
/ (dm
+ 1);
2057 /* Use the nominal value 10 ms if the read MDAT is zero,
2058 * the nominal value of DETO is 20 ms.
2060 if (dev
->devslp_timing
[ATA_LOG_DEVSLP_VALID
] &
2061 ATA_LOG_DEVSLP_VALID_MASK
) {
2062 mdat
= dev
->devslp_timing
[ATA_LOG_DEVSLP_MDAT
] &
2063 ATA_LOG_DEVSLP_MDAT_MASK
;
2066 deto
= dev
->devslp_timing
[ATA_LOG_DEVSLP_DETO
];
2074 devslp
|= ((dito
<< PORT_DEVSLP_DITO_OFFSET
) |
2075 (mdat
<< PORT_DEVSLP_MDAT_OFFSET
) |
2076 (deto
<< PORT_DEVSLP_DETO_OFFSET
) |
2078 writel(devslp
, port_mmio
+ PORT_DEVSLP
);
2080 ahci_start_engine(ap
);
2082 /* enable device sleep feature for the drive */
2083 err_mask
= ata_dev_set_feature(dev
,
2084 SETFEATURES_SATA_ENABLE
,
2086 if (err_mask
&& err_mask
!= AC_ERR_DEV
)
2087 ata_dev_warn(dev
, "failed to enable DEVSLP\n");
2090 static void ahci_enable_fbs(struct ata_port
*ap
)
2092 struct ahci_port_priv
*pp
= ap
->private_data
;
2093 void __iomem
*port_mmio
= ahci_port_base(ap
);
2097 if (!pp
->fbs_supported
)
2100 fbs
= readl(port_mmio
+ PORT_FBS
);
2101 if (fbs
& PORT_FBS_EN
) {
2102 pp
->fbs_enabled
= true;
2103 pp
->fbs_last_dev
= -1; /* initialization */
2107 rc
= ahci_stop_engine(ap
);
2111 writel(fbs
| PORT_FBS_EN
, port_mmio
+ PORT_FBS
);
2112 fbs
= readl(port_mmio
+ PORT_FBS
);
2113 if (fbs
& PORT_FBS_EN
) {
2114 dev_info(ap
->host
->dev
, "FBS is enabled\n");
2115 pp
->fbs_enabled
= true;
2116 pp
->fbs_last_dev
= -1; /* initialization */
2118 dev_err(ap
->host
->dev
, "Failed to enable FBS\n");
2120 ahci_start_engine(ap
);
2123 static void ahci_disable_fbs(struct ata_port
*ap
)
2125 struct ahci_port_priv
*pp
= ap
->private_data
;
2126 void __iomem
*port_mmio
= ahci_port_base(ap
);
2130 if (!pp
->fbs_supported
)
2133 fbs
= readl(port_mmio
+ PORT_FBS
);
2134 if ((fbs
& PORT_FBS_EN
) == 0) {
2135 pp
->fbs_enabled
= false;
2139 rc
= ahci_stop_engine(ap
);
2143 writel(fbs
& ~PORT_FBS_EN
, port_mmio
+ PORT_FBS
);
2144 fbs
= readl(port_mmio
+ PORT_FBS
);
2145 if (fbs
& PORT_FBS_EN
)
2146 dev_err(ap
->host
->dev
, "Failed to disable FBS\n");
2148 dev_info(ap
->host
->dev
, "FBS is disabled\n");
2149 pp
->fbs_enabled
= false;
2152 ahci_start_engine(ap
);
2155 static void ahci_pmp_attach(struct ata_port
*ap
)
2157 void __iomem
*port_mmio
= ahci_port_base(ap
);
2158 struct ahci_port_priv
*pp
= ap
->private_data
;
2161 cmd
= readl(port_mmio
+ PORT_CMD
);
2162 cmd
|= PORT_CMD_PMP
;
2163 writel(cmd
, port_mmio
+ PORT_CMD
);
2165 ahci_enable_fbs(ap
);
2167 pp
->intr_mask
|= PORT_IRQ_BAD_PMP
;
2170 * We must not change the port interrupt mask register if the
2171 * port is marked frozen, the value in pp->intr_mask will be
2172 * restored later when the port is thawed.
2174 * Note that during initialization, the port is marked as
2175 * frozen since the irq handler is not yet registered.
2177 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
))
2178 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
2181 static void ahci_pmp_detach(struct ata_port
*ap
)
2183 void __iomem
*port_mmio
= ahci_port_base(ap
);
2184 struct ahci_port_priv
*pp
= ap
->private_data
;
2187 ahci_disable_fbs(ap
);
2189 cmd
= readl(port_mmio
+ PORT_CMD
);
2190 cmd
&= ~PORT_CMD_PMP
;
2191 writel(cmd
, port_mmio
+ PORT_CMD
);
2193 pp
->intr_mask
&= ~PORT_IRQ_BAD_PMP
;
2195 /* see comment above in ahci_pmp_attach() */
2196 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
))
2197 writel(pp
->intr_mask
, port_mmio
+ PORT_IRQ_MASK
);
2200 int ahci_port_resume(struct ata_port
*ap
)
2203 ahci_start_port(ap
);
2205 if (sata_pmp_attached(ap
))
2206 ahci_pmp_attach(ap
);
2208 ahci_pmp_detach(ap
);
2212 EXPORT_SYMBOL_GPL(ahci_port_resume
);
2215 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
)
2217 const char *emsg
= NULL
;
2220 rc
= ahci_deinit_port(ap
, &emsg
);
2222 ahci_power_down(ap
);
2224 ata_port_err(ap
, "%s (%d)\n", emsg
, rc
);
2225 ata_port_freeze(ap
);
2232 static int ahci_port_start(struct ata_port
*ap
)
2234 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
2235 struct device
*dev
= ap
->host
->dev
;
2236 struct ahci_port_priv
*pp
;
2239 size_t dma_sz
, rx_fis_sz
;
2241 pp
= devm_kzalloc(dev
, sizeof(*pp
), GFP_KERNEL
);
2245 if (ap
->host
->n_ports
> 1) {
2246 pp
->irq_desc
= devm_kzalloc(dev
, 8, GFP_KERNEL
);
2247 if (!pp
->irq_desc
) {
2248 devm_kfree(dev
, pp
);
2251 snprintf(pp
->irq_desc
, 8,
2252 "%s%d", dev_driver_string(dev
), ap
->port_no
);
2255 /* check FBS capability */
2256 if ((hpriv
->cap
& HOST_CAP_FBS
) && sata_pmp_supported(ap
)) {
2257 void __iomem
*port_mmio
= ahci_port_base(ap
);
2258 u32 cmd
= readl(port_mmio
+ PORT_CMD
);
2259 if (cmd
& PORT_CMD_FBSCP
)
2260 pp
->fbs_supported
= true;
2261 else if (hpriv
->flags
& AHCI_HFLAG_YES_FBS
) {
2262 dev_info(dev
, "port %d can do FBS, forcing FBSCP\n",
2264 pp
->fbs_supported
= true;
2266 dev_warn(dev
, "port %d is not capable of FBS\n",
2270 if (pp
->fbs_supported
) {
2271 dma_sz
= AHCI_PORT_PRIV_FBS_DMA_SZ
;
2272 rx_fis_sz
= AHCI_RX_FIS_SZ
* 16;
2274 dma_sz
= AHCI_PORT_PRIV_DMA_SZ
;
2275 rx_fis_sz
= AHCI_RX_FIS_SZ
;
2278 mem
= dmam_alloc_coherent(dev
, dma_sz
, &mem_dma
, GFP_KERNEL
);
2281 memset(mem
, 0, dma_sz
);
2284 * First item in chunk of DMA memory: 32-slot command table,
2285 * 32 bytes each in size
2288 pp
->cmd_slot_dma
= mem_dma
;
2290 mem
+= AHCI_CMD_SLOT_SZ
;
2291 mem_dma
+= AHCI_CMD_SLOT_SZ
;
2294 * Second item: Received-FIS area
2297 pp
->rx_fis_dma
= mem_dma
;
2300 mem_dma
+= rx_fis_sz
;
2303 * Third item: data area for storing a single command
2304 * and its scatter-gather table
2307 pp
->cmd_tbl_dma
= mem_dma
;
2310 * Save off initial list of interrupts to be enabled.
2311 * This could be changed later
2313 pp
->intr_mask
= DEF_PORT_IRQ
;
2316 * Switch to per-port locking in case each port has its own MSI vector.
2318 if ((hpriv
->flags
& AHCI_HFLAG_MULTI_MSI
)) {
2319 spin_lock_init(&pp
->lock
);
2320 ap
->lock
= &pp
->lock
;
2323 ap
->private_data
= pp
;
2325 /* engage engines, captain */
2326 return ahci_port_resume(ap
);
2329 static void ahci_port_stop(struct ata_port
*ap
)
2331 const char *emsg
= NULL
;
2334 /* de-initialize port */
2335 rc
= ahci_deinit_port(ap
, &emsg
);
2337 ata_port_warn(ap
, "%s (%d)\n", emsg
, rc
);
2340 void ahci_print_info(struct ata_host
*host
, const char *scc_s
)
2342 struct ahci_host_priv
*hpriv
= host
->private_data
;
2343 void __iomem
*mmio
= hpriv
->mmio
;
2344 u32 vers
, cap
, cap2
, impl
, speed
;
2345 const char *speed_s
;
2347 vers
= readl(mmio
+ HOST_VERSION
);
2350 impl
= hpriv
->port_map
;
2352 speed
= (cap
>> 20) & 0xf;
2355 else if (speed
== 2)
2357 else if (speed
== 3)
2363 "AHCI %02x%02x.%02x%02x "
2364 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2367 (vers
>> 24) & 0xff,
2368 (vers
>> 16) & 0xff,
2372 ((cap
>> 8) & 0x1f) + 1,
2386 cap
& HOST_CAP_64
? "64bit " : "",
2387 cap
& HOST_CAP_NCQ
? "ncq " : "",
2388 cap
& HOST_CAP_SNTF
? "sntf " : "",
2389 cap
& HOST_CAP_MPS
? "ilck " : "",
2390 cap
& HOST_CAP_SSS
? "stag " : "",
2391 cap
& HOST_CAP_ALPM
? "pm " : "",
2392 cap
& HOST_CAP_LED
? "led " : "",
2393 cap
& HOST_CAP_CLO
? "clo " : "",
2394 cap
& HOST_CAP_ONLY
? "only " : "",
2395 cap
& HOST_CAP_PMP
? "pmp " : "",
2396 cap
& HOST_CAP_FBS
? "fbs " : "",
2397 cap
& HOST_CAP_PIO_MULTI
? "pio " : "",
2398 cap
& HOST_CAP_SSC
? "slum " : "",
2399 cap
& HOST_CAP_PART
? "part " : "",
2400 cap
& HOST_CAP_CCC
? "ccc " : "",
2401 cap
& HOST_CAP_EMS
? "ems " : "",
2402 cap
& HOST_CAP_SXS
? "sxs " : "",
2403 cap2
& HOST_CAP2_DESO
? "deso " : "",
2404 cap2
& HOST_CAP2_SADM
? "sadm " : "",
2405 cap2
& HOST_CAP2_SDS
? "sds " : "",
2406 cap2
& HOST_CAP2_APST
? "apst " : "",
2407 cap2
& HOST_CAP2_NVMHCI
? "nvmp " : "",
2408 cap2
& HOST_CAP2_BOH
? "boh " : ""
2411 EXPORT_SYMBOL_GPL(ahci_print_info
);
2413 void ahci_set_em_messages(struct ahci_host_priv
*hpriv
,
2414 struct ata_port_info
*pi
)
2417 void __iomem
*mmio
= hpriv
->mmio
;
2418 u32 em_loc
= readl(mmio
+ HOST_EM_LOC
);
2419 u32 em_ctl
= readl(mmio
+ HOST_EM_CTL
);
2421 if (!ahci_em_messages
|| !(hpriv
->cap
& HOST_CAP_EMS
))
2424 messages
= (em_ctl
& EM_CTRL_MSG_TYPE
) >> 16;
2428 hpriv
->em_loc
= ((em_loc
>> 16) * 4);
2429 hpriv
->em_buf_sz
= ((em_loc
& 0xff) * 4);
2430 hpriv
->em_msg_type
= messages
;
2431 pi
->flags
|= ATA_FLAG_EM
;
2432 if (!(em_ctl
& EM_CTL_ALHD
))
2433 pi
->flags
|= ATA_FLAG_SW_ACTIVITY
;
2436 EXPORT_SYMBOL_GPL(ahci_set_em_messages
);
2438 MODULE_AUTHOR("Jeff Garzik");
2439 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2440 MODULE_LICENSE("GPL");