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libata: add deadline support to prereset and reset methods
[deliverable/linux.git] / drivers / ata / pata_amd.c
1 /*
2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based on pata-sil680. Errata information is taken from data sheets
7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
8 * claimed by sata-nv.c.
9 *
10 * TODO:
11 * Variable system clock when/if it makes sense
12 * Power management on ports
13 *
14 *
15 * Documentation publically available.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <scsi/scsi_host.h>
25 #include <linux/libata.h>
26
27 #define DRV_NAME "pata_amd"
28 #define DRV_VERSION "0.3.8"
29
30 /**
31 * timing_setup - shared timing computation and load
32 * @ap: ATA port being set up
33 * @adev: drive being configured
34 * @offset: port offset
35 * @speed: target speed
36 * @clock: clock multiplier (number of times 33MHz for this part)
37 *
38 * Perform the actual timing set up for Nvidia or AMD PATA devices.
39 * The actual devices vary so they all call into this helper function
40 * providing the clock multipler and offset (because AMD and Nvidia put
41 * the ports at different locations).
42 */
43
44 static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
45 {
46 static const unsigned char amd_cyc2udma[] = {
47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
48 };
49
50 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
51 struct ata_device *peer = ata_dev_pair(adev);
52 int dn = ap->port_no * 2 + adev->devno;
53 struct ata_timing at, apeer;
54 int T, UT;
55 const int amd_clock = 33333; /* KHz. */
56 u8 t;
57
58 T = 1000000000 / amd_clock;
59 UT = T / min_t(int, max_t(int, clock, 1), 2);
60
61 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
62 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
63 return;
64 }
65
66 if (peer) {
67 /* This may be over conservative */
68 if (peer->dma_mode) {
69 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
70 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
71 }
72 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
73 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
74 }
75
76 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
77 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
78
79 /*
80 * Now do the setup work
81 */
82
83 /* Configure the address set up timing */
84 pci_read_config_byte(pdev, offset + 0x0C, &t);
85 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
86 pci_write_config_byte(pdev, offset + 0x0C , t);
87
88 /* Configure the 8bit I/O timing */
89 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
90 ((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1));
91
92 /* Drive timing */
93 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
94 ((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1));
95
96 switch (clock) {
97 case 1:
98 t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03;
99 break;
100
101 case 2:
102 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
103 break;
104
105 case 3:
106 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
107 break;
108
109 case 4:
110 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
111 break;
112
113 default:
114 return;
115 }
116
117 /* UDMA timing */
118 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
119 }
120
121 /**
122 * amd_probe_init - perform reset handling
123 * @ap: ATA port
124 * @deadline: deadline jiffies for the operation
125 *
126 * Reset sequence checking enable bits to see which ports are
127 * active.
128 */
129
130 static int amd_pre_reset(struct ata_port *ap, unsigned long deadline)
131 {
132 static const struct pci_bits amd_enable_bits[] = {
133 { 0x40, 1, 0x02, 0x02 },
134 { 0x40, 1, 0x01, 0x01 }
135 };
136
137 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
138
139 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
140 return -ENOENT;
141
142 return ata_std_prereset(ap, deadline);
143 }
144
145 static void amd_error_handler(struct ata_port *ap)
146 {
147 return ata_bmdma_drive_eh(ap, amd_pre_reset,
148 ata_std_softreset, NULL,
149 ata_std_postreset);
150 }
151
152 static int amd_cable_detect(struct ata_port *ap)
153 {
154 static const u32 bitmask[2] = {0x03, 0x0C};
155 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
156 u8 ata66;
157
158 pci_read_config_byte(pdev, 0x42, &ata66);
159 if (ata66 & bitmask[ap->port_no])
160 return ATA_CBL_PATA80;
161 return ATA_CBL_PATA40;
162 }
163
164 /**
165 * amd33_set_piomode - set initial PIO mode data
166 * @ap: ATA interface
167 * @adev: ATA device
168 *
169 * Program the AMD registers for PIO mode.
170 */
171
172 static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
173 {
174 timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
175 }
176
177 static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
178 {
179 timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
180 }
181
182 static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
183 {
184 timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
185 }
186
187 static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
188 {
189 timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
190 }
191
192 /**
193 * amd33_set_dmamode - set initial DMA mode data
194 * @ap: ATA interface
195 * @adev: ATA device
196 *
197 * Program the MWDMA/UDMA modes for the AMD and Nvidia
198 * chipset.
199 */
200
201 static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
202 {
203 timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
204 }
205
206 static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
207 {
208 timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
209 }
210
211 static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
212 {
213 timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
214 }
215
216 static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
217 {
218 timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
219 }
220
221
222 /**
223 * nv_probe_init - cable detection
224 * @ap: ATA port
225 *
226 * Perform cable detection. The BIOS stores this in PCI config
227 * space for us.
228 */
229
230 static int nv_pre_reset(struct ata_port *ap, unsigned long deadline)
231 {
232 static const struct pci_bits nv_enable_bits[] = {
233 { 0x50, 1, 0x02, 0x02 },
234 { 0x50, 1, 0x01, 0x01 }
235 };
236
237 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
238
239 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
240 return -ENOENT;
241
242 return ata_std_prereset(ap, deadline);
243 }
244
245 static void nv_error_handler(struct ata_port *ap)
246 {
247 ata_bmdma_drive_eh(ap, nv_pre_reset,
248 ata_std_softreset, NULL,
249 ata_std_postreset);
250 }
251
252 static int nv_cable_detect(struct ata_port *ap)
253 {
254 static const u8 bitmask[2] = {0x03, 0x0C};
255 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
256 u8 ata66;
257 u16 udma;
258 int cbl;
259
260 pci_read_config_byte(pdev, 0x52, &ata66);
261 if (ata66 & bitmask[ap->port_no])
262 cbl = ATA_CBL_PATA80;
263 else
264 cbl = ATA_CBL_PATA40;
265
266 /* We now have to double check because the Nvidia boxes BIOS
267 doesn't always set the cable bits but does set mode bits */
268 pci_read_config_word(pdev, 0x62 - 2 * ap->port_no, &udma);
269 if ((udma & 0xC4) == 0xC4 || (udma & 0xC400) == 0xC400)
270 cbl = ATA_CBL_PATA80;
271 return cbl;
272 }
273
274 /**
275 * nv100_set_piomode - set initial PIO mode data
276 * @ap: ATA interface
277 * @adev: ATA device
278 *
279 * Program the AMD registers for PIO mode.
280 */
281
282 static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
283 {
284 timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
285 }
286
287 static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
288 {
289 timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
290 }
291
292 /**
293 * nv100_set_dmamode - set initial DMA mode data
294 * @ap: ATA interface
295 * @adev: ATA device
296 *
297 * Program the MWDMA/UDMA modes for the AMD and Nvidia
298 * chipset.
299 */
300
301 static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
302 {
303 timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
304 }
305
306 static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
307 {
308 timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
309 }
310
311 static struct scsi_host_template amd_sht = {
312 .module = THIS_MODULE,
313 .name = DRV_NAME,
314 .ioctl = ata_scsi_ioctl,
315 .queuecommand = ata_scsi_queuecmd,
316 .can_queue = ATA_DEF_QUEUE,
317 .this_id = ATA_SHT_THIS_ID,
318 .sg_tablesize = LIBATA_MAX_PRD,
319 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
320 .emulated = ATA_SHT_EMULATED,
321 .use_clustering = ATA_SHT_USE_CLUSTERING,
322 .proc_name = DRV_NAME,
323 .dma_boundary = ATA_DMA_BOUNDARY,
324 .slave_configure = ata_scsi_slave_config,
325 .slave_destroy = ata_scsi_slave_destroy,
326 .bios_param = ata_std_bios_param,
327 #ifdef CONFIG_PM
328 .resume = ata_scsi_device_resume,
329 .suspend = ata_scsi_device_suspend,
330 #endif
331 };
332
333 static struct ata_port_operations amd33_port_ops = {
334 .port_disable = ata_port_disable,
335 .set_piomode = amd33_set_piomode,
336 .set_dmamode = amd33_set_dmamode,
337 .mode_filter = ata_pci_default_filter,
338 .tf_load = ata_tf_load,
339 .tf_read = ata_tf_read,
340 .check_status = ata_check_status,
341 .exec_command = ata_exec_command,
342 .dev_select = ata_std_dev_select,
343
344 .freeze = ata_bmdma_freeze,
345 .thaw = ata_bmdma_thaw,
346 .error_handler = amd_error_handler,
347 .post_internal_cmd = ata_bmdma_post_internal_cmd,
348 .cable_detect = ata_cable_40wire,
349
350 .bmdma_setup = ata_bmdma_setup,
351 .bmdma_start = ata_bmdma_start,
352 .bmdma_stop = ata_bmdma_stop,
353 .bmdma_status = ata_bmdma_status,
354
355 .qc_prep = ata_qc_prep,
356 .qc_issue = ata_qc_issue_prot,
357
358 .data_xfer = ata_data_xfer,
359
360 .irq_handler = ata_interrupt,
361 .irq_clear = ata_bmdma_irq_clear,
362 .irq_on = ata_irq_on,
363 .irq_ack = ata_irq_ack,
364
365 .port_start = ata_port_start,
366 };
367
368 static struct ata_port_operations amd66_port_ops = {
369 .port_disable = ata_port_disable,
370 .set_piomode = amd66_set_piomode,
371 .set_dmamode = amd66_set_dmamode,
372 .mode_filter = ata_pci_default_filter,
373 .tf_load = ata_tf_load,
374 .tf_read = ata_tf_read,
375 .check_status = ata_check_status,
376 .exec_command = ata_exec_command,
377 .dev_select = ata_std_dev_select,
378
379 .freeze = ata_bmdma_freeze,
380 .thaw = ata_bmdma_thaw,
381 .error_handler = amd_error_handler,
382 .post_internal_cmd = ata_bmdma_post_internal_cmd,
383 .cable_detect = ata_cable_unknown,
384
385 .bmdma_setup = ata_bmdma_setup,
386 .bmdma_start = ata_bmdma_start,
387 .bmdma_stop = ata_bmdma_stop,
388 .bmdma_status = ata_bmdma_status,
389
390 .qc_prep = ata_qc_prep,
391 .qc_issue = ata_qc_issue_prot,
392
393 .data_xfer = ata_data_xfer,
394
395 .irq_handler = ata_interrupt,
396 .irq_clear = ata_bmdma_irq_clear,
397 .irq_on = ata_irq_on,
398 .irq_ack = ata_irq_ack,
399
400 .port_start = ata_port_start,
401 };
402
403 static struct ata_port_operations amd100_port_ops = {
404 .port_disable = ata_port_disable,
405 .set_piomode = amd100_set_piomode,
406 .set_dmamode = amd100_set_dmamode,
407 .mode_filter = ata_pci_default_filter,
408 .tf_load = ata_tf_load,
409 .tf_read = ata_tf_read,
410 .check_status = ata_check_status,
411 .exec_command = ata_exec_command,
412 .dev_select = ata_std_dev_select,
413
414 .freeze = ata_bmdma_freeze,
415 .thaw = ata_bmdma_thaw,
416 .error_handler = amd_error_handler,
417 .post_internal_cmd = ata_bmdma_post_internal_cmd,
418 .cable_detect = ata_cable_unknown,
419
420 .bmdma_setup = ata_bmdma_setup,
421 .bmdma_start = ata_bmdma_start,
422 .bmdma_stop = ata_bmdma_stop,
423 .bmdma_status = ata_bmdma_status,
424
425 .qc_prep = ata_qc_prep,
426 .qc_issue = ata_qc_issue_prot,
427
428 .data_xfer = ata_data_xfer,
429
430 .irq_handler = ata_interrupt,
431 .irq_clear = ata_bmdma_irq_clear,
432 .irq_on = ata_irq_on,
433 .irq_ack = ata_irq_ack,
434
435 .port_start = ata_port_start,
436 };
437
438 static struct ata_port_operations amd133_port_ops = {
439 .port_disable = ata_port_disable,
440 .set_piomode = amd133_set_piomode,
441 .set_dmamode = amd133_set_dmamode,
442 .mode_filter = ata_pci_default_filter,
443 .tf_load = ata_tf_load,
444 .tf_read = ata_tf_read,
445 .check_status = ata_check_status,
446 .exec_command = ata_exec_command,
447 .dev_select = ata_std_dev_select,
448
449 .freeze = ata_bmdma_freeze,
450 .thaw = ata_bmdma_thaw,
451 .error_handler = amd_error_handler,
452 .post_internal_cmd = ata_bmdma_post_internal_cmd,
453 .cable_detect = amd_cable_detect,
454
455 .bmdma_setup = ata_bmdma_setup,
456 .bmdma_start = ata_bmdma_start,
457 .bmdma_stop = ata_bmdma_stop,
458 .bmdma_status = ata_bmdma_status,
459
460 .qc_prep = ata_qc_prep,
461 .qc_issue = ata_qc_issue_prot,
462
463 .data_xfer = ata_data_xfer,
464
465 .irq_handler = ata_interrupt,
466 .irq_clear = ata_bmdma_irq_clear,
467 .irq_on = ata_irq_on,
468 .irq_ack = ata_irq_ack,
469
470 .port_start = ata_port_start,
471 };
472
473 static struct ata_port_operations nv100_port_ops = {
474 .port_disable = ata_port_disable,
475 .set_piomode = nv100_set_piomode,
476 .set_dmamode = nv100_set_dmamode,
477 .mode_filter = ata_pci_default_filter,
478 .tf_load = ata_tf_load,
479 .tf_read = ata_tf_read,
480 .check_status = ata_check_status,
481 .exec_command = ata_exec_command,
482 .dev_select = ata_std_dev_select,
483
484 .freeze = ata_bmdma_freeze,
485 .thaw = ata_bmdma_thaw,
486 .error_handler = nv_error_handler,
487 .post_internal_cmd = ata_bmdma_post_internal_cmd,
488 .cable_detect = nv_cable_detect,
489
490 .bmdma_setup = ata_bmdma_setup,
491 .bmdma_start = ata_bmdma_start,
492 .bmdma_stop = ata_bmdma_stop,
493 .bmdma_status = ata_bmdma_status,
494
495 .qc_prep = ata_qc_prep,
496 .qc_issue = ata_qc_issue_prot,
497
498 .data_xfer = ata_data_xfer,
499
500 .irq_handler = ata_interrupt,
501 .irq_clear = ata_bmdma_irq_clear,
502 .irq_on = ata_irq_on,
503 .irq_ack = ata_irq_ack,
504
505 .port_start = ata_port_start,
506 };
507
508 static struct ata_port_operations nv133_port_ops = {
509 .port_disable = ata_port_disable,
510 .set_piomode = nv133_set_piomode,
511 .set_dmamode = nv133_set_dmamode,
512 .mode_filter = ata_pci_default_filter,
513 .tf_load = ata_tf_load,
514 .tf_read = ata_tf_read,
515 .check_status = ata_check_status,
516 .exec_command = ata_exec_command,
517 .dev_select = ata_std_dev_select,
518
519 .freeze = ata_bmdma_freeze,
520 .thaw = ata_bmdma_thaw,
521 .error_handler = nv_error_handler,
522 .post_internal_cmd = ata_bmdma_post_internal_cmd,
523 .cable_detect = nv_cable_detect,
524
525 .bmdma_setup = ata_bmdma_setup,
526 .bmdma_start = ata_bmdma_start,
527 .bmdma_stop = ata_bmdma_stop,
528 .bmdma_status = ata_bmdma_status,
529
530 .qc_prep = ata_qc_prep,
531 .qc_issue = ata_qc_issue_prot,
532
533 .data_xfer = ata_data_xfer,
534
535 .irq_handler = ata_interrupt,
536 .irq_clear = ata_bmdma_irq_clear,
537 .irq_on = ata_irq_on,
538 .irq_ack = ata_irq_ack,
539
540 .port_start = ata_port_start,
541 };
542
543 static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
544 {
545 static struct ata_port_info info[10] = {
546 { /* 0: AMD 7401 */
547 .sht = &amd_sht,
548 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
549 .pio_mask = 0x1f,
550 .mwdma_mask = 0x07, /* No SWDMA */
551 .udma_mask = 0x07, /* UDMA 33 */
552 .port_ops = &amd33_port_ops
553 },
554 { /* 1: Early AMD7409 - no swdma */
555 .sht = &amd_sht,
556 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
557 .pio_mask = 0x1f,
558 .mwdma_mask = 0x07,
559 .udma_mask = 0x1f, /* UDMA 66 */
560 .port_ops = &amd66_port_ops
561 },
562 { /* 2: AMD 7409, no swdma errata */
563 .sht = &amd_sht,
564 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
565 .pio_mask = 0x1f,
566 .mwdma_mask = 0x07,
567 .udma_mask = 0x1f, /* UDMA 66 */
568 .port_ops = &amd66_port_ops
569 },
570 { /* 3: AMD 7411 */
571 .sht = &amd_sht,
572 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
573 .pio_mask = 0x1f,
574 .mwdma_mask = 0x07,
575 .udma_mask = 0x3f, /* UDMA 100 */
576 .port_ops = &amd100_port_ops
577 },
578 { /* 4: AMD 7441 */
579 .sht = &amd_sht,
580 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
581 .pio_mask = 0x1f,
582 .mwdma_mask = 0x07,
583 .udma_mask = 0x3f, /* UDMA 100 */
584 .port_ops = &amd100_port_ops
585 },
586 { /* 5: AMD 8111*/
587 .sht = &amd_sht,
588 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
589 .pio_mask = 0x1f,
590 .mwdma_mask = 0x07,
591 .udma_mask = 0x7f, /* UDMA 133, no swdma */
592 .port_ops = &amd133_port_ops
593 },
594 { /* 6: AMD 8111 UDMA 100 (Serenade) */
595 .sht = &amd_sht,
596 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
597 .pio_mask = 0x1f,
598 .mwdma_mask = 0x07,
599 .udma_mask = 0x3f, /* UDMA 100, no swdma */
600 .port_ops = &amd133_port_ops
601 },
602 { /* 7: Nvidia Nforce */
603 .sht = &amd_sht,
604 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
605 .pio_mask = 0x1f,
606 .mwdma_mask = 0x07,
607 .udma_mask = 0x3f, /* UDMA 100 */
608 .port_ops = &nv100_port_ops
609 },
610 { /* 8: Nvidia Nforce2 and later */
611 .sht = &amd_sht,
612 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
613 .pio_mask = 0x1f,
614 .mwdma_mask = 0x07,
615 .udma_mask = 0x7f, /* UDMA 133, no swdma */
616 .port_ops = &nv133_port_ops
617 },
618 { /* 9: AMD CS5536 (Geode companion) */
619 .sht = &amd_sht,
620 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
621 .pio_mask = 0x1f,
622 .mwdma_mask = 0x07,
623 .udma_mask = 0x3f, /* UDMA 100 */
624 .port_ops = &amd100_port_ops
625 }
626 };
627 static struct ata_port_info *port_info[2];
628 static int printed_version;
629 int type = id->driver_data;
630 u8 rev;
631 u8 fifo;
632
633 if (!printed_version++)
634 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
635
636 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
637 pci_read_config_byte(pdev, 0x41, &fifo);
638
639 /* Check for AMD7409 without swdma errata and if found adjust type */
640 if (type == 1 && rev > 0x7)
641 type = 2;
642
643 /* Check for AMD7411 */
644 if (type == 3)
645 /* FIFO is broken */
646 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
647 else
648 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
649
650 /* Serenade ? */
651 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
652 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
653 type = 6; /* UDMA 100 only */
654
655 if (type < 3)
656 ata_pci_clear_simplex(pdev);
657
658 /* And fire it up */
659
660 port_info[0] = port_info[1] = &info[type];
661 return ata_pci_init_one(pdev, port_info, 2);
662 }
663
664 #ifdef CONFIG_PM
665 static int amd_reinit_one(struct pci_dev *pdev)
666 {
667 if (pdev->vendor == PCI_VENDOR_ID_AMD) {
668 u8 fifo;
669 pci_read_config_byte(pdev, 0x41, &fifo);
670 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
671 /* FIFO is broken */
672 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
673 else
674 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
675 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
676 pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
677 ata_pci_clear_simplex(pdev);
678 }
679 return ata_pci_device_resume(pdev);
680 }
681 #endif
682
683 static const struct pci_device_id amd[] = {
684 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
685 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
686 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
687 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
688 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
689 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
690 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
691 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
692 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
693 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
694 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
695 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
696 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
697 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
698 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
699 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
700 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
701 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
702
703 { },
704 };
705
706 static struct pci_driver amd_pci_driver = {
707 .name = DRV_NAME,
708 .id_table = amd,
709 .probe = amd_init_one,
710 .remove = ata_pci_remove_one,
711 #ifdef CONFIG_PM
712 .suspend = ata_pci_device_suspend,
713 .resume = amd_reinit_one,
714 #endif
715 };
716
717 static int __init amd_init(void)
718 {
719 return pci_register_driver(&amd_pci_driver);
720 }
721
722 static void __exit amd_exit(void)
723 {
724 pci_unregister_driver(&amd_pci_driver);
725 }
726
727 MODULE_AUTHOR("Alan Cox");
728 MODULE_DESCRIPTION("low-level driver for AMD PATA IDE");
729 MODULE_LICENSE("GPL");
730 MODULE_DEVICE_TABLE(pci, amd);
731 MODULE_VERSION(DRV_VERSION);
732
733 module_init(amd_init);
734 module_exit(amd_exit);
Linux kernel - Deliverables
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