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pata_hpt37x: Further small fixes
[deliverable/linux.git] / drivers / ata / pata_hpt37x.c
1 /*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 * Portions Copyright (C) 2005-2006 MontaVista Software, Inc.
12 *
13 * TODO
14 * PLL mode
15 * Look into engine reset on timeout errors. Should not be
16 * required.
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <scsi/scsi_host.h>
26 #include <linux/libata.h>
27
28 #define DRV_NAME "pata_hpt37x"
29 #define DRV_VERSION "0.6.5"
30
31 struct hpt_clock {
32 u8 xfer_speed;
33 u32 timing;
34 };
35
36 struct hpt_chip {
37 const char *name;
38 unsigned int base;
39 struct hpt_clock const *clocks[4];
40 };
41
42 /* key for bus clock timings
43 * bit
44 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
45 * DMA. cycles = value + 1
46 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
47 * DMA. cycles = value + 1
48 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
49 * register access.
50 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
51 * register access.
52 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
53 * during task file register access.
54 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
55 * xfer.
56 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
57 * register access.
58 * 28 UDMA enable
59 * 29 DMA enable
60 * 30 PIO_MST enable. if set, the chip is in bus master mode during
61 * PIO.
62 * 31 FIFO enable.
63 */
64
65 static struct hpt_clock hpt37x_timings_33[] = {
66 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
67 { XFER_UDMA_5, 0x12446231 },
68 { XFER_UDMA_4, 0x12446231 },
69 { XFER_UDMA_3, 0x126c6231 },
70 { XFER_UDMA_2, 0x12486231 },
71 { XFER_UDMA_1, 0x124c6233 },
72 { XFER_UDMA_0, 0x12506297 },
73
74 { XFER_MW_DMA_2, 0x22406c31 },
75 { XFER_MW_DMA_1, 0x22406c33 },
76 { XFER_MW_DMA_0, 0x22406c97 },
77
78 { XFER_PIO_4, 0x06414e31 },
79 { XFER_PIO_3, 0x06414e42 },
80 { XFER_PIO_2, 0x06414e53 },
81 { XFER_PIO_1, 0x06814e93 },
82 { XFER_PIO_0, 0x06814ea7 }
83 };
84
85 static struct hpt_clock hpt37x_timings_50[] = {
86 { XFER_UDMA_6, 0x12848242 },
87 { XFER_UDMA_5, 0x12848242 },
88 { XFER_UDMA_4, 0x12ac8242 },
89 { XFER_UDMA_3, 0x128c8242 },
90 { XFER_UDMA_2, 0x120c8242 },
91 { XFER_UDMA_1, 0x12148254 },
92 { XFER_UDMA_0, 0x121882ea },
93
94 { XFER_MW_DMA_2, 0x22808242 },
95 { XFER_MW_DMA_1, 0x22808254 },
96 { XFER_MW_DMA_0, 0x228082ea },
97
98 { XFER_PIO_4, 0x0a81f442 },
99 { XFER_PIO_3, 0x0a81f443 },
100 { XFER_PIO_2, 0x0a81f454 },
101 { XFER_PIO_1, 0x0ac1f465 },
102 { XFER_PIO_0, 0x0ac1f48a }
103 };
104
105 static struct hpt_clock hpt37x_timings_66[] = {
106 { XFER_UDMA_6, 0x1c869c62 },
107 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
108 { XFER_UDMA_4, 0x1c8a9c62 },
109 { XFER_UDMA_3, 0x1c8e9c62 },
110 { XFER_UDMA_2, 0x1c929c62 },
111 { XFER_UDMA_1, 0x1c9a9c62 },
112 { XFER_UDMA_0, 0x1c829c62 },
113
114 { XFER_MW_DMA_2, 0x2c829c62 },
115 { XFER_MW_DMA_1, 0x2c829c66 },
116 { XFER_MW_DMA_0, 0x2c829d2e },
117
118 { XFER_PIO_4, 0x0c829c62 },
119 { XFER_PIO_3, 0x0c829c84 },
120 { XFER_PIO_2, 0x0c829ca6 },
121 { XFER_PIO_1, 0x0d029d26 },
122 { XFER_PIO_0, 0x0d029d5e }
123 };
124
125
126 static const struct hpt_chip hpt370 = {
127 "HPT370",
128 48,
129 {
130 hpt37x_timings_33,
131 NULL,
132 NULL,
133 NULL
134 }
135 };
136
137 static const struct hpt_chip hpt370a = {
138 "HPT370A",
139 48,
140 {
141 hpt37x_timings_33,
142 NULL,
143 hpt37x_timings_50,
144 NULL
145 }
146 };
147
148 static const struct hpt_chip hpt372 = {
149 "HPT372",
150 55,
151 {
152 hpt37x_timings_33,
153 NULL,
154 hpt37x_timings_50,
155 hpt37x_timings_66
156 }
157 };
158
159 static const struct hpt_chip hpt302 = {
160 "HPT302",
161 66,
162 {
163 hpt37x_timings_33,
164 NULL,
165 hpt37x_timings_50,
166 hpt37x_timings_66
167 }
168 };
169
170 static const struct hpt_chip hpt371 = {
171 "HPT371",
172 66,
173 {
174 hpt37x_timings_33,
175 NULL,
176 hpt37x_timings_50,
177 hpt37x_timings_66
178 }
179 };
180
181 static const struct hpt_chip hpt372a = {
182 "HPT372A",
183 66,
184 {
185 hpt37x_timings_33,
186 NULL,
187 hpt37x_timings_50,
188 hpt37x_timings_66
189 }
190 };
191
192 static const struct hpt_chip hpt374 = {
193 "HPT374",
194 48,
195 {
196 hpt37x_timings_33,
197 NULL,
198 NULL,
199 NULL
200 }
201 };
202
203 /**
204 * hpt37x_find_mode - reset the hpt37x bus
205 * @ap: ATA port
206 * @speed: transfer mode
207 *
208 * Return the 32bit register programming information for this channel
209 * that matches the speed provided.
210 */
211
212 static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
213 {
214 struct hpt_clock *clocks = ap->host->private_data;
215
216 while(clocks->xfer_speed) {
217 if (clocks->xfer_speed == speed)
218 return clocks->timing;
219 clocks++;
220 }
221 BUG();
222 return 0xffffffffU; /* silence compiler warning */
223 }
224
225 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
226 {
227 unsigned char model_num[ATA_ID_PROD_LEN + 1];
228 int i = 0;
229
230 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
231
232 while (list[i] != NULL) {
233 if (!strcmp(list[i], model_num)) {
234 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
235 modestr, list[i]);
236 return 1;
237 }
238 i++;
239 }
240 return 0;
241 }
242
243 static const char *bad_ata33[] = {
244 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
245 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
246 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
247 "Maxtor 90510D4",
248 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
249 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
250 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
251 NULL
252 };
253
254 static const char *bad_ata100_5[] = {
255 "IBM-DTLA-307075",
256 "IBM-DTLA-307060",
257 "IBM-DTLA-307045",
258 "IBM-DTLA-307030",
259 "IBM-DTLA-307020",
260 "IBM-DTLA-307015",
261 "IBM-DTLA-305040",
262 "IBM-DTLA-305030",
263 "IBM-DTLA-305020",
264 "IC35L010AVER07-0",
265 "IC35L020AVER07-0",
266 "IC35L030AVER07-0",
267 "IC35L040AVER07-0",
268 "IC35L060AVER07-0",
269 "WDC AC310200R",
270 NULL
271 };
272
273 /**
274 * hpt370_filter - mode selection filter
275 * @adev: ATA device
276 *
277 * Block UDMA on devices that cause trouble with this controller.
278 */
279
280 static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
281 {
282 if (adev->class == ATA_DEV_ATA) {
283 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
284 mask &= ~ATA_MASK_UDMA;
285 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
286 mask &= ~(0x1F << ATA_SHIFT_UDMA);
287 }
288 return ata_pci_default_filter(adev, mask);
289 }
290
291 /**
292 * hpt370a_filter - mode selection filter
293 * @adev: ATA device
294 *
295 * Block UDMA on devices that cause trouble with this controller.
296 */
297
298 static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
299 {
300 if (adev->class != ATA_DEV_ATA) {
301 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
302 mask &= ~ (0x1F << ATA_SHIFT_UDMA);
303 }
304 return ata_pci_default_filter(adev, mask);
305 }
306
307 /**
308 * hpt37x_pre_reset - reset the hpt37x bus
309 * @ap: ATA port to reset
310 *
311 * Perform the initial reset handling for the 370/372 and 374 func 0
312 */
313
314 static int hpt37x_pre_reset(struct ata_port *ap)
315 {
316 u8 scr2, ata66;
317 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
318 static const struct pci_bits hpt37x_enable_bits[] = {
319 { 0x50, 1, 0x04, 0x04 },
320 { 0x54, 1, 0x04, 0x04 }
321 };
322 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
323 return -ENOENT;
324
325 pci_read_config_byte(pdev, 0x5B, &scr2);
326 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
327 /* Cable register now active */
328 pci_read_config_byte(pdev, 0x5A, &ata66);
329 /* Restore state */
330 pci_write_config_byte(pdev, 0x5B, scr2);
331
332 if (ata66 & (1 << ap->port_no))
333 ap->cbl = ATA_CBL_PATA40;
334 else
335 ap->cbl = ATA_CBL_PATA80;
336
337 /* Reset the state machine */
338 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
339 udelay(100);
340
341 return ata_std_prereset(ap);
342 }
343
344 /**
345 * hpt37x_error_handler - reset the hpt374
346 * @ap: ATA port to reset
347 *
348 * Perform probe for HPT37x, except for HPT374 channel 2
349 */
350
351 static void hpt37x_error_handler(struct ata_port *ap)
352 {
353 ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
354 }
355
356 static int hpt374_pre_reset(struct ata_port *ap)
357 {
358 static const struct pci_bits hpt37x_enable_bits[] = {
359 { 0x50, 1, 0x04, 0x04 },
360 { 0x54, 1, 0x04, 0x04 }
361 };
362 u16 mcr3, mcr6;
363 u8 ata66;
364 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
365
366 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
367 return -ENOENT;
368
369 /* Do the extra channel work */
370 pci_read_config_word(pdev, 0x52, &mcr3);
371 pci_read_config_word(pdev, 0x56, &mcr6);
372 /* Set bit 15 of 0x52 to enable TCBLID as input
373 Set bit 15 of 0x56 to enable FCBLID as input
374 */
375 pci_write_config_word(pdev, 0x52, mcr3 | 0x8000);
376 pci_write_config_word(pdev, 0x56, mcr6 | 0x8000);
377 pci_read_config_byte(pdev, 0x5A, &ata66);
378 /* Reset TCBLID/FCBLID to output */
379 pci_write_config_word(pdev, 0x52, mcr3);
380 pci_write_config_word(pdev, 0x56, mcr6);
381
382 if (ata66 & (1 << ap->port_no))
383 ap->cbl = ATA_CBL_PATA40;
384 else
385 ap->cbl = ATA_CBL_PATA80;
386
387 /* Reset the state machine */
388 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
389 udelay(100);
390
391 return ata_std_prereset(ap);
392 }
393
394 /**
395 * hpt374_error_handler - reset the hpt374
396 * @classes:
397 *
398 * The 374 cable detect is a little different due to the extra
399 * channels. The function 0 channels work like usual but function 1
400 * is special
401 */
402
403 static void hpt374_error_handler(struct ata_port *ap)
404 {
405 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
406
407 if (!(PCI_FUNC(pdev->devfn) & 1))
408 hpt37x_error_handler(ap);
409 else
410 ata_bmdma_drive_eh(ap, hpt374_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
411 }
412
413 /**
414 * hpt370_set_piomode - PIO setup
415 * @ap: ATA interface
416 * @adev: device on the interface
417 *
418 * Perform PIO mode setup.
419 */
420
421 static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
422 {
423 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
424 u32 addr1, addr2;
425 u32 reg;
426 u32 mode;
427 u8 fast;
428
429 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
430 addr2 = 0x51 + 4 * ap->port_no;
431
432 /* Fast interrupt prediction disable, hold off interrupt disable */
433 pci_read_config_byte(pdev, addr2, &fast);
434 fast &= ~0x02;
435 fast |= 0x01;
436 pci_write_config_byte(pdev, addr2, fast);
437
438 pci_read_config_dword(pdev, addr1, &reg);
439 mode = hpt37x_find_mode(ap, adev->pio_mode);
440 mode &= ~0x8000000; /* No FIFO in PIO */
441 mode &= ~0x30070000; /* Leave config bits alone */
442 reg &= 0x30070000; /* Strip timing bits */
443 pci_write_config_dword(pdev, addr1, reg | mode);
444 }
445
446 /**
447 * hpt370_set_dmamode - DMA timing setup
448 * @ap: ATA interface
449 * @adev: Device being configured
450 *
451 * Set up the channel for MWDMA or UDMA modes. Much the same as with
452 * PIO, load the mode number and then set MWDMA or UDMA flag.
453 */
454
455 static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
456 {
457 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
458 u32 addr1, addr2;
459 u32 reg;
460 u32 mode;
461 u8 fast;
462
463 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
464 addr2 = 0x51 + 4 * ap->port_no;
465
466 /* Fast interrupt prediction disable, hold off interrupt disable */
467 pci_read_config_byte(pdev, addr2, &fast);
468 fast &= ~0x02;
469 fast |= 0x01;
470 pci_write_config_byte(pdev, addr2, fast);
471
472 pci_read_config_dword(pdev, addr1, &reg);
473 mode = hpt37x_find_mode(ap, adev->dma_mode);
474 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
475 mode &= ~0xC0000000; /* Leave config bits alone */
476 reg &= 0xC0000000; /* Strip timing bits */
477 pci_write_config_dword(pdev, addr1, reg | mode);
478 }
479
480 /**
481 * hpt370_bmdma_start - DMA engine begin
482 * @qc: ATA command
483 *
484 * The 370 and 370A want us to reset the DMA engine each time we
485 * use it. The 372 and later are fine.
486 */
487
488 static void hpt370_bmdma_start(struct ata_queued_cmd *qc)
489 {
490 struct ata_port *ap = qc->ap;
491 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
492 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
493 udelay(10);
494 ata_bmdma_start(qc);
495 }
496
497 /**
498 * hpt370_bmdma_end - DMA engine stop
499 * @qc: ATA command
500 *
501 * Work around the HPT370 DMA engine.
502 */
503
504 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
505 {
506 struct ata_port *ap = qc->ap;
507 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
508 u8 dma_stat = ioread8(ap->ioaddr.bmdma_addr + 2);
509 u8 dma_cmd;
510 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
511
512 if (dma_stat & 0x01) {
513 udelay(20);
514 dma_stat = ioread8(bmdma + 2);
515 }
516 if (dma_stat & 0x01) {
517 /* Clear the engine */
518 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
519 udelay(10);
520 /* Stop DMA */
521 dma_cmd = ioread8(bmdma );
522 iowrite8(dma_cmd & 0xFE, bmdma);
523 /* Clear Error */
524 dma_stat = ioread8(bmdma + 2);
525 iowrite8(dma_stat | 0x06 , bmdma + 2);
526 /* Clear the engine */
527 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
528 udelay(10);
529 }
530 ata_bmdma_stop(qc);
531 }
532
533 /**
534 * hpt372_set_piomode - PIO setup
535 * @ap: ATA interface
536 * @adev: device on the interface
537 *
538 * Perform PIO mode setup.
539 */
540
541 static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
542 {
543 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
544 u32 addr1, addr2;
545 u32 reg;
546 u32 mode;
547 u8 fast;
548
549 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
550 addr2 = 0x51 + 4 * ap->port_no;
551
552 /* Fast interrupt prediction disable, hold off interrupt disable */
553 pci_read_config_byte(pdev, addr2, &fast);
554 fast &= ~0x07;
555 pci_write_config_byte(pdev, addr2, fast);
556
557 pci_read_config_dword(pdev, addr1, &reg);
558 mode = hpt37x_find_mode(ap, adev->pio_mode);
559
560 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
561 mode &= ~0x80000000; /* No FIFO in PIO */
562 mode &= ~0x30070000; /* Leave config bits alone */
563 reg &= 0x30070000; /* Strip timing bits */
564 pci_write_config_dword(pdev, addr1, reg | mode);
565 }
566
567 /**
568 * hpt372_set_dmamode - DMA timing setup
569 * @ap: ATA interface
570 * @adev: Device being configured
571 *
572 * Set up the channel for MWDMA or UDMA modes. Much the same as with
573 * PIO, load the mode number and then set MWDMA or UDMA flag.
574 */
575
576 static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
577 {
578 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
579 u32 addr1, addr2;
580 u32 reg;
581 u32 mode;
582 u8 fast;
583
584 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
585 addr2 = 0x51 + 4 * ap->port_no;
586
587 /* Fast interrupt prediction disable, hold off interrupt disable */
588 pci_read_config_byte(pdev, addr2, &fast);
589 fast &= ~0x07;
590 pci_write_config_byte(pdev, addr2, fast);
591
592 pci_read_config_dword(pdev, addr1, &reg);
593 mode = hpt37x_find_mode(ap, adev->dma_mode);
594 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
595 mode &= ~0xC0000000; /* Leave config bits alone */
596 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */
597 reg &= 0xC0000000; /* Strip timing bits */
598 pci_write_config_dword(pdev, addr1, reg | mode);
599 }
600
601 /**
602 * hpt37x_bmdma_end - DMA engine stop
603 * @qc: ATA command
604 *
605 * Clean up after the HPT372 and later DMA engine
606 */
607
608 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
609 {
610 struct ata_port *ap = qc->ap;
611 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
612 int mscreg = 0x50 + 4 * ap->port_no;
613 u8 bwsr_stat, msc_stat;
614
615 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
616 pci_read_config_byte(pdev, mscreg, &msc_stat);
617 if (bwsr_stat & (1 << ap->port_no))
618 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
619 ata_bmdma_stop(qc);
620 }
621
622
623 static struct scsi_host_template hpt37x_sht = {
624 .module = THIS_MODULE,
625 .name = DRV_NAME,
626 .ioctl = ata_scsi_ioctl,
627 .queuecommand = ata_scsi_queuecmd,
628 .can_queue = ATA_DEF_QUEUE,
629 .this_id = ATA_SHT_THIS_ID,
630 .sg_tablesize = LIBATA_MAX_PRD,
631 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
632 .emulated = ATA_SHT_EMULATED,
633 .use_clustering = ATA_SHT_USE_CLUSTERING,
634 .proc_name = DRV_NAME,
635 .dma_boundary = ATA_DMA_BOUNDARY,
636 .slave_configure = ata_scsi_slave_config,
637 .slave_destroy = ata_scsi_slave_destroy,
638 .bios_param = ata_std_bios_param,
639 };
640
641 /*
642 * Configuration for HPT370
643 */
644
645 static struct ata_port_operations hpt370_port_ops = {
646 .port_disable = ata_port_disable,
647 .set_piomode = hpt370_set_piomode,
648 .set_dmamode = hpt370_set_dmamode,
649 .mode_filter = hpt370_filter,
650
651 .tf_load = ata_tf_load,
652 .tf_read = ata_tf_read,
653 .check_status = ata_check_status,
654 .exec_command = ata_exec_command,
655 .dev_select = ata_std_dev_select,
656
657 .freeze = ata_bmdma_freeze,
658 .thaw = ata_bmdma_thaw,
659 .error_handler = hpt37x_error_handler,
660 .post_internal_cmd = ata_bmdma_post_internal_cmd,
661
662 .bmdma_setup = ata_bmdma_setup,
663 .bmdma_start = hpt370_bmdma_start,
664 .bmdma_stop = hpt370_bmdma_stop,
665 .bmdma_status = ata_bmdma_status,
666
667 .qc_prep = ata_qc_prep,
668 .qc_issue = ata_qc_issue_prot,
669
670 .data_xfer = ata_data_xfer,
671
672 .irq_handler = ata_interrupt,
673 .irq_clear = ata_bmdma_irq_clear,
674 .irq_on = ata_irq_on,
675 .irq_ack = ata_irq_ack,
676
677 .port_start = ata_port_start,
678 };
679
680 /*
681 * Configuration for HPT370A. Close to 370 but less filters
682 */
683
684 static struct ata_port_operations hpt370a_port_ops = {
685 .port_disable = ata_port_disable,
686 .set_piomode = hpt370_set_piomode,
687 .set_dmamode = hpt370_set_dmamode,
688 .mode_filter = hpt370a_filter,
689
690 .tf_load = ata_tf_load,
691 .tf_read = ata_tf_read,
692 .check_status = ata_check_status,
693 .exec_command = ata_exec_command,
694 .dev_select = ata_std_dev_select,
695
696 .freeze = ata_bmdma_freeze,
697 .thaw = ata_bmdma_thaw,
698 .error_handler = hpt37x_error_handler,
699 .post_internal_cmd = ata_bmdma_post_internal_cmd,
700
701 .bmdma_setup = ata_bmdma_setup,
702 .bmdma_start = hpt370_bmdma_start,
703 .bmdma_stop = hpt370_bmdma_stop,
704 .bmdma_status = ata_bmdma_status,
705
706 .qc_prep = ata_qc_prep,
707 .qc_issue = ata_qc_issue_prot,
708
709 .data_xfer = ata_data_xfer,
710
711 .irq_handler = ata_interrupt,
712 .irq_clear = ata_bmdma_irq_clear,
713 .irq_on = ata_irq_on,
714 .irq_ack = ata_irq_ack,
715
716 .port_start = ata_port_start,
717 };
718
719 /*
720 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
721 * and DMA mode setting functionality.
722 */
723
724 static struct ata_port_operations hpt372_port_ops = {
725 .port_disable = ata_port_disable,
726 .set_piomode = hpt372_set_piomode,
727 .set_dmamode = hpt372_set_dmamode,
728 .mode_filter = ata_pci_default_filter,
729
730 .tf_load = ata_tf_load,
731 .tf_read = ata_tf_read,
732 .check_status = ata_check_status,
733 .exec_command = ata_exec_command,
734 .dev_select = ata_std_dev_select,
735
736 .freeze = ata_bmdma_freeze,
737 .thaw = ata_bmdma_thaw,
738 .error_handler = hpt37x_error_handler,
739 .post_internal_cmd = ata_bmdma_post_internal_cmd,
740
741 .bmdma_setup = ata_bmdma_setup,
742 .bmdma_start = ata_bmdma_start,
743 .bmdma_stop = hpt37x_bmdma_stop,
744 .bmdma_status = ata_bmdma_status,
745
746 .qc_prep = ata_qc_prep,
747 .qc_issue = ata_qc_issue_prot,
748
749 .data_xfer = ata_data_xfer,
750
751 .irq_handler = ata_interrupt,
752 .irq_clear = ata_bmdma_irq_clear,
753 .irq_on = ata_irq_on,
754 .irq_ack = ata_irq_ack,
755
756 .port_start = ata_port_start,
757 };
758
759 /*
760 * Configuration for HPT374. Mode setting works like 372 and friends
761 * but we have a different cable detection procedure.
762 */
763
764 static struct ata_port_operations hpt374_port_ops = {
765 .port_disable = ata_port_disable,
766 .set_piomode = hpt372_set_piomode,
767 .set_dmamode = hpt372_set_dmamode,
768 .mode_filter = ata_pci_default_filter,
769
770 .tf_load = ata_tf_load,
771 .tf_read = ata_tf_read,
772 .check_status = ata_check_status,
773 .exec_command = ata_exec_command,
774 .dev_select = ata_std_dev_select,
775
776 .freeze = ata_bmdma_freeze,
777 .thaw = ata_bmdma_thaw,
778 .error_handler = hpt374_error_handler,
779 .post_internal_cmd = ata_bmdma_post_internal_cmd,
780
781 .bmdma_setup = ata_bmdma_setup,
782 .bmdma_start = ata_bmdma_start,
783 .bmdma_stop = hpt37x_bmdma_stop,
784 .bmdma_status = ata_bmdma_status,
785
786 .qc_prep = ata_qc_prep,
787 .qc_issue = ata_qc_issue_prot,
788
789 .data_xfer = ata_data_xfer,
790
791 .irq_handler = ata_interrupt,
792 .irq_clear = ata_bmdma_irq_clear,
793 .irq_on = ata_irq_on,
794 .irq_ack = ata_irq_ack,
795
796 .port_start = ata_port_start,
797 };
798
799 /**
800 * htp37x_clock_slot - Turn timing to PC clock entry
801 * @freq: Reported frequency timing
802 * @base: Base timing
803 *
804 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
805 * and 3 for 66Mhz)
806 */
807
808 static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
809 {
810 unsigned int f = (base * freq) / 192; /* Mhz */
811 if (f < 40)
812 return 0; /* 33Mhz slot */
813 if (f < 45)
814 return 1; /* 40Mhz slot */
815 if (f < 55)
816 return 2; /* 50Mhz slot */
817 return 3; /* 60Mhz slot */
818 }
819
820 /**
821 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
822 * @dev: PCI device
823 *
824 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
825 * succeeds
826 */
827
828 static int hpt37x_calibrate_dpll(struct pci_dev *dev)
829 {
830 u8 reg5b;
831 u32 reg5c;
832 int tries;
833
834 for(tries = 0; tries < 0x5000; tries++) {
835 udelay(50);
836 pci_read_config_byte(dev, 0x5b, &reg5b);
837 if (reg5b & 0x80) {
838 /* See if it stays set */
839 for(tries = 0; tries < 0x1000; tries ++) {
840 pci_read_config_byte(dev, 0x5b, &reg5b);
841 /* Failed ? */
842 if ((reg5b & 0x80) == 0)
843 return 0;
844 }
845 /* Turn off tuning, we have the DPLL set */
846 pci_read_config_dword(dev, 0x5c, &reg5c);
847 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
848 return 1;
849 }
850 }
851 /* Never went stable */
852 return 0;
853 }
854 /**
855 * hpt37x_init_one - Initialise an HPT37X/302
856 * @dev: PCI device
857 * @id: Entry in match table
858 *
859 * Initialise an HPT37x device. There are some interesting complications
860 * here. Firstly the chip may report 366 and be one of several variants.
861 * Secondly all the timings depend on the clock for the chip which we must
862 * detect and look up
863 *
864 * This is the known chip mappings. It may be missing a couple of later
865 * releases.
866 *
867 * Chip version PCI Rev Notes
868 * HPT366 4 (HPT366) 0 Other driver
869 * HPT366 4 (HPT366) 1 Other driver
870 * HPT368 4 (HPT366) 2 Other driver
871 * HPT370 4 (HPT366) 3 UDMA100
872 * HPT370A 4 (HPT366) 4 UDMA100
873 * HPT372 4 (HPT366) 5 UDMA133 (1)
874 * HPT372N 4 (HPT366) 6 Other driver
875 * HPT372A 5 (HPT372) 1 UDMA133 (1)
876 * HPT372N 5 (HPT372) 2 Other driver
877 * HPT302 6 (HPT302) 1 UDMA133
878 * HPT302N 6 (HPT302) 2 Other driver
879 * HPT371 7 (HPT371) * UDMA133
880 * HPT374 8 (HPT374) * UDMA133 4 channel
881 * HPT372N 9 (HPT372N) * Other driver
882 *
883 * (1) UDMA133 support depends on the bus clock
884 */
885
886 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
887 {
888 /* HPT370 - UDMA100 */
889 static struct ata_port_info info_hpt370 = {
890 .sht = &hpt37x_sht,
891 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
892 .pio_mask = 0x1f,
893 .mwdma_mask = 0x07,
894 .udma_mask = 0x3f,
895 .port_ops = &hpt370_port_ops
896 };
897 /* HPT370A - UDMA100 */
898 static struct ata_port_info info_hpt370a = {
899 .sht = &hpt37x_sht,
900 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
901 .pio_mask = 0x1f,
902 .mwdma_mask = 0x07,
903 .udma_mask = 0x3f,
904 .port_ops = &hpt370a_port_ops
905 };
906 /* HPT370 - UDMA100 */
907 static struct ata_port_info info_hpt370_33 = {
908 .sht = &hpt37x_sht,
909 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
910 .pio_mask = 0x1f,
911 .mwdma_mask = 0x07,
912 .udma_mask = 0x0f,
913 .port_ops = &hpt370_port_ops
914 };
915 /* HPT370A - UDMA100 */
916 static struct ata_port_info info_hpt370a_33 = {
917 .sht = &hpt37x_sht,
918 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
919 .pio_mask = 0x1f,
920 .mwdma_mask = 0x07,
921 .udma_mask = 0x0f,
922 .port_ops = &hpt370a_port_ops
923 };
924 /* HPT371, 372 and friends - UDMA133 */
925 static struct ata_port_info info_hpt372 = {
926 .sht = &hpt37x_sht,
927 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
928 .pio_mask = 0x1f,
929 .mwdma_mask = 0x07,
930 .udma_mask = 0x7f,
931 .port_ops = &hpt372_port_ops
932 };
933 /* HPT371, 372 and friends - UDMA100 at 50MHz clock */
934 static struct ata_port_info info_hpt372_50 = {
935 .sht = &hpt37x_sht,
936 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
937 .pio_mask = 0x1f,
938 .mwdma_mask = 0x07,
939 .udma_mask = 0x3f,
940 .port_ops = &hpt372_port_ops
941 };
942 /* HPT374 - UDMA133 */
943 static struct ata_port_info info_hpt374 = {
944 .sht = &hpt37x_sht,
945 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
946 .pio_mask = 0x1f,
947 .mwdma_mask = 0x07,
948 .udma_mask = 0x7f,
949 .port_ops = &hpt374_port_ops
950 };
951
952 static const int MHz[4] = { 33, 40, 50, 66 };
953
954 struct ata_port_info *port_info[2];
955 struct ata_port_info *port;
956
957 u8 irqmask;
958 u32 class_rev;
959 u8 mcr1;
960 u32 freq;
961 int prefer_dpll = 1;
962
963 unsigned long iobase = pci_resource_start(dev, 4);
964
965 const struct hpt_chip *chip_table;
966 int clock_slot;
967
968 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
969 class_rev &= 0xFF;
970
971 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
972 /* May be a later chip in disguise. Check */
973 /* Older chips are in the HPT366 driver. Ignore them */
974 if (class_rev < 3)
975 return -ENODEV;
976 /* N series chips have their own driver. Ignore */
977 if (class_rev == 6)
978 return -ENODEV;
979
980 switch(class_rev) {
981 case 3:
982 port = &info_hpt370;
983 chip_table = &hpt370;
984 prefer_dpll = 0;
985 break;
986 case 4:
987 port = &info_hpt370a;
988 chip_table = &hpt370a;
989 prefer_dpll = 0;
990 break;
991 case 5:
992 port = &info_hpt372;
993 chip_table = &hpt372;
994 break;
995 default:
996 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
997 return -ENODEV;
998 }
999 } else {
1000 switch(dev->device) {
1001 case PCI_DEVICE_ID_TTI_HPT372:
1002 /* 372N if rev >= 2*/
1003 if (class_rev >= 2)
1004 return -ENODEV;
1005 port = &info_hpt372;
1006 chip_table = &hpt372a;
1007 break;
1008 case PCI_DEVICE_ID_TTI_HPT302:
1009 /* 302N if rev > 1 */
1010 if (class_rev > 1)
1011 return -ENODEV;
1012 port = &info_hpt372;
1013 /* Check this */
1014 chip_table = &hpt302;
1015 break;
1016 case PCI_DEVICE_ID_TTI_HPT371:
1017 if (class_rev > 1)
1018 return -ENODEV;
1019 port = &info_hpt372;
1020 chip_table = &hpt371;
1021 /* Single channel device, master is not present
1022 but the BIOS (or us for non x86) must mark it
1023 absent */
1024 pci_read_config_byte(dev, 0x50, &mcr1);
1025 mcr1 &= ~0x04;
1026 pci_write_config_byte(dev, 0x50, mcr1);
1027 break;
1028 case PCI_DEVICE_ID_TTI_HPT374:
1029 chip_table = &hpt374;
1030 port = &info_hpt374;
1031 break;
1032 default:
1033 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
1034 return -ENODEV;
1035 }
1036 }
1037 /* Ok so this is a chip we support */
1038
1039 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1040 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1041 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1042 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1043
1044 pci_read_config_byte(dev, 0x5A, &irqmask);
1045 irqmask &= ~0x10;
1046 pci_write_config_byte(dev, 0x5a, irqmask);
1047
1048 /*
1049 * default to pci clock. make sure MA15/16 are set to output
1050 * to prevent drives having problems with 40-pin cables. Needed
1051 * for some drives such as IBM-DTLA which will not enter ready
1052 * state on reset when PDIAG is a input.
1053 */
1054
1055 pci_write_config_byte(dev, 0x5b, 0x23);
1056
1057 /*
1058 * HighPoint does this for HPT372A.
1059 * NOTE: This register is only writeable via I/O space.
1060 */
1061 if (chip_table == &hpt372a)
1062 outb(0x0e, iobase + 0x9c);
1063
1064 /* Some devices do not let this value be accessed via PCI space
1065 according to the old driver */
1066
1067 freq = inl(iobase + 0x90);
1068 if ((freq >> 12) != 0xABCDE) {
1069 int i;
1070 u8 sr;
1071 u32 total = 0;
1072
1073 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
1074
1075 /* This is the process the HPT371 BIOS is reported to use */
1076 for(i = 0; i < 128; i++) {
1077 pci_read_config_byte(dev, 0x78, &sr);
1078 total += sr & 0x1FF;
1079 udelay(15);
1080 }
1081 freq = total / 128;
1082 }
1083 freq &= 0x1FF;
1084
1085 /*
1086 * Turn the frequency check into a band and then find a timing
1087 * table to match it.
1088 */
1089
1090 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
1091 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
1092 /*
1093 * We need to try PLL mode instead
1094 *
1095 * For non UDMA133 capable devices we should
1096 * use a 50MHz DPLL by choice
1097 */
1098 unsigned int f_low, f_high;
1099 int adjust;
1100
1101 clock_slot = 2;
1102 if (port->udma_mask & 0xE0)
1103 clock_slot = 3;
1104
1105 f_low = (MHz[clock_slot] * chip_table->base) / 192;
1106 f_high = f_low + 2;
1107
1108 /* Select the DPLL clock. */
1109 pci_write_config_byte(dev, 0x5b, 0x21);
1110
1111 for(adjust = 0; adjust < 8; adjust++) {
1112 if (hpt37x_calibrate_dpll(dev))
1113 break;
1114 /* See if it'll settle at a fractionally different clock */
1115 if ((adjust & 3) == 3) {
1116 f_low --;
1117 f_high ++;
1118 }
1119 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
1120 }
1121 if (adjust == 8) {
1122 printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n");
1123 return -ENODEV;
1124 }
1125 if (clock_slot == 3)
1126 port->private_data = (void *)hpt37x_timings_66;
1127 else
1128 port->private_data = (void *)hpt37x_timings_50;
1129
1130 printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[clock_slot]);
1131 } else {
1132 port->private_data = (void *)chip_table->clocks[clock_slot];
1133 /*
1134 * Perform a final fixup. Note that we will have used the
1135 * DPLL on the HPT372 which means we don't have to worry
1136 * about lack of UDMA133 support on lower clocks
1137 */
1138
1139 if (clock_slot < 2 && port == &info_hpt370)
1140 port = &info_hpt370_33;
1141 if (clock_slot < 2 && port == &info_hpt370a)
1142 port = &info_hpt370a_33;
1143 printk(KERN_INFO "hpt37x: %s: Bus clock %dMHz.\n", chip_table->name, MHz[clock_slot]);
1144 }
1145
1146 port_info[0] = port_info[1] = port;
1147 /* Now kick off ATA set up */
1148 return ata_pci_init_one(dev, port_info, 2);
1149 }
1150
1151 static const struct pci_device_id hpt37x[] = {
1152 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1153 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1154 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1155 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1156 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1157
1158 { },
1159 };
1160
1161 static struct pci_driver hpt37x_pci_driver = {
1162 .name = DRV_NAME,
1163 .id_table = hpt37x,
1164 .probe = hpt37x_init_one,
1165 .remove = ata_pci_remove_one
1166 };
1167
1168 static int __init hpt37x_init(void)
1169 {
1170 return pci_register_driver(&hpt37x_pci_driver);
1171 }
1172
1173 static void __exit hpt37x_exit(void)
1174 {
1175 pci_unregister_driver(&hpt37x_pci_driver);
1176 }
1177
1178 MODULE_AUTHOR("Alan Cox");
1179 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1180 MODULE_LICENSE("GPL");
1181 MODULE_DEVICE_TABLE(pci, hpt37x);
1182 MODULE_VERSION(DRV_VERSION);
1183
1184 module_init(hpt37x_init);
1185 module_exit(hpt37x_exit);
Linux kernel - Deliverables
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