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libata: implement and use SHT initializers
[deliverable/linux.git] / drivers / ata / pata_hpt37x.c
1 /*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
12 *
13 * TODO
14 * Look into engine reset on timeout errors. Should not be required.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/blkdev.h>
22 #include <linux/delay.h>
23 #include <scsi/scsi_host.h>
24 #include <linux/libata.h>
25
26 #define DRV_NAME "pata_hpt37x"
27 #define DRV_VERSION "0.6.11"
28
29 struct hpt_clock {
30 u8 xfer_speed;
31 u32 timing;
32 };
33
34 struct hpt_chip {
35 const char *name;
36 unsigned int base;
37 struct hpt_clock const *clocks[4];
38 };
39
40 /* key for bus clock timings
41 * bit
42 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
43 * DMA. cycles = value + 1
44 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
45 * DMA. cycles = value + 1
46 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
47 * register access.
48 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
49 * register access.
50 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
51 * during task file register access.
52 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
53 * xfer.
54 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
55 * register access.
56 * 28 UDMA enable
57 * 29 DMA enable
58 * 30 PIO_MST enable. if set, the chip is in bus master mode during
59 * PIO.
60 * 31 FIFO enable.
61 */
62
63 static struct hpt_clock hpt37x_timings_33[] = {
64 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
65 { XFER_UDMA_5, 0x12446231 },
66 { XFER_UDMA_4, 0x12446231 },
67 { XFER_UDMA_3, 0x126c6231 },
68 { XFER_UDMA_2, 0x12486231 },
69 { XFER_UDMA_1, 0x124c6233 },
70 { XFER_UDMA_0, 0x12506297 },
71
72 { XFER_MW_DMA_2, 0x22406c31 },
73 { XFER_MW_DMA_1, 0x22406c33 },
74 { XFER_MW_DMA_0, 0x22406c97 },
75
76 { XFER_PIO_4, 0x06414e31 },
77 { XFER_PIO_3, 0x06414e42 },
78 { XFER_PIO_2, 0x06414e53 },
79 { XFER_PIO_1, 0x06814e93 },
80 { XFER_PIO_0, 0x06814ea7 }
81 };
82
83 static struct hpt_clock hpt37x_timings_50[] = {
84 { XFER_UDMA_6, 0x12848242 },
85 { XFER_UDMA_5, 0x12848242 },
86 { XFER_UDMA_4, 0x12ac8242 },
87 { XFER_UDMA_3, 0x128c8242 },
88 { XFER_UDMA_2, 0x120c8242 },
89 { XFER_UDMA_1, 0x12148254 },
90 { XFER_UDMA_0, 0x121882ea },
91
92 { XFER_MW_DMA_2, 0x22808242 },
93 { XFER_MW_DMA_1, 0x22808254 },
94 { XFER_MW_DMA_0, 0x228082ea },
95
96 { XFER_PIO_4, 0x0a81f442 },
97 { XFER_PIO_3, 0x0a81f443 },
98 { XFER_PIO_2, 0x0a81f454 },
99 { XFER_PIO_1, 0x0ac1f465 },
100 { XFER_PIO_0, 0x0ac1f48a }
101 };
102
103 static struct hpt_clock hpt37x_timings_66[] = {
104 { XFER_UDMA_6, 0x1c869c62 },
105 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
106 { XFER_UDMA_4, 0x1c8a9c62 },
107 { XFER_UDMA_3, 0x1c8e9c62 },
108 { XFER_UDMA_2, 0x1c929c62 },
109 { XFER_UDMA_1, 0x1c9a9c62 },
110 { XFER_UDMA_0, 0x1c829c62 },
111
112 { XFER_MW_DMA_2, 0x2c829c62 },
113 { XFER_MW_DMA_1, 0x2c829c66 },
114 { XFER_MW_DMA_0, 0x2c829d2e },
115
116 { XFER_PIO_4, 0x0c829c62 },
117 { XFER_PIO_3, 0x0c829c84 },
118 { XFER_PIO_2, 0x0c829ca6 },
119 { XFER_PIO_1, 0x0d029d26 },
120 { XFER_PIO_0, 0x0d029d5e }
121 };
122
123
124 static const struct hpt_chip hpt370 = {
125 "HPT370",
126 48,
127 {
128 hpt37x_timings_33,
129 NULL,
130 NULL,
131 NULL
132 }
133 };
134
135 static const struct hpt_chip hpt370a = {
136 "HPT370A",
137 48,
138 {
139 hpt37x_timings_33,
140 NULL,
141 hpt37x_timings_50,
142 NULL
143 }
144 };
145
146 static const struct hpt_chip hpt372 = {
147 "HPT372",
148 55,
149 {
150 hpt37x_timings_33,
151 NULL,
152 hpt37x_timings_50,
153 hpt37x_timings_66
154 }
155 };
156
157 static const struct hpt_chip hpt302 = {
158 "HPT302",
159 66,
160 {
161 hpt37x_timings_33,
162 NULL,
163 hpt37x_timings_50,
164 hpt37x_timings_66
165 }
166 };
167
168 static const struct hpt_chip hpt371 = {
169 "HPT371",
170 66,
171 {
172 hpt37x_timings_33,
173 NULL,
174 hpt37x_timings_50,
175 hpt37x_timings_66
176 }
177 };
178
179 static const struct hpt_chip hpt372a = {
180 "HPT372A",
181 66,
182 {
183 hpt37x_timings_33,
184 NULL,
185 hpt37x_timings_50,
186 hpt37x_timings_66
187 }
188 };
189
190 static const struct hpt_chip hpt374 = {
191 "HPT374",
192 48,
193 {
194 hpt37x_timings_33,
195 NULL,
196 NULL,
197 NULL
198 }
199 };
200
201 /**
202 * hpt37x_find_mode - reset the hpt37x bus
203 * @ap: ATA port
204 * @speed: transfer mode
205 *
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
208 */
209
210 static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
211 {
212 struct hpt_clock *clocks = ap->host->private_data;
213
214 while(clocks->xfer_speed) {
215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
217 clocks++;
218 }
219 BUG();
220 return 0xffffffffU; /* silence compiler warning */
221 }
222
223 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
224 {
225 unsigned char model_num[ATA_ID_PROD_LEN + 1];
226 int i = 0;
227
228 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
229
230 while (list[i] != NULL) {
231 if (!strcmp(list[i], model_num)) {
232 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
233 modestr, list[i]);
234 return 1;
235 }
236 i++;
237 }
238 return 0;
239 }
240
241 static const char *bad_ata33[] = {
242 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
243 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
244 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
245 "Maxtor 90510D4",
246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
248 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
249 NULL
250 };
251
252 static const char *bad_ata100_5[] = {
253 "IBM-DTLA-307075",
254 "IBM-DTLA-307060",
255 "IBM-DTLA-307045",
256 "IBM-DTLA-307030",
257 "IBM-DTLA-307020",
258 "IBM-DTLA-307015",
259 "IBM-DTLA-305040",
260 "IBM-DTLA-305030",
261 "IBM-DTLA-305020",
262 "IC35L010AVER07-0",
263 "IC35L020AVER07-0",
264 "IC35L030AVER07-0",
265 "IC35L040AVER07-0",
266 "IC35L060AVER07-0",
267 "WDC AC310200R",
268 NULL
269 };
270
271 /**
272 * hpt370_filter - mode selection filter
273 * @adev: ATA device
274 *
275 * Block UDMA on devices that cause trouble with this controller.
276 */
277
278 static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
279 {
280 if (adev->class == ATA_DEV_ATA) {
281 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
282 mask &= ~ATA_MASK_UDMA;
283 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
284 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
285 }
286 return ata_pci_default_filter(adev, mask);
287 }
288
289 /**
290 * hpt370a_filter - mode selection filter
291 * @adev: ATA device
292 *
293 * Block UDMA on devices that cause trouble with this controller.
294 */
295
296 static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
297 {
298 if (adev->class == ATA_DEV_ATA) {
299 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
300 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
301 }
302 return ata_pci_default_filter(adev, mask);
303 }
304
305 /**
306 * hpt37x_pre_reset - reset the hpt37x bus
307 * @link: ATA link to reset
308 * @deadline: deadline jiffies for the operation
309 *
310 * Perform the initial reset handling for the 370/372 and 374 func 0
311 */
312
313 static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
314 {
315 u8 scr2, ata66;
316 struct ata_port *ap = link->ap;
317 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
318 static const struct pci_bits hpt37x_enable_bits[] = {
319 { 0x50, 1, 0x04, 0x04 },
320 { 0x54, 1, 0x04, 0x04 }
321 };
322 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
323 return -ENOENT;
324
325 pci_read_config_byte(pdev, 0x5B, &scr2);
326 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
327 /* Cable register now active */
328 pci_read_config_byte(pdev, 0x5A, &ata66);
329 /* Restore state */
330 pci_write_config_byte(pdev, 0x5B, scr2);
331
332 if (ata66 & (2 >> ap->port_no))
333 ap->cbl = ATA_CBL_PATA40;
334 else
335 ap->cbl = ATA_CBL_PATA80;
336
337 /* Reset the state machine */
338 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
339 udelay(100);
340
341 return ata_std_prereset(link, deadline);
342 }
343
344 /**
345 * hpt37x_error_handler - reset the hpt374
346 * @ap: ATA port to reset
347 *
348 * Perform probe for HPT37x, except for HPT374 channel 2
349 */
350
351 static void hpt37x_error_handler(struct ata_port *ap)
352 {
353 ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
354 }
355
356 static int hpt374_pre_reset(struct ata_link *link, unsigned long deadline)
357 {
358 static const struct pci_bits hpt37x_enable_bits[] = {
359 { 0x50, 1, 0x04, 0x04 },
360 { 0x54, 1, 0x04, 0x04 }
361 };
362 u16 mcr3;
363 u8 ata66;
364 struct ata_port *ap = link->ap;
365 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
366 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
367
368 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
369 return -ENOENT;
370
371 /* Do the extra channel work */
372 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
373 /* Set bit 15 of 0x52 to enable TCBLID as input
374 */
375 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
376 pci_read_config_byte(pdev, 0x5A, &ata66);
377 /* Reset TCBLID/FCBLID to output */
378 pci_write_config_word(pdev, mcrbase + 2, mcr3);
379
380 if (ata66 & (2 >> ap->port_no))
381 ap->cbl = ATA_CBL_PATA40;
382 else
383 ap->cbl = ATA_CBL_PATA80;
384
385 /* Reset the state machine */
386 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
387 udelay(100);
388
389 return ata_std_prereset(link, deadline);
390 }
391
392 /**
393 * hpt374_error_handler - reset the hpt374
394 * @classes:
395 *
396 * The 374 cable detect is a little different due to the extra
397 * channels. The function 0 channels work like usual but function 1
398 * is special
399 */
400
401 static void hpt374_error_handler(struct ata_port *ap)
402 {
403 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
404
405 if (!(PCI_FUNC(pdev->devfn) & 1))
406 hpt37x_error_handler(ap);
407 else
408 ata_bmdma_drive_eh(ap, hpt374_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
409 }
410
411 /**
412 * hpt370_set_piomode - PIO setup
413 * @ap: ATA interface
414 * @adev: device on the interface
415 *
416 * Perform PIO mode setup.
417 */
418
419 static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
420 {
421 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
422 u32 addr1, addr2;
423 u32 reg;
424 u32 mode;
425 u8 fast;
426
427 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
428 addr2 = 0x51 + 4 * ap->port_no;
429
430 /* Fast interrupt prediction disable, hold off interrupt disable */
431 pci_read_config_byte(pdev, addr2, &fast);
432 fast &= ~0x02;
433 fast |= 0x01;
434 pci_write_config_byte(pdev, addr2, fast);
435
436 pci_read_config_dword(pdev, addr1, &reg);
437 mode = hpt37x_find_mode(ap, adev->pio_mode);
438 mode &= ~0x8000000; /* No FIFO in PIO */
439 mode &= ~0x30070000; /* Leave config bits alone */
440 reg &= 0x30070000; /* Strip timing bits */
441 pci_write_config_dword(pdev, addr1, reg | mode);
442 }
443
444 /**
445 * hpt370_set_dmamode - DMA timing setup
446 * @ap: ATA interface
447 * @adev: Device being configured
448 *
449 * Set up the channel for MWDMA or UDMA modes. Much the same as with
450 * PIO, load the mode number and then set MWDMA or UDMA flag.
451 */
452
453 static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
454 {
455 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
456 u32 addr1, addr2;
457 u32 reg;
458 u32 mode;
459 u8 fast;
460
461 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
462 addr2 = 0x51 + 4 * ap->port_no;
463
464 /* Fast interrupt prediction disable, hold off interrupt disable */
465 pci_read_config_byte(pdev, addr2, &fast);
466 fast &= ~0x02;
467 fast |= 0x01;
468 pci_write_config_byte(pdev, addr2, fast);
469
470 pci_read_config_dword(pdev, addr1, &reg);
471 mode = hpt37x_find_mode(ap, adev->dma_mode);
472 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
473 mode &= ~0xC0000000; /* Leave config bits alone */
474 reg &= 0xC0000000; /* Strip timing bits */
475 pci_write_config_dword(pdev, addr1, reg | mode);
476 }
477
478 /**
479 * hpt370_bmdma_start - DMA engine begin
480 * @qc: ATA command
481 *
482 * The 370 and 370A want us to reset the DMA engine each time we
483 * use it. The 372 and later are fine.
484 */
485
486 static void hpt370_bmdma_start(struct ata_queued_cmd *qc)
487 {
488 struct ata_port *ap = qc->ap;
489 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
490 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
491 udelay(10);
492 ata_bmdma_start(qc);
493 }
494
495 /**
496 * hpt370_bmdma_end - DMA engine stop
497 * @qc: ATA command
498 *
499 * Work around the HPT370 DMA engine.
500 */
501
502 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
503 {
504 struct ata_port *ap = qc->ap;
505 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
506 u8 dma_stat = ioread8(ap->ioaddr.bmdma_addr + 2);
507 u8 dma_cmd;
508 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
509
510 if (dma_stat & 0x01) {
511 udelay(20);
512 dma_stat = ioread8(bmdma + 2);
513 }
514 if (dma_stat & 0x01) {
515 /* Clear the engine */
516 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
517 udelay(10);
518 /* Stop DMA */
519 dma_cmd = ioread8(bmdma );
520 iowrite8(dma_cmd & 0xFE, bmdma);
521 /* Clear Error */
522 dma_stat = ioread8(bmdma + 2);
523 iowrite8(dma_stat | 0x06 , bmdma + 2);
524 /* Clear the engine */
525 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
526 udelay(10);
527 }
528 ata_bmdma_stop(qc);
529 }
530
531 /**
532 * hpt372_set_piomode - PIO setup
533 * @ap: ATA interface
534 * @adev: device on the interface
535 *
536 * Perform PIO mode setup.
537 */
538
539 static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
540 {
541 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
542 u32 addr1, addr2;
543 u32 reg;
544 u32 mode;
545 u8 fast;
546
547 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
548 addr2 = 0x51 + 4 * ap->port_no;
549
550 /* Fast interrupt prediction disable, hold off interrupt disable */
551 pci_read_config_byte(pdev, addr2, &fast);
552 fast &= ~0x07;
553 pci_write_config_byte(pdev, addr2, fast);
554
555 pci_read_config_dword(pdev, addr1, &reg);
556 mode = hpt37x_find_mode(ap, adev->pio_mode);
557
558 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
559 mode &= ~0x80000000; /* No FIFO in PIO */
560 mode &= ~0x30070000; /* Leave config bits alone */
561 reg &= 0x30070000; /* Strip timing bits */
562 pci_write_config_dword(pdev, addr1, reg | mode);
563 }
564
565 /**
566 * hpt372_set_dmamode - DMA timing setup
567 * @ap: ATA interface
568 * @adev: Device being configured
569 *
570 * Set up the channel for MWDMA or UDMA modes. Much the same as with
571 * PIO, load the mode number and then set MWDMA or UDMA flag.
572 */
573
574 static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
575 {
576 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
577 u32 addr1, addr2;
578 u32 reg;
579 u32 mode;
580 u8 fast;
581
582 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
583 addr2 = 0x51 + 4 * ap->port_no;
584
585 /* Fast interrupt prediction disable, hold off interrupt disable */
586 pci_read_config_byte(pdev, addr2, &fast);
587 fast &= ~0x07;
588 pci_write_config_byte(pdev, addr2, fast);
589
590 pci_read_config_dword(pdev, addr1, &reg);
591 mode = hpt37x_find_mode(ap, adev->dma_mode);
592 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
593 mode &= ~0xC0000000; /* Leave config bits alone */
594 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */
595 reg &= 0xC0000000; /* Strip timing bits */
596 pci_write_config_dword(pdev, addr1, reg | mode);
597 }
598
599 /**
600 * hpt37x_bmdma_end - DMA engine stop
601 * @qc: ATA command
602 *
603 * Clean up after the HPT372 and later DMA engine
604 */
605
606 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
607 {
608 struct ata_port *ap = qc->ap;
609 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
610 int mscreg = 0x50 + 4 * ap->port_no;
611 u8 bwsr_stat, msc_stat;
612
613 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
614 pci_read_config_byte(pdev, mscreg, &msc_stat);
615 if (bwsr_stat & (1 << ap->port_no))
616 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
617 ata_bmdma_stop(qc);
618 }
619
620
621 static struct scsi_host_template hpt37x_sht = {
622 ATA_BMDMA_SHT(DRV_NAME),
623 };
624
625 /*
626 * Configuration for HPT370
627 */
628
629 static struct ata_port_operations hpt370_port_ops = {
630 .set_piomode = hpt370_set_piomode,
631 .set_dmamode = hpt370_set_dmamode,
632 .mode_filter = hpt370_filter,
633
634 .tf_load = ata_tf_load,
635 .tf_read = ata_tf_read,
636 .check_status = ata_check_status,
637 .exec_command = ata_exec_command,
638 .dev_select = ata_std_dev_select,
639
640 .freeze = ata_bmdma_freeze,
641 .thaw = ata_bmdma_thaw,
642 .error_handler = hpt37x_error_handler,
643 .post_internal_cmd = ata_bmdma_post_internal_cmd,
644
645 .bmdma_setup = ata_bmdma_setup,
646 .bmdma_start = hpt370_bmdma_start,
647 .bmdma_stop = hpt370_bmdma_stop,
648 .bmdma_status = ata_bmdma_status,
649
650 .qc_prep = ata_qc_prep,
651 .qc_issue = ata_qc_issue_prot,
652
653 .data_xfer = ata_data_xfer,
654
655 .irq_handler = ata_interrupt,
656 .irq_clear = ata_bmdma_irq_clear,
657 .irq_on = ata_irq_on,
658
659 .port_start = ata_sff_port_start,
660 };
661
662 /*
663 * Configuration for HPT370A. Close to 370 but less filters
664 */
665
666 static struct ata_port_operations hpt370a_port_ops = {
667 .set_piomode = hpt370_set_piomode,
668 .set_dmamode = hpt370_set_dmamode,
669 .mode_filter = hpt370a_filter,
670
671 .tf_load = ata_tf_load,
672 .tf_read = ata_tf_read,
673 .check_status = ata_check_status,
674 .exec_command = ata_exec_command,
675 .dev_select = ata_std_dev_select,
676
677 .freeze = ata_bmdma_freeze,
678 .thaw = ata_bmdma_thaw,
679 .error_handler = hpt37x_error_handler,
680 .post_internal_cmd = ata_bmdma_post_internal_cmd,
681
682 .bmdma_setup = ata_bmdma_setup,
683 .bmdma_start = hpt370_bmdma_start,
684 .bmdma_stop = hpt370_bmdma_stop,
685 .bmdma_status = ata_bmdma_status,
686
687 .qc_prep = ata_qc_prep,
688 .qc_issue = ata_qc_issue_prot,
689
690 .data_xfer = ata_data_xfer,
691
692 .irq_handler = ata_interrupt,
693 .irq_clear = ata_bmdma_irq_clear,
694 .irq_on = ata_irq_on,
695
696 .port_start = ata_sff_port_start,
697 };
698
699 /*
700 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
701 * and DMA mode setting functionality.
702 */
703
704 static struct ata_port_operations hpt372_port_ops = {
705 .set_piomode = hpt372_set_piomode,
706 .set_dmamode = hpt372_set_dmamode,
707 .mode_filter = ata_pci_default_filter,
708
709 .tf_load = ata_tf_load,
710 .tf_read = ata_tf_read,
711 .check_status = ata_check_status,
712 .exec_command = ata_exec_command,
713 .dev_select = ata_std_dev_select,
714
715 .freeze = ata_bmdma_freeze,
716 .thaw = ata_bmdma_thaw,
717 .error_handler = hpt37x_error_handler,
718 .post_internal_cmd = ata_bmdma_post_internal_cmd,
719
720 .bmdma_setup = ata_bmdma_setup,
721 .bmdma_start = ata_bmdma_start,
722 .bmdma_stop = hpt37x_bmdma_stop,
723 .bmdma_status = ata_bmdma_status,
724
725 .qc_prep = ata_qc_prep,
726 .qc_issue = ata_qc_issue_prot,
727
728 .data_xfer = ata_data_xfer,
729
730 .irq_handler = ata_interrupt,
731 .irq_clear = ata_bmdma_irq_clear,
732 .irq_on = ata_irq_on,
733
734 .port_start = ata_sff_port_start,
735 };
736
737 /*
738 * Configuration for HPT374. Mode setting works like 372 and friends
739 * but we have a different cable detection procedure.
740 */
741
742 static struct ata_port_operations hpt374_port_ops = {
743 .set_piomode = hpt372_set_piomode,
744 .set_dmamode = hpt372_set_dmamode,
745 .mode_filter = ata_pci_default_filter,
746
747 .tf_load = ata_tf_load,
748 .tf_read = ata_tf_read,
749 .check_status = ata_check_status,
750 .exec_command = ata_exec_command,
751 .dev_select = ata_std_dev_select,
752
753 .freeze = ata_bmdma_freeze,
754 .thaw = ata_bmdma_thaw,
755 .error_handler = hpt374_error_handler,
756 .post_internal_cmd = ata_bmdma_post_internal_cmd,
757
758 .bmdma_setup = ata_bmdma_setup,
759 .bmdma_start = ata_bmdma_start,
760 .bmdma_stop = hpt37x_bmdma_stop,
761 .bmdma_status = ata_bmdma_status,
762
763 .qc_prep = ata_qc_prep,
764 .qc_issue = ata_qc_issue_prot,
765
766 .data_xfer = ata_data_xfer,
767
768 .irq_handler = ata_interrupt,
769 .irq_clear = ata_bmdma_irq_clear,
770 .irq_on = ata_irq_on,
771
772 .port_start = ata_sff_port_start,
773 };
774
775 /**
776 * htp37x_clock_slot - Turn timing to PC clock entry
777 * @freq: Reported frequency timing
778 * @base: Base timing
779 *
780 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
781 * and 3 for 66Mhz)
782 */
783
784 static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
785 {
786 unsigned int f = (base * freq) / 192; /* Mhz */
787 if (f < 40)
788 return 0; /* 33Mhz slot */
789 if (f < 45)
790 return 1; /* 40Mhz slot */
791 if (f < 55)
792 return 2; /* 50Mhz slot */
793 return 3; /* 60Mhz slot */
794 }
795
796 /**
797 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
798 * @dev: PCI device
799 *
800 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
801 * succeeds
802 */
803
804 static int hpt37x_calibrate_dpll(struct pci_dev *dev)
805 {
806 u8 reg5b;
807 u32 reg5c;
808 int tries;
809
810 for(tries = 0; tries < 0x5000; tries++) {
811 udelay(50);
812 pci_read_config_byte(dev, 0x5b, &reg5b);
813 if (reg5b & 0x80) {
814 /* See if it stays set */
815 for(tries = 0; tries < 0x1000; tries ++) {
816 pci_read_config_byte(dev, 0x5b, &reg5b);
817 /* Failed ? */
818 if ((reg5b & 0x80) == 0)
819 return 0;
820 }
821 /* Turn off tuning, we have the DPLL set */
822 pci_read_config_dword(dev, 0x5c, &reg5c);
823 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
824 return 1;
825 }
826 }
827 /* Never went stable */
828 return 0;
829 }
830
831 static u32 hpt374_read_freq(struct pci_dev *pdev)
832 {
833 u32 freq;
834 unsigned long io_base = pci_resource_start(pdev, 4);
835 if (PCI_FUNC(pdev->devfn) & 1) {
836 struct pci_dev *pdev_0;
837
838 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
839 /* Someone hot plugged the controller on us ? */
840 if (pdev_0 == NULL)
841 return 0;
842 io_base = pci_resource_start(pdev_0, 4);
843 freq = inl(io_base + 0x90);
844 pci_dev_put(pdev_0);
845 } else
846 freq = inl(io_base + 0x90);
847 return freq;
848 }
849
850 /**
851 * hpt37x_init_one - Initialise an HPT37X/302
852 * @dev: PCI device
853 * @id: Entry in match table
854 *
855 * Initialise an HPT37x device. There are some interesting complications
856 * here. Firstly the chip may report 366 and be one of several variants.
857 * Secondly all the timings depend on the clock for the chip which we must
858 * detect and look up
859 *
860 * This is the known chip mappings. It may be missing a couple of later
861 * releases.
862 *
863 * Chip version PCI Rev Notes
864 * HPT366 4 (HPT366) 0 Other driver
865 * HPT366 4 (HPT366) 1 Other driver
866 * HPT368 4 (HPT366) 2 Other driver
867 * HPT370 4 (HPT366) 3 UDMA100
868 * HPT370A 4 (HPT366) 4 UDMA100
869 * HPT372 4 (HPT366) 5 UDMA133 (1)
870 * HPT372N 4 (HPT366) 6 Other driver
871 * HPT372A 5 (HPT372) 1 UDMA133 (1)
872 * HPT372N 5 (HPT372) 2 Other driver
873 * HPT302 6 (HPT302) 1 UDMA133
874 * HPT302N 6 (HPT302) 2 Other driver
875 * HPT371 7 (HPT371) * UDMA133
876 * HPT374 8 (HPT374) * UDMA133 4 channel
877 * HPT372N 9 (HPT372N) * Other driver
878 *
879 * (1) UDMA133 support depends on the bus clock
880 */
881
882 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
883 {
884 /* HPT370 - UDMA100 */
885 static const struct ata_port_info info_hpt370 = {
886 .sht = &hpt37x_sht,
887 .flags = ATA_FLAG_SLAVE_POSS,
888 .pio_mask = 0x1f,
889 .mwdma_mask = 0x07,
890 .udma_mask = ATA_UDMA5,
891 .port_ops = &hpt370_port_ops
892 };
893 /* HPT370A - UDMA100 */
894 static const struct ata_port_info info_hpt370a = {
895 .sht = &hpt37x_sht,
896 .flags = ATA_FLAG_SLAVE_POSS,
897 .pio_mask = 0x1f,
898 .mwdma_mask = 0x07,
899 .udma_mask = ATA_UDMA5,
900 .port_ops = &hpt370a_port_ops
901 };
902 /* HPT370 - UDMA100 */
903 static const struct ata_port_info info_hpt370_33 = {
904 .sht = &hpt37x_sht,
905 .flags = ATA_FLAG_SLAVE_POSS,
906 .pio_mask = 0x1f,
907 .mwdma_mask = 0x07,
908 .udma_mask = ATA_UDMA5,
909 .port_ops = &hpt370_port_ops
910 };
911 /* HPT370A - UDMA100 */
912 static const struct ata_port_info info_hpt370a_33 = {
913 .sht = &hpt37x_sht,
914 .flags = ATA_FLAG_SLAVE_POSS,
915 .pio_mask = 0x1f,
916 .mwdma_mask = 0x07,
917 .udma_mask = ATA_UDMA5,
918 .port_ops = &hpt370a_port_ops
919 };
920 /* HPT371, 372 and friends - UDMA133 */
921 static const struct ata_port_info info_hpt372 = {
922 .sht = &hpt37x_sht,
923 .flags = ATA_FLAG_SLAVE_POSS,
924 .pio_mask = 0x1f,
925 .mwdma_mask = 0x07,
926 .udma_mask = ATA_UDMA6,
927 .port_ops = &hpt372_port_ops
928 };
929 /* HPT374 - UDMA100 */
930 static const struct ata_port_info info_hpt374 = {
931 .sht = &hpt37x_sht,
932 .flags = ATA_FLAG_SLAVE_POSS,
933 .pio_mask = 0x1f,
934 .mwdma_mask = 0x07,
935 .udma_mask = ATA_UDMA5,
936 .port_ops = &hpt374_port_ops
937 };
938
939 static const int MHz[4] = { 33, 40, 50, 66 };
940 const struct ata_port_info *port;
941 void *private_data = NULL;
942 struct ata_port_info port_info;
943 const struct ata_port_info *ppi[] = { &port_info, NULL };
944
945 u8 irqmask;
946 u32 class_rev;
947 u8 mcr1;
948 u32 freq;
949 int prefer_dpll = 1;
950
951 unsigned long iobase = pci_resource_start(dev, 4);
952
953 const struct hpt_chip *chip_table;
954 int clock_slot;
955 int rc;
956
957 rc = pcim_enable_device(dev);
958 if (rc)
959 return rc;
960
961 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
962 class_rev &= 0xFF;
963
964 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
965 /* May be a later chip in disguise. Check */
966 /* Older chips are in the HPT366 driver. Ignore them */
967 if (class_rev < 3)
968 return -ENODEV;
969 /* N series chips have their own driver. Ignore */
970 if (class_rev == 6)
971 return -ENODEV;
972
973 switch(class_rev) {
974 case 3:
975 port = &info_hpt370;
976 chip_table = &hpt370;
977 prefer_dpll = 0;
978 break;
979 case 4:
980 port = &info_hpt370a;
981 chip_table = &hpt370a;
982 prefer_dpll = 0;
983 break;
984 case 5:
985 port = &info_hpt372;
986 chip_table = &hpt372;
987 break;
988 default:
989 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
990 return -ENODEV;
991 }
992 } else {
993 switch(dev->device) {
994 case PCI_DEVICE_ID_TTI_HPT372:
995 /* 372N if rev >= 2*/
996 if (class_rev >= 2)
997 return -ENODEV;
998 port = &info_hpt372;
999 chip_table = &hpt372a;
1000 break;
1001 case PCI_DEVICE_ID_TTI_HPT302:
1002 /* 302N if rev > 1 */
1003 if (class_rev > 1)
1004 return -ENODEV;
1005 port = &info_hpt372;
1006 /* Check this */
1007 chip_table = &hpt302;
1008 break;
1009 case PCI_DEVICE_ID_TTI_HPT371:
1010 if (class_rev > 1)
1011 return -ENODEV;
1012 port = &info_hpt372;
1013 chip_table = &hpt371;
1014 /* Single channel device, master is not present
1015 but the BIOS (or us for non x86) must mark it
1016 absent */
1017 pci_read_config_byte(dev, 0x50, &mcr1);
1018 mcr1 &= ~0x04;
1019 pci_write_config_byte(dev, 0x50, mcr1);
1020 break;
1021 case PCI_DEVICE_ID_TTI_HPT374:
1022 chip_table = &hpt374;
1023 port = &info_hpt374;
1024 break;
1025 default:
1026 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
1027 return -ENODEV;
1028 }
1029 }
1030 /* Ok so this is a chip we support */
1031
1032 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1033 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1034 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1035 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1036
1037 pci_read_config_byte(dev, 0x5A, &irqmask);
1038 irqmask &= ~0x10;
1039 pci_write_config_byte(dev, 0x5a, irqmask);
1040
1041 /*
1042 * default to pci clock. make sure MA15/16 are set to output
1043 * to prevent drives having problems with 40-pin cables. Needed
1044 * for some drives such as IBM-DTLA which will not enter ready
1045 * state on reset when PDIAG is a input.
1046 */
1047
1048 pci_write_config_byte(dev, 0x5b, 0x23);
1049
1050 /*
1051 * HighPoint does this for HPT372A.
1052 * NOTE: This register is only writeable via I/O space.
1053 */
1054 if (chip_table == &hpt372a)
1055 outb(0x0e, iobase + 0x9c);
1056
1057 /* Some devices do not let this value be accessed via PCI space
1058 according to the old driver. In addition we must use the value
1059 from FN 0 on the HPT374 */
1060
1061 if (chip_table == &hpt374) {
1062 freq = hpt374_read_freq(dev);
1063 if (freq == 0)
1064 return -ENODEV;
1065 } else
1066 freq = inl(iobase + 0x90);
1067
1068 if ((freq >> 12) != 0xABCDE) {
1069 int i;
1070 u8 sr;
1071 u32 total = 0;
1072
1073 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
1074
1075 /* This is the process the HPT371 BIOS is reported to use */
1076 for(i = 0; i < 128; i++) {
1077 pci_read_config_byte(dev, 0x78, &sr);
1078 total += sr & 0x1FF;
1079 udelay(15);
1080 }
1081 freq = total / 128;
1082 }
1083 freq &= 0x1FF;
1084
1085 /*
1086 * Turn the frequency check into a band and then find a timing
1087 * table to match it.
1088 */
1089
1090 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
1091 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
1092 /*
1093 * We need to try PLL mode instead
1094 *
1095 * For non UDMA133 capable devices we should
1096 * use a 50MHz DPLL by choice
1097 */
1098 unsigned int f_low, f_high;
1099 int dpll, adjust;
1100
1101 /* Compute DPLL */
1102 dpll = (port->udma_mask & 0xC0) ? 3 : 2;
1103
1104 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
1105 f_high = f_low + 2;
1106 if (clock_slot > 1)
1107 f_high += 2;
1108
1109 /* Select the DPLL clock. */
1110 pci_write_config_byte(dev, 0x5b, 0x21);
1111 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
1112
1113 for(adjust = 0; adjust < 8; adjust++) {
1114 if (hpt37x_calibrate_dpll(dev))
1115 break;
1116 /* See if it'll settle at a fractionally different clock */
1117 if (adjust & 1)
1118 f_low -= adjust >> 1;
1119 else
1120 f_high += adjust >> 1;
1121 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
1122 }
1123 if (adjust == 8) {
1124 printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n");
1125 return -ENODEV;
1126 }
1127 if (dpll == 3)
1128 private_data = (void *)hpt37x_timings_66;
1129 else
1130 private_data = (void *)hpt37x_timings_50;
1131
1132 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
1133 MHz[clock_slot], MHz[dpll]);
1134 } else {
1135 private_data = (void *)chip_table->clocks[clock_slot];
1136 /*
1137 * Perform a final fixup. Note that we will have used the
1138 * DPLL on the HPT372 which means we don't have to worry
1139 * about lack of UDMA133 support on lower clocks
1140 */
1141
1142 if (clock_slot < 2 && port == &info_hpt370)
1143 port = &info_hpt370_33;
1144 if (clock_slot < 2 && port == &info_hpt370a)
1145 port = &info_hpt370a_33;
1146 printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n",
1147 chip_table->name, MHz[clock_slot]);
1148 }
1149
1150 /* Now kick off ATA set up */
1151 port_info = *port;
1152 port_info.private_data = private_data;
1153
1154 return ata_pci_init_one(dev, ppi);
1155 }
1156
1157 static const struct pci_device_id hpt37x[] = {
1158 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1159 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1160 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1161 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1162 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1163
1164 { },
1165 };
1166
1167 static struct pci_driver hpt37x_pci_driver = {
1168 .name = DRV_NAME,
1169 .id_table = hpt37x,
1170 .probe = hpt37x_init_one,
1171 .remove = ata_pci_remove_one
1172 };
1173
1174 static int __init hpt37x_init(void)
1175 {
1176 return pci_register_driver(&hpt37x_pci_driver);
1177 }
1178
1179 static void __exit hpt37x_exit(void)
1180 {
1181 pci_unregister_driver(&hpt37x_pci_driver);
1182 }
1183
1184 MODULE_AUTHOR("Alan Cox");
1185 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1186 MODULE_LICENSE("GPL");
1187 MODULE_DEVICE_TABLE(pci, hpt37x);
1188 MODULE_VERSION(DRV_VERSION);
1189
1190 module_init(hpt37x_init);
1191 module_exit(hpt37x_exit);
Linux kernel - Deliverables
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