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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
[deliverable/linux.git] / drivers / ata / pata_hpt37x.c
1 /*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
12 *
13 * TODO
14 * Look into engine reset on timeout errors. Should not be required.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/blkdev.h>
22 #include <linux/delay.h>
23 #include <scsi/scsi_host.h>
24 #include <linux/libata.h>
25
26 #define DRV_NAME "pata_hpt37x"
27 #define DRV_VERSION "0.6.9"
28
29 struct hpt_clock {
30 u8 xfer_speed;
31 u32 timing;
32 };
33
34 struct hpt_chip {
35 const char *name;
36 unsigned int base;
37 struct hpt_clock const *clocks[4];
38 };
39
40 /* key for bus clock timings
41 * bit
42 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
43 * DMA. cycles = value + 1
44 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
45 * DMA. cycles = value + 1
46 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
47 * register access.
48 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
49 * register access.
50 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
51 * during task file register access.
52 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
53 * xfer.
54 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
55 * register access.
56 * 28 UDMA enable
57 * 29 DMA enable
58 * 30 PIO_MST enable. if set, the chip is in bus master mode during
59 * PIO.
60 * 31 FIFO enable.
61 */
62
63 static struct hpt_clock hpt37x_timings_33[] = {
64 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
65 { XFER_UDMA_5, 0x12446231 },
66 { XFER_UDMA_4, 0x12446231 },
67 { XFER_UDMA_3, 0x126c6231 },
68 { XFER_UDMA_2, 0x12486231 },
69 { XFER_UDMA_1, 0x124c6233 },
70 { XFER_UDMA_0, 0x12506297 },
71
72 { XFER_MW_DMA_2, 0x22406c31 },
73 { XFER_MW_DMA_1, 0x22406c33 },
74 { XFER_MW_DMA_0, 0x22406c97 },
75
76 { XFER_PIO_4, 0x06414e31 },
77 { XFER_PIO_3, 0x06414e42 },
78 { XFER_PIO_2, 0x06414e53 },
79 { XFER_PIO_1, 0x06814e93 },
80 { XFER_PIO_0, 0x06814ea7 }
81 };
82
83 static struct hpt_clock hpt37x_timings_50[] = {
84 { XFER_UDMA_6, 0x12848242 },
85 { XFER_UDMA_5, 0x12848242 },
86 { XFER_UDMA_4, 0x12ac8242 },
87 { XFER_UDMA_3, 0x128c8242 },
88 { XFER_UDMA_2, 0x120c8242 },
89 { XFER_UDMA_1, 0x12148254 },
90 { XFER_UDMA_0, 0x121882ea },
91
92 { XFER_MW_DMA_2, 0x22808242 },
93 { XFER_MW_DMA_1, 0x22808254 },
94 { XFER_MW_DMA_0, 0x228082ea },
95
96 { XFER_PIO_4, 0x0a81f442 },
97 { XFER_PIO_3, 0x0a81f443 },
98 { XFER_PIO_2, 0x0a81f454 },
99 { XFER_PIO_1, 0x0ac1f465 },
100 { XFER_PIO_0, 0x0ac1f48a }
101 };
102
103 static struct hpt_clock hpt37x_timings_66[] = {
104 { XFER_UDMA_6, 0x1c869c62 },
105 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
106 { XFER_UDMA_4, 0x1c8a9c62 },
107 { XFER_UDMA_3, 0x1c8e9c62 },
108 { XFER_UDMA_2, 0x1c929c62 },
109 { XFER_UDMA_1, 0x1c9a9c62 },
110 { XFER_UDMA_0, 0x1c829c62 },
111
112 { XFER_MW_DMA_2, 0x2c829c62 },
113 { XFER_MW_DMA_1, 0x2c829c66 },
114 { XFER_MW_DMA_0, 0x2c829d2e },
115
116 { XFER_PIO_4, 0x0c829c62 },
117 { XFER_PIO_3, 0x0c829c84 },
118 { XFER_PIO_2, 0x0c829ca6 },
119 { XFER_PIO_1, 0x0d029d26 },
120 { XFER_PIO_0, 0x0d029d5e }
121 };
122
123
124 static const struct hpt_chip hpt370 = {
125 "HPT370",
126 48,
127 {
128 hpt37x_timings_33,
129 NULL,
130 NULL,
131 NULL
132 }
133 };
134
135 static const struct hpt_chip hpt370a = {
136 "HPT370A",
137 48,
138 {
139 hpt37x_timings_33,
140 NULL,
141 hpt37x_timings_50,
142 NULL
143 }
144 };
145
146 static const struct hpt_chip hpt372 = {
147 "HPT372",
148 55,
149 {
150 hpt37x_timings_33,
151 NULL,
152 hpt37x_timings_50,
153 hpt37x_timings_66
154 }
155 };
156
157 static const struct hpt_chip hpt302 = {
158 "HPT302",
159 66,
160 {
161 hpt37x_timings_33,
162 NULL,
163 hpt37x_timings_50,
164 hpt37x_timings_66
165 }
166 };
167
168 static const struct hpt_chip hpt371 = {
169 "HPT371",
170 66,
171 {
172 hpt37x_timings_33,
173 NULL,
174 hpt37x_timings_50,
175 hpt37x_timings_66
176 }
177 };
178
179 static const struct hpt_chip hpt372a = {
180 "HPT372A",
181 66,
182 {
183 hpt37x_timings_33,
184 NULL,
185 hpt37x_timings_50,
186 hpt37x_timings_66
187 }
188 };
189
190 static const struct hpt_chip hpt374 = {
191 "HPT374",
192 48,
193 {
194 hpt37x_timings_33,
195 NULL,
196 NULL,
197 NULL
198 }
199 };
200
201 /**
202 * hpt37x_find_mode - reset the hpt37x bus
203 * @ap: ATA port
204 * @speed: transfer mode
205 *
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
208 */
209
210 static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
211 {
212 struct hpt_clock *clocks = ap->host->private_data;
213
214 while(clocks->xfer_speed) {
215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
217 clocks++;
218 }
219 BUG();
220 return 0xffffffffU; /* silence compiler warning */
221 }
222
223 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
224 {
225 unsigned char model_num[ATA_ID_PROD_LEN + 1];
226 int i = 0;
227
228 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
229
230 while (list[i] != NULL) {
231 if (!strcmp(list[i], model_num)) {
232 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
233 modestr, list[i]);
234 return 1;
235 }
236 i++;
237 }
238 return 0;
239 }
240
241 static const char *bad_ata33[] = {
242 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
243 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
244 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
245 "Maxtor 90510D4",
246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
248 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
249 NULL
250 };
251
252 static const char *bad_ata100_5[] = {
253 "IBM-DTLA-307075",
254 "IBM-DTLA-307060",
255 "IBM-DTLA-307045",
256 "IBM-DTLA-307030",
257 "IBM-DTLA-307020",
258 "IBM-DTLA-307015",
259 "IBM-DTLA-305040",
260 "IBM-DTLA-305030",
261 "IBM-DTLA-305020",
262 "IC35L010AVER07-0",
263 "IC35L020AVER07-0",
264 "IC35L030AVER07-0",
265 "IC35L040AVER07-0",
266 "IC35L060AVER07-0",
267 "WDC AC310200R",
268 NULL
269 };
270
271 /**
272 * hpt370_filter - mode selection filter
273 * @adev: ATA device
274 *
275 * Block UDMA on devices that cause trouble with this controller.
276 */
277
278 static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
279 {
280 if (adev->class == ATA_DEV_ATA) {
281 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
282 mask &= ~ATA_MASK_UDMA;
283 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
284 mask &= ~(0x1F << ATA_SHIFT_UDMA);
285 }
286 return ata_pci_default_filter(adev, mask);
287 }
288
289 /**
290 * hpt370a_filter - mode selection filter
291 * @adev: ATA device
292 *
293 * Block UDMA on devices that cause trouble with this controller.
294 */
295
296 static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
297 {
298 if (adev->class != ATA_DEV_ATA) {
299 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
300 mask &= ~ (0x1F << ATA_SHIFT_UDMA);
301 }
302 return ata_pci_default_filter(adev, mask);
303 }
304
305 /**
306 * hpt37x_pre_reset - reset the hpt37x bus
307 * @link: ATA link to reset
308 * @deadline: deadline jiffies for the operation
309 *
310 * Perform the initial reset handling for the 370/372 and 374 func 0
311 */
312
313 static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
314 {
315 u8 scr2, ata66;
316 struct ata_port *ap = link->ap;
317 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
318 static const struct pci_bits hpt37x_enable_bits[] = {
319 { 0x50, 1, 0x04, 0x04 },
320 { 0x54, 1, 0x04, 0x04 }
321 };
322 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
323 return -ENOENT;
324
325 pci_read_config_byte(pdev, 0x5B, &scr2);
326 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
327 /* Cable register now active */
328 pci_read_config_byte(pdev, 0x5A, &ata66);
329 /* Restore state */
330 pci_write_config_byte(pdev, 0x5B, scr2);
331
332 if (ata66 & (1 << ap->port_no))
333 ap->cbl = ATA_CBL_PATA40;
334 else
335 ap->cbl = ATA_CBL_PATA80;
336
337 /* Reset the state machine */
338 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
339 udelay(100);
340
341 return ata_std_prereset(link, deadline);
342 }
343
344 /**
345 * hpt37x_error_handler - reset the hpt374
346 * @ap: ATA port to reset
347 *
348 * Perform probe for HPT37x, except for HPT374 channel 2
349 */
350
351 static void hpt37x_error_handler(struct ata_port *ap)
352 {
353 ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
354 }
355
356 static int hpt374_pre_reset(struct ata_link *link, unsigned long deadline)
357 {
358 static const struct pci_bits hpt37x_enable_bits[] = {
359 { 0x50, 1, 0x04, 0x04 },
360 { 0x54, 1, 0x04, 0x04 }
361 };
362 u16 mcr3, mcr6;
363 u8 ata66;
364 struct ata_port *ap = link->ap;
365 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
366
367 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
368 return -ENOENT;
369
370 /* Do the extra channel work */
371 pci_read_config_word(pdev, 0x52, &mcr3);
372 pci_read_config_word(pdev, 0x56, &mcr6);
373 /* Set bit 15 of 0x52 to enable TCBLID as input
374 Set bit 15 of 0x56 to enable FCBLID as input
375 */
376 pci_write_config_word(pdev, 0x52, mcr3 | 0x8000);
377 pci_write_config_word(pdev, 0x56, mcr6 | 0x8000);
378 pci_read_config_byte(pdev, 0x5A, &ata66);
379 /* Reset TCBLID/FCBLID to output */
380 pci_write_config_word(pdev, 0x52, mcr3);
381 pci_write_config_word(pdev, 0x56, mcr6);
382
383 if (ata66 & (1 << ap->port_no))
384 ap->cbl = ATA_CBL_PATA40;
385 else
386 ap->cbl = ATA_CBL_PATA80;
387
388 /* Reset the state machine */
389 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
390 udelay(100);
391
392 return ata_std_prereset(link, deadline);
393 }
394
395 /**
396 * hpt374_error_handler - reset the hpt374
397 * @classes:
398 *
399 * The 374 cable detect is a little different due to the extra
400 * channels. The function 0 channels work like usual but function 1
401 * is special
402 */
403
404 static void hpt374_error_handler(struct ata_port *ap)
405 {
406 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
407
408 if (!(PCI_FUNC(pdev->devfn) & 1))
409 hpt37x_error_handler(ap);
410 else
411 ata_bmdma_drive_eh(ap, hpt374_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
412 }
413
414 /**
415 * hpt370_set_piomode - PIO setup
416 * @ap: ATA interface
417 * @adev: device on the interface
418 *
419 * Perform PIO mode setup.
420 */
421
422 static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
423 {
424 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
425 u32 addr1, addr2;
426 u32 reg;
427 u32 mode;
428 u8 fast;
429
430 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
431 addr2 = 0x51 + 4 * ap->port_no;
432
433 /* Fast interrupt prediction disable, hold off interrupt disable */
434 pci_read_config_byte(pdev, addr2, &fast);
435 fast &= ~0x02;
436 fast |= 0x01;
437 pci_write_config_byte(pdev, addr2, fast);
438
439 pci_read_config_dword(pdev, addr1, &reg);
440 mode = hpt37x_find_mode(ap, adev->pio_mode);
441 mode &= ~0x8000000; /* No FIFO in PIO */
442 mode &= ~0x30070000; /* Leave config bits alone */
443 reg &= 0x30070000; /* Strip timing bits */
444 pci_write_config_dword(pdev, addr1, reg | mode);
445 }
446
447 /**
448 * hpt370_set_dmamode - DMA timing setup
449 * @ap: ATA interface
450 * @adev: Device being configured
451 *
452 * Set up the channel for MWDMA or UDMA modes. Much the same as with
453 * PIO, load the mode number and then set MWDMA or UDMA flag.
454 */
455
456 static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
457 {
458 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
459 u32 addr1, addr2;
460 u32 reg;
461 u32 mode;
462 u8 fast;
463
464 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
465 addr2 = 0x51 + 4 * ap->port_no;
466
467 /* Fast interrupt prediction disable, hold off interrupt disable */
468 pci_read_config_byte(pdev, addr2, &fast);
469 fast &= ~0x02;
470 fast |= 0x01;
471 pci_write_config_byte(pdev, addr2, fast);
472
473 pci_read_config_dword(pdev, addr1, &reg);
474 mode = hpt37x_find_mode(ap, adev->dma_mode);
475 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
476 mode &= ~0xC0000000; /* Leave config bits alone */
477 reg &= 0xC0000000; /* Strip timing bits */
478 pci_write_config_dword(pdev, addr1, reg | mode);
479 }
480
481 /**
482 * hpt370_bmdma_start - DMA engine begin
483 * @qc: ATA command
484 *
485 * The 370 and 370A want us to reset the DMA engine each time we
486 * use it. The 372 and later are fine.
487 */
488
489 static void hpt370_bmdma_start(struct ata_queued_cmd *qc)
490 {
491 struct ata_port *ap = qc->ap;
492 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
493 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
494 udelay(10);
495 ata_bmdma_start(qc);
496 }
497
498 /**
499 * hpt370_bmdma_end - DMA engine stop
500 * @qc: ATA command
501 *
502 * Work around the HPT370 DMA engine.
503 */
504
505 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
506 {
507 struct ata_port *ap = qc->ap;
508 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
509 u8 dma_stat = ioread8(ap->ioaddr.bmdma_addr + 2);
510 u8 dma_cmd;
511 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
512
513 if (dma_stat & 0x01) {
514 udelay(20);
515 dma_stat = ioread8(bmdma + 2);
516 }
517 if (dma_stat & 0x01) {
518 /* Clear the engine */
519 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
520 udelay(10);
521 /* Stop DMA */
522 dma_cmd = ioread8(bmdma );
523 iowrite8(dma_cmd & 0xFE, bmdma);
524 /* Clear Error */
525 dma_stat = ioread8(bmdma + 2);
526 iowrite8(dma_stat | 0x06 , bmdma + 2);
527 /* Clear the engine */
528 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
529 udelay(10);
530 }
531 ata_bmdma_stop(qc);
532 }
533
534 /**
535 * hpt372_set_piomode - PIO setup
536 * @ap: ATA interface
537 * @adev: device on the interface
538 *
539 * Perform PIO mode setup.
540 */
541
542 static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
543 {
544 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
545 u32 addr1, addr2;
546 u32 reg;
547 u32 mode;
548 u8 fast;
549
550 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
551 addr2 = 0x51 + 4 * ap->port_no;
552
553 /* Fast interrupt prediction disable, hold off interrupt disable */
554 pci_read_config_byte(pdev, addr2, &fast);
555 fast &= ~0x07;
556 pci_write_config_byte(pdev, addr2, fast);
557
558 pci_read_config_dword(pdev, addr1, &reg);
559 mode = hpt37x_find_mode(ap, adev->pio_mode);
560
561 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
562 mode &= ~0x80000000; /* No FIFO in PIO */
563 mode &= ~0x30070000; /* Leave config bits alone */
564 reg &= 0x30070000; /* Strip timing bits */
565 pci_write_config_dword(pdev, addr1, reg | mode);
566 }
567
568 /**
569 * hpt372_set_dmamode - DMA timing setup
570 * @ap: ATA interface
571 * @adev: Device being configured
572 *
573 * Set up the channel for MWDMA or UDMA modes. Much the same as with
574 * PIO, load the mode number and then set MWDMA or UDMA flag.
575 */
576
577 static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
578 {
579 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
580 u32 addr1, addr2;
581 u32 reg;
582 u32 mode;
583 u8 fast;
584
585 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
586 addr2 = 0x51 + 4 * ap->port_no;
587
588 /* Fast interrupt prediction disable, hold off interrupt disable */
589 pci_read_config_byte(pdev, addr2, &fast);
590 fast &= ~0x07;
591 pci_write_config_byte(pdev, addr2, fast);
592
593 pci_read_config_dword(pdev, addr1, &reg);
594 mode = hpt37x_find_mode(ap, adev->dma_mode);
595 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
596 mode &= ~0xC0000000; /* Leave config bits alone */
597 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */
598 reg &= 0xC0000000; /* Strip timing bits */
599 pci_write_config_dword(pdev, addr1, reg | mode);
600 }
601
602 /**
603 * hpt37x_bmdma_end - DMA engine stop
604 * @qc: ATA command
605 *
606 * Clean up after the HPT372 and later DMA engine
607 */
608
609 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
610 {
611 struct ata_port *ap = qc->ap;
612 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
613 int mscreg = 0x50 + 4 * ap->port_no;
614 u8 bwsr_stat, msc_stat;
615
616 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
617 pci_read_config_byte(pdev, mscreg, &msc_stat);
618 if (bwsr_stat & (1 << ap->port_no))
619 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
620 ata_bmdma_stop(qc);
621 }
622
623
624 static struct scsi_host_template hpt37x_sht = {
625 .module = THIS_MODULE,
626 .name = DRV_NAME,
627 .ioctl = ata_scsi_ioctl,
628 .queuecommand = ata_scsi_queuecmd,
629 .can_queue = ATA_DEF_QUEUE,
630 .this_id = ATA_SHT_THIS_ID,
631 .sg_tablesize = LIBATA_MAX_PRD,
632 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
633 .emulated = ATA_SHT_EMULATED,
634 .use_clustering = ATA_SHT_USE_CLUSTERING,
635 .proc_name = DRV_NAME,
636 .dma_boundary = ATA_DMA_BOUNDARY,
637 .slave_configure = ata_scsi_slave_config,
638 .slave_destroy = ata_scsi_slave_destroy,
639 .bios_param = ata_std_bios_param,
640 };
641
642 /*
643 * Configuration for HPT370
644 */
645
646 static struct ata_port_operations hpt370_port_ops = {
647 .set_piomode = hpt370_set_piomode,
648 .set_dmamode = hpt370_set_dmamode,
649 .mode_filter = hpt370_filter,
650
651 .tf_load = ata_tf_load,
652 .tf_read = ata_tf_read,
653 .check_status = ata_check_status,
654 .exec_command = ata_exec_command,
655 .dev_select = ata_std_dev_select,
656
657 .freeze = ata_bmdma_freeze,
658 .thaw = ata_bmdma_thaw,
659 .error_handler = hpt37x_error_handler,
660 .post_internal_cmd = ata_bmdma_post_internal_cmd,
661
662 .bmdma_setup = ata_bmdma_setup,
663 .bmdma_start = hpt370_bmdma_start,
664 .bmdma_stop = hpt370_bmdma_stop,
665 .bmdma_status = ata_bmdma_status,
666
667 .qc_prep = ata_qc_prep,
668 .qc_issue = ata_qc_issue_prot,
669
670 .data_xfer = ata_data_xfer,
671
672 .irq_handler = ata_interrupt,
673 .irq_clear = ata_bmdma_irq_clear,
674 .irq_on = ata_irq_on,
675
676 .port_start = ata_sff_port_start,
677 };
678
679 /*
680 * Configuration for HPT370A. Close to 370 but less filters
681 */
682
683 static struct ata_port_operations hpt370a_port_ops = {
684 .set_piomode = hpt370_set_piomode,
685 .set_dmamode = hpt370_set_dmamode,
686 .mode_filter = hpt370a_filter,
687
688 .tf_load = ata_tf_load,
689 .tf_read = ata_tf_read,
690 .check_status = ata_check_status,
691 .exec_command = ata_exec_command,
692 .dev_select = ata_std_dev_select,
693
694 .freeze = ata_bmdma_freeze,
695 .thaw = ata_bmdma_thaw,
696 .error_handler = hpt37x_error_handler,
697 .post_internal_cmd = ata_bmdma_post_internal_cmd,
698
699 .bmdma_setup = ata_bmdma_setup,
700 .bmdma_start = hpt370_bmdma_start,
701 .bmdma_stop = hpt370_bmdma_stop,
702 .bmdma_status = ata_bmdma_status,
703
704 .qc_prep = ata_qc_prep,
705 .qc_issue = ata_qc_issue_prot,
706
707 .data_xfer = ata_data_xfer,
708
709 .irq_handler = ata_interrupt,
710 .irq_clear = ata_bmdma_irq_clear,
711 .irq_on = ata_irq_on,
712
713 .port_start = ata_sff_port_start,
714 };
715
716 /*
717 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
718 * and DMA mode setting functionality.
719 */
720
721 static struct ata_port_operations hpt372_port_ops = {
722 .set_piomode = hpt372_set_piomode,
723 .set_dmamode = hpt372_set_dmamode,
724 .mode_filter = ata_pci_default_filter,
725
726 .tf_load = ata_tf_load,
727 .tf_read = ata_tf_read,
728 .check_status = ata_check_status,
729 .exec_command = ata_exec_command,
730 .dev_select = ata_std_dev_select,
731
732 .freeze = ata_bmdma_freeze,
733 .thaw = ata_bmdma_thaw,
734 .error_handler = hpt37x_error_handler,
735 .post_internal_cmd = ata_bmdma_post_internal_cmd,
736
737 .bmdma_setup = ata_bmdma_setup,
738 .bmdma_start = ata_bmdma_start,
739 .bmdma_stop = hpt37x_bmdma_stop,
740 .bmdma_status = ata_bmdma_status,
741
742 .qc_prep = ata_qc_prep,
743 .qc_issue = ata_qc_issue_prot,
744
745 .data_xfer = ata_data_xfer,
746
747 .irq_handler = ata_interrupt,
748 .irq_clear = ata_bmdma_irq_clear,
749 .irq_on = ata_irq_on,
750
751 .port_start = ata_sff_port_start,
752 };
753
754 /*
755 * Configuration for HPT374. Mode setting works like 372 and friends
756 * but we have a different cable detection procedure.
757 */
758
759 static struct ata_port_operations hpt374_port_ops = {
760 .set_piomode = hpt372_set_piomode,
761 .set_dmamode = hpt372_set_dmamode,
762 .mode_filter = ata_pci_default_filter,
763
764 .tf_load = ata_tf_load,
765 .tf_read = ata_tf_read,
766 .check_status = ata_check_status,
767 .exec_command = ata_exec_command,
768 .dev_select = ata_std_dev_select,
769
770 .freeze = ata_bmdma_freeze,
771 .thaw = ata_bmdma_thaw,
772 .error_handler = hpt374_error_handler,
773 .post_internal_cmd = ata_bmdma_post_internal_cmd,
774
775 .bmdma_setup = ata_bmdma_setup,
776 .bmdma_start = ata_bmdma_start,
777 .bmdma_stop = hpt37x_bmdma_stop,
778 .bmdma_status = ata_bmdma_status,
779
780 .qc_prep = ata_qc_prep,
781 .qc_issue = ata_qc_issue_prot,
782
783 .data_xfer = ata_data_xfer,
784
785 .irq_handler = ata_interrupt,
786 .irq_clear = ata_bmdma_irq_clear,
787 .irq_on = ata_irq_on,
788
789 .port_start = ata_sff_port_start,
790 };
791
792 /**
793 * htp37x_clock_slot - Turn timing to PC clock entry
794 * @freq: Reported frequency timing
795 * @base: Base timing
796 *
797 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
798 * and 3 for 66Mhz)
799 */
800
801 static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
802 {
803 unsigned int f = (base * freq) / 192; /* Mhz */
804 if (f < 40)
805 return 0; /* 33Mhz slot */
806 if (f < 45)
807 return 1; /* 40Mhz slot */
808 if (f < 55)
809 return 2; /* 50Mhz slot */
810 return 3; /* 60Mhz slot */
811 }
812
813 /**
814 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
815 * @dev: PCI device
816 *
817 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
818 * succeeds
819 */
820
821 static int hpt37x_calibrate_dpll(struct pci_dev *dev)
822 {
823 u8 reg5b;
824 u32 reg5c;
825 int tries;
826
827 for(tries = 0; tries < 0x5000; tries++) {
828 udelay(50);
829 pci_read_config_byte(dev, 0x5b, &reg5b);
830 if (reg5b & 0x80) {
831 /* See if it stays set */
832 for(tries = 0; tries < 0x1000; tries ++) {
833 pci_read_config_byte(dev, 0x5b, &reg5b);
834 /* Failed ? */
835 if ((reg5b & 0x80) == 0)
836 return 0;
837 }
838 /* Turn off tuning, we have the DPLL set */
839 pci_read_config_dword(dev, 0x5c, &reg5c);
840 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
841 return 1;
842 }
843 }
844 /* Never went stable */
845 return 0;
846 }
847 /**
848 * hpt37x_init_one - Initialise an HPT37X/302
849 * @dev: PCI device
850 * @id: Entry in match table
851 *
852 * Initialise an HPT37x device. There are some interesting complications
853 * here. Firstly the chip may report 366 and be one of several variants.
854 * Secondly all the timings depend on the clock for the chip which we must
855 * detect and look up
856 *
857 * This is the known chip mappings. It may be missing a couple of later
858 * releases.
859 *
860 * Chip version PCI Rev Notes
861 * HPT366 4 (HPT366) 0 Other driver
862 * HPT366 4 (HPT366) 1 Other driver
863 * HPT368 4 (HPT366) 2 Other driver
864 * HPT370 4 (HPT366) 3 UDMA100
865 * HPT370A 4 (HPT366) 4 UDMA100
866 * HPT372 4 (HPT366) 5 UDMA133 (1)
867 * HPT372N 4 (HPT366) 6 Other driver
868 * HPT372A 5 (HPT372) 1 UDMA133 (1)
869 * HPT372N 5 (HPT372) 2 Other driver
870 * HPT302 6 (HPT302) 1 UDMA133
871 * HPT302N 6 (HPT302) 2 Other driver
872 * HPT371 7 (HPT371) * UDMA133
873 * HPT374 8 (HPT374) * UDMA133 4 channel
874 * HPT372N 9 (HPT372N) * Other driver
875 *
876 * (1) UDMA133 support depends on the bus clock
877 */
878
879 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
880 {
881 /* HPT370 - UDMA100 */
882 static const struct ata_port_info info_hpt370 = {
883 .sht = &hpt37x_sht,
884 .flags = ATA_FLAG_SLAVE_POSS,
885 .pio_mask = 0x1f,
886 .mwdma_mask = 0x07,
887 .udma_mask = ATA_UDMA5,
888 .port_ops = &hpt370_port_ops
889 };
890 /* HPT370A - UDMA100 */
891 static const struct ata_port_info info_hpt370a = {
892 .sht = &hpt37x_sht,
893 .flags = ATA_FLAG_SLAVE_POSS,
894 .pio_mask = 0x1f,
895 .mwdma_mask = 0x07,
896 .udma_mask = ATA_UDMA5,
897 .port_ops = &hpt370a_port_ops
898 };
899 /* HPT370 - UDMA100 */
900 static const struct ata_port_info info_hpt370_33 = {
901 .sht = &hpt37x_sht,
902 .flags = ATA_FLAG_SLAVE_POSS,
903 .pio_mask = 0x1f,
904 .mwdma_mask = 0x07,
905 .udma_mask = 0x0f,
906 .port_ops = &hpt370_port_ops
907 };
908 /* HPT370A - UDMA100 */
909 static const struct ata_port_info info_hpt370a_33 = {
910 .sht = &hpt37x_sht,
911 .flags = ATA_FLAG_SLAVE_POSS,
912 .pio_mask = 0x1f,
913 .mwdma_mask = 0x07,
914 .udma_mask = 0x0f,
915 .port_ops = &hpt370a_port_ops
916 };
917 /* HPT371, 372 and friends - UDMA133 */
918 static const struct ata_port_info info_hpt372 = {
919 .sht = &hpt37x_sht,
920 .flags = ATA_FLAG_SLAVE_POSS,
921 .pio_mask = 0x1f,
922 .mwdma_mask = 0x07,
923 .udma_mask = ATA_UDMA6,
924 .port_ops = &hpt372_port_ops
925 };
926 /* HPT374 - UDMA100 */
927 static const struct ata_port_info info_hpt374 = {
928 .sht = &hpt37x_sht,
929 .flags = ATA_FLAG_SLAVE_POSS,
930 .pio_mask = 0x1f,
931 .mwdma_mask = 0x07,
932 .udma_mask = ATA_UDMA5,
933 .port_ops = &hpt374_port_ops
934 };
935
936 static const int MHz[4] = { 33, 40, 50, 66 };
937 const struct ata_port_info *port;
938 void *private_data = NULL;
939 struct ata_port_info port_info;
940 const struct ata_port_info *ppi[] = { &port_info, NULL };
941
942 u8 irqmask;
943 u32 class_rev;
944 u8 mcr1;
945 u32 freq;
946 int prefer_dpll = 1;
947
948 unsigned long iobase = pci_resource_start(dev, 4);
949
950 const struct hpt_chip *chip_table;
951 int clock_slot;
952
953 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
954 class_rev &= 0xFF;
955
956 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
957 /* May be a later chip in disguise. Check */
958 /* Older chips are in the HPT366 driver. Ignore them */
959 if (class_rev < 3)
960 return -ENODEV;
961 /* N series chips have their own driver. Ignore */
962 if (class_rev == 6)
963 return -ENODEV;
964
965 switch(class_rev) {
966 case 3:
967 port = &info_hpt370;
968 chip_table = &hpt370;
969 prefer_dpll = 0;
970 break;
971 case 4:
972 port = &info_hpt370a;
973 chip_table = &hpt370a;
974 prefer_dpll = 0;
975 break;
976 case 5:
977 port = &info_hpt372;
978 chip_table = &hpt372;
979 break;
980 default:
981 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
982 return -ENODEV;
983 }
984 } else {
985 switch(dev->device) {
986 case PCI_DEVICE_ID_TTI_HPT372:
987 /* 372N if rev >= 2*/
988 if (class_rev >= 2)
989 return -ENODEV;
990 port = &info_hpt372;
991 chip_table = &hpt372a;
992 break;
993 case PCI_DEVICE_ID_TTI_HPT302:
994 /* 302N if rev > 1 */
995 if (class_rev > 1)
996 return -ENODEV;
997 port = &info_hpt372;
998 /* Check this */
999 chip_table = &hpt302;
1000 break;
1001 case PCI_DEVICE_ID_TTI_HPT371:
1002 if (class_rev > 1)
1003 return -ENODEV;
1004 port = &info_hpt372;
1005 chip_table = &hpt371;
1006 /* Single channel device, master is not present
1007 but the BIOS (or us for non x86) must mark it
1008 absent */
1009 pci_read_config_byte(dev, 0x50, &mcr1);
1010 mcr1 &= ~0x04;
1011 pci_write_config_byte(dev, 0x50, mcr1);
1012 break;
1013 case PCI_DEVICE_ID_TTI_HPT374:
1014 chip_table = &hpt374;
1015 port = &info_hpt374;
1016 break;
1017 default:
1018 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
1019 return -ENODEV;
1020 }
1021 }
1022 /* Ok so this is a chip we support */
1023
1024 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1025 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1026 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1027 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1028
1029 pci_read_config_byte(dev, 0x5A, &irqmask);
1030 irqmask &= ~0x10;
1031 pci_write_config_byte(dev, 0x5a, irqmask);
1032
1033 /*
1034 * default to pci clock. make sure MA15/16 are set to output
1035 * to prevent drives having problems with 40-pin cables. Needed
1036 * for some drives such as IBM-DTLA which will not enter ready
1037 * state on reset when PDIAG is a input.
1038 */
1039
1040 pci_write_config_byte(dev, 0x5b, 0x23);
1041
1042 /*
1043 * HighPoint does this for HPT372A.
1044 * NOTE: This register is only writeable via I/O space.
1045 */
1046 if (chip_table == &hpt372a)
1047 outb(0x0e, iobase + 0x9c);
1048
1049 /* Some devices do not let this value be accessed via PCI space
1050 according to the old driver */
1051
1052 freq = inl(iobase + 0x90);
1053 if ((freq >> 12) != 0xABCDE) {
1054 int i;
1055 u8 sr;
1056 u32 total = 0;
1057
1058 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
1059
1060 /* This is the process the HPT371 BIOS is reported to use */
1061 for(i = 0; i < 128; i++) {
1062 pci_read_config_byte(dev, 0x78, &sr);
1063 total += sr & 0x1FF;
1064 udelay(15);
1065 }
1066 freq = total / 128;
1067 }
1068 freq &= 0x1FF;
1069
1070 /*
1071 * Turn the frequency check into a band and then find a timing
1072 * table to match it.
1073 */
1074
1075 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
1076 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
1077 /*
1078 * We need to try PLL mode instead
1079 *
1080 * For non UDMA133 capable devices we should
1081 * use a 50MHz DPLL by choice
1082 */
1083 unsigned int f_low, f_high;
1084 int dpll, adjust;
1085
1086 /* Compute DPLL */
1087 dpll = (port->udma_mask & 0xC0) ? 3 : 2;
1088
1089 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
1090 f_high = f_low + 2;
1091 if (clock_slot > 1)
1092 f_high += 2;
1093
1094 /* Select the DPLL clock. */
1095 pci_write_config_byte(dev, 0x5b, 0x21);
1096 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
1097
1098 for(adjust = 0; adjust < 8; adjust++) {
1099 if (hpt37x_calibrate_dpll(dev))
1100 break;
1101 /* See if it'll settle at a fractionally different clock */
1102 if (adjust & 1)
1103 f_low -= adjust >> 1;
1104 else
1105 f_high += adjust >> 1;
1106 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
1107 }
1108 if (adjust == 8) {
1109 printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n");
1110 return -ENODEV;
1111 }
1112 if (dpll == 3)
1113 private_data = (void *)hpt37x_timings_66;
1114 else
1115 private_data = (void *)hpt37x_timings_50;
1116
1117 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
1118 MHz[clock_slot], MHz[dpll]);
1119 } else {
1120 private_data = (void *)chip_table->clocks[clock_slot];
1121 /*
1122 * Perform a final fixup. Note that we will have used the
1123 * DPLL on the HPT372 which means we don't have to worry
1124 * about lack of UDMA133 support on lower clocks
1125 */
1126
1127 if (clock_slot < 2 && port == &info_hpt370)
1128 port = &info_hpt370_33;
1129 if (clock_slot < 2 && port == &info_hpt370a)
1130 port = &info_hpt370a_33;
1131 printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n",
1132 chip_table->name, MHz[clock_slot]);
1133 }
1134
1135 /* Now kick off ATA set up */
1136 port_info = *port;
1137 port_info.private_data = private_data;
1138
1139 return ata_pci_init_one(dev, ppi);
1140 }
1141
1142 static const struct pci_device_id hpt37x[] = {
1143 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1144 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1145 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1146 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1147 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1148
1149 { },
1150 };
1151
1152 static struct pci_driver hpt37x_pci_driver = {
1153 .name = DRV_NAME,
1154 .id_table = hpt37x,
1155 .probe = hpt37x_init_one,
1156 .remove = ata_pci_remove_one
1157 };
1158
1159 static int __init hpt37x_init(void)
1160 {
1161 return pci_register_driver(&hpt37x_pci_driver);
1162 }
1163
1164 static void __exit hpt37x_exit(void)
1165 {
1166 pci_unregister_driver(&hpt37x_pci_driver);
1167 }
1168
1169 MODULE_AUTHOR("Alan Cox");
1170 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1171 MODULE_LICENSE("GPL");
1172 MODULE_DEVICE_TABLE(pci, hpt37x);
1173 MODULE_VERSION(DRV_VERSION);
1174
1175 module_init(hpt37x_init);
1176 module_exit(hpt37x_exit);
Linux kernel - Deliverables
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