drivers/ata/pata_optidma.c

   1 /*
   2  * pata_optidma.c       - Opti DMA PATA for new ATA layer
   3  *                        (C) 2006 Red Hat Inc
   4  *                        Alan Cox <alan@redhat.com>
   5  *
   6  *      The Opti DMA controllers are related to the older PIO PCI controllers
   7  *      and indeed the VLB ones. The main differences are that the timing
   8  *      numbers are now based off PCI clocks not VLB and differ, and that
   9  *      MWDMA is supported.
  10  *
  11  *      This driver should support Viper-N+, FireStar, FireStar Plus.
  12  *
  13  *      These devices support virtual DMA for read (aka the CS5520). Later
  14  *      chips support UDMA33, but only if the rest of the board logic does,
  15  *      so you have to get this right. We don't support the virtual DMA
  16  *      but we do handle UDMA.
  17  *
  18  *      Bits that are worth knowing
  19  *              Most control registers are shadowed into I/O registers
  20  *              0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
  21  *              Virtual DMA registers *move* between rev 0x02 and rev 0x10
  22  *              UDMA requires a 66MHz FSB
  23  *
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include <linux/init.h>
  30 #include <linux/blkdev.h>
  31 #include <linux/delay.h>
  32 #include <scsi/scsi_host.h>
  33 #include <linux/libata.h>
  34
  35 #define DRV_NAME "pata_optidma"
  36 #define DRV_VERSION "0.3.2"
  37
  38 enum {
  39         READ_REG        = 0,    /* index of Read cycle timing register */
  40         WRITE_REG       = 1,    /* index of Write cycle timing register */
  41         CNTRL_REG       = 3,    /* index of Control register */
  42         STRAP_REG       = 5,    /* index of Strap register */
  43         MISC_REG        = 6     /* index of Miscellaneous register */
  44 };
  45
  46 static int pci_clock;   /* 0 = 33 1 = 25 */
  47
  48 /**
  49  *      optidma_pre_reset               -       probe begin
  50  *      @link: ATA link
  51  *      @deadline: deadline jiffies for the operation
  52  *
  53  *      Set up cable type and use generic probe init
  54  */
  55
  56 static int optidma_pre_reset(struct ata_link *link, unsigned long deadline)
  57 {
  58         struct ata_port *ap = link->ap;
  59         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  60         static const struct pci_bits optidma_enable_bits = {
  61                 0x40, 1, 0x08, 0x00
  62         };
  63
  64         if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
  65                 return -ENOENT;
  66
  67         return ata_std_prereset(link, deadline);
  68 }
  69
  70 /**
  71  *      optidma_probe_reset             -       probe reset
  72  *      @ap: ATA port
  73  *
  74  *      Perform the ATA probe and bus reset sequence plus specific handling
  75  *      for this hardware. The Opti needs little handling - we have no UDMA66
  76  *      capability that needs cable detection. All we must do is check the port
  77  *      is enabled.
  78  */
  79
  80 static void optidma_error_handler(struct ata_port *ap)
  81 {
  82         ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
  83 }
  84
  85 /**
  86  *      optidma_unlock          -       unlock control registers
  87  *      @ap: ATA port
  88  *
  89  *      Unlock the control register block for this adapter. Registers must not
  90  *      be unlocked in a situation where libata might look at them.
  91  */
  92
  93 static void optidma_unlock(struct ata_port *ap)
  94 {
  95         void __iomem *regio = ap->ioaddr.cmd_addr;
  96
  97         /* These 3 unlock the control register access */
  98         ioread16(regio + 1);
  99         ioread16(regio + 1);
 100         iowrite8(3, regio + 2);
 101 }
 102
 103 /**
 104  *      optidma_lock            -       issue temporary relock
 105  *      @ap: ATA port
 106  *
 107  *      Re-lock the configuration register settings.
 108  */
 109
 110 static void optidma_lock(struct ata_port *ap)
 111 {
 112         void __iomem *regio = ap->ioaddr.cmd_addr;
 113
 114         /* Relock */
 115         iowrite8(0x83, regio + 2);
 116 }
 117
 118 /**
 119  *      optidma_mode_setup      -       set mode data
 120  *      @ap: ATA interface
 121  *      @adev: ATA device
 122  *      @mode: Mode to set
 123  *
 124  *      Called to do the DMA or PIO mode setup. Timing numbers are all
 125  *      pre computed to keep the code clean. There are two tables depending
 126  *      on the hardware clock speed.
 127  *
 128  *      WARNING: While we do this the IDE registers vanish. If we take an
 129  *      IRQ here we depend on the host set locking to avoid catastrophe.
 130  */
 131
 132 static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
 133 {
 134         struct ata_device *pair = ata_dev_pair(adev);
 135         int pio = adev->pio_mode - XFER_PIO_0;
 136         int dma = adev->dma_mode - XFER_MW_DMA_0;
 137         void __iomem *regio = ap->ioaddr.cmd_addr;
 138         u8 addr;
 139
 140         /* Address table precomputed with a DCLK of 2 */
 141         static const u8 addr_timing[2][5] = {
 142                 { 0x30, 0x20, 0x20, 0x10, 0x10 },
 143                 { 0x20, 0x20, 0x10, 0x10, 0x10 }
 144         };
 145         static const u8 data_rec_timing[2][5] = {
 146                 { 0x59, 0x46, 0x30, 0x20, 0x20 },
 147                 { 0x46, 0x32, 0x20, 0x20, 0x10 }
 148         };
 149         static const u8 dma_data_rec_timing[2][3] = {
 150                 { 0x76, 0x20, 0x20 },
 151                 { 0x54, 0x20, 0x10 }
 152         };
 153
 154         /* Switch from IDE to control mode */
 155         optidma_unlock(ap);
 156
 157
 158         /*
 159          *      As with many controllers the address setup time is shared
 160          *      and must suit both devices if present. FIXME: Check if we
 161          *      need to look at slowest of PIO/DMA mode of either device
 162          */
 163
 164         if (mode >= XFER_MW_DMA_0)
 165                 addr = 0;
 166         else
 167                 addr = addr_timing[pci_clock][pio];
 168
 169         if (pair) {
 170                 u8 pair_addr;
 171                 /* Hardware constraint */
 172                 if (pair->dma_mode)
 173                         pair_addr = 0;
 174                 else
 175                         pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
 176                 if (pair_addr > addr)
 177                         addr = pair_addr;
 178         }
 179
 180         /* Commence primary programming sequence */
 181         /* First we load the device number into the timing select */
 182         iowrite8(adev->devno, regio + MISC_REG);
 183         /* Now we load the data timings into read data/write data */
 184         if (mode < XFER_MW_DMA_0) {
 185                 iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
 186                 iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
 187         } else if (mode < XFER_UDMA_0) {
 188                 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
 189                 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
 190         }
 191         /* Finally we load the address setup into the misc register */
 192         iowrite8(addr | adev->devno, regio + MISC_REG);
 193
 194         /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
 195         iowrite8(0x85, regio + CNTRL_REG);
 196
 197         /* Switch back to IDE mode */
 198         optidma_lock(ap);
 199
 200         /* Note: at this point our programming is incomplete. We are
 201            not supposed to program PCI 0x43 "things we hacked onto the chip"
 202            until we've done both sets of PIO/DMA timings */
 203 }
 204
 205 /**
 206  *      optiplus_mode_setup     -       DMA setup for Firestar Plus
 207  *      @ap: ATA port
 208  *      @adev: device
 209  *      @mode: desired mode
 210  *
 211  *      The Firestar plus has additional UDMA functionality for UDMA0-2 and
 212  *      requires we do some additional work. Because the base work we must do
 213  *      is mostly shared we wrap the Firestar setup functionality in this
 214  *      one
 215  */
 216
 217 static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
 218 {
 219         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 220         u8 udcfg;
 221         u8 udslave;
 222         int dev2 = 2 * adev->devno;
 223         int unit = 2 * ap->port_no + adev->devno;
 224         int udma = mode - XFER_UDMA_0;
 225
 226         pci_read_config_byte(pdev, 0x44, &udcfg);
 227         if (mode <= XFER_UDMA_0) {
 228                 udcfg &= ~(1 << unit);
 229                 optidma_mode_setup(ap, adev, adev->dma_mode);
 230         } else {
 231                 udcfg |=  (1 << unit);
 232                 if (ap->port_no) {
 233                         pci_read_config_byte(pdev, 0x45, &udslave);
 234                         udslave &= ~(0x03 << dev2);
 235                         udslave |= (udma << dev2);
 236                         pci_write_config_byte(pdev, 0x45, udslave);
 237                 } else {
 238                         udcfg &= ~(0x30 << dev2);
 239                         udcfg |= (udma << dev2);
 240                 }
 241         }
 242         pci_write_config_byte(pdev, 0x44, udcfg);
 243 }
 244
 245 /**
 246  *      optidma_set_pio_mode    -       PIO setup callback
 247  *      @ap: ATA port
 248  *      @adev: Device
 249  *
 250  *      The libata core provides separate functions for handling PIO and
 251  *      DMA programming. The architecture of the Firestar makes it easier
 252  *      for us to have a common function so we provide wrappers
 253  */
 254
 255 static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
 256 {
 257         optidma_mode_setup(ap, adev, adev->pio_mode);
 258 }
 259
 260 /**
 261  *      optidma_set_dma_mode    -       DMA setup callback
 262  *      @ap: ATA port
 263  *      @adev: Device
 264  *
 265  *      The libata core provides separate functions for handling PIO and
 266  *      DMA programming. The architecture of the Firestar makes it easier
 267  *      for us to have a common function so we provide wrappers
 268  */
 269
 270 static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
 271 {
 272         optidma_mode_setup(ap, adev, adev->dma_mode);
 273 }
 274
 275 /**
 276  *      optiplus_set_pio_mode   -       PIO setup callback
 277  *      @ap: ATA port
 278  *      @adev: Device
 279  *
 280  *      The libata core provides separate functions for handling PIO and
 281  *      DMA programming. The architecture of the Firestar makes it easier
 282  *      for us to have a common function so we provide wrappers
 283  */
 284
 285 static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
 286 {
 287         optiplus_mode_setup(ap, adev, adev->pio_mode);
 288 }
 289
 290 /**
 291  *      optiplus_set_dma_mode   -       DMA setup callback
 292  *      @ap: ATA port
 293  *      @adev: Device
 294  *
 295  *      The libata core provides separate functions for handling PIO and
 296  *      DMA programming. The architecture of the Firestar makes it easier
 297  *      for us to have a common function so we provide wrappers
 298  */
 299
 300 static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
 301 {
 302         optiplus_mode_setup(ap, adev, adev->dma_mode);
 303 }
 304
 305 /**
 306  *      optidma_make_bits       -       PCI setup helper
 307  *      @adev: ATA device
 308  *
 309  *      Turn the ATA device setup into PCI configuration bits
 310  *      for register 0x43 and return the two bits needed.
 311  */
 312
 313 static u8 optidma_make_bits43(struct ata_device *adev)
 314 {
 315         static const u8 bits43[5] = {
 316                 0, 0, 0, 1, 2
 317         };
 318         if (!ata_dev_enabled(adev))
 319                 return 0;
 320         if (adev->dma_mode)
 321                 return adev->dma_mode - XFER_MW_DMA_0;
 322         return bits43[adev->pio_mode - XFER_PIO_0];
 323 }
 324
 325 /**
 326  *      optidma_set_mode        -       mode setup
 327  *      @link: link to set up
 328  *
 329  *      Use the standard setup to tune the chipset and then finalise the
 330  *      configuration by writing the nibble of extra bits of data into
 331  *      the chip.
 332  */
 333
 334 static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed)
 335 {
 336         struct ata_port *ap = link->ap;
 337         u8 r;
 338         int nybble = 4 * ap->port_no;
 339         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 340         int rc  = ata_do_set_mode(link, r_failed);
 341         if (rc == 0) {
 342                 pci_read_config_byte(pdev, 0x43, &r);
 343
 344                 r &= (0x0F << nybble);
 345                 r |= (optidma_make_bits43(&link->device[0]) +
 346                      (optidma_make_bits43(&link->device[0]) << 2)) << nybble;
 347                 pci_write_config_byte(pdev, 0x43, r);
 348         }
 349         return rc;
 350 }
 351
 352 static struct scsi_host_template optidma_sht = {
 353         ATA_BMDMA_SHT(DRV_NAME),
 354 };
 355
 356 static struct ata_port_operations optidma_port_ops = {
 357         .inherits       = &ata_bmdma_port_ops,
 358         .cable_detect   = ata_cable_40wire,
 359         .set_piomode    = optidma_set_pio_mode,
 360         .set_dmamode    = optidma_set_dma_mode,
 361         .set_mode       = optidma_set_mode,
 362         .error_handler  = optidma_error_handler,
 363 };
 364
 365 static struct ata_port_operations optiplus_port_ops = {
 366         .inherits       = &optidma_port_ops,
 367         .set_piomode    = optiplus_set_pio_mode,
 368         .set_dmamode    = optiplus_set_dma_mode,
 369 };
 370
 371 /**
 372  *      optiplus_with_udma      -       Look for UDMA capable setup
 373  *      @pdev; ATA controller
 374  */
 375
 376 static int optiplus_with_udma(struct pci_dev *pdev)
 377 {
 378         u8 r;
 379         int ret = 0;
 380         int ioport = 0x22;
 381         struct pci_dev *dev1;
 382
 383         /* Find function 1 */
 384         dev1 = pci_get_device(0x1045, 0xC701, NULL);
 385         if (dev1 == NULL)
 386                 return 0;
 387
 388         /* Rev must be >= 0x10 */
 389         pci_read_config_byte(dev1, 0x08, &r);
 390         if (r < 0x10)
 391                 goto done_nomsg;
 392         /* Read the chipset system configuration to check our mode */
 393         pci_read_config_byte(dev1, 0x5F, &r);
 394         ioport |= (r << 8);
 395         outb(0x10, ioport);
 396         /* Must be 66Mhz sync */
 397         if ((inb(ioport + 2) & 1) == 0)
 398                 goto done;
 399
 400         /* Check the ATA arbitration/timing is suitable */
 401         pci_read_config_byte(pdev, 0x42, &r);
 402         if ((r & 0x36) != 0x36)
 403                 goto done;
 404         pci_read_config_byte(dev1, 0x52, &r);
 405         if (r & 0x80)   /* IDEDIR disabled */
 406                 ret = 1;
 407 done:
 408         printk(KERN_WARNING "UDMA not supported in this configuration.\n");
 409 done_nomsg:             /* Wrong chip revision */
 410         pci_dev_put(dev1);
 411         return ret;
 412 }
 413
 414 static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 415 {
 416         static const struct ata_port_info info_82c700 = {
 417                 .flags = ATA_FLAG_SLAVE_POSS,
 418                 .pio_mask = 0x1f,
 419                 .mwdma_mask = 0x07,
 420                 .port_ops = &optidma_port_ops
 421         };
 422         static const struct ata_port_info info_82c700_udma = {
 423                 .flags = ATA_FLAG_SLAVE_POSS,
 424                 .pio_mask = 0x1f,
 425                 .mwdma_mask = 0x07,
 426                 .udma_mask = 0x07,
 427                 .port_ops = &optiplus_port_ops
 428         };
 429         const struct ata_port_info *ppi[] = { &info_82c700, NULL };
 430         static int printed_version;
 431         int rc;
 432
 433         if (!printed_version++)
 434                 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
 435
 436         rc = pcim_enable_device(dev);
 437         if (rc)
 438                 return rc;
 439
 440         /* Fixed location chipset magic */
 441         inw(0x1F1);
 442         inw(0x1F1);
 443         pci_clock = inb(0x1F5) & 1;             /* 0 = 33Mhz, 1 = 25Mhz */
 444
 445         if (optiplus_with_udma(dev))
 446                 ppi[0] = &info_82c700_udma;
 447
 448         return ata_pci_init_one(dev, ppi, &optidma_sht);
 449 }
 450
 451 static const struct pci_device_id optidma[] = {
 452         { PCI_VDEVICE(OPTI, 0xD568), },         /* Opti 82C700 */
 453
 454         { },
 455 };
 456
 457 static struct pci_driver optidma_pci_driver = {
 458         .name           = DRV_NAME,
 459         .id_table       = optidma,
 460         .probe          = optidma_init_one,
 461         .remove         = ata_pci_remove_one,
 462 #ifdef CONFIG_PM
 463         .suspend        = ata_pci_device_suspend,
 464         .resume         = ata_pci_device_resume,
 465 #endif
 466 };
 467
 468 static int __init optidma_init(void)
 469 {
 470         return pci_register_driver(&optidma_pci_driver);
 471 }
 472
 473 static void __exit optidma_exit(void)
 474 {
 475         pci_unregister_driver(&optidma_pci_driver);
 476 }
 477
 478 MODULE_AUTHOR("Alan Cox");
 479 MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
 480 MODULE_LICENSE("GPL");
 481 MODULE_DEVICE_TABLE(pci, optidma);
 482 MODULE_VERSION(DRV_VERSION);
 483
 484 module_init(optidma_init);
 485 module_exit(optidma_exit);