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[deliverable/linux.git] / drivers / ata / pata_pdc2027x.c
1 /*
2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Ported to libata by:
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
11 *
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 *
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
17 *
18 *
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
21 *
22 * Hardware information only available under NDA.
23 *
24 */
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <scsi/scsi.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
36
37 #define DRV_NAME "pata_pdc2027x"
38 #define DRV_VERSION "1.0"
39 #undef PDC_DEBUG
40
41 #ifdef PDC_DEBUG
42 #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
43 #else
44 #define PDPRINTK(fmt, args...)
45 #endif
46
47 enum {
48 PDC_MMIO_BAR = 5,
49
50 PDC_UDMA_100 = 0,
51 PDC_UDMA_133 = 1,
52
53 PDC_100_MHZ = 100000000,
54 PDC_133_MHZ = 133333333,
55
56 PDC_SYS_CTL = 0x1100,
57 PDC_ATA_CTL = 0x1104,
58 PDC_GLOBAL_CTL = 0x1108,
59 PDC_CTCR0 = 0x110C,
60 PDC_CTCR1 = 0x1110,
61 PDC_BYTE_COUNT = 0x1120,
62 PDC_PLL_CTL = 0x1202,
63 };
64
65 static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
66 static void pdc2027x_error_handler(struct ata_port *ap);
67 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
68 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
69 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
70 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
71 static int pdc2027x_cable_detect(struct ata_port *ap);
72 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
73
74 /*
75 * ATA Timing Tables based on 133MHz controller clock.
76 * These tables are only used when the controller is in 133MHz clock.
77 * If the controller is in 100MHz clock, the ASIC hardware will
78 * set the timing registers automatically when "set feature" command
79 * is issued to the device. However, if the controller clock is 133MHz,
80 * the following tables must be used.
81 */
82 static struct pdc2027x_pio_timing {
83 u8 value0, value1, value2;
84 } pdc2027x_pio_timing_tbl [] = {
85 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
86 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
87 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
88 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
89 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
90 };
91
92 static struct pdc2027x_mdma_timing {
93 u8 value0, value1;
94 } pdc2027x_mdma_timing_tbl [] = {
95 { 0xdf, 0x5f }, /* MDMA mode 0 */
96 { 0x6b, 0x27 }, /* MDMA mode 1 */
97 { 0x69, 0x25 }, /* MDMA mode 2 */
98 };
99
100 static struct pdc2027x_udma_timing {
101 u8 value0, value1, value2;
102 } pdc2027x_udma_timing_tbl [] = {
103 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
104 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
105 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
106 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
107 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
108 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
109 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
110 };
111
112 static const struct pci_device_id pdc2027x_pci_tbl[] = {
113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
117 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
118 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
119 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
120
121 { } /* terminate list */
122 };
123
124 static struct pci_driver pdc2027x_pci_driver = {
125 .name = DRV_NAME,
126 .id_table = pdc2027x_pci_tbl,
127 .probe = pdc2027x_init_one,
128 .remove = ata_pci_remove_one,
129 };
130
131 static struct scsi_host_template pdc2027x_sht = {
132 .module = THIS_MODULE,
133 .name = DRV_NAME,
134 .ioctl = ata_scsi_ioctl,
135 .queuecommand = ata_scsi_queuecmd,
136 .can_queue = ATA_DEF_QUEUE,
137 .this_id = ATA_SHT_THIS_ID,
138 .sg_tablesize = LIBATA_MAX_PRD,
139 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
140 .emulated = ATA_SHT_EMULATED,
141 .use_clustering = ATA_SHT_USE_CLUSTERING,
142 .proc_name = DRV_NAME,
143 .dma_boundary = ATA_DMA_BOUNDARY,
144 .slave_configure = ata_scsi_slave_config,
145 .slave_destroy = ata_scsi_slave_destroy,
146 .bios_param = ata_std_bios_param,
147 };
148
149 static struct ata_port_operations pdc2027x_pata100_ops = {
150 .port_disable = ata_port_disable,
151 .mode_filter = ata_pci_default_filter,
152
153 .tf_load = ata_tf_load,
154 .tf_read = ata_tf_read,
155 .check_status = ata_check_status,
156 .exec_command = ata_exec_command,
157 .dev_select = ata_std_dev_select,
158
159 .check_atapi_dma = pdc2027x_check_atapi_dma,
160 .bmdma_setup = ata_bmdma_setup,
161 .bmdma_start = ata_bmdma_start,
162 .bmdma_stop = ata_bmdma_stop,
163 .bmdma_status = ata_bmdma_status,
164 .qc_prep = ata_qc_prep,
165 .qc_issue = ata_qc_issue_prot,
166 .data_xfer = ata_data_xfer,
167
168 .freeze = ata_bmdma_freeze,
169 .thaw = ata_bmdma_thaw,
170 .error_handler = pdc2027x_error_handler,
171 .post_internal_cmd = ata_bmdma_post_internal_cmd,
172 .cable_detect = pdc2027x_cable_detect,
173
174 .irq_clear = ata_bmdma_irq_clear,
175 .irq_on = ata_irq_on,
176
177 .port_start = ata_port_start,
178 };
179
180 static struct ata_port_operations pdc2027x_pata133_ops = {
181 .port_disable = ata_port_disable,
182 .set_piomode = pdc2027x_set_piomode,
183 .set_dmamode = pdc2027x_set_dmamode,
184 .set_mode = pdc2027x_set_mode,
185 .mode_filter = pdc2027x_mode_filter,
186
187 .tf_load = ata_tf_load,
188 .tf_read = ata_tf_read,
189 .check_status = ata_check_status,
190 .exec_command = ata_exec_command,
191 .dev_select = ata_std_dev_select,
192
193 .check_atapi_dma = pdc2027x_check_atapi_dma,
194 .bmdma_setup = ata_bmdma_setup,
195 .bmdma_start = ata_bmdma_start,
196 .bmdma_stop = ata_bmdma_stop,
197 .bmdma_status = ata_bmdma_status,
198 .qc_prep = ata_qc_prep,
199 .qc_issue = ata_qc_issue_prot,
200 .data_xfer = ata_data_xfer,
201
202 .freeze = ata_bmdma_freeze,
203 .thaw = ata_bmdma_thaw,
204 .error_handler = pdc2027x_error_handler,
205 .post_internal_cmd = ata_bmdma_post_internal_cmd,
206 .cable_detect = pdc2027x_cable_detect,
207
208 .irq_clear = ata_bmdma_irq_clear,
209 .irq_on = ata_irq_on,
210
211 .port_start = ata_port_start,
212 };
213
214 static struct ata_port_info pdc2027x_port_info[] = {
215 /* PDC_UDMA_100 */
216 {
217 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
218 ATA_FLAG_MMIO,
219 .pio_mask = 0x1f, /* pio0-4 */
220 .mwdma_mask = 0x07, /* mwdma0-2 */
221 .udma_mask = ATA_UDMA5, /* udma0-5 */
222 .port_ops = &pdc2027x_pata100_ops,
223 },
224 /* PDC_UDMA_133 */
225 {
226 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
227 ATA_FLAG_MMIO,
228 .pio_mask = 0x1f, /* pio0-4 */
229 .mwdma_mask = 0x07, /* mwdma0-2 */
230 .udma_mask = ATA_UDMA6, /* udma0-6 */
231 .port_ops = &pdc2027x_pata133_ops,
232 },
233 };
234
235 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
236 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
237 MODULE_LICENSE("GPL");
238 MODULE_VERSION(DRV_VERSION);
239 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
240
241 /**
242 * port_mmio - Get the MMIO address of PDC2027x extended registers
243 * @ap: Port
244 * @offset: offset from mmio base
245 */
246 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
247 {
248 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
249 }
250
251 /**
252 * dev_mmio - Get the MMIO address of PDC2027x extended registers
253 * @ap: Port
254 * @adev: device
255 * @offset: offset from mmio base
256 */
257 static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
258 {
259 u8 adj = (adev->devno) ? 0x08 : 0x00;
260 return port_mmio(ap, offset) + adj;
261 }
262
263 /**
264 * pdc2027x_pata_cable_detect - Probe host controller cable detect info
265 * @ap: Port for which cable detect info is desired
266 *
267 * Read 80c cable indicator from Promise extended register.
268 * This register is latched when the system is reset.
269 *
270 * LOCKING:
271 * None (inherited from caller).
272 */
273 static int pdc2027x_cable_detect(struct ata_port *ap)
274 {
275 u32 cgcr;
276
277 /* check cable detect results */
278 cgcr = readl(port_mmio(ap, PDC_GLOBAL_CTL));
279 if (cgcr & (1 << 26))
280 goto cbl40;
281
282 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
283
284 return ATA_CBL_PATA80;
285 cbl40:
286 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
287 return ATA_CBL_PATA40;
288 }
289
290 /**
291 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
292 * @ap: Port to check
293 */
294 static inline int pdc2027x_port_enabled(struct ata_port *ap)
295 {
296 return readb(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
297 }
298
299 /**
300 * pdc2027x_prereset - prereset for PATA host controller
301 * @link: Target link
302 * @deadline: deadline jiffies for the operation
303 *
304 * Probeinit including cable detection.
305 *
306 * LOCKING:
307 * None (inherited from caller).
308 */
309
310 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
311 {
312 /* Check whether port enabled */
313 if (!pdc2027x_port_enabled(link->ap))
314 return -ENOENT;
315 return ata_std_prereset(link, deadline);
316 }
317
318 /**
319 * pdc2027x_error_handler - Perform reset on PATA port and classify
320 * @ap: Port to reset
321 *
322 * Reset PATA phy and classify attached devices.
323 *
324 * LOCKING:
325 * None (inherited from caller).
326 */
327
328 static void pdc2027x_error_handler(struct ata_port *ap)
329 {
330 ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset);
331 }
332
333 /**
334 * pdc2720x_mode_filter - mode selection filter
335 * @adev: ATA device
336 * @mask: list of modes proposed
337 *
338 * Block UDMA on devices that cause trouble with this controller.
339 */
340
341 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
342 {
343 unsigned char model_num[ATA_ID_PROD_LEN + 1];
344 struct ata_device *pair = ata_dev_pair(adev);
345
346 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
347 return ata_pci_default_filter(adev, mask);
348
349 /* Check for slave of a Maxtor at UDMA6 */
350 ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
351 ATA_ID_PROD_LEN + 1);
352 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
353 if(strstr(model_num, "Maxtor") == 0 && pair->dma_mode == XFER_UDMA_6)
354 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
355
356 return ata_pci_default_filter(adev, mask);
357 }
358
359 /**
360 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
361 * @ap: Port to configure
362 * @adev: um
363 * @pio: PIO mode, 0 - 4
364 *
365 * Set PIO mode for device.
366 *
367 * LOCKING:
368 * None (inherited from caller).
369 */
370
371 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
372 {
373 unsigned int pio = adev->pio_mode - XFER_PIO_0;
374 u32 ctcr0, ctcr1;
375
376 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
377
378 /* Sanity check */
379 if (pio > 4) {
380 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
381 return;
382
383 }
384
385 /* Set the PIO timing registers using value table for 133MHz */
386 PDPRINTK("Set pio regs... \n");
387
388 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
389 ctcr0 &= 0xffff0000;
390 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
391 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
392 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
393
394 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
395 ctcr1 &= 0x00ffffff;
396 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
397 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
398
399 PDPRINTK("Set pio regs done\n");
400
401 PDPRINTK("Set to pio mode[%u] \n", pio);
402 }
403
404 /**
405 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
406 * @ap: Port to configure
407 * @adev: um
408 * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
409 *
410 * Set UDMA mode for device.
411 *
412 * LOCKING:
413 * None (inherited from caller).
414 */
415 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
416 {
417 unsigned int dma_mode = adev->dma_mode;
418 u32 ctcr0, ctcr1;
419
420 if ((dma_mode >= XFER_UDMA_0) &&
421 (dma_mode <= XFER_UDMA_6)) {
422 /* Set the UDMA timing registers with value table for 133MHz */
423 unsigned int udma_mode = dma_mode & 0x07;
424
425 if (dma_mode == XFER_UDMA_2) {
426 /*
427 * Turn off tHOLD.
428 * If tHOLD is '1', the hardware will add half clock for data hold time.
429 * This code segment seems to be no effect. tHOLD will be overwritten below.
430 */
431 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
432 writel(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
433 }
434
435 PDPRINTK("Set udma regs... \n");
436
437 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
438 ctcr1 &= 0xff000000;
439 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
440 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
441 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
442 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
443
444 PDPRINTK("Set udma regs done\n");
445
446 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
447
448 } else if ((dma_mode >= XFER_MW_DMA_0) &&
449 (dma_mode <= XFER_MW_DMA_2)) {
450 /* Set the MDMA timing registers with value table for 133MHz */
451 unsigned int mdma_mode = dma_mode & 0x07;
452
453 PDPRINTK("Set mdma regs... \n");
454 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
455
456 ctcr0 &= 0x0000ffff;
457 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
458 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
459
460 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
461 PDPRINTK("Set mdma regs done\n");
462
463 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
464 } else {
465 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
466 }
467 }
468
469 /**
470 * pdc2027x_set_mode - Set the timing registers back to correct values.
471 * @link: link to configure
472 * @r_failed: Returned device for failure
473 *
474 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
475 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
476 * This function overwrites the possibly incorrect values set by the hardware to be correct.
477 */
478 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed)
479 {
480 struct ata_port *ap = link->ap;
481 struct ata_device *dev;
482 int rc;
483
484 rc = ata_do_set_mode(link, r_failed);
485 if (rc < 0)
486 return rc;
487
488 ata_link_for_each_dev(dev, link) {
489 if (ata_dev_enabled(dev)) {
490
491 pdc2027x_set_piomode(ap, dev);
492
493 /*
494 * Enable prefetch if the device support PIO only.
495 */
496 if (dev->xfer_shift == ATA_SHIFT_PIO) {
497 u32 ctcr1 = readl(dev_mmio(ap, dev, PDC_CTCR1));
498 ctcr1 |= (1 << 25);
499 writel(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
500
501 PDPRINTK("Turn on prefetch\n");
502 } else {
503 pdc2027x_set_dmamode(ap, dev);
504 }
505 }
506 }
507 return 0;
508 }
509
510 /**
511 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
512 * @qc: Metadata associated with taskfile to check
513 *
514 * LOCKING:
515 * None (inherited from caller).
516 *
517 * RETURNS: 0 when ATAPI DMA can be used
518 * 1 otherwise
519 */
520 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
521 {
522 struct scsi_cmnd *cmd = qc->scsicmd;
523 u8 *scsicmd = cmd->cmnd;
524 int rc = 1; /* atapi dma off by default */
525
526 /*
527 * This workaround is from Promise's GPL driver.
528 * If ATAPI DMA is used for commands not in the
529 * following white list, say MODE_SENSE and REQUEST_SENSE,
530 * pdc2027x might hit the irq lost problem.
531 */
532 switch (scsicmd[0]) {
533 case READ_10:
534 case WRITE_10:
535 case READ_12:
536 case WRITE_12:
537 case READ_6:
538 case WRITE_6:
539 case 0xad: /* READ_DVD_STRUCTURE */
540 case 0xbe: /* READ_CD */
541 /* ATAPI DMA is ok */
542 rc = 0;
543 break;
544 default:
545 ;
546 }
547
548 return rc;
549 }
550
551 /**
552 * pdc_read_counter - Read the ctr counter
553 * @host: target ATA host
554 */
555
556 static long pdc_read_counter(struct ata_host *host)
557 {
558 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
559 long counter;
560 int retry = 1;
561 u32 bccrl, bccrh, bccrlv, bccrhv;
562
563 retry:
564 bccrl = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
565 bccrh = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
566 rmb();
567
568 /* Read the counter values again for verification */
569 bccrlv = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
570 bccrhv = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
571 rmb();
572
573 counter = (bccrh << 15) | bccrl;
574
575 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
576 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
577
578 /*
579 * The 30-bit decreasing counter are read by 2 pieces.
580 * Incorrect value may be read when both bccrh and bccrl are changing.
581 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
582 */
583 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
584 retry--;
585 PDPRINTK("rereading counter\n");
586 goto retry;
587 }
588
589 return counter;
590 }
591
592 /**
593 * adjust_pll - Adjust the PLL input clock in Hz.
594 *
595 * @pdc_controller: controller specific information
596 * @host: target ATA host
597 * @pll_clock: The input of PLL in HZ
598 */
599 static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
600 {
601 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
602 u16 pll_ctl;
603 long pll_clock_khz = pll_clock / 1000;
604 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
605 long ratio = pout_required / pll_clock_khz;
606 int F, R;
607
608 /* Sanity check */
609 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
610 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
611 return;
612 }
613
614 #ifdef PDC_DEBUG
615 PDPRINTK("pout_required is %ld\n", pout_required);
616
617 /* Show the current clock value of PLL control register
618 * (maybe already configured by the firmware)
619 */
620 pll_ctl = readw(mmio_base + PDC_PLL_CTL);
621
622 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
623 #endif
624
625 /*
626 * Calculate the ratio of F, R and OD
627 * POUT = (F + 2) / (( R + 2) * NO)
628 */
629 if (ratio < 8600L) { /* 8.6x */
630 /* Using NO = 0x01, R = 0x0D */
631 R = 0x0d;
632 } else if (ratio < 12900L) { /* 12.9x */
633 /* Using NO = 0x01, R = 0x08 */
634 R = 0x08;
635 } else if (ratio < 16100L) { /* 16.1x */
636 /* Using NO = 0x01, R = 0x06 */
637 R = 0x06;
638 } else if (ratio < 64000L) { /* 64x */
639 R = 0x00;
640 } else {
641 /* Invalid ratio */
642 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
643 return;
644 }
645
646 F = (ratio * (R+2)) / 1000 - 2;
647
648 if (unlikely(F < 0 || F > 127)) {
649 /* Invalid F */
650 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
651 return;
652 }
653
654 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
655
656 pll_ctl = (R << 8) | F;
657
658 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
659
660 writew(pll_ctl, mmio_base + PDC_PLL_CTL);
661 readw(mmio_base + PDC_PLL_CTL); /* flush */
662
663 /* Wait the PLL circuit to be stable */
664 mdelay(30);
665
666 #ifdef PDC_DEBUG
667 /*
668 * Show the current clock value of PLL control register
669 * (maybe configured by the firmware)
670 */
671 pll_ctl = readw(mmio_base + PDC_PLL_CTL);
672
673 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
674 #endif
675
676 return;
677 }
678
679 /**
680 * detect_pll_input_clock - Detect the PLL input clock in Hz.
681 * @host: target ATA host
682 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
683 * Half of the PCI clock.
684 */
685 static long pdc_detect_pll_input_clock(struct ata_host *host)
686 {
687 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
688 u32 scr;
689 long start_count, end_count;
690 struct timeval start_time, end_time;
691 long pll_clock, usec_elapsed;
692
693 /* Start the test mode */
694 scr = readl(mmio_base + PDC_SYS_CTL);
695 PDPRINTK("scr[%X]\n", scr);
696 writel(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
697 readl(mmio_base + PDC_SYS_CTL); /* flush */
698
699 /* Read current counter value */
700 start_count = pdc_read_counter(host);
701 do_gettimeofday(&start_time);
702
703 /* Let the counter run for 100 ms. */
704 mdelay(100);
705
706 /* Read the counter values again */
707 end_count = pdc_read_counter(host);
708 do_gettimeofday(&end_time);
709
710 /* Stop the test mode */
711 scr = readl(mmio_base + PDC_SYS_CTL);
712 PDPRINTK("scr[%X]\n", scr);
713 writel(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
714 readl(mmio_base + PDC_SYS_CTL); /* flush */
715
716 /* calculate the input clock in Hz */
717 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
718 (end_time.tv_usec - start_time.tv_usec);
719
720 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
721 (100000000 / usec_elapsed);
722
723 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
724 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
725
726 return pll_clock;
727 }
728
729 /**
730 * pdc_hardware_init - Initialize the hardware.
731 * @host: target ATA host
732 * @board_idx: board identifier
733 */
734 static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
735 {
736 long pll_clock;
737
738 /*
739 * Detect PLL input clock rate.
740 * On some system, where PCI bus is running at non-standard clock rate.
741 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
742 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
743 */
744 pll_clock = pdc_detect_pll_input_clock(host);
745
746 if (pll_clock < 0) /* counter overflow? Try again. */
747 pll_clock = pdc_detect_pll_input_clock(host);
748
749 dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
750
751 /* Adjust PLL control register */
752 pdc_adjust_pll(host, pll_clock, board_idx);
753
754 return 0;
755 }
756
757 /**
758 * pdc_ata_setup_port - setup the mmio address
759 * @port: ata ioports to setup
760 * @base: base address
761 */
762 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
763 {
764 port->cmd_addr =
765 port->data_addr = base;
766 port->feature_addr =
767 port->error_addr = base + 0x05;
768 port->nsect_addr = base + 0x0a;
769 port->lbal_addr = base + 0x0f;
770 port->lbam_addr = base + 0x10;
771 port->lbah_addr = base + 0x15;
772 port->device_addr = base + 0x1a;
773 port->command_addr =
774 port->status_addr = base + 0x1f;
775 port->altstatus_addr =
776 port->ctl_addr = base + 0x81a;
777 }
778
779 /**
780 * pdc2027x_init_one - PCI probe function
781 * Called when an instance of PCI adapter is inserted.
782 * This function checks whether the hardware is supported,
783 * initialize hardware and register an instance of ata_host to
784 * libata. (implements struct pci_driver.probe() )
785 *
786 * @pdev: instance of pci_dev found
787 * @ent: matching entry in the id_tbl[]
788 */
789 static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
790 {
791 static int printed_version;
792 unsigned int board_idx = (unsigned int) ent->driver_data;
793 const struct ata_port_info *ppi[] =
794 { &pdc2027x_port_info[board_idx], NULL };
795 struct ata_host *host;
796 void __iomem *mmio_base;
797 int rc;
798
799 if (!printed_version++)
800 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
801
802 /* alloc host */
803 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
804 if (!host)
805 return -ENOMEM;
806
807 /* acquire resources and fill host */
808 rc = pcim_enable_device(pdev);
809 if (rc)
810 return rc;
811
812 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
813 if (rc)
814 return rc;
815 host->iomap = pcim_iomap_table(pdev);
816
817 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
818 if (rc)
819 return rc;
820
821 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
822 if (rc)
823 return rc;
824
825 mmio_base = host->iomap[PDC_MMIO_BAR];
826
827 pdc_ata_setup_port(&host->ports[0]->ioaddr, mmio_base + 0x17c0);
828 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x1000;
829 pdc_ata_setup_port(&host->ports[1]->ioaddr, mmio_base + 0x15c0);
830 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x1008;
831
832 //pci_enable_intx(pdev);
833
834 /* initialize adapter */
835 if (pdc_hardware_init(host, board_idx) != 0)
836 return -EIO;
837
838 pci_set_master(pdev);
839 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
840 &pdc2027x_sht);
841 }
842
843 /**
844 * pdc2027x_init - Called after this module is loaded into the kernel.
845 */
846 static int __init pdc2027x_init(void)
847 {
848 return pci_register_driver(&pdc2027x_pci_driver);
849 }
850
851 /**
852 * pdc2027x_exit - Called before this module unloaded from the kernel
853 */
854 static void __exit pdc2027x_exit(void)
855 {
856 pci_unregister_driver(&pdc2027x_pci_driver);
857 }
858
859 module_init(pdc2027x_init);
860 module_exit(pdc2027x_exit);
Linux kernel - Deliverables
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