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[deliverable/linux.git] / drivers / ata / pdc_adma.c
1 /*
2 * pdc_adma.c - Pacific Digital Corporation ADMA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Mark Lord
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 *
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
29 *
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
45
46 #define DRV_NAME "pdc_adma"
47 #define DRV_VERSION "1.0"
48
49 /* macro to calculate base address for ATA regs */
50 #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
51
52 /* macro to calculate base address for ADMA regs */
53 #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
54
55 /* macro to obtain addresses from ata_port */
56 #define ADMA_PORT_REGS(ap) \
57 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
58
59 enum {
60 ADMA_MMIO_BAR = 4,
61
62 ADMA_PORTS = 2,
63 ADMA_CPB_BYTES = 40,
64 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
65 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
66
67 ADMA_DMA_BOUNDARY = 0xffffffff,
68
69 /* global register offsets */
70 ADMA_MODE_LOCK = 0x00c7,
71
72 /* per-channel register offsets */
73 ADMA_CONTROL = 0x0000, /* ADMA control */
74 ADMA_STATUS = 0x0002, /* ADMA status */
75 ADMA_CPB_COUNT = 0x0004, /* CPB count */
76 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
77 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
78 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
79 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
80 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
81
82 /* ADMA_CONTROL register bits */
83 aNIEN = (1 << 8), /* irq mask: 1==masked */
84 aGO = (1 << 7), /* packet trigger ("Go!") */
85 aRSTADM = (1 << 5), /* ADMA logic reset */
86 aPIOMD4 = 0x0003, /* PIO mode 4 */
87
88 /* ADMA_STATUS register bits */
89 aPSD = (1 << 6),
90 aUIRQ = (1 << 4),
91 aPERR = (1 << 0),
92
93 /* CPB bits */
94 cDONE = (1 << 0),
95 cATERR = (1 << 3),
96
97 cVLD = (1 << 0),
98 cDAT = (1 << 2),
99 cIEN = (1 << 3),
100
101 /* PRD bits */
102 pORD = (1 << 4),
103 pDIRO = (1 << 5),
104 pEND = (1 << 7),
105
106 /* ATA register flags */
107 rIGN = (1 << 5),
108 rEND = (1 << 7),
109
110 /* ATA register addresses */
111 ADMA_REGS_CONTROL = 0x0e,
112 ADMA_REGS_SECTOR_COUNT = 0x12,
113 ADMA_REGS_LBA_LOW = 0x13,
114 ADMA_REGS_LBA_MID = 0x14,
115 ADMA_REGS_LBA_HIGH = 0x15,
116 ADMA_REGS_DEVICE = 0x16,
117 ADMA_REGS_COMMAND = 0x17,
118
119 /* PCI device IDs */
120 board_1841_idx = 0, /* ADMA 2-port controller */
121 };
122
123 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
124
125 struct adma_port_priv {
126 u8 *pkt;
127 dma_addr_t pkt_dma;
128 adma_state_t state;
129 };
130
131 static int adma_ata_init_one(struct pci_dev *pdev,
132 const struct pci_device_id *ent);
133 static int adma_port_start(struct ata_port *ap);
134 static void adma_host_stop(struct ata_host *host);
135 static void adma_port_stop(struct ata_port *ap);
136 static void adma_qc_prep(struct ata_queued_cmd *qc);
137 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
138 static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
139 static void adma_bmdma_stop(struct ata_queued_cmd *qc);
140 static u8 adma_bmdma_status(struct ata_port *ap);
141 static void adma_freeze(struct ata_port *ap);
142 static void adma_thaw(struct ata_port *ap);
143 static void adma_error_handler(struct ata_port *ap);
144
145 static struct scsi_host_template adma_ata_sht = {
146 .module = THIS_MODULE,
147 .name = DRV_NAME,
148 .ioctl = ata_scsi_ioctl,
149 .queuecommand = ata_scsi_queuecmd,
150 .slave_configure = ata_scsi_slave_config,
151 .slave_destroy = ata_scsi_slave_destroy,
152 .bios_param = ata_std_bios_param,
153 .proc_name = DRV_NAME,
154 .can_queue = ATA_DEF_QUEUE,
155 .this_id = ATA_SHT_THIS_ID,
156 .sg_tablesize = LIBATA_MAX_PRD,
157 .dma_boundary = ADMA_DMA_BOUNDARY,
158 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
159 .use_clustering = ENABLE_CLUSTERING,
160 .emulated = ATA_SHT_EMULATED,
161 };
162
163 static const struct ata_port_operations adma_ata_ops = {
164 .tf_load = ata_tf_load,
165 .tf_read = ata_tf_read,
166 .exec_command = ata_exec_command,
167 .check_status = ata_check_status,
168 .dev_select = ata_std_dev_select,
169 .check_atapi_dma = adma_check_atapi_dma,
170 .data_xfer = ata_data_xfer,
171 .qc_prep = adma_qc_prep,
172 .qc_issue = adma_qc_issue,
173 .freeze = adma_freeze,
174 .thaw = adma_thaw,
175 .error_handler = adma_error_handler,
176 .irq_clear = ata_noop_irq_clear,
177 .irq_on = ata_irq_on,
178 .port_start = adma_port_start,
179 .port_stop = adma_port_stop,
180 .host_stop = adma_host_stop,
181 .bmdma_stop = adma_bmdma_stop,
182 .bmdma_status = adma_bmdma_status,
183 };
184
185 static struct ata_port_info adma_port_info[] = {
186 /* board_1841_idx */
187 {
188 .flags = ATA_FLAG_SLAVE_POSS |
189 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
190 ATA_FLAG_PIO_POLLING,
191 .pio_mask = 0x10, /* pio4 */
192 .udma_mask = ATA_UDMA4,
193 .port_ops = &adma_ata_ops,
194 },
195 };
196
197 static const struct pci_device_id adma_ata_pci_tbl[] = {
198 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
199
200 { } /* terminate list */
201 };
202
203 static struct pci_driver adma_ata_pci_driver = {
204 .name = DRV_NAME,
205 .id_table = adma_ata_pci_tbl,
206 .probe = adma_ata_init_one,
207 .remove = ata_pci_remove_one,
208 };
209
210 static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
211 {
212 return 1; /* ATAPI DMA not yet supported */
213 }
214
215 static void adma_bmdma_stop(struct ata_queued_cmd *qc)
216 {
217 /* nothing */
218 }
219
220 static u8 adma_bmdma_status(struct ata_port *ap)
221 {
222 return 0;
223 }
224
225 static void adma_reset_engine(struct ata_port *ap)
226 {
227 void __iomem *chan = ADMA_PORT_REGS(ap);
228
229 /* reset ADMA to idle state */
230 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
231 udelay(2);
232 writew(aPIOMD4, chan + ADMA_CONTROL);
233 udelay(2);
234 }
235
236 static void adma_reinit_engine(struct ata_port *ap)
237 {
238 struct adma_port_priv *pp = ap->private_data;
239 void __iomem *chan = ADMA_PORT_REGS(ap);
240
241 /* mask/clear ATA interrupts */
242 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
243 ata_check_status(ap);
244
245 /* reset the ADMA engine */
246 adma_reset_engine(ap);
247
248 /* set in-FIFO threshold to 0x100 */
249 writew(0x100, chan + ADMA_FIFO_IN);
250
251 /* set CPB pointer */
252 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
253
254 /* set out-FIFO threshold to 0x100 */
255 writew(0x100, chan + ADMA_FIFO_OUT);
256
257 /* set CPB count */
258 writew(1, chan + ADMA_CPB_COUNT);
259
260 /* read/discard ADMA status */
261 readb(chan + ADMA_STATUS);
262 }
263
264 static inline void adma_enter_reg_mode(struct ata_port *ap)
265 {
266 void __iomem *chan = ADMA_PORT_REGS(ap);
267
268 writew(aPIOMD4, chan + ADMA_CONTROL);
269 readb(chan + ADMA_STATUS); /* flush */
270 }
271
272 static void adma_freeze(struct ata_port *ap)
273 {
274 void __iomem *chan = ADMA_PORT_REGS(ap);
275
276 /* mask/clear ATA interrupts */
277 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
278 ata_check_status(ap);
279
280 /* reset ADMA to idle state */
281 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
282 udelay(2);
283 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
284 udelay(2);
285 }
286
287 static void adma_thaw(struct ata_port *ap)
288 {
289 adma_reinit_engine(ap);
290 }
291
292 static int adma_prereset(struct ata_link *link, unsigned long deadline)
293 {
294 struct ata_port *ap = link->ap;
295 struct adma_port_priv *pp = ap->private_data;
296
297 if (pp->state != adma_state_idle) /* healthy paranoia */
298 pp->state = adma_state_mmio;
299 adma_reinit_engine(ap);
300
301 return ata_std_prereset(link, deadline);
302 }
303
304 static void adma_error_handler(struct ata_port *ap)
305 {
306 ata_do_eh(ap, adma_prereset, ata_std_softreset, NULL,
307 ata_std_postreset);
308 }
309
310 static int adma_fill_sg(struct ata_queued_cmd *qc)
311 {
312 struct scatterlist *sg;
313 struct ata_port *ap = qc->ap;
314 struct adma_port_priv *pp = ap->private_data;
315 u8 *buf = pp->pkt, *last_buf = NULL;
316 int i = (2 + buf[3]) * 8;
317 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
318 unsigned int si;
319
320 for_each_sg(qc->sg, sg, qc->n_elem, si) {
321 u32 addr;
322 u32 len;
323
324 addr = (u32)sg_dma_address(sg);
325 *(__le32 *)(buf + i) = cpu_to_le32(addr);
326 i += 4;
327
328 len = sg_dma_len(sg) >> 3;
329 *(__le32 *)(buf + i) = cpu_to_le32(len);
330 i += 4;
331
332 last_buf = &buf[i];
333 buf[i++] = pFLAGS;
334 buf[i++] = qc->dev->dma_mode & 0xf;
335 buf[i++] = 0; /* pPKLW */
336 buf[i++] = 0; /* reserved */
337
338 *(__le32 *)(buf + i) =
339 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
340 i += 4;
341
342 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
343 (unsigned long)addr, len);
344 }
345
346 if (likely(last_buf))
347 *last_buf |= pEND;
348
349 return i;
350 }
351
352 static void adma_qc_prep(struct ata_queued_cmd *qc)
353 {
354 struct adma_port_priv *pp = qc->ap->private_data;
355 u8 *buf = pp->pkt;
356 u32 pkt_dma = (u32)pp->pkt_dma;
357 int i = 0;
358
359 VPRINTK("ENTER\n");
360
361 adma_enter_reg_mode(qc->ap);
362 if (qc->tf.protocol != ATA_PROT_DMA) {
363 ata_qc_prep(qc);
364 return;
365 }
366
367 buf[i++] = 0; /* Response flags */
368 buf[i++] = 0; /* reserved */
369 buf[i++] = cVLD | cDAT | cIEN;
370 i++; /* cLEN, gets filled in below */
371
372 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
373 i += 4; /* cNCPB */
374 i += 4; /* cPRD, gets filled in below */
375
376 buf[i++] = 0; /* reserved */
377 buf[i++] = 0; /* reserved */
378 buf[i++] = 0; /* reserved */
379 buf[i++] = 0; /* reserved */
380
381 /* ATA registers; must be a multiple of 4 */
382 buf[i++] = qc->tf.device;
383 buf[i++] = ADMA_REGS_DEVICE;
384 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
385 buf[i++] = qc->tf.hob_nsect;
386 buf[i++] = ADMA_REGS_SECTOR_COUNT;
387 buf[i++] = qc->tf.hob_lbal;
388 buf[i++] = ADMA_REGS_LBA_LOW;
389 buf[i++] = qc->tf.hob_lbam;
390 buf[i++] = ADMA_REGS_LBA_MID;
391 buf[i++] = qc->tf.hob_lbah;
392 buf[i++] = ADMA_REGS_LBA_HIGH;
393 }
394 buf[i++] = qc->tf.nsect;
395 buf[i++] = ADMA_REGS_SECTOR_COUNT;
396 buf[i++] = qc->tf.lbal;
397 buf[i++] = ADMA_REGS_LBA_LOW;
398 buf[i++] = qc->tf.lbam;
399 buf[i++] = ADMA_REGS_LBA_MID;
400 buf[i++] = qc->tf.lbah;
401 buf[i++] = ADMA_REGS_LBA_HIGH;
402 buf[i++] = 0;
403 buf[i++] = ADMA_REGS_CONTROL;
404 buf[i++] = rIGN;
405 buf[i++] = 0;
406 buf[i++] = qc->tf.command;
407 buf[i++] = ADMA_REGS_COMMAND | rEND;
408
409 buf[3] = (i >> 3) - 2; /* cLEN */
410 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
411
412 i = adma_fill_sg(qc);
413 wmb(); /* flush PRDs and pkt to memory */
414 #if 0
415 /* dump out CPB + PRDs for debug */
416 {
417 int j, len = 0;
418 static char obuf[2048];
419 for (j = 0; j < i; ++j) {
420 len += sprintf(obuf+len, "%02x ", buf[j]);
421 if ((j & 7) == 7) {
422 printk("%s\n", obuf);
423 len = 0;
424 }
425 }
426 if (len)
427 printk("%s\n", obuf);
428 }
429 #endif
430 }
431
432 static inline void adma_packet_start(struct ata_queued_cmd *qc)
433 {
434 struct ata_port *ap = qc->ap;
435 void __iomem *chan = ADMA_PORT_REGS(ap);
436
437 VPRINTK("ENTER, ap %p\n", ap);
438
439 /* fire up the ADMA engine */
440 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
441 }
442
443 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
444 {
445 struct adma_port_priv *pp = qc->ap->private_data;
446
447 switch (qc->tf.protocol) {
448 case ATA_PROT_DMA:
449 pp->state = adma_state_pkt;
450 adma_packet_start(qc);
451 return 0;
452
453 case ATAPI_PROT_DMA:
454 BUG();
455 break;
456
457 default:
458 break;
459 }
460
461 pp->state = adma_state_mmio;
462 return ata_qc_issue_prot(qc);
463 }
464
465 static inline unsigned int adma_intr_pkt(struct ata_host *host)
466 {
467 unsigned int handled = 0, port_no;
468
469 for (port_no = 0; port_no < host->n_ports; ++port_no) {
470 struct ata_port *ap = host->ports[port_no];
471 struct adma_port_priv *pp;
472 struct ata_queued_cmd *qc;
473 void __iomem *chan = ADMA_PORT_REGS(ap);
474 u8 status = readb(chan + ADMA_STATUS);
475
476 if (status == 0)
477 continue;
478 handled = 1;
479 adma_enter_reg_mode(ap);
480 if (ap->flags & ATA_FLAG_DISABLED)
481 continue;
482 pp = ap->private_data;
483 if (!pp || pp->state != adma_state_pkt)
484 continue;
485 qc = ata_qc_from_tag(ap, ap->link.active_tag);
486 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
487 if (status & aPERR)
488 qc->err_mask |= AC_ERR_HOST_BUS;
489 else if ((status & (aPSD | aUIRQ)))
490 qc->err_mask |= AC_ERR_OTHER;
491
492 if (pp->pkt[0] & cATERR)
493 qc->err_mask |= AC_ERR_DEV;
494 else if (pp->pkt[0] != cDONE)
495 qc->err_mask |= AC_ERR_OTHER;
496
497 if (!qc->err_mask)
498 ata_qc_complete(qc);
499 else {
500 struct ata_eh_info *ehi = &ap->link.eh_info;
501 ata_ehi_clear_desc(ehi);
502 ata_ehi_push_desc(ehi,
503 "ADMA-status 0x%02X", status);
504 ata_ehi_push_desc(ehi,
505 "pkt[0] 0x%02X", pp->pkt[0]);
506
507 if (qc->err_mask == AC_ERR_DEV)
508 ata_port_abort(ap);
509 else
510 ata_port_freeze(ap);
511 }
512 }
513 }
514 return handled;
515 }
516
517 static inline unsigned int adma_intr_mmio(struct ata_host *host)
518 {
519 unsigned int handled = 0, port_no;
520
521 for (port_no = 0; port_no < host->n_ports; ++port_no) {
522 struct ata_port *ap;
523 ap = host->ports[port_no];
524 if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
525 struct ata_queued_cmd *qc;
526 struct adma_port_priv *pp = ap->private_data;
527 if (!pp || pp->state != adma_state_mmio)
528 continue;
529 qc = ata_qc_from_tag(ap, ap->link.active_tag);
530 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
531
532 /* check main status, clearing INTRQ */
533 u8 status = ata_check_status(ap);
534 if ((status & ATA_BUSY))
535 continue;
536 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
537 ap->print_id, qc->tf.protocol, status);
538
539 /* complete taskfile transaction */
540 pp->state = adma_state_idle;
541 qc->err_mask |= ac_err_mask(status);
542 if (!qc->err_mask)
543 ata_qc_complete(qc);
544 else {
545 struct ata_eh_info *ehi =
546 &ap->link.eh_info;
547 ata_ehi_clear_desc(ehi);
548 ata_ehi_push_desc(ehi,
549 "status 0x%02X", status);
550
551 if (qc->err_mask == AC_ERR_DEV)
552 ata_port_abort(ap);
553 else
554 ata_port_freeze(ap);
555 }
556 handled = 1;
557 }
558 }
559 }
560 return handled;
561 }
562
563 static irqreturn_t adma_intr(int irq, void *dev_instance)
564 {
565 struct ata_host *host = dev_instance;
566 unsigned int handled = 0;
567
568 VPRINTK("ENTER\n");
569
570 spin_lock(&host->lock);
571 handled = adma_intr_pkt(host) | adma_intr_mmio(host);
572 spin_unlock(&host->lock);
573
574 VPRINTK("EXIT\n");
575
576 return IRQ_RETVAL(handled);
577 }
578
579 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
580 {
581 port->cmd_addr =
582 port->data_addr = base + 0x000;
583 port->error_addr =
584 port->feature_addr = base + 0x004;
585 port->nsect_addr = base + 0x008;
586 port->lbal_addr = base + 0x00c;
587 port->lbam_addr = base + 0x010;
588 port->lbah_addr = base + 0x014;
589 port->device_addr = base + 0x018;
590 port->status_addr =
591 port->command_addr = base + 0x01c;
592 port->altstatus_addr =
593 port->ctl_addr = base + 0x038;
594 }
595
596 static int adma_port_start(struct ata_port *ap)
597 {
598 struct device *dev = ap->host->dev;
599 struct adma_port_priv *pp;
600 int rc;
601
602 rc = ata_port_start(ap);
603 if (rc)
604 return rc;
605 adma_enter_reg_mode(ap);
606 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
607 if (!pp)
608 return -ENOMEM;
609 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
610 GFP_KERNEL);
611 if (!pp->pkt)
612 return -ENOMEM;
613 /* paranoia? */
614 if ((pp->pkt_dma & 7) != 0) {
615 printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
616 (u32)pp->pkt_dma);
617 return -ENOMEM;
618 }
619 memset(pp->pkt, 0, ADMA_PKT_BYTES);
620 ap->private_data = pp;
621 adma_reinit_engine(ap);
622 return 0;
623 }
624
625 static void adma_port_stop(struct ata_port *ap)
626 {
627 adma_reset_engine(ap);
628 }
629
630 static void adma_host_stop(struct ata_host *host)
631 {
632 unsigned int port_no;
633
634 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
635 adma_reset_engine(host->ports[port_no]);
636 }
637
638 static void adma_host_init(struct ata_host *host, unsigned int chip_id)
639 {
640 unsigned int port_no;
641
642 /* enable/lock aGO operation */
643 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
644
645 /* reset the ADMA logic */
646 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
647 adma_reset_engine(host->ports[port_no]);
648 }
649
650 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
651 {
652 int rc;
653
654 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
655 if (rc) {
656 dev_printk(KERN_ERR, &pdev->dev,
657 "32-bit DMA enable failed\n");
658 return rc;
659 }
660 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
661 if (rc) {
662 dev_printk(KERN_ERR, &pdev->dev,
663 "32-bit consistent DMA enable failed\n");
664 return rc;
665 }
666 return 0;
667 }
668
669 static int adma_ata_init_one(struct pci_dev *pdev,
670 const struct pci_device_id *ent)
671 {
672 static int printed_version;
673 unsigned int board_idx = (unsigned int) ent->driver_data;
674 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
675 struct ata_host *host;
676 void __iomem *mmio_base;
677 int rc, port_no;
678
679 if (!printed_version++)
680 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
681
682 /* alloc host */
683 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
684 if (!host)
685 return -ENOMEM;
686
687 /* acquire resources and fill host */
688 rc = pcim_enable_device(pdev);
689 if (rc)
690 return rc;
691
692 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
693 return -ENODEV;
694
695 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
696 if (rc)
697 return rc;
698 host->iomap = pcim_iomap_table(pdev);
699 mmio_base = host->iomap[ADMA_MMIO_BAR];
700
701 rc = adma_set_dma_masks(pdev, mmio_base);
702 if (rc)
703 return rc;
704
705 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
706 struct ata_port *ap = host->ports[port_no];
707 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
708 unsigned int offset = port_base - mmio_base;
709
710 adma_ata_setup_port(&ap->ioaddr, port_base);
711
712 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
713 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
714 }
715
716 /* initialize adapter */
717 adma_host_init(host, board_idx);
718
719 pci_set_master(pdev);
720 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
721 &adma_ata_sht);
722 }
723
724 static int __init adma_ata_init(void)
725 {
726 return pci_register_driver(&adma_ata_pci_driver);
727 }
728
729 static void __exit adma_ata_exit(void)
730 {
731 pci_unregister_driver(&adma_ata_pci_driver);
732 }
733
734 MODULE_AUTHOR("Mark Lord");
735 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
736 MODULE_LICENSE("GPL");
737 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
738 MODULE_VERSION(DRV_VERSION);
739
740 module_init(adma_ata_init);
741 module_exit(adma_ata_exit);
Linux kernel - Deliverables
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