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libata: implement and use SHT initializers
[deliverable/linux.git] / drivers / ata / pdc_adma.c
1 /*
2 * pdc_adma.c - Pacific Digital Corporation ADMA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Mark Lord
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 *
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
29 *
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
45
46 #define DRV_NAME "pdc_adma"
47 #define DRV_VERSION "1.0"
48
49 /* macro to calculate base address for ATA regs */
50 #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
51
52 /* macro to calculate base address for ADMA regs */
53 #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
54
55 /* macro to obtain addresses from ata_port */
56 #define ADMA_PORT_REGS(ap) \
57 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
58
59 enum {
60 ADMA_MMIO_BAR = 4,
61
62 ADMA_PORTS = 2,
63 ADMA_CPB_BYTES = 40,
64 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
65 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
66
67 ADMA_DMA_BOUNDARY = 0xffffffff,
68
69 /* global register offsets */
70 ADMA_MODE_LOCK = 0x00c7,
71
72 /* per-channel register offsets */
73 ADMA_CONTROL = 0x0000, /* ADMA control */
74 ADMA_STATUS = 0x0002, /* ADMA status */
75 ADMA_CPB_COUNT = 0x0004, /* CPB count */
76 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
77 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
78 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
79 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
80 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
81
82 /* ADMA_CONTROL register bits */
83 aNIEN = (1 << 8), /* irq mask: 1==masked */
84 aGO = (1 << 7), /* packet trigger ("Go!") */
85 aRSTADM = (1 << 5), /* ADMA logic reset */
86 aPIOMD4 = 0x0003, /* PIO mode 4 */
87
88 /* ADMA_STATUS register bits */
89 aPSD = (1 << 6),
90 aUIRQ = (1 << 4),
91 aPERR = (1 << 0),
92
93 /* CPB bits */
94 cDONE = (1 << 0),
95 cATERR = (1 << 3),
96
97 cVLD = (1 << 0),
98 cDAT = (1 << 2),
99 cIEN = (1 << 3),
100
101 /* PRD bits */
102 pORD = (1 << 4),
103 pDIRO = (1 << 5),
104 pEND = (1 << 7),
105
106 /* ATA register flags */
107 rIGN = (1 << 5),
108 rEND = (1 << 7),
109
110 /* ATA register addresses */
111 ADMA_REGS_CONTROL = 0x0e,
112 ADMA_REGS_SECTOR_COUNT = 0x12,
113 ADMA_REGS_LBA_LOW = 0x13,
114 ADMA_REGS_LBA_MID = 0x14,
115 ADMA_REGS_LBA_HIGH = 0x15,
116 ADMA_REGS_DEVICE = 0x16,
117 ADMA_REGS_COMMAND = 0x17,
118
119 /* PCI device IDs */
120 board_1841_idx = 0, /* ADMA 2-port controller */
121 };
122
123 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
124
125 struct adma_port_priv {
126 u8 *pkt;
127 dma_addr_t pkt_dma;
128 adma_state_t state;
129 };
130
131 static int adma_ata_init_one(struct pci_dev *pdev,
132 const struct pci_device_id *ent);
133 static int adma_port_start(struct ata_port *ap);
134 static void adma_host_stop(struct ata_host *host);
135 static void adma_port_stop(struct ata_port *ap);
136 static void adma_qc_prep(struct ata_queued_cmd *qc);
137 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
138 static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
139 static void adma_bmdma_stop(struct ata_queued_cmd *qc);
140 static u8 adma_bmdma_status(struct ata_port *ap);
141 static void adma_freeze(struct ata_port *ap);
142 static void adma_thaw(struct ata_port *ap);
143 static void adma_error_handler(struct ata_port *ap);
144
145 static struct scsi_host_template adma_ata_sht = {
146 ATA_BASE_SHT(DRV_NAME),
147 .sg_tablesize = LIBATA_MAX_PRD,
148 .dma_boundary = ADMA_DMA_BOUNDARY,
149 };
150
151 static const struct ata_port_operations adma_ata_ops = {
152 .tf_load = ata_tf_load,
153 .tf_read = ata_tf_read,
154 .exec_command = ata_exec_command,
155 .check_status = ata_check_status,
156 .dev_select = ata_std_dev_select,
157 .check_atapi_dma = adma_check_atapi_dma,
158 .data_xfer = ata_data_xfer,
159 .qc_prep = adma_qc_prep,
160 .qc_issue = adma_qc_issue,
161 .freeze = adma_freeze,
162 .thaw = adma_thaw,
163 .error_handler = adma_error_handler,
164 .irq_clear = ata_noop_irq_clear,
165 .irq_on = ata_irq_on,
166 .port_start = adma_port_start,
167 .port_stop = adma_port_stop,
168 .host_stop = adma_host_stop,
169 .bmdma_stop = adma_bmdma_stop,
170 .bmdma_status = adma_bmdma_status,
171 };
172
173 static struct ata_port_info adma_port_info[] = {
174 /* board_1841_idx */
175 {
176 .flags = ATA_FLAG_SLAVE_POSS |
177 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
178 ATA_FLAG_PIO_POLLING,
179 .pio_mask = 0x10, /* pio4 */
180 .udma_mask = ATA_UDMA4,
181 .port_ops = &adma_ata_ops,
182 },
183 };
184
185 static const struct pci_device_id adma_ata_pci_tbl[] = {
186 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
187
188 { } /* terminate list */
189 };
190
191 static struct pci_driver adma_ata_pci_driver = {
192 .name = DRV_NAME,
193 .id_table = adma_ata_pci_tbl,
194 .probe = adma_ata_init_one,
195 .remove = ata_pci_remove_one,
196 };
197
198 static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
199 {
200 return 1; /* ATAPI DMA not yet supported */
201 }
202
203 static void adma_bmdma_stop(struct ata_queued_cmd *qc)
204 {
205 /* nothing */
206 }
207
208 static u8 adma_bmdma_status(struct ata_port *ap)
209 {
210 return 0;
211 }
212
213 static void adma_reset_engine(struct ata_port *ap)
214 {
215 void __iomem *chan = ADMA_PORT_REGS(ap);
216
217 /* reset ADMA to idle state */
218 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
219 udelay(2);
220 writew(aPIOMD4, chan + ADMA_CONTROL);
221 udelay(2);
222 }
223
224 static void adma_reinit_engine(struct ata_port *ap)
225 {
226 struct adma_port_priv *pp = ap->private_data;
227 void __iomem *chan = ADMA_PORT_REGS(ap);
228
229 /* mask/clear ATA interrupts */
230 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
231 ata_check_status(ap);
232
233 /* reset the ADMA engine */
234 adma_reset_engine(ap);
235
236 /* set in-FIFO threshold to 0x100 */
237 writew(0x100, chan + ADMA_FIFO_IN);
238
239 /* set CPB pointer */
240 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
241
242 /* set out-FIFO threshold to 0x100 */
243 writew(0x100, chan + ADMA_FIFO_OUT);
244
245 /* set CPB count */
246 writew(1, chan + ADMA_CPB_COUNT);
247
248 /* read/discard ADMA status */
249 readb(chan + ADMA_STATUS);
250 }
251
252 static inline void adma_enter_reg_mode(struct ata_port *ap)
253 {
254 void __iomem *chan = ADMA_PORT_REGS(ap);
255
256 writew(aPIOMD4, chan + ADMA_CONTROL);
257 readb(chan + ADMA_STATUS); /* flush */
258 }
259
260 static void adma_freeze(struct ata_port *ap)
261 {
262 void __iomem *chan = ADMA_PORT_REGS(ap);
263
264 /* mask/clear ATA interrupts */
265 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
266 ata_check_status(ap);
267
268 /* reset ADMA to idle state */
269 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
270 udelay(2);
271 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
272 udelay(2);
273 }
274
275 static void adma_thaw(struct ata_port *ap)
276 {
277 adma_reinit_engine(ap);
278 }
279
280 static int adma_prereset(struct ata_link *link, unsigned long deadline)
281 {
282 struct ata_port *ap = link->ap;
283 struct adma_port_priv *pp = ap->private_data;
284
285 if (pp->state != adma_state_idle) /* healthy paranoia */
286 pp->state = adma_state_mmio;
287 adma_reinit_engine(ap);
288
289 return ata_std_prereset(link, deadline);
290 }
291
292 static void adma_error_handler(struct ata_port *ap)
293 {
294 ata_do_eh(ap, adma_prereset, ata_std_softreset, NULL,
295 ata_std_postreset);
296 }
297
298 static int adma_fill_sg(struct ata_queued_cmd *qc)
299 {
300 struct scatterlist *sg;
301 struct ata_port *ap = qc->ap;
302 struct adma_port_priv *pp = ap->private_data;
303 u8 *buf = pp->pkt, *last_buf = NULL;
304 int i = (2 + buf[3]) * 8;
305 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
306 unsigned int si;
307
308 for_each_sg(qc->sg, sg, qc->n_elem, si) {
309 u32 addr;
310 u32 len;
311
312 addr = (u32)sg_dma_address(sg);
313 *(__le32 *)(buf + i) = cpu_to_le32(addr);
314 i += 4;
315
316 len = sg_dma_len(sg) >> 3;
317 *(__le32 *)(buf + i) = cpu_to_le32(len);
318 i += 4;
319
320 last_buf = &buf[i];
321 buf[i++] = pFLAGS;
322 buf[i++] = qc->dev->dma_mode & 0xf;
323 buf[i++] = 0; /* pPKLW */
324 buf[i++] = 0; /* reserved */
325
326 *(__le32 *)(buf + i) =
327 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
328 i += 4;
329
330 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
331 (unsigned long)addr, len);
332 }
333
334 if (likely(last_buf))
335 *last_buf |= pEND;
336
337 return i;
338 }
339
340 static void adma_qc_prep(struct ata_queued_cmd *qc)
341 {
342 struct adma_port_priv *pp = qc->ap->private_data;
343 u8 *buf = pp->pkt;
344 u32 pkt_dma = (u32)pp->pkt_dma;
345 int i = 0;
346
347 VPRINTK("ENTER\n");
348
349 adma_enter_reg_mode(qc->ap);
350 if (qc->tf.protocol != ATA_PROT_DMA) {
351 ata_qc_prep(qc);
352 return;
353 }
354
355 buf[i++] = 0; /* Response flags */
356 buf[i++] = 0; /* reserved */
357 buf[i++] = cVLD | cDAT | cIEN;
358 i++; /* cLEN, gets filled in below */
359
360 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
361 i += 4; /* cNCPB */
362 i += 4; /* cPRD, gets filled in below */
363
364 buf[i++] = 0; /* reserved */
365 buf[i++] = 0; /* reserved */
366 buf[i++] = 0; /* reserved */
367 buf[i++] = 0; /* reserved */
368
369 /* ATA registers; must be a multiple of 4 */
370 buf[i++] = qc->tf.device;
371 buf[i++] = ADMA_REGS_DEVICE;
372 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
373 buf[i++] = qc->tf.hob_nsect;
374 buf[i++] = ADMA_REGS_SECTOR_COUNT;
375 buf[i++] = qc->tf.hob_lbal;
376 buf[i++] = ADMA_REGS_LBA_LOW;
377 buf[i++] = qc->tf.hob_lbam;
378 buf[i++] = ADMA_REGS_LBA_MID;
379 buf[i++] = qc->tf.hob_lbah;
380 buf[i++] = ADMA_REGS_LBA_HIGH;
381 }
382 buf[i++] = qc->tf.nsect;
383 buf[i++] = ADMA_REGS_SECTOR_COUNT;
384 buf[i++] = qc->tf.lbal;
385 buf[i++] = ADMA_REGS_LBA_LOW;
386 buf[i++] = qc->tf.lbam;
387 buf[i++] = ADMA_REGS_LBA_MID;
388 buf[i++] = qc->tf.lbah;
389 buf[i++] = ADMA_REGS_LBA_HIGH;
390 buf[i++] = 0;
391 buf[i++] = ADMA_REGS_CONTROL;
392 buf[i++] = rIGN;
393 buf[i++] = 0;
394 buf[i++] = qc->tf.command;
395 buf[i++] = ADMA_REGS_COMMAND | rEND;
396
397 buf[3] = (i >> 3) - 2; /* cLEN */
398 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
399
400 i = adma_fill_sg(qc);
401 wmb(); /* flush PRDs and pkt to memory */
402 #if 0
403 /* dump out CPB + PRDs for debug */
404 {
405 int j, len = 0;
406 static char obuf[2048];
407 for (j = 0; j < i; ++j) {
408 len += sprintf(obuf+len, "%02x ", buf[j]);
409 if ((j & 7) == 7) {
410 printk("%s\n", obuf);
411 len = 0;
412 }
413 }
414 if (len)
415 printk("%s\n", obuf);
416 }
417 #endif
418 }
419
420 static inline void adma_packet_start(struct ata_queued_cmd *qc)
421 {
422 struct ata_port *ap = qc->ap;
423 void __iomem *chan = ADMA_PORT_REGS(ap);
424
425 VPRINTK("ENTER, ap %p\n", ap);
426
427 /* fire up the ADMA engine */
428 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
429 }
430
431 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
432 {
433 struct adma_port_priv *pp = qc->ap->private_data;
434
435 switch (qc->tf.protocol) {
436 case ATA_PROT_DMA:
437 pp->state = adma_state_pkt;
438 adma_packet_start(qc);
439 return 0;
440
441 case ATAPI_PROT_DMA:
442 BUG();
443 break;
444
445 default:
446 break;
447 }
448
449 pp->state = adma_state_mmio;
450 return ata_qc_issue_prot(qc);
451 }
452
453 static inline unsigned int adma_intr_pkt(struct ata_host *host)
454 {
455 unsigned int handled = 0, port_no;
456
457 for (port_no = 0; port_no < host->n_ports; ++port_no) {
458 struct ata_port *ap = host->ports[port_no];
459 struct adma_port_priv *pp;
460 struct ata_queued_cmd *qc;
461 void __iomem *chan = ADMA_PORT_REGS(ap);
462 u8 status = readb(chan + ADMA_STATUS);
463
464 if (status == 0)
465 continue;
466 handled = 1;
467 adma_enter_reg_mode(ap);
468 if (ap->flags & ATA_FLAG_DISABLED)
469 continue;
470 pp = ap->private_data;
471 if (!pp || pp->state != adma_state_pkt)
472 continue;
473 qc = ata_qc_from_tag(ap, ap->link.active_tag);
474 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
475 if (status & aPERR)
476 qc->err_mask |= AC_ERR_HOST_BUS;
477 else if ((status & (aPSD | aUIRQ)))
478 qc->err_mask |= AC_ERR_OTHER;
479
480 if (pp->pkt[0] & cATERR)
481 qc->err_mask |= AC_ERR_DEV;
482 else if (pp->pkt[0] != cDONE)
483 qc->err_mask |= AC_ERR_OTHER;
484
485 if (!qc->err_mask)
486 ata_qc_complete(qc);
487 else {
488 struct ata_eh_info *ehi = &ap->link.eh_info;
489 ata_ehi_clear_desc(ehi);
490 ata_ehi_push_desc(ehi,
491 "ADMA-status 0x%02X", status);
492 ata_ehi_push_desc(ehi,
493 "pkt[0] 0x%02X", pp->pkt[0]);
494
495 if (qc->err_mask == AC_ERR_DEV)
496 ata_port_abort(ap);
497 else
498 ata_port_freeze(ap);
499 }
500 }
501 }
502 return handled;
503 }
504
505 static inline unsigned int adma_intr_mmio(struct ata_host *host)
506 {
507 unsigned int handled = 0, port_no;
508
509 for (port_no = 0; port_no < host->n_ports; ++port_no) {
510 struct ata_port *ap;
511 ap = host->ports[port_no];
512 if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
513 struct ata_queued_cmd *qc;
514 struct adma_port_priv *pp = ap->private_data;
515 if (!pp || pp->state != adma_state_mmio)
516 continue;
517 qc = ata_qc_from_tag(ap, ap->link.active_tag);
518 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
519
520 /* check main status, clearing INTRQ */
521 u8 status = ata_check_status(ap);
522 if ((status & ATA_BUSY))
523 continue;
524 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
525 ap->print_id, qc->tf.protocol, status);
526
527 /* complete taskfile transaction */
528 pp->state = adma_state_idle;
529 qc->err_mask |= ac_err_mask(status);
530 if (!qc->err_mask)
531 ata_qc_complete(qc);
532 else {
533 struct ata_eh_info *ehi =
534 &ap->link.eh_info;
535 ata_ehi_clear_desc(ehi);
536 ata_ehi_push_desc(ehi,
537 "status 0x%02X", status);
538
539 if (qc->err_mask == AC_ERR_DEV)
540 ata_port_abort(ap);
541 else
542 ata_port_freeze(ap);
543 }
544 handled = 1;
545 }
546 }
547 }
548 return handled;
549 }
550
551 static irqreturn_t adma_intr(int irq, void *dev_instance)
552 {
553 struct ata_host *host = dev_instance;
554 unsigned int handled = 0;
555
556 VPRINTK("ENTER\n");
557
558 spin_lock(&host->lock);
559 handled = adma_intr_pkt(host) | adma_intr_mmio(host);
560 spin_unlock(&host->lock);
561
562 VPRINTK("EXIT\n");
563
564 return IRQ_RETVAL(handled);
565 }
566
567 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
568 {
569 port->cmd_addr =
570 port->data_addr = base + 0x000;
571 port->error_addr =
572 port->feature_addr = base + 0x004;
573 port->nsect_addr = base + 0x008;
574 port->lbal_addr = base + 0x00c;
575 port->lbam_addr = base + 0x010;
576 port->lbah_addr = base + 0x014;
577 port->device_addr = base + 0x018;
578 port->status_addr =
579 port->command_addr = base + 0x01c;
580 port->altstatus_addr =
581 port->ctl_addr = base + 0x038;
582 }
583
584 static int adma_port_start(struct ata_port *ap)
585 {
586 struct device *dev = ap->host->dev;
587 struct adma_port_priv *pp;
588 int rc;
589
590 rc = ata_port_start(ap);
591 if (rc)
592 return rc;
593 adma_enter_reg_mode(ap);
594 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
595 if (!pp)
596 return -ENOMEM;
597 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
598 GFP_KERNEL);
599 if (!pp->pkt)
600 return -ENOMEM;
601 /* paranoia? */
602 if ((pp->pkt_dma & 7) != 0) {
603 printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
604 (u32)pp->pkt_dma);
605 return -ENOMEM;
606 }
607 memset(pp->pkt, 0, ADMA_PKT_BYTES);
608 ap->private_data = pp;
609 adma_reinit_engine(ap);
610 return 0;
611 }
612
613 static void adma_port_stop(struct ata_port *ap)
614 {
615 adma_reset_engine(ap);
616 }
617
618 static void adma_host_stop(struct ata_host *host)
619 {
620 unsigned int port_no;
621
622 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
623 adma_reset_engine(host->ports[port_no]);
624 }
625
626 static void adma_host_init(struct ata_host *host, unsigned int chip_id)
627 {
628 unsigned int port_no;
629
630 /* enable/lock aGO operation */
631 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
632
633 /* reset the ADMA logic */
634 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
635 adma_reset_engine(host->ports[port_no]);
636 }
637
638 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
639 {
640 int rc;
641
642 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
643 if (rc) {
644 dev_printk(KERN_ERR, &pdev->dev,
645 "32-bit DMA enable failed\n");
646 return rc;
647 }
648 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
649 if (rc) {
650 dev_printk(KERN_ERR, &pdev->dev,
651 "32-bit consistent DMA enable failed\n");
652 return rc;
653 }
654 return 0;
655 }
656
657 static int adma_ata_init_one(struct pci_dev *pdev,
658 const struct pci_device_id *ent)
659 {
660 static int printed_version;
661 unsigned int board_idx = (unsigned int) ent->driver_data;
662 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
663 struct ata_host *host;
664 void __iomem *mmio_base;
665 int rc, port_no;
666
667 if (!printed_version++)
668 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
669
670 /* alloc host */
671 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
672 if (!host)
673 return -ENOMEM;
674
675 /* acquire resources and fill host */
676 rc = pcim_enable_device(pdev);
677 if (rc)
678 return rc;
679
680 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
681 return -ENODEV;
682
683 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
684 if (rc)
685 return rc;
686 host->iomap = pcim_iomap_table(pdev);
687 mmio_base = host->iomap[ADMA_MMIO_BAR];
688
689 rc = adma_set_dma_masks(pdev, mmio_base);
690 if (rc)
691 return rc;
692
693 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
694 struct ata_port *ap = host->ports[port_no];
695 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
696 unsigned int offset = port_base - mmio_base;
697
698 adma_ata_setup_port(&ap->ioaddr, port_base);
699
700 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
701 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
702 }
703
704 /* initialize adapter */
705 adma_host_init(host, board_idx);
706
707 pci_set_master(pdev);
708 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
709 &adma_ata_sht);
710 }
711
712 static int __init adma_ata_init(void)
713 {
714 return pci_register_driver(&adma_ata_pci_driver);
715 }
716
717 static void __exit adma_ata_exit(void)
718 {
719 pci_unregister_driver(&adma_ata_pci_driver);
720 }
721
722 MODULE_AUTHOR("Mark Lord");
723 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
724 MODULE_LICENSE("GPL");
725 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
726 MODULE_VERSION(DRV_VERSION);
727
728 module_init(adma_ata_init);
729 module_exit(adma_ata_exit);
Linux kernel - Deliverables
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