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Merge branch 'devicetree/next' of git://git.secretlab.ca/git/linux-2.6
[deliverable/linux.git] / drivers / ata / sata_fsl.c
1 /*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22
23 #include <scsi/scsi_host.h>
24 #include <scsi/scsi_cmnd.h>
25 #include <linux/libata.h>
26 #include <asm/io.h>
27 #include <linux/of_platform.h>
28
29 /* Controller information */
30 enum {
31 SATA_FSL_QUEUE_DEPTH = 16,
32 SATA_FSL_MAX_PRD = 63,
33 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
34 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
35
36 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
37 ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN),
38
39 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
40 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
41 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
42
43 /*
44 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
45 * chained indirect PRDEs upto a max count of 63.
46 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
47 * be setup as an indirect descriptor, pointing to it's next
48 * (contiguous) PRDE. Though chained indirect PRDE arrays are
49 * supported,it will be more efficient to use a direct PRDT and
50 * a single chain/link to indirect PRDE array/PRDT.
51 */
52
53 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
54 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
55 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
56 SATA_FSL_CMD_DESC_RSRVD = 16,
57
58 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
59 SATA_FSL_CMD_DESC_SFIS_SZ +
60 SATA_FSL_CMD_DESC_ACMD_SZ +
61 SATA_FSL_CMD_DESC_RSRVD +
62 SATA_FSL_MAX_PRD * 16),
63
64 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
65 (SATA_FSL_CMD_DESC_CFIS_SZ +
66 SATA_FSL_CMD_DESC_SFIS_SZ +
67 SATA_FSL_CMD_DESC_ACMD_SZ +
68 SATA_FSL_CMD_DESC_RSRVD),
69
70 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
71 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
72 SATA_FSL_CMD_DESC_AR_SZ),
73
74 /*
75 * MPC8315 has two SATA controllers, SATA1 & SATA2
76 * (one port per controller)
77 * MPC837x has 2/4 controllers, one port per controller
78 */
79
80 SATA_FSL_MAX_PORTS = 1,
81
82 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
83 };
84
85 /*
86 * Host Controller command register set - per port
87 */
88 enum {
89 CQ = 0,
90 CA = 8,
91 CC = 0x10,
92 CE = 0x18,
93 DE = 0x20,
94 CHBA = 0x24,
95 HSTATUS = 0x28,
96 HCONTROL = 0x2C,
97 CQPMP = 0x30,
98 SIGNATURE = 0x34,
99 ICC = 0x38,
100
101 /*
102 * Host Status Register (HStatus) bitdefs
103 */
104 ONLINE = (1 << 31),
105 GOING_OFFLINE = (1 << 30),
106 BIST_ERR = (1 << 29),
107
108 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
109 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
110 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
111 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
112 FATAL_ERR_DATA_OVERRUN = (1 << 12),
113 FATAL_ERR_CRC_ERR_TX = (1 << 11),
114 FATAL_ERR_CRC_ERR_RX = (1 << 10),
115 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
116 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
117
118 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
119 FATAL_ERR_PARITY_ERR_TX |
120 FATAL_ERR_PARITY_ERR_RX |
121 FATAL_ERR_DATA_UNDERRUN |
122 FATAL_ERR_DATA_OVERRUN |
123 FATAL_ERR_CRC_ERR_TX |
124 FATAL_ERR_CRC_ERR_RX |
125 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
126
127 INT_ON_FATAL_ERR = (1 << 5),
128 INT_ON_PHYRDY_CHG = (1 << 4),
129
130 INT_ON_SIGNATURE_UPDATE = (1 << 3),
131 INT_ON_SNOTIFY_UPDATE = (1 << 2),
132 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
133 INT_ON_CMD_COMPLETE = 1,
134
135 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
136 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
137
138 /*
139 * Host Control Register (HControl) bitdefs
140 */
141 HCONTROL_ONLINE_PHY_RST = (1 << 31),
142 HCONTROL_FORCE_OFFLINE = (1 << 30),
143 HCONTROL_PARITY_PROT_MOD = (1 << 14),
144 HCONTROL_DPATH_PARITY = (1 << 12),
145 HCONTROL_SNOOP_ENABLE = (1 << 10),
146 HCONTROL_PMP_ATTACHED = (1 << 9),
147 HCONTROL_COPYOUT_STATFIS = (1 << 8),
148 IE_ON_FATAL_ERR = (1 << 5),
149 IE_ON_PHYRDY_CHG = (1 << 4),
150 IE_ON_SIGNATURE_UPDATE = (1 << 3),
151 IE_ON_SNOTIFY_UPDATE = (1 << 2),
152 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
153 IE_ON_CMD_COMPLETE = 1,
154
155 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
156 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
157 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
158
159 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
160 DATA_SNOOP_ENABLE = (1 << 22),
161 };
162
163 /*
164 * SATA Superset Registers
165 */
166 enum {
167 SSTATUS = 0,
168 SERROR = 4,
169 SCONTROL = 8,
170 SNOTIFY = 0xC,
171 };
172
173 /*
174 * Control Status Register Set
175 */
176 enum {
177 TRANSCFG = 0,
178 TRANSSTATUS = 4,
179 LINKCFG = 8,
180 LINKCFG1 = 0xC,
181 LINKCFG2 = 0x10,
182 LINKSTATUS = 0x14,
183 LINKSTATUS1 = 0x18,
184 PHYCTRLCFG = 0x1C,
185 COMMANDSTAT = 0x20,
186 };
187
188 /* TRANSCFG (transport-layer) configuration control */
189 enum {
190 TRANSCFG_RX_WATER_MARK = (1 << 4),
191 };
192
193 /* PHY (link-layer) configuration control */
194 enum {
195 PHY_BIST_ENABLE = 0x01,
196 };
197
198 /*
199 * Command Header Table entry, i.e, command slot
200 * 4 Dwords per command slot, command header size == 64 Dwords.
201 */
202 struct cmdhdr_tbl_entry {
203 u32 cda;
204 u32 prde_fis_len;
205 u32 ttl;
206 u32 desc_info;
207 };
208
209 /*
210 * Description information bitdefs
211 */
212 enum {
213 CMD_DESC_RES = (1 << 11),
214 VENDOR_SPECIFIC_BIST = (1 << 10),
215 CMD_DESC_SNOOP_ENABLE = (1 << 9),
216 FPDMA_QUEUED_CMD = (1 << 8),
217 SRST_CMD = (1 << 7),
218 BIST = (1 << 6),
219 ATAPI_CMD = (1 << 5),
220 };
221
222 /*
223 * Command Descriptor
224 */
225 struct command_desc {
226 u8 cfis[8 * 4];
227 u8 sfis[8 * 4];
228 u8 acmd[4 * 4];
229 u8 fill[4 * 4];
230 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
231 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
232 };
233
234 /*
235 * Physical region table descriptor(PRD)
236 */
237
238 struct prde {
239 u32 dba;
240 u8 fill[2 * 4];
241 u32 ddc_and_ext;
242 };
243
244 /*
245 * ata_port private data
246 * This is our per-port instance data.
247 */
248 struct sata_fsl_port_priv {
249 struct cmdhdr_tbl_entry *cmdslot;
250 dma_addr_t cmdslot_paddr;
251 struct command_desc *cmdentry;
252 dma_addr_t cmdentry_paddr;
253 };
254
255 /*
256 * ata_port->host_set private data
257 */
258 struct sata_fsl_host_priv {
259 void __iomem *hcr_base;
260 void __iomem *ssr_base;
261 void __iomem *csr_base;
262 int irq;
263 };
264
265 static inline unsigned int sata_fsl_tag(unsigned int tag,
266 void __iomem *hcr_base)
267 {
268 /* We let libATA core do actual (queue) tag allocation */
269
270 /* all non NCQ/queued commands should have tag#0 */
271 if (ata_tag_internal(tag)) {
272 DPRINTK("mapping internal cmds to tag#0\n");
273 return 0;
274 }
275
276 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
277 DPRINTK("tag %d invalid : out of range\n", tag);
278 return 0;
279 }
280
281 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
282 DPRINTK("tag %d invalid : in use!!\n", tag);
283 return 0;
284 }
285
286 return tag;
287 }
288
289 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
290 unsigned int tag, u32 desc_info,
291 u32 data_xfer_len, u8 num_prde,
292 u8 fis_len)
293 {
294 dma_addr_t cmd_descriptor_address;
295
296 cmd_descriptor_address = pp->cmdentry_paddr +
297 tag * SATA_FSL_CMD_DESC_SIZE;
298
299 /* NOTE: both data_xfer_len & fis_len are Dword counts */
300
301 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
302 pp->cmdslot[tag].prde_fis_len =
303 cpu_to_le32((num_prde << 16) | (fis_len << 2));
304 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
305 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
306
307 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
308 pp->cmdslot[tag].cda,
309 pp->cmdslot[tag].prde_fis_len,
310 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
311
312 }
313
314 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
315 u32 *ttl, dma_addr_t cmd_desc_paddr)
316 {
317 struct scatterlist *sg;
318 unsigned int num_prde = 0;
319 u32 ttl_dwords = 0;
320
321 /*
322 * NOTE : direct & indirect prdt's are contiguously allocated
323 */
324 struct prde *prd = (struct prde *)&((struct command_desc *)
325 cmd_desc)->prdt;
326
327 struct prde *prd_ptr_to_indirect_ext = NULL;
328 unsigned indirect_ext_segment_sz = 0;
329 dma_addr_t indirect_ext_segment_paddr;
330 unsigned int si;
331
332 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
333
334 indirect_ext_segment_paddr = cmd_desc_paddr +
335 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
336
337 for_each_sg(qc->sg, sg, qc->n_elem, si) {
338 dma_addr_t sg_addr = sg_dma_address(sg);
339 u32 sg_len = sg_dma_len(sg);
340
341 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
342 (unsigned long long)sg_addr, sg_len);
343
344 /* warn if each s/g element is not dword aligned */
345 if (sg_addr & 0x03)
346 ata_port_printk(qc->ap, KERN_ERR,
347 "s/g addr unaligned : 0x%llx\n",
348 (unsigned long long)sg_addr);
349 if (sg_len & 0x03)
350 ata_port_printk(qc->ap, KERN_ERR,
351 "s/g len unaligned : 0x%x\n", sg_len);
352
353 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
354 sg_next(sg) != NULL) {
355 VPRINTK("setting indirect prde\n");
356 prd_ptr_to_indirect_ext = prd;
357 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
358 indirect_ext_segment_sz = 0;
359 ++prd;
360 ++num_prde;
361 }
362
363 ttl_dwords += sg_len;
364 prd->dba = cpu_to_le32(sg_addr);
365 prd->ddc_and_ext =
366 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03));
367
368 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
369 ttl_dwords, prd->dba, prd->ddc_and_ext);
370
371 ++num_prde;
372 ++prd;
373 if (prd_ptr_to_indirect_ext)
374 indirect_ext_segment_sz += sg_len;
375 }
376
377 if (prd_ptr_to_indirect_ext) {
378 /* set indirect extension flag along with indirect ext. size */
379 prd_ptr_to_indirect_ext->ddc_and_ext =
380 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
381 DATA_SNOOP_ENABLE |
382 (indirect_ext_segment_sz & ~0x03)));
383 }
384
385 *ttl = ttl_dwords;
386 return num_prde;
387 }
388
389 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
390 {
391 struct ata_port *ap = qc->ap;
392 struct sata_fsl_port_priv *pp = ap->private_data;
393 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
394 void __iomem *hcr_base = host_priv->hcr_base;
395 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
396 struct command_desc *cd;
397 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
398 u32 num_prde = 0;
399 u32 ttl_dwords = 0;
400 dma_addr_t cd_paddr;
401
402 cd = (struct command_desc *)pp->cmdentry + tag;
403 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
404
405 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
406
407 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
408 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
409
410 if (qc->tf.protocol == ATA_PROT_NCQ) {
411 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
412 cd->cfis[3], cd->cfis[11]);
413 }
414
415 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
416 if (ata_is_atapi(qc->tf.protocol)) {
417 desc_info |= ATAPI_CMD;
418 memset((void *)&cd->acmd, 0, 32);
419 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
420 }
421
422 if (qc->flags & ATA_QCFLAG_DMAMAP)
423 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
424 &ttl_dwords, cd_paddr);
425
426 if (qc->tf.protocol == ATA_PROT_NCQ)
427 desc_info |= FPDMA_QUEUED_CMD;
428
429 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
430 num_prde, 5);
431
432 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
433 desc_info, ttl_dwords, num_prde);
434 }
435
436 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
437 {
438 struct ata_port *ap = qc->ap;
439 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
440 void __iomem *hcr_base = host_priv->hcr_base;
441 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
442
443 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
444 ioread32(CQ + hcr_base),
445 ioread32(CA + hcr_base),
446 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
447
448 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
449
450 /* Simply queue command to the controller/device */
451 iowrite32(1 << tag, CQ + hcr_base);
452
453 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
454 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
455
456 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
457 ioread32(CE + hcr_base),
458 ioread32(DE + hcr_base),
459 ioread32(CC + hcr_base),
460 ioread32(COMMANDSTAT + host_priv->csr_base));
461
462 return 0;
463 }
464
465 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
466 {
467 struct sata_fsl_port_priv *pp = qc->ap->private_data;
468 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
469 void __iomem *hcr_base = host_priv->hcr_base;
470 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
471 struct command_desc *cd;
472
473 cd = pp->cmdentry + tag;
474
475 ata_tf_from_fis(cd->sfis, &qc->result_tf);
476 return true;
477 }
478
479 static int sata_fsl_scr_write(struct ata_link *link,
480 unsigned int sc_reg_in, u32 val)
481 {
482 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
483 void __iomem *ssr_base = host_priv->ssr_base;
484 unsigned int sc_reg;
485
486 switch (sc_reg_in) {
487 case SCR_STATUS:
488 case SCR_ERROR:
489 case SCR_CONTROL:
490 case SCR_ACTIVE:
491 sc_reg = sc_reg_in;
492 break;
493 default:
494 return -EINVAL;
495 }
496
497 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
498
499 iowrite32(val, ssr_base + (sc_reg * 4));
500 return 0;
501 }
502
503 static int sata_fsl_scr_read(struct ata_link *link,
504 unsigned int sc_reg_in, u32 *val)
505 {
506 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
507 void __iomem *ssr_base = host_priv->ssr_base;
508 unsigned int sc_reg;
509
510 switch (sc_reg_in) {
511 case SCR_STATUS:
512 case SCR_ERROR:
513 case SCR_CONTROL:
514 case SCR_ACTIVE:
515 sc_reg = sc_reg_in;
516 break;
517 default:
518 return -EINVAL;
519 }
520
521 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
522
523 *val = ioread32(ssr_base + (sc_reg * 4));
524 return 0;
525 }
526
527 static void sata_fsl_freeze(struct ata_port *ap)
528 {
529 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
530 void __iomem *hcr_base = host_priv->hcr_base;
531 u32 temp;
532
533 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
534 ioread32(CQ + hcr_base),
535 ioread32(CA + hcr_base),
536 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
537 VPRINTK("CmdStat = 0x%x\n",
538 ioread32(host_priv->csr_base + COMMANDSTAT));
539
540 /* disable interrupts on the controller/port */
541 temp = ioread32(hcr_base + HCONTROL);
542 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
543
544 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
545 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
546 }
547
548 static void sata_fsl_thaw(struct ata_port *ap)
549 {
550 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
551 void __iomem *hcr_base = host_priv->hcr_base;
552 u32 temp;
553
554 /* ack. any pending IRQs for this controller/port */
555 temp = ioread32(hcr_base + HSTATUS);
556
557 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
558
559 if (temp & 0x3F)
560 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
561
562 /* enable interrupts on the controller/port */
563 temp = ioread32(hcr_base + HCONTROL);
564 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
565
566 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
567 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
568 }
569
570 static void sata_fsl_pmp_attach(struct ata_port *ap)
571 {
572 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
573 void __iomem *hcr_base = host_priv->hcr_base;
574 u32 temp;
575
576 temp = ioread32(hcr_base + HCONTROL);
577 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
578 }
579
580 static void sata_fsl_pmp_detach(struct ata_port *ap)
581 {
582 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
583 void __iomem *hcr_base = host_priv->hcr_base;
584 u32 temp;
585
586 temp = ioread32(hcr_base + HCONTROL);
587 temp &= ~HCONTROL_PMP_ATTACHED;
588 iowrite32(temp, hcr_base + HCONTROL);
589
590 /* enable interrupts on the controller/port */
591 temp = ioread32(hcr_base + HCONTROL);
592 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
593
594 }
595
596 static int sata_fsl_port_start(struct ata_port *ap)
597 {
598 struct device *dev = ap->host->dev;
599 struct sata_fsl_port_priv *pp;
600 void *mem;
601 dma_addr_t mem_dma;
602 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
603 void __iomem *hcr_base = host_priv->hcr_base;
604 u32 temp;
605
606 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
607 if (!pp)
608 return -ENOMEM;
609
610 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
611 GFP_KERNEL);
612 if (!mem) {
613 kfree(pp);
614 return -ENOMEM;
615 }
616 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
617
618 pp->cmdslot = mem;
619 pp->cmdslot_paddr = mem_dma;
620
621 mem += SATA_FSL_CMD_SLOT_SIZE;
622 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
623
624 pp->cmdentry = mem;
625 pp->cmdentry_paddr = mem_dma;
626
627 ap->private_data = pp;
628
629 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
630 pp->cmdslot_paddr, pp->cmdentry_paddr);
631
632 /* Now, update the CHBA register in host controller cmd register set */
633 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
634
635 /*
636 * Now, we can bring the controller on-line & also initiate
637 * the COMINIT sequence, we simply return here and the boot-probing
638 * & device discovery process is re-initiated by libATA using a
639 * Softreset EH (dummy) session. Hence, boot probing and device
640 * discovey will be part of sata_fsl_softreset() callback.
641 */
642
643 temp = ioread32(hcr_base + HCONTROL);
644 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
645
646 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
647 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
648 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
649
650 #ifdef CONFIG_MPC8315_DS
651 /*
652 * Workaround for 8315DS board 3gbps link-up issue,
653 * currently limit SATA port to GEN1 speed
654 */
655 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
656 temp &= ~(0xF << 4);
657 temp |= (0x1 << 4);
658 sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp);
659
660 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
661 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n",
662 temp);
663 #endif
664
665 return 0;
666 }
667
668 static void sata_fsl_port_stop(struct ata_port *ap)
669 {
670 struct device *dev = ap->host->dev;
671 struct sata_fsl_port_priv *pp = ap->private_data;
672 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
673 void __iomem *hcr_base = host_priv->hcr_base;
674 u32 temp;
675
676 /*
677 * Force host controller to go off-line, aborting current operations
678 */
679 temp = ioread32(hcr_base + HCONTROL);
680 temp &= ~HCONTROL_ONLINE_PHY_RST;
681 temp |= HCONTROL_FORCE_OFFLINE;
682 iowrite32(temp, hcr_base + HCONTROL);
683
684 /* Poll for controller to go offline - should happen immediately */
685 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
686
687 ap->private_data = NULL;
688 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
689 pp->cmdslot, pp->cmdslot_paddr);
690
691 kfree(pp);
692 }
693
694 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
695 {
696 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
697 void __iomem *hcr_base = host_priv->hcr_base;
698 struct ata_taskfile tf;
699 u32 temp;
700
701 temp = ioread32(hcr_base + SIGNATURE);
702
703 VPRINTK("raw sig = 0x%x\n", temp);
704 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
705 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
706
707 tf.lbah = (temp >> 24) & 0xff;
708 tf.lbam = (temp >> 16) & 0xff;
709 tf.lbal = (temp >> 8) & 0xff;
710 tf.nsect = temp & 0xff;
711
712 return ata_dev_classify(&tf);
713 }
714
715 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
716 unsigned long deadline)
717 {
718 struct ata_port *ap = link->ap;
719 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
720 void __iomem *hcr_base = host_priv->hcr_base;
721 u32 temp;
722 int i = 0;
723 unsigned long start_jiffies;
724
725 DPRINTK("in xx_hardreset\n");
726
727 try_offline_again:
728 /*
729 * Force host controller to go off-line, aborting current operations
730 */
731 temp = ioread32(hcr_base + HCONTROL);
732 temp &= ~HCONTROL_ONLINE_PHY_RST;
733 iowrite32(temp, hcr_base + HCONTROL);
734
735 /* Poll for controller to go offline */
736 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
737 1, 500);
738
739 if (temp & ONLINE) {
740 ata_port_printk(ap, KERN_ERR,
741 "Hardreset failed, not off-lined %d\n", i);
742
743 /*
744 * Try to offline controller atleast twice
745 */
746 i++;
747 if (i == 2)
748 goto err;
749 else
750 goto try_offline_again;
751 }
752
753 DPRINTK("hardreset, controller off-lined\n");
754 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
755 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
756
757 /*
758 * PHY reset should remain asserted for atleast 1ms
759 */
760 ata_msleep(ap, 1);
761
762 /*
763 * Now, bring the host controller online again, this can take time
764 * as PHY reset and communication establishment, 1st D2H FIS and
765 * device signature update is done, on safe side assume 500ms
766 * NOTE : Host online status may be indicated immediately!!
767 */
768
769 temp = ioread32(hcr_base + HCONTROL);
770 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
771 temp |= HCONTROL_PMP_ATTACHED;
772 iowrite32(temp, hcr_base + HCONTROL);
773
774 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
775
776 if (!(temp & ONLINE)) {
777 ata_port_printk(ap, KERN_ERR,
778 "Hardreset failed, not on-lined\n");
779 goto err;
780 }
781
782 DPRINTK("hardreset, controller off-lined & on-lined\n");
783 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
784 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
785
786 /*
787 * First, wait for the PHYRDY change to occur before waiting for
788 * the signature, and also verify if SStatus indicates device
789 * presence
790 */
791
792 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
793 if ((!(temp & 0x10)) || ata_link_offline(link)) {
794 ata_port_printk(ap, KERN_WARNING,
795 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
796 ioread32(hcr_base + HSTATUS));
797 *class = ATA_DEV_NONE;
798 return 0;
799 }
800
801 /*
802 * Wait for the first D2H from device,i.e,signature update notification
803 */
804 start_jiffies = jiffies;
805 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
806 500, jiffies_to_msecs(deadline - start_jiffies));
807
808 if ((temp & 0xFF) != 0x18) {
809 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
810 *class = ATA_DEV_NONE;
811 goto do_followup_srst;
812 } else {
813 ata_port_printk(ap, KERN_INFO,
814 "Signature Update detected @ %d msecs\n",
815 jiffies_to_msecs(jiffies - start_jiffies));
816 *class = sata_fsl_dev_classify(ap);
817 return 0;
818 }
819
820 do_followup_srst:
821 /*
822 * request libATA to perform follow-up softreset
823 */
824 return -EAGAIN;
825
826 err:
827 return -EIO;
828 }
829
830 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
831 unsigned long deadline)
832 {
833 struct ata_port *ap = link->ap;
834 struct sata_fsl_port_priv *pp = ap->private_data;
835 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
836 void __iomem *hcr_base = host_priv->hcr_base;
837 int pmp = sata_srst_pmp(link);
838 u32 temp;
839 struct ata_taskfile tf;
840 u8 *cfis;
841 u32 Serror;
842
843 DPRINTK("in xx_softreset\n");
844
845 if (ata_link_offline(link)) {
846 DPRINTK("PHY reports no device\n");
847 *class = ATA_DEV_NONE;
848 return 0;
849 }
850
851 /*
852 * Send a device reset (SRST) explicitly on command slot #0
853 * Check : will the command queue (reg) be cleared during offlining ??
854 * Also we will be online only if Phy commn. has been established
855 * and device presence has been detected, therefore if we have
856 * reached here, we can send a command to the target device
857 */
858
859 DPRINTK("Sending SRST/device reset\n");
860
861 ata_tf_init(link->device, &tf);
862 cfis = (u8 *) &pp->cmdentry->cfis;
863
864 /* device reset/SRST is a control register update FIS, uses tag0 */
865 sata_fsl_setup_cmd_hdr_entry(pp, 0,
866 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
867
868 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
869 ata_tf_to_fis(&tf, pmp, 0, cfis);
870
871 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
872 cfis[0], cfis[1], cfis[2], cfis[3]);
873
874 /*
875 * Queue SRST command to the controller/device, ensure that no
876 * other commands are active on the controller/device
877 */
878
879 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
880 ioread32(CQ + hcr_base),
881 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
882
883 iowrite32(0xFFFF, CC + hcr_base);
884 if (pmp != SATA_PMP_CTRL_PORT)
885 iowrite32(pmp, CQPMP + hcr_base);
886 iowrite32(1, CQ + hcr_base);
887
888 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
889 if (temp & 0x1) {
890 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
891
892 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
893 ioread32(CQ + hcr_base),
894 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
895
896 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
897
898 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
899 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
900 DPRINTK("Serror = 0x%x\n", Serror);
901 goto err;
902 }
903
904 ata_msleep(ap, 1);
905
906 /*
907 * SATA device enters reset state after receving a Control register
908 * FIS with SRST bit asserted and it awaits another H2D Control reg.
909 * FIS with SRST bit cleared, then the device does internal diags &
910 * initialization, followed by indicating it's initialization status
911 * using ATA signature D2H register FIS to the host controller.
912 */
913
914 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
915 0, 0, 5);
916
917 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
918 ata_tf_to_fis(&tf, pmp, 0, cfis);
919
920 if (pmp != SATA_PMP_CTRL_PORT)
921 iowrite32(pmp, CQPMP + hcr_base);
922 iowrite32(1, CQ + hcr_base);
923 ata_msleep(ap, 150); /* ?? */
924
925 /*
926 * The above command would have signalled an interrupt on command
927 * complete, which needs special handling, by clearing the Nth
928 * command bit of the CCreg
929 */
930 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
931
932 DPRINTK("SATA FSL : Now checking device signature\n");
933
934 *class = ATA_DEV_NONE;
935
936 /* Verify if SStatus indicates device presence */
937 if (ata_link_online(link)) {
938 /*
939 * if we are here, device presence has been detected,
940 * 1st D2H FIS would have been received, but sfis in
941 * command desc. is not updated, but signature register
942 * would have been updated
943 */
944
945 *class = sata_fsl_dev_classify(ap);
946
947 DPRINTK("class = %d\n", *class);
948 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
949 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
950 }
951
952 return 0;
953
954 err:
955 return -EIO;
956 }
957
958 static void sata_fsl_error_handler(struct ata_port *ap)
959 {
960
961 DPRINTK("in xx_error_handler\n");
962 sata_pmp_error_handler(ap);
963
964 }
965
966 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
967 {
968 if (qc->flags & ATA_QCFLAG_FAILED)
969 qc->err_mask |= AC_ERR_OTHER;
970
971 if (qc->err_mask) {
972 /* make DMA engine forget about the failed command */
973
974 }
975 }
976
977 static void sata_fsl_error_intr(struct ata_port *ap)
978 {
979 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
980 void __iomem *hcr_base = host_priv->hcr_base;
981 u32 hstatus, dereg=0, cereg = 0, SError = 0;
982 unsigned int err_mask = 0, action = 0;
983 int freeze = 0, abort=0;
984 struct ata_link *link = NULL;
985 struct ata_queued_cmd *qc = NULL;
986 struct ata_eh_info *ehi;
987
988 hstatus = ioread32(hcr_base + HSTATUS);
989 cereg = ioread32(hcr_base + CE);
990
991 /* first, analyze and record host port events */
992 link = &ap->link;
993 ehi = &link->eh_info;
994 ata_ehi_clear_desc(ehi);
995
996 /*
997 * Handle & Clear SError
998 */
999
1000 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1001 if (unlikely(SError & 0xFFFF0000))
1002 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
1003
1004 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1005 hstatus, cereg, ioread32(hcr_base + DE), SError);
1006
1007 /* handle fatal errors */
1008 if (hstatus & FATAL_ERROR_DECODE) {
1009 ehi->err_mask |= AC_ERR_ATA_BUS;
1010 ehi->action |= ATA_EH_SOFTRESET;
1011
1012 freeze = 1;
1013 }
1014
1015 /* Handle SDB FIS receive & notify update */
1016 if (hstatus & INT_ON_SNOTIFY_UPDATE)
1017 sata_async_notification(ap);
1018
1019 /* Handle PHYRDY change notification */
1020 if (hstatus & INT_ON_PHYRDY_CHG) {
1021 DPRINTK("SATA FSL: PHYRDY change indication\n");
1022
1023 /* Setup a soft-reset EH action */
1024 ata_ehi_hotplugged(ehi);
1025 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1026 freeze = 1;
1027 }
1028
1029 /* handle single device errors */
1030 if (cereg) {
1031 /*
1032 * clear the command error, also clears queue to the device
1033 * in error, and we can (re)issue commands to this device.
1034 * When a device is in error all commands queued into the
1035 * host controller and at the device are considered aborted
1036 * and the queue for that device is stopped. Now, after
1037 * clearing the device error, we can issue commands to the
1038 * device to interrogate it to find the source of the error.
1039 */
1040 abort = 1;
1041
1042 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1043 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1044
1045 /* find out the offending link and qc */
1046 if (ap->nr_pmp_links) {
1047 unsigned int dev_num;
1048
1049 dereg = ioread32(hcr_base + DE);
1050 iowrite32(dereg, hcr_base + DE);
1051 iowrite32(cereg, hcr_base + CE);
1052
1053 dev_num = ffs(dereg) - 1;
1054 if (dev_num < ap->nr_pmp_links && dereg != 0) {
1055 link = &ap->pmp_link[dev_num];
1056 ehi = &link->eh_info;
1057 qc = ata_qc_from_tag(ap, link->active_tag);
1058 /*
1059 * We should consider this as non fatal error,
1060 * and TF must be updated as done below.
1061 */
1062
1063 err_mask |= AC_ERR_DEV;
1064
1065 } else {
1066 err_mask |= AC_ERR_HSM;
1067 action |= ATA_EH_HARDRESET;
1068 freeze = 1;
1069 }
1070 } else {
1071 dereg = ioread32(hcr_base + DE);
1072 iowrite32(dereg, hcr_base + DE);
1073 iowrite32(cereg, hcr_base + CE);
1074
1075 qc = ata_qc_from_tag(ap, link->active_tag);
1076 /*
1077 * We should consider this as non fatal error,
1078 * and TF must be updated as done below.
1079 */
1080 err_mask |= AC_ERR_DEV;
1081 }
1082 }
1083
1084 /* record error info */
1085 if (qc)
1086 qc->err_mask |= err_mask;
1087 else
1088 ehi->err_mask |= err_mask;
1089
1090 ehi->action |= action;
1091
1092 /* freeze or abort */
1093 if (freeze)
1094 ata_port_freeze(ap);
1095 else if (abort) {
1096 if (qc)
1097 ata_link_abort(qc->dev->link);
1098 else
1099 ata_port_abort(ap);
1100 }
1101 }
1102
1103 static void sata_fsl_host_intr(struct ata_port *ap)
1104 {
1105 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1106 void __iomem *hcr_base = host_priv->hcr_base;
1107 u32 hstatus, done_mask = 0;
1108 struct ata_queued_cmd *qc;
1109 u32 SError;
1110
1111 hstatus = ioread32(hcr_base + HSTATUS);
1112
1113 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1114
1115 if (unlikely(SError & 0xFFFF0000)) {
1116 DPRINTK("serror @host_intr : 0x%x\n", SError);
1117 sata_fsl_error_intr(ap);
1118 }
1119
1120 if (unlikely(hstatus & INT_ON_ERROR)) {
1121 DPRINTK("error interrupt!!\n");
1122 sata_fsl_error_intr(ap);
1123 return;
1124 }
1125
1126 /* Read command completed register */
1127 done_mask = ioread32(hcr_base + CC);
1128
1129 VPRINTK("Status of all queues :\n");
1130 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1131 done_mask,
1132 ioread32(hcr_base + CA),
1133 ioread32(hcr_base + CE),
1134 ioread32(hcr_base + CQ),
1135 ap->qc_active);
1136
1137 if (done_mask & ap->qc_active) {
1138 int i;
1139 /* clear CC bit, this will also complete the interrupt */
1140 iowrite32(done_mask, hcr_base + CC);
1141
1142 DPRINTK("Status of all queues :\n");
1143 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1144 done_mask, ioread32(hcr_base + CA),
1145 ioread32(hcr_base + CE));
1146
1147 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1148 if (done_mask & (1 << i))
1149 DPRINTK
1150 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1151 i, ioread32(hcr_base + CC),
1152 ioread32(hcr_base + CA));
1153 }
1154 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
1155 return;
1156
1157 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) {
1158 iowrite32(1, hcr_base + CC);
1159 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1160
1161 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1162 ioread32(hcr_base + CC));
1163
1164 if (qc) {
1165 ata_qc_complete(qc);
1166 }
1167 } else {
1168 /* Spurious Interrupt!! */
1169 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1170 ioread32(hcr_base + CC));
1171 iowrite32(done_mask, hcr_base + CC);
1172 return;
1173 }
1174 }
1175
1176 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1177 {
1178 struct ata_host *host = dev_instance;
1179 struct sata_fsl_host_priv *host_priv = host->private_data;
1180 void __iomem *hcr_base = host_priv->hcr_base;
1181 u32 interrupt_enables;
1182 unsigned handled = 0;
1183 struct ata_port *ap;
1184
1185 /* ack. any pending IRQs for this controller/port */
1186 interrupt_enables = ioread32(hcr_base + HSTATUS);
1187 interrupt_enables &= 0x3F;
1188
1189 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1190
1191 if (!interrupt_enables)
1192 return IRQ_NONE;
1193
1194 spin_lock(&host->lock);
1195
1196 /* Assuming one port per host controller */
1197
1198 ap = host->ports[0];
1199 if (ap) {
1200 sata_fsl_host_intr(ap);
1201 } else {
1202 dev_printk(KERN_WARNING, host->dev,
1203 "interrupt on disabled port 0\n");
1204 }
1205
1206 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1207 handled = 1;
1208
1209 spin_unlock(&host->lock);
1210
1211 return IRQ_RETVAL(handled);
1212 }
1213
1214 /*
1215 * Multiple ports are represented by multiple SATA controllers with
1216 * one port per controller
1217 */
1218 static int sata_fsl_init_controller(struct ata_host *host)
1219 {
1220 struct sata_fsl_host_priv *host_priv = host->private_data;
1221 void __iomem *hcr_base = host_priv->hcr_base;
1222 u32 temp;
1223
1224 /*
1225 * NOTE : We cannot bring the controller online before setting
1226 * the CHBA, hence main controller initialization is done as
1227 * part of the port_start() callback
1228 */
1229
1230 /* ack. any pending IRQs for this controller/port */
1231 temp = ioread32(hcr_base + HSTATUS);
1232 if (temp & 0x3F)
1233 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1234
1235 /* Keep interrupts disabled on the controller */
1236 temp = ioread32(hcr_base + HCONTROL);
1237 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1238
1239 /* Disable interrupt coalescing control(icc), for the moment */
1240 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1241 iowrite32(0x01000000, hcr_base + ICC);
1242
1243 /* clear error registers, SError is cleared by libATA */
1244 iowrite32(0x00000FFFF, hcr_base + CE);
1245 iowrite32(0x00000FFFF, hcr_base + DE);
1246
1247 /*
1248 * host controller will be brought on-line, during xx_port_start()
1249 * callback, that should also initiate the OOB, COMINIT sequence
1250 */
1251
1252 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1253 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1254
1255 return 0;
1256 }
1257
1258 /*
1259 * scsi mid-layer and libata interface structures
1260 */
1261 static struct scsi_host_template sata_fsl_sht = {
1262 ATA_NCQ_SHT("sata_fsl"),
1263 .can_queue = SATA_FSL_QUEUE_DEPTH,
1264 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1265 .dma_boundary = ATA_DMA_BOUNDARY,
1266 };
1267
1268 static struct ata_port_operations sata_fsl_ops = {
1269 .inherits = &sata_pmp_port_ops,
1270
1271 .qc_defer = ata_std_qc_defer,
1272 .qc_prep = sata_fsl_qc_prep,
1273 .qc_issue = sata_fsl_qc_issue,
1274 .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1275
1276 .scr_read = sata_fsl_scr_read,
1277 .scr_write = sata_fsl_scr_write,
1278
1279 .freeze = sata_fsl_freeze,
1280 .thaw = sata_fsl_thaw,
1281 .softreset = sata_fsl_softreset,
1282 .hardreset = sata_fsl_hardreset,
1283 .pmp_softreset = sata_fsl_softreset,
1284 .error_handler = sata_fsl_error_handler,
1285 .post_internal_cmd = sata_fsl_post_internal_cmd,
1286
1287 .port_start = sata_fsl_port_start,
1288 .port_stop = sata_fsl_port_stop,
1289
1290 .pmp_attach = sata_fsl_pmp_attach,
1291 .pmp_detach = sata_fsl_pmp_detach,
1292 };
1293
1294 static const struct ata_port_info sata_fsl_port_info[] = {
1295 {
1296 .flags = SATA_FSL_HOST_FLAGS,
1297 .pio_mask = ATA_PIO4,
1298 .udma_mask = ATA_UDMA6,
1299 .port_ops = &sata_fsl_ops,
1300 },
1301 };
1302
1303 static int sata_fsl_probe(struct platform_device *ofdev)
1304 {
1305 int retval = -ENXIO;
1306 void __iomem *hcr_base = NULL;
1307 void __iomem *ssr_base = NULL;
1308 void __iomem *csr_base = NULL;
1309 struct sata_fsl_host_priv *host_priv = NULL;
1310 int irq;
1311 struct ata_host *host;
1312 u32 temp;
1313
1314 struct ata_port_info pi = sata_fsl_port_info[0];
1315 const struct ata_port_info *ppi[] = { &pi, NULL };
1316
1317 dev_printk(KERN_INFO, &ofdev->dev,
1318 "Sata FSL Platform/CSB Driver init\n");
1319
1320 hcr_base = of_iomap(ofdev->dev.of_node, 0);
1321 if (!hcr_base)
1322 goto error_exit_with_cleanup;
1323
1324 ssr_base = hcr_base + 0x100;
1325 csr_base = hcr_base + 0x140;
1326
1327 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1328 temp = ioread32(csr_base + TRANSCFG);
1329 temp = temp & 0xffffffe0;
1330 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1331 }
1332
1333 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1334 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1335 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1336
1337 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1338 if (!host_priv)
1339 goto error_exit_with_cleanup;
1340
1341 host_priv->hcr_base = hcr_base;
1342 host_priv->ssr_base = ssr_base;
1343 host_priv->csr_base = csr_base;
1344
1345 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1346 if (irq < 0) {
1347 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n");
1348 goto error_exit_with_cleanup;
1349 }
1350 host_priv->irq = irq;
1351
1352 /* allocate host structure */
1353 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1354
1355 /* host->iomap is not used currently */
1356 host->private_data = host_priv;
1357
1358 /* initialize host controller */
1359 sata_fsl_init_controller(host);
1360
1361 /*
1362 * Now, register with libATA core, this will also initiate the
1363 * device discovery process, invoking our port_start() handler &
1364 * error_handler() to execute a dummy Softreset EH session
1365 */
1366 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1367 &sata_fsl_sht);
1368
1369 dev_set_drvdata(&ofdev->dev, host);
1370
1371 return 0;
1372
1373 error_exit_with_cleanup:
1374
1375 if (hcr_base)
1376 iounmap(hcr_base);
1377 if (host_priv)
1378 kfree(host_priv);
1379
1380 return retval;
1381 }
1382
1383 static int sata_fsl_remove(struct platform_device *ofdev)
1384 {
1385 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
1386 struct sata_fsl_host_priv *host_priv = host->private_data;
1387
1388 ata_host_detach(host);
1389
1390 dev_set_drvdata(&ofdev->dev, NULL);
1391
1392 irq_dispose_mapping(host_priv->irq);
1393 iounmap(host_priv->hcr_base);
1394 kfree(host_priv);
1395
1396 return 0;
1397 }
1398
1399 #ifdef CONFIG_PM
1400 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1401 {
1402 struct ata_host *host = dev_get_drvdata(&op->dev);
1403 return ata_host_suspend(host, state);
1404 }
1405
1406 static int sata_fsl_resume(struct platform_device *op)
1407 {
1408 struct ata_host *host = dev_get_drvdata(&op->dev);
1409 struct sata_fsl_host_priv *host_priv = host->private_data;
1410 int ret;
1411 void __iomem *hcr_base = host_priv->hcr_base;
1412 struct ata_port *ap = host->ports[0];
1413 struct sata_fsl_port_priv *pp = ap->private_data;
1414
1415 ret = sata_fsl_init_controller(host);
1416 if (ret) {
1417 dev_printk(KERN_ERR, &op->dev,
1418 "Error initialize hardware\n");
1419 return ret;
1420 }
1421
1422 /* Recovery the CHBA register in host controller cmd register set */
1423 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1424
1425 ata_host_resume(host);
1426 return 0;
1427 }
1428 #endif
1429
1430 static struct of_device_id fsl_sata_match[] = {
1431 {
1432 .compatible = "fsl,pq-sata",
1433 },
1434 {},
1435 };
1436
1437 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1438
1439 static struct platform_driver fsl_sata_driver = {
1440 .driver = {
1441 .name = "fsl-sata",
1442 .owner = THIS_MODULE,
1443 .of_match_table = fsl_sata_match,
1444 },
1445 .probe = sata_fsl_probe,
1446 .remove = sata_fsl_remove,
1447 #ifdef CONFIG_PM
1448 .suspend = sata_fsl_suspend,
1449 .resume = sata_fsl_resume,
1450 #endif
1451 };
1452
1453 static int __init sata_fsl_init(void)
1454 {
1455 platform_driver_register(&fsl_sata_driver);
1456 return 0;
1457 }
1458
1459 static void __exit sata_fsl_exit(void)
1460 {
1461 platform_driver_unregister(&fsl_sata_driver);
1462 }
1463
1464 MODULE_LICENSE("GPL");
1465 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1466 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1467 MODULE_VERSION("1.10");
1468
1469 module_init(sata_fsl_init);
1470 module_exit(sata_fsl_exit);
Linux kernel - Deliverables
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