2 * sata_inic162x.c - Driver for Initio 162x SATA controllers
4 * Copyright 2006 SUSE Linux Products GmbH
5 * Copyright 2006 Tejun Heo <teheo@novell.com>
7 * This file is released under GPL v2.
9 * This controller is eccentric and easily locks up if something isn't
10 * right. Documentation is available at initio's website but it only
11 * documents registers (not programming model).
15 * - ATAPI read works but burning doesn't. This thing is really
16 * peculiar about ATAPI and I couldn't figure out how ATAPI PIO and
17 * ATAPI DMA WRITE should be programmed. If you've got a clue, be
19 * - Both STR and STD work.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <scsi/scsi_host.h>
26 #include <linux/libata.h>
27 #include <linux/blkdev.h>
28 #include <scsi/scsi_device.h>
30 #define DRV_NAME "sata_inic162x"
31 #define DRV_VERSION "0.3"
45 /* registers for ATA TF operation */
52 PORT_PRD_XFERLEN
= 0x10,
60 HCTL_IRQOFF
= (1 << 8), /* global IRQ off */
61 HCTL_PWRDWN
= (1 << 13), /* power down PHYs */
62 HCTL_SOFTRST
= (1 << 13), /* global reset (no phy reset) */
63 HCTL_RPGSEL
= (1 << 15), /* register page select */
65 HCTL_KNOWN_BITS
= HCTL_IRQOFF
| HCTL_PWRDWN
| HCTL_SOFTRST
|
68 /* HOST_IRQ_(STAT|MASK) bits */
69 HIRQ_PORT0
= (1 << 0),
70 HIRQ_PORT1
= (1 << 1),
71 HIRQ_SOFT
= (1 << 14),
72 HIRQ_GLOBAL
= (1 << 15), /* STAT only */
74 /* PORT_IRQ_(STAT|MASK) bits */
75 PIRQ_OFFLINE
= (1 << 0), /* device unplugged */
76 PIRQ_ONLINE
= (1 << 1), /* device plugged */
77 PIRQ_COMPLETE
= (1 << 2), /* completion interrupt */
78 PIRQ_FATAL
= (1 << 3), /* fatal error */
79 PIRQ_ATA
= (1 << 4), /* ATA interrupt */
80 PIRQ_REPLY
= (1 << 5), /* reply FIFO not empty */
81 PIRQ_PENDING
= (1 << 7), /* port IRQ pending (STAT only) */
83 PIRQ_ERR
= PIRQ_OFFLINE
| PIRQ_ONLINE
| PIRQ_FATAL
,
85 PIRQ_MASK_DMA_READ
= PIRQ_REPLY
| PIRQ_ATA
,
86 PIRQ_MASK_OTHER
= PIRQ_REPLY
| PIRQ_COMPLETE
,
87 PIRQ_MASK_FREEZE
= 0xff,
89 /* PORT_PRD_CTL bits */
90 PRD_CTL_START
= (1 << 0),
91 PRD_CTL_WR
= (1 << 3),
92 PRD_CTL_DMAEN
= (1 << 7), /* DMA enable */
94 /* PORT_IDMA_CTL bits */
95 IDMA_CTL_RST_ATA
= (1 << 2), /* hardreset ATA bus */
96 IDMA_CTL_RST_IDMA
= (1 << 5), /* reset IDMA machinary */
97 IDMA_CTL_GO
= (1 << 7), /* IDMA mode go */
98 IDMA_CTL_ATA_NIEN
= (1 << 8), /* ATA IRQ disable */
101 struct inic_host_priv
{
105 struct inic_port_priv
{
111 static struct scsi_host_template inic_sht
= {
112 ATA_BMDMA_SHT(DRV_NAME
),
115 static const int scr_map
[] = {
121 static void __iomem
*inic_port_base(struct ata_port
*ap
)
123 return ap
->host
->iomap
[MMIO_BAR
] + ap
->port_no
* PORT_SIZE
;
126 static void __inic_set_pirq_mask(struct ata_port
*ap
, u8 mask
)
128 void __iomem
*port_base
= inic_port_base(ap
);
129 struct inic_port_priv
*pp
= ap
->private_data
;
131 writeb(mask
, port_base
+ PORT_IRQ_MASK
);
132 pp
->cached_pirq_mask
= mask
;
135 static void inic_set_pirq_mask(struct ata_port
*ap
, u8 mask
)
137 struct inic_port_priv
*pp
= ap
->private_data
;
139 if (pp
->cached_pirq_mask
!= mask
)
140 __inic_set_pirq_mask(ap
, mask
);
143 static void inic_reset_port(void __iomem
*port_base
)
145 void __iomem
*idma_ctl
= port_base
+ PORT_IDMA_CTL
;
148 ctl
= readw(idma_ctl
);
149 ctl
&= ~(IDMA_CTL_RST_IDMA
| IDMA_CTL_ATA_NIEN
| IDMA_CTL_GO
);
151 /* mask IRQ and assert reset */
152 writew(ctl
| IDMA_CTL_RST_IDMA
| IDMA_CTL_ATA_NIEN
, idma_ctl
);
153 readw(idma_ctl
); /* flush */
155 /* give it some time */
159 writew(ctl
| IDMA_CTL_ATA_NIEN
, idma_ctl
);
162 writeb(0xff, port_base
+ PORT_IRQ_STAT
);
164 /* reenable ATA IRQ, turn off IDMA mode */
165 writew(ctl
, idma_ctl
);
168 static int inic_scr_read(struct ata_port
*ap
, unsigned sc_reg
, u32
*val
)
170 void __iomem
*scr_addr
= ap
->ioaddr
.scr_addr
;
173 if (unlikely(sc_reg
>= ARRAY_SIZE(scr_map
)))
176 addr
= scr_addr
+ scr_map
[sc_reg
] * 4;
177 *val
= readl(scr_addr
+ scr_map
[sc_reg
] * 4);
179 /* this controller has stuck DIAG.N, ignore it */
180 if (sc_reg
== SCR_ERROR
)
181 *val
&= ~SERR_PHYRDY_CHG
;
185 static int inic_scr_write(struct ata_port
*ap
, unsigned sc_reg
, u32 val
)
187 void __iomem
*scr_addr
= ap
->ioaddr
.scr_addr
;
190 if (unlikely(sc_reg
>= ARRAY_SIZE(scr_map
)))
193 addr
= scr_addr
+ scr_map
[sc_reg
] * 4;
194 writel(val
, scr_addr
+ scr_map
[sc_reg
] * 4);
199 * In TF mode, inic162x is very similar to SFF device. TF registers
200 * function the same. DMA engine behaves similary using the same PRD
201 * format as BMDMA but different command register, interrupt and event
202 * notification methods are used. The following inic_bmdma_*()
203 * functions do the impedance matching.
205 static void inic_bmdma_setup(struct ata_queued_cmd
*qc
)
207 struct ata_port
*ap
= qc
->ap
;
208 struct inic_port_priv
*pp
= ap
->private_data
;
209 void __iomem
*port_base
= inic_port_base(ap
);
210 int rw
= qc
->tf
.flags
& ATA_TFLAG_WRITE
;
212 /* make sure device sees PRD table writes */
215 /* load transfer length */
216 writel(qc
->nbytes
, port_base
+ PORT_PRD_XFERLEN
);
218 /* turn on DMA and specify data direction */
219 pp
->cached_prdctl
= pp
->dfl_prdctl
| PRD_CTL_DMAEN
;
221 pp
->cached_prdctl
|= PRD_CTL_WR
;
222 writeb(pp
->cached_prdctl
, port_base
+ PORT_PRD_CTL
);
224 /* issue r/w command */
225 ap
->ops
->exec_command(ap
, &qc
->tf
);
228 static void inic_bmdma_start(struct ata_queued_cmd
*qc
)
230 struct ata_port
*ap
= qc
->ap
;
231 struct inic_port_priv
*pp
= ap
->private_data
;
232 void __iomem
*port_base
= inic_port_base(ap
);
234 /* start host DMA transaction */
235 pp
->cached_prdctl
|= PRD_CTL_START
;
236 writeb(pp
->cached_prdctl
, port_base
+ PORT_PRD_CTL
);
239 static void inic_bmdma_stop(struct ata_queued_cmd
*qc
)
241 struct ata_port
*ap
= qc
->ap
;
242 struct inic_port_priv
*pp
= ap
->private_data
;
243 void __iomem
*port_base
= inic_port_base(ap
);
245 /* stop DMA engine */
246 writeb(pp
->dfl_prdctl
, port_base
+ PORT_PRD_CTL
);
249 static u8
inic_bmdma_status(struct ata_port
*ap
)
251 /* event is already verified by the interrupt handler */
255 static void inic_host_intr(struct ata_port
*ap
)
257 void __iomem
*port_base
= inic_port_base(ap
);
258 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
261 /* fetch and clear irq */
262 irq_stat
= readb(port_base
+ PORT_IRQ_STAT
);
263 writeb(irq_stat
, port_base
+ PORT_IRQ_STAT
);
265 if (likely(!(irq_stat
& PIRQ_ERR
))) {
266 struct ata_queued_cmd
*qc
=
267 ata_qc_from_tag(ap
, ap
->link
.active_tag
);
269 if (unlikely(!qc
|| (qc
->tf
.flags
& ATA_TFLAG_POLLING
))) {
270 ata_chk_status(ap
); /* clear ATA interrupt */
274 if (likely(ata_host_intr(ap
, qc
)))
277 ata_chk_status(ap
); /* clear ATA interrupt */
278 ata_port_printk(ap
, KERN_WARNING
, "unhandled "
279 "interrupt, irq_stat=%x\n", irq_stat
);
284 ata_ehi_push_desc(ehi
, "irq_stat=0x%x", irq_stat
);
286 if (irq_stat
& (PIRQ_OFFLINE
| PIRQ_ONLINE
)) {
287 ata_ehi_hotplugged(ehi
);
293 static irqreturn_t
inic_interrupt(int irq
, void *dev_instance
)
295 struct ata_host
*host
= dev_instance
;
296 void __iomem
*mmio_base
= host
->iomap
[MMIO_BAR
];
300 host_irq_stat
= readw(mmio_base
+ HOST_IRQ_STAT
);
302 if (unlikely(!(host_irq_stat
& HIRQ_GLOBAL
)))
305 spin_lock(&host
->lock
);
307 for (i
= 0; i
< NR_PORTS
; i
++) {
308 struct ata_port
*ap
= host
->ports
[i
];
310 if (!(host_irq_stat
& (HIRQ_PORT0
<< i
)))
313 if (likely(ap
&& !(ap
->flags
& ATA_FLAG_DISABLED
))) {
318 dev_printk(KERN_ERR
, host
->dev
, "interrupt "
319 "from disabled port %d (0x%x)\n",
324 spin_unlock(&host
->lock
);
327 return IRQ_RETVAL(handled
);
330 static unsigned int inic_qc_issue(struct ata_queued_cmd
*qc
)
332 struct ata_port
*ap
= qc
->ap
;
334 /* ATA IRQ doesn't wait for DMA transfer completion and vice
335 * versa. Mask IRQ selectively to detect command completion.
336 * Without it, ATA DMA read command can cause data corruption.
338 * Something similar might be needed for ATAPI writes. I
339 * tried a lot of combinations but couldn't find the solution.
341 if (qc
->tf
.protocol
== ATA_PROT_DMA
&&
342 !(qc
->tf
.flags
& ATA_TFLAG_WRITE
))
343 inic_set_pirq_mask(ap
, PIRQ_MASK_DMA_READ
);
345 inic_set_pirq_mask(ap
, PIRQ_MASK_OTHER
);
347 /* Issuing a command to yet uninitialized port locks up the
348 * controller. Most of the time, this happens for the first
349 * command after reset which are ATA and ATAPI IDENTIFYs.
350 * Fast fail if stat is 0x7f or 0xff for those commands.
352 if (unlikely(qc
->tf
.command
== ATA_CMD_ID_ATA
||
353 qc
->tf
.command
== ATA_CMD_ID_ATAPI
)) {
354 u8 stat
= ata_chk_status(ap
);
355 if (stat
== 0x7f || stat
== 0xff)
359 return ata_qc_issue_prot(qc
);
362 static void inic_freeze(struct ata_port
*ap
)
364 void __iomem
*port_base
= inic_port_base(ap
);
366 __inic_set_pirq_mask(ap
, PIRQ_MASK_FREEZE
);
369 writeb(0xff, port_base
+ PORT_IRQ_STAT
);
371 readb(port_base
+ PORT_IRQ_STAT
); /* flush */
374 static void inic_thaw(struct ata_port
*ap
)
376 void __iomem
*port_base
= inic_port_base(ap
);
379 writeb(0xff, port_base
+ PORT_IRQ_STAT
);
381 __inic_set_pirq_mask(ap
, PIRQ_MASK_OTHER
);
383 readb(port_base
+ PORT_IRQ_STAT
); /* flush */
387 * SRST and SControl hardreset don't give valid signature on this
388 * controller. Only controller specific hardreset mechanism works.
390 static int inic_hardreset(struct ata_link
*link
, unsigned int *class,
391 unsigned long deadline
)
393 struct ata_port
*ap
= link
->ap
;
394 void __iomem
*port_base
= inic_port_base(ap
);
395 void __iomem
*idma_ctl
= port_base
+ PORT_IDMA_CTL
;
396 const unsigned long *timing
= sata_ehc_deb_timing(&link
->eh_context
);
400 /* hammer it into sane state */
401 inic_reset_port(port_base
);
403 val
= readw(idma_ctl
);
404 writew(val
| IDMA_CTL_RST_ATA
, idma_ctl
);
405 readw(idma_ctl
); /* flush */
407 writew(val
& ~IDMA_CTL_RST_ATA
, idma_ctl
);
409 rc
= sata_link_resume(link
, timing
, deadline
);
411 ata_link_printk(link
, KERN_WARNING
, "failed to resume "
412 "link after reset (errno=%d)\n", rc
);
416 *class = ATA_DEV_NONE
;
417 if (ata_link_online(link
)) {
418 struct ata_taskfile tf
;
420 /* wait a while before checking status */
421 ata_wait_after_reset(ap
, deadline
);
423 rc
= ata_wait_ready(ap
, deadline
);
424 /* link occupied, -ENODEV too is an error */
426 ata_link_printk(link
, KERN_WARNING
, "device not ready "
427 "after hardreset (errno=%d)\n", rc
);
431 ata_tf_read(ap
, &tf
);
432 *class = ata_dev_classify(&tf
);
433 if (*class == ATA_DEV_UNKNOWN
)
434 *class = ATA_DEV_NONE
;
440 static void inic_error_handler(struct ata_port
*ap
)
442 void __iomem
*port_base
= inic_port_base(ap
);
443 struct inic_port_priv
*pp
= ap
->private_data
;
446 /* reset PIO HSM and stop DMA engine */
447 inic_reset_port(port_base
);
449 spin_lock_irqsave(ap
->lock
, flags
);
450 ap
->hsm_task_state
= HSM_ST_IDLE
;
451 writeb(pp
->dfl_prdctl
, port_base
+ PORT_PRD_CTL
);
452 spin_unlock_irqrestore(ap
->lock
, flags
);
454 /* PIO and DMA engines have been stopped, perform recovery */
455 ata_std_error_handler(ap
);
458 static void inic_post_internal_cmd(struct ata_queued_cmd
*qc
)
460 /* make DMA engine forget about the failed command */
461 if (qc
->flags
& ATA_QCFLAG_FAILED
)
462 inic_reset_port(inic_port_base(qc
->ap
));
465 static void inic_dev_config(struct ata_device
*dev
)
467 /* inic can only handle upto LBA28 max sectors */
468 if (dev
->max_sectors
> ATA_MAX_SECTORS
)
469 dev
->max_sectors
= ATA_MAX_SECTORS
;
471 if (dev
->n_sectors
>= 1 << 28) {
472 ata_dev_printk(dev
, KERN_ERR
,
473 "ERROR: This driver doesn't support LBA48 yet and may cause\n"
474 " data corruption on such devices. Disabling.\n");
475 ata_dev_disable(dev
);
479 static void init_port(struct ata_port
*ap
)
481 void __iomem
*port_base
= inic_port_base(ap
);
483 /* Setup PRD address */
484 writel(ap
->prd_dma
, port_base
+ PORT_PRD_ADDR
);
487 static int inic_port_resume(struct ata_port
*ap
)
493 static int inic_port_start(struct ata_port
*ap
)
495 void __iomem
*port_base
= inic_port_base(ap
);
496 struct inic_port_priv
*pp
;
500 /* alloc and initialize private data */
501 pp
= devm_kzalloc(ap
->host
->dev
, sizeof(*pp
), GFP_KERNEL
);
504 ap
->private_data
= pp
;
506 /* default PRD_CTL value, DMAEN, WR and START off */
507 tmp
= readb(port_base
+ PORT_PRD_CTL
);
508 tmp
&= ~(PRD_CTL_DMAEN
| PRD_CTL_WR
| PRD_CTL_START
);
509 pp
->dfl_prdctl
= tmp
;
511 /* Alloc resources */
512 rc
= ata_port_start(ap
);
523 static struct ata_port_operations inic_port_ops
= {
524 .inherits
= &ata_sff_port_ops
,
526 .bmdma_setup
= inic_bmdma_setup
,
527 .bmdma_start
= inic_bmdma_start
,
528 .bmdma_stop
= inic_bmdma_stop
,
529 .bmdma_status
= inic_bmdma_status
,
530 .qc_issue
= inic_qc_issue
,
532 .freeze
= inic_freeze
,
534 .softreset
= ATA_OP_NULL
, /* softreset is broken */
535 .hardreset
= inic_hardreset
,
536 .error_handler
= inic_error_handler
,
537 .post_internal_cmd
= inic_post_internal_cmd
,
538 .dev_config
= inic_dev_config
,
540 .scr_read
= inic_scr_read
,
541 .scr_write
= inic_scr_write
,
543 .port_resume
= inic_port_resume
,
544 .port_start
= inic_port_start
,
547 static struct ata_port_info inic_port_info
= {
548 /* For some reason, ATAPI_PROT_PIO is broken on this
549 * controller, and no, PIO_POLLING does't fix it. It somehow
550 * manages to report the wrong ireason and ignoring ireason
551 * results in machine lock up. Tell libata to always prefer
554 .flags
= ATA_FLAG_SATA
| ATA_FLAG_PIO_DMA
,
555 .pio_mask
= 0x1f, /* pio0-4 */
556 .mwdma_mask
= 0x07, /* mwdma0-2 */
557 .udma_mask
= ATA_UDMA6
,
558 .port_ops
= &inic_port_ops
561 static int init_controller(void __iomem
*mmio_base
, u16 hctl
)
566 hctl
&= ~HCTL_KNOWN_BITS
;
568 /* Soft reset whole controller. Spec says reset duration is 3
569 * PCI clocks, be generous and give it 10ms.
571 writew(hctl
| HCTL_SOFTRST
, mmio_base
+ HOST_CTL
);
572 readw(mmio_base
+ HOST_CTL
); /* flush */
574 for (i
= 0; i
< 10; i
++) {
576 val
= readw(mmio_base
+ HOST_CTL
);
577 if (!(val
& HCTL_SOFTRST
))
581 if (val
& HCTL_SOFTRST
)
584 /* mask all interrupts and reset ports */
585 for (i
= 0; i
< NR_PORTS
; i
++) {
586 void __iomem
*port_base
= mmio_base
+ i
* PORT_SIZE
;
588 writeb(0xff, port_base
+ PORT_IRQ_MASK
);
589 inic_reset_port(port_base
);
592 /* port IRQ is masked now, unmask global IRQ */
593 writew(hctl
& ~HCTL_IRQOFF
, mmio_base
+ HOST_CTL
);
594 val
= readw(mmio_base
+ HOST_IRQ_MASK
);
595 val
&= ~(HIRQ_PORT0
| HIRQ_PORT1
);
596 writew(val
, mmio_base
+ HOST_IRQ_MASK
);
602 static int inic_pci_device_resume(struct pci_dev
*pdev
)
604 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
605 struct inic_host_priv
*hpriv
= host
->private_data
;
606 void __iomem
*mmio_base
= host
->iomap
[MMIO_BAR
];
609 rc
= ata_pci_device_do_resume(pdev
);
613 if (pdev
->dev
.power
.power_state
.event
== PM_EVENT_SUSPEND
) {
614 rc
= init_controller(mmio_base
, hpriv
->cached_hctl
);
619 ata_host_resume(host
);
625 static int inic_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
627 static int printed_version
;
628 const struct ata_port_info
*ppi
[] = { &inic_port_info
, NULL
};
629 struct ata_host
*host
;
630 struct inic_host_priv
*hpriv
;
631 void __iomem
* const *iomap
;
634 if (!printed_version
++)
635 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
638 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, NR_PORTS
);
639 hpriv
= devm_kzalloc(&pdev
->dev
, sizeof(*hpriv
), GFP_KERNEL
);
643 host
->private_data
= hpriv
;
645 /* acquire resources and fill host */
646 rc
= pcim_enable_device(pdev
);
650 rc
= pcim_iomap_regions(pdev
, 0x3f, DRV_NAME
);
653 host
->iomap
= iomap
= pcim_iomap_table(pdev
);
655 for (i
= 0; i
< NR_PORTS
; i
++) {
656 struct ata_port
*ap
= host
->ports
[i
];
657 struct ata_ioports
*port
= &ap
->ioaddr
;
658 unsigned int offset
= i
* PORT_SIZE
;
660 port
->cmd_addr
= iomap
[2 * i
];
661 port
->altstatus_addr
=
662 port
->ctl_addr
= (void __iomem
*)
663 ((unsigned long)iomap
[2 * i
+ 1] | ATA_PCI_CTL_OFS
);
664 port
->scr_addr
= iomap
[MMIO_BAR
] + offset
+ PORT_SCR
;
668 ata_port_pbar_desc(ap
, MMIO_BAR
, -1, "mmio");
669 ata_port_pbar_desc(ap
, MMIO_BAR
, offset
, "port");
670 ata_port_desc(ap
, "cmd 0x%llx ctl 0x%llx",
671 (unsigned long long)pci_resource_start(pdev
, 2 * i
),
672 (unsigned long long)pci_resource_start(pdev
, (2 * i
+ 1)) |
676 hpriv
->cached_hctl
= readw(iomap
[MMIO_BAR
] + HOST_CTL
);
678 /* Set dma_mask. This devices doesn't support 64bit addressing. */
679 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
681 dev_printk(KERN_ERR
, &pdev
->dev
,
682 "32-bit DMA enable failed\n");
686 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
688 dev_printk(KERN_ERR
, &pdev
->dev
,
689 "32-bit consistent DMA enable failed\n");
694 * This controller is braindamaged. dma_boundary is 0xffff
695 * like others but it will lock up the whole machine HARD if
696 * 65536 byte PRD entry is fed. Reduce maximum segment size.
698 rc
= pci_set_dma_max_seg_size(pdev
, 65536 - 512);
700 dev_printk(KERN_ERR
, &pdev
->dev
,
701 "failed to set the maximum segment size.\n");
705 rc
= init_controller(iomap
[MMIO_BAR
], hpriv
->cached_hctl
);
707 dev_printk(KERN_ERR
, &pdev
->dev
,
708 "failed to initialize controller\n");
712 pci_set_master(pdev
);
713 return ata_host_activate(host
, pdev
->irq
, inic_interrupt
, IRQF_SHARED
,
717 static const struct pci_device_id inic_pci_tbl
[] = {
718 { PCI_VDEVICE(INIT
, 0x1622), },
722 static struct pci_driver inic_pci_driver
= {
724 .id_table
= inic_pci_tbl
,
726 .suspend
= ata_pci_device_suspend
,
727 .resume
= inic_pci_device_resume
,
729 .probe
= inic_init_one
,
730 .remove
= ata_pci_remove_one
,
733 static int __init
inic_init(void)
735 return pci_register_driver(&inic_pci_driver
);
738 static void __exit
inic_exit(void)
740 pci_unregister_driver(&inic_pci_driver
);
743 MODULE_AUTHOR("Tejun Heo");
744 MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
745 MODULE_LICENSE("GPL v2");
746 MODULE_DEVICE_TABLE(pci
, inic_pci_tbl
);
747 MODULE_VERSION(DRV_VERSION
);
749 module_init(inic_init
);
750 module_exit(inic_exit
);