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libata: bump versions
[deliverable/linux.git] / drivers / ata / sata_nv.c
1 /*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
32 * CK804/MCP04 controllers support an alternate programming interface
33 * similar to the ADMA specification (with some modifications).
34 * This allows the use of NCQ. Non-DMA-mapped ATA commands are still
35 * sent through the legacy interface.
36 *
37 */
38
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/init.h>
43 #include <linux/blkdev.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/device.h>
47 #include <scsi/scsi_host.h>
48 #include <scsi/scsi_device.h>
49 #include <linux/libata.h>
50
51 #define DRV_NAME "sata_nv"
52 #define DRV_VERSION "3.4"
53
54 #define NV_ADMA_DMA_BOUNDARY 0xffffffffUL
55
56 enum {
57 NV_MMIO_BAR = 5,
58
59 NV_PORTS = 2,
60 NV_PIO_MASK = 0x1f,
61 NV_MWDMA_MASK = 0x07,
62 NV_UDMA_MASK = 0x7f,
63 NV_PORT0_SCR_REG_OFFSET = 0x00,
64 NV_PORT1_SCR_REG_OFFSET = 0x40,
65
66 /* INT_STATUS/ENABLE */
67 NV_INT_STATUS = 0x10,
68 NV_INT_ENABLE = 0x11,
69 NV_INT_STATUS_CK804 = 0x440,
70 NV_INT_ENABLE_CK804 = 0x441,
71
72 /* INT_STATUS/ENABLE bits */
73 NV_INT_DEV = 0x01,
74 NV_INT_PM = 0x02,
75 NV_INT_ADDED = 0x04,
76 NV_INT_REMOVED = 0x08,
77
78 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
79
80 NV_INT_ALL = 0x0f,
81 NV_INT_MASK = NV_INT_DEV |
82 NV_INT_ADDED | NV_INT_REMOVED,
83
84 /* INT_CONFIG */
85 NV_INT_CONFIG = 0x12,
86 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
87
88 // For PCI config register 20
89 NV_MCP_SATA_CFG_20 = 0x50,
90 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
91 NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17),
92 NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16),
93 NV_MCP_SATA_CFG_20_PORT0_PWB_EN = (1 << 14),
94 NV_MCP_SATA_CFG_20_PORT1_PWB_EN = (1 << 12),
95
96 NV_ADMA_MAX_CPBS = 32,
97 NV_ADMA_CPB_SZ = 128,
98 NV_ADMA_APRD_SZ = 16,
99 NV_ADMA_SGTBL_LEN = (1024 - NV_ADMA_CPB_SZ) /
100 NV_ADMA_APRD_SZ,
101 NV_ADMA_SGTBL_TOTAL_LEN = NV_ADMA_SGTBL_LEN + 5,
102 NV_ADMA_SGTBL_SZ = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ,
103 NV_ADMA_PORT_PRIV_DMA_SZ = NV_ADMA_MAX_CPBS *
104 (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ),
105
106 /* BAR5 offset to ADMA general registers */
107 NV_ADMA_GEN = 0x400,
108 NV_ADMA_GEN_CTL = 0x00,
109 NV_ADMA_NOTIFIER_CLEAR = 0x30,
110
111 /* BAR5 offset to ADMA ports */
112 NV_ADMA_PORT = 0x480,
113
114 /* size of ADMA port register space */
115 NV_ADMA_PORT_SIZE = 0x100,
116
117 /* ADMA port registers */
118 NV_ADMA_CTL = 0x40,
119 NV_ADMA_CPB_COUNT = 0x42,
120 NV_ADMA_NEXT_CPB_IDX = 0x43,
121 NV_ADMA_STAT = 0x44,
122 NV_ADMA_CPB_BASE_LOW = 0x48,
123 NV_ADMA_CPB_BASE_HIGH = 0x4C,
124 NV_ADMA_APPEND = 0x50,
125 NV_ADMA_NOTIFIER = 0x68,
126 NV_ADMA_NOTIFIER_ERROR = 0x6C,
127
128 /* NV_ADMA_CTL register bits */
129 NV_ADMA_CTL_HOTPLUG_IEN = (1 << 0),
130 NV_ADMA_CTL_CHANNEL_RESET = (1 << 5),
131 NV_ADMA_CTL_GO = (1 << 7),
132 NV_ADMA_CTL_AIEN = (1 << 8),
133 NV_ADMA_CTL_READ_NON_COHERENT = (1 << 11),
134 NV_ADMA_CTL_WRITE_NON_COHERENT = (1 << 12),
135
136 /* CPB response flag bits */
137 NV_CPB_RESP_DONE = (1 << 0),
138 NV_CPB_RESP_ATA_ERR = (1 << 3),
139 NV_CPB_RESP_CMD_ERR = (1 << 4),
140 NV_CPB_RESP_CPB_ERR = (1 << 7),
141
142 /* CPB control flag bits */
143 NV_CPB_CTL_CPB_VALID = (1 << 0),
144 NV_CPB_CTL_QUEUE = (1 << 1),
145 NV_CPB_CTL_APRD_VALID = (1 << 2),
146 NV_CPB_CTL_IEN = (1 << 3),
147 NV_CPB_CTL_FPDMA = (1 << 4),
148
149 /* APRD flags */
150 NV_APRD_WRITE = (1 << 1),
151 NV_APRD_END = (1 << 2),
152 NV_APRD_CONT = (1 << 3),
153
154 /* NV_ADMA_STAT flags */
155 NV_ADMA_STAT_TIMEOUT = (1 << 0),
156 NV_ADMA_STAT_HOTUNPLUG = (1 << 1),
157 NV_ADMA_STAT_HOTPLUG = (1 << 2),
158 NV_ADMA_STAT_CPBERR = (1 << 4),
159 NV_ADMA_STAT_SERROR = (1 << 5),
160 NV_ADMA_STAT_CMD_COMPLETE = (1 << 6),
161 NV_ADMA_STAT_IDLE = (1 << 8),
162 NV_ADMA_STAT_LEGACY = (1 << 9),
163 NV_ADMA_STAT_STOPPED = (1 << 10),
164 NV_ADMA_STAT_DONE = (1 << 12),
165 NV_ADMA_STAT_ERR = NV_ADMA_STAT_CPBERR |
166 NV_ADMA_STAT_TIMEOUT,
167
168 /* port flags */
169 NV_ADMA_PORT_REGISTER_MODE = (1 << 0),
170 NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1),
171
172 };
173
174 /* ADMA Physical Region Descriptor - one SG segment */
175 struct nv_adma_prd {
176 __le64 addr;
177 __le32 len;
178 u8 flags;
179 u8 packet_len;
180 __le16 reserved;
181 };
182
183 enum nv_adma_regbits {
184 CMDEND = (1 << 15), /* end of command list */
185 WNB = (1 << 14), /* wait-not-BSY */
186 IGN = (1 << 13), /* ignore this entry */
187 CS1n = (1 << (4 + 8)), /* std. PATA signals follow... */
188 DA2 = (1 << (2 + 8)),
189 DA1 = (1 << (1 + 8)),
190 DA0 = (1 << (0 + 8)),
191 };
192
193 /* ADMA Command Parameter Block
194 The first 5 SG segments are stored inside the Command Parameter Block itself.
195 If there are more than 5 segments the remainder are stored in a separate
196 memory area indicated by next_aprd. */
197 struct nv_adma_cpb {
198 u8 resp_flags; /* 0 */
199 u8 reserved1; /* 1 */
200 u8 ctl_flags; /* 2 */
201 /* len is length of taskfile in 64 bit words */
202 u8 len; /* 3 */
203 u8 tag; /* 4 */
204 u8 next_cpb_idx; /* 5 */
205 __le16 reserved2; /* 6-7 */
206 __le16 tf[12]; /* 8-31 */
207 struct nv_adma_prd aprd[5]; /* 32-111 */
208 __le64 next_aprd; /* 112-119 */
209 __le64 reserved3; /* 120-127 */
210 };
211
212
213 struct nv_adma_port_priv {
214 struct nv_adma_cpb *cpb;
215 dma_addr_t cpb_dma;
216 struct nv_adma_prd *aprd;
217 dma_addr_t aprd_dma;
218 void __iomem * ctl_block;
219 void __iomem * gen_block;
220 void __iomem * notifier_clear_block;
221 u8 flags;
222 int last_issue_ncq;
223 };
224
225 struct nv_host_priv {
226 unsigned long type;
227 };
228
229 #define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & ( 1 << (19 + (12 * (PORT)))))
230
231 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
232 #ifdef CONFIG_PM
233 static int nv_pci_device_resume(struct pci_dev *pdev);
234 #endif
235 static void nv_ck804_host_stop(struct ata_host *host);
236 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
237 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
238 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
239 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
240 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
241
242 static void nv_nf2_freeze(struct ata_port *ap);
243 static void nv_nf2_thaw(struct ata_port *ap);
244 static void nv_ck804_freeze(struct ata_port *ap);
245 static void nv_ck804_thaw(struct ata_port *ap);
246 static void nv_error_handler(struct ata_port *ap);
247 static int nv_adma_slave_config(struct scsi_device *sdev);
248 static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
249 static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
250 static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc);
251 static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance);
252 static void nv_adma_irq_clear(struct ata_port *ap);
253 static int nv_adma_port_start(struct ata_port *ap);
254 static void nv_adma_port_stop(struct ata_port *ap);
255 #ifdef CONFIG_PM
256 static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg);
257 static int nv_adma_port_resume(struct ata_port *ap);
258 #endif
259 static void nv_adma_freeze(struct ata_port *ap);
260 static void nv_adma_thaw(struct ata_port *ap);
261 static void nv_adma_error_handler(struct ata_port *ap);
262 static void nv_adma_host_stop(struct ata_host *host);
263 static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc);
264 static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
265
266 enum nv_host_type
267 {
268 GENERIC,
269 NFORCE2,
270 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
271 CK804,
272 ADMA
273 };
274
275 static const struct pci_device_id nv_pci_tbl[] = {
276 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
277 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
278 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
279 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
280 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
281 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
282 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
283 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC },
284 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC },
285 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC },
286 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC },
287 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
288 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
289 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
290
291 { } /* terminate list */
292 };
293
294 static struct pci_driver nv_pci_driver = {
295 .name = DRV_NAME,
296 .id_table = nv_pci_tbl,
297 .probe = nv_init_one,
298 #ifdef CONFIG_PM
299 .suspend = ata_pci_device_suspend,
300 .resume = nv_pci_device_resume,
301 #endif
302 .remove = ata_pci_remove_one,
303 };
304
305 static struct scsi_host_template nv_sht = {
306 .module = THIS_MODULE,
307 .name = DRV_NAME,
308 .ioctl = ata_scsi_ioctl,
309 .queuecommand = ata_scsi_queuecmd,
310 .can_queue = ATA_DEF_QUEUE,
311 .this_id = ATA_SHT_THIS_ID,
312 .sg_tablesize = LIBATA_MAX_PRD,
313 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
314 .emulated = ATA_SHT_EMULATED,
315 .use_clustering = ATA_SHT_USE_CLUSTERING,
316 .proc_name = DRV_NAME,
317 .dma_boundary = ATA_DMA_BOUNDARY,
318 .slave_configure = ata_scsi_slave_config,
319 .slave_destroy = ata_scsi_slave_destroy,
320 .bios_param = ata_std_bios_param,
321 };
322
323 static struct scsi_host_template nv_adma_sht = {
324 .module = THIS_MODULE,
325 .name = DRV_NAME,
326 .ioctl = ata_scsi_ioctl,
327 .queuecommand = ata_scsi_queuecmd,
328 .can_queue = NV_ADMA_MAX_CPBS,
329 .this_id = ATA_SHT_THIS_ID,
330 .sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN,
331 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
332 .emulated = ATA_SHT_EMULATED,
333 .use_clustering = ATA_SHT_USE_CLUSTERING,
334 .proc_name = DRV_NAME,
335 .dma_boundary = NV_ADMA_DMA_BOUNDARY,
336 .slave_configure = nv_adma_slave_config,
337 .slave_destroy = ata_scsi_slave_destroy,
338 .bios_param = ata_std_bios_param,
339 };
340
341 static const struct ata_port_operations nv_generic_ops = {
342 .port_disable = ata_port_disable,
343 .tf_load = ata_tf_load,
344 .tf_read = ata_tf_read,
345 .exec_command = ata_exec_command,
346 .check_status = ata_check_status,
347 .dev_select = ata_std_dev_select,
348 .bmdma_setup = ata_bmdma_setup,
349 .bmdma_start = ata_bmdma_start,
350 .bmdma_stop = ata_bmdma_stop,
351 .bmdma_status = ata_bmdma_status,
352 .qc_prep = ata_qc_prep,
353 .qc_issue = ata_qc_issue_prot,
354 .freeze = ata_bmdma_freeze,
355 .thaw = ata_bmdma_thaw,
356 .error_handler = nv_error_handler,
357 .post_internal_cmd = ata_bmdma_post_internal_cmd,
358 .data_xfer = ata_data_xfer,
359 .irq_clear = ata_bmdma_irq_clear,
360 .irq_on = ata_irq_on,
361 .irq_ack = ata_irq_ack,
362 .scr_read = nv_scr_read,
363 .scr_write = nv_scr_write,
364 .port_start = ata_port_start,
365 };
366
367 static const struct ata_port_operations nv_nf2_ops = {
368 .port_disable = ata_port_disable,
369 .tf_load = ata_tf_load,
370 .tf_read = ata_tf_read,
371 .exec_command = ata_exec_command,
372 .check_status = ata_check_status,
373 .dev_select = ata_std_dev_select,
374 .bmdma_setup = ata_bmdma_setup,
375 .bmdma_start = ata_bmdma_start,
376 .bmdma_stop = ata_bmdma_stop,
377 .bmdma_status = ata_bmdma_status,
378 .qc_prep = ata_qc_prep,
379 .qc_issue = ata_qc_issue_prot,
380 .freeze = nv_nf2_freeze,
381 .thaw = nv_nf2_thaw,
382 .error_handler = nv_error_handler,
383 .post_internal_cmd = ata_bmdma_post_internal_cmd,
384 .data_xfer = ata_data_xfer,
385 .irq_clear = ata_bmdma_irq_clear,
386 .irq_on = ata_irq_on,
387 .irq_ack = ata_irq_ack,
388 .scr_read = nv_scr_read,
389 .scr_write = nv_scr_write,
390 .port_start = ata_port_start,
391 };
392
393 static const struct ata_port_operations nv_ck804_ops = {
394 .port_disable = ata_port_disable,
395 .tf_load = ata_tf_load,
396 .tf_read = ata_tf_read,
397 .exec_command = ata_exec_command,
398 .check_status = ata_check_status,
399 .dev_select = ata_std_dev_select,
400 .bmdma_setup = ata_bmdma_setup,
401 .bmdma_start = ata_bmdma_start,
402 .bmdma_stop = ata_bmdma_stop,
403 .bmdma_status = ata_bmdma_status,
404 .qc_prep = ata_qc_prep,
405 .qc_issue = ata_qc_issue_prot,
406 .freeze = nv_ck804_freeze,
407 .thaw = nv_ck804_thaw,
408 .error_handler = nv_error_handler,
409 .post_internal_cmd = ata_bmdma_post_internal_cmd,
410 .data_xfer = ata_data_xfer,
411 .irq_clear = ata_bmdma_irq_clear,
412 .irq_on = ata_irq_on,
413 .irq_ack = ata_irq_ack,
414 .scr_read = nv_scr_read,
415 .scr_write = nv_scr_write,
416 .port_start = ata_port_start,
417 .host_stop = nv_ck804_host_stop,
418 };
419
420 static const struct ata_port_operations nv_adma_ops = {
421 .port_disable = ata_port_disable,
422 .tf_load = ata_tf_load,
423 .tf_read = nv_adma_tf_read,
424 .check_atapi_dma = nv_adma_check_atapi_dma,
425 .exec_command = ata_exec_command,
426 .check_status = ata_check_status,
427 .dev_select = ata_std_dev_select,
428 .bmdma_setup = ata_bmdma_setup,
429 .bmdma_start = ata_bmdma_start,
430 .bmdma_stop = ata_bmdma_stop,
431 .bmdma_status = ata_bmdma_status,
432 .qc_prep = nv_adma_qc_prep,
433 .qc_issue = nv_adma_qc_issue,
434 .freeze = nv_adma_freeze,
435 .thaw = nv_adma_thaw,
436 .error_handler = nv_adma_error_handler,
437 .post_internal_cmd = nv_adma_post_internal_cmd,
438 .data_xfer = ata_data_xfer,
439 .irq_clear = nv_adma_irq_clear,
440 .irq_on = ata_irq_on,
441 .irq_ack = ata_irq_ack,
442 .scr_read = nv_scr_read,
443 .scr_write = nv_scr_write,
444 .port_start = nv_adma_port_start,
445 .port_stop = nv_adma_port_stop,
446 #ifdef CONFIG_PM
447 .port_suspend = nv_adma_port_suspend,
448 .port_resume = nv_adma_port_resume,
449 #endif
450 .host_stop = nv_adma_host_stop,
451 };
452
453 static const struct ata_port_info nv_port_info[] = {
454 /* generic */
455 {
456 .sht = &nv_sht,
457 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
458 ATA_FLAG_HRST_TO_RESUME,
459 .pio_mask = NV_PIO_MASK,
460 .mwdma_mask = NV_MWDMA_MASK,
461 .udma_mask = NV_UDMA_MASK,
462 .port_ops = &nv_generic_ops,
463 .irq_handler = nv_generic_interrupt,
464 },
465 /* nforce2/3 */
466 {
467 .sht = &nv_sht,
468 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
469 ATA_FLAG_HRST_TO_RESUME,
470 .pio_mask = NV_PIO_MASK,
471 .mwdma_mask = NV_MWDMA_MASK,
472 .udma_mask = NV_UDMA_MASK,
473 .port_ops = &nv_nf2_ops,
474 .irq_handler = nv_nf2_interrupt,
475 },
476 /* ck804 */
477 {
478 .sht = &nv_sht,
479 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
480 ATA_FLAG_HRST_TO_RESUME,
481 .pio_mask = NV_PIO_MASK,
482 .mwdma_mask = NV_MWDMA_MASK,
483 .udma_mask = NV_UDMA_MASK,
484 .port_ops = &nv_ck804_ops,
485 .irq_handler = nv_ck804_interrupt,
486 },
487 /* ADMA */
488 {
489 .sht = &nv_adma_sht,
490 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
491 ATA_FLAG_HRST_TO_RESUME |
492 ATA_FLAG_MMIO | ATA_FLAG_NCQ,
493 .pio_mask = NV_PIO_MASK,
494 .mwdma_mask = NV_MWDMA_MASK,
495 .udma_mask = NV_UDMA_MASK,
496 .port_ops = &nv_adma_ops,
497 .irq_handler = nv_adma_interrupt,
498 },
499 };
500
501 MODULE_AUTHOR("NVIDIA");
502 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
503 MODULE_LICENSE("GPL");
504 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
505 MODULE_VERSION(DRV_VERSION);
506
507 static int adma_enabled = 1;
508
509 static void nv_adma_register_mode(struct ata_port *ap)
510 {
511 struct nv_adma_port_priv *pp = ap->private_data;
512 void __iomem *mmio = pp->ctl_block;
513 u16 tmp, status;
514 int count = 0;
515
516 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
517 return;
518
519 status = readw(mmio + NV_ADMA_STAT);
520 while(!(status & NV_ADMA_STAT_IDLE) && count < 20) {
521 ndelay(50);
522 status = readw(mmio + NV_ADMA_STAT);
523 count++;
524 }
525 if(count == 20)
526 ata_port_printk(ap, KERN_WARNING,
527 "timeout waiting for ADMA IDLE, stat=0x%hx\n",
528 status);
529
530 tmp = readw(mmio + NV_ADMA_CTL);
531 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
532
533 count = 0;
534 status = readw(mmio + NV_ADMA_STAT);
535 while(!(status & NV_ADMA_STAT_LEGACY) && count < 20) {
536 ndelay(50);
537 status = readw(mmio + NV_ADMA_STAT);
538 count++;
539 }
540 if(count == 20)
541 ata_port_printk(ap, KERN_WARNING,
542 "timeout waiting for ADMA LEGACY, stat=0x%hx\n",
543 status);
544
545 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
546 }
547
548 static void nv_adma_mode(struct ata_port *ap)
549 {
550 struct nv_adma_port_priv *pp = ap->private_data;
551 void __iomem *mmio = pp->ctl_block;
552 u16 tmp, status;
553 int count = 0;
554
555 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
556 return;
557
558 WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
559
560 tmp = readw(mmio + NV_ADMA_CTL);
561 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
562
563 status = readw(mmio + NV_ADMA_STAT);
564 while(((status & NV_ADMA_STAT_LEGACY) ||
565 !(status & NV_ADMA_STAT_IDLE)) && count < 20) {
566 ndelay(50);
567 status = readw(mmio + NV_ADMA_STAT);
568 count++;
569 }
570 if(count == 20)
571 ata_port_printk(ap, KERN_WARNING,
572 "timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n",
573 status);
574
575 pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
576 }
577
578 static int nv_adma_slave_config(struct scsi_device *sdev)
579 {
580 struct ata_port *ap = ata_shost_to_port(sdev->host);
581 struct nv_adma_port_priv *pp = ap->private_data;
582 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
583 u64 bounce_limit;
584 unsigned long segment_boundary;
585 unsigned short sg_tablesize;
586 int rc;
587 int adma_enable;
588 u32 current_reg, new_reg, config_mask;
589
590 rc = ata_scsi_slave_config(sdev);
591
592 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
593 /* Not a proper libata device, ignore */
594 return rc;
595
596 if (ap->device[sdev->id].class == ATA_DEV_ATAPI) {
597 /*
598 * NVIDIA reports that ADMA mode does not support ATAPI commands.
599 * Therefore ATAPI commands are sent through the legacy interface.
600 * However, the legacy interface only supports 32-bit DMA.
601 * Restrict DMA parameters as required by the legacy interface
602 * when an ATAPI device is connected.
603 */
604 bounce_limit = ATA_DMA_MASK;
605 segment_boundary = ATA_DMA_BOUNDARY;
606 /* Subtract 1 since an extra entry may be needed for padding, see
607 libata-scsi.c */
608 sg_tablesize = LIBATA_MAX_PRD - 1;
609
610 /* Since the legacy DMA engine is in use, we need to disable ADMA
611 on the port. */
612 adma_enable = 0;
613 nv_adma_register_mode(ap);
614 }
615 else {
616 bounce_limit = *ap->dev->dma_mask;
617 segment_boundary = NV_ADMA_DMA_BOUNDARY;
618 sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN;
619 adma_enable = 1;
620 }
621
622 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &current_reg);
623
624 if(ap->port_no == 1)
625 config_mask = NV_MCP_SATA_CFG_20_PORT1_EN |
626 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
627 else
628 config_mask = NV_MCP_SATA_CFG_20_PORT0_EN |
629 NV_MCP_SATA_CFG_20_PORT0_PWB_EN;
630
631 if(adma_enable) {
632 new_reg = current_reg | config_mask;
633 pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE;
634 }
635 else {
636 new_reg = current_reg & ~config_mask;
637 pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE;
638 }
639
640 if(current_reg != new_reg)
641 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg);
642
643 blk_queue_bounce_limit(sdev->request_queue, bounce_limit);
644 blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
645 blk_queue_max_hw_segments(sdev->request_queue, sg_tablesize);
646 ata_port_printk(ap, KERN_INFO,
647 "bounce limit 0x%llX, segment boundary 0x%lX, hw segs %hu\n",
648 (unsigned long long)bounce_limit, segment_boundary, sg_tablesize);
649 return rc;
650 }
651
652 static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc)
653 {
654 struct nv_adma_port_priv *pp = qc->ap->private_data;
655 return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
656 }
657
658 static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
659 {
660 /* Since commands where a result TF is requested are not
661 executed in ADMA mode, the only time this function will be called
662 in ADMA mode will be if a command fails. In this case we
663 don't care about going into register mode with ADMA commands
664 pending, as the commands will all shortly be aborted anyway. */
665 nv_adma_register_mode(ap);
666
667 ata_tf_read(ap, tf);
668 }
669
670 static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb)
671 {
672 unsigned int idx = 0;
673
674 if(tf->flags & ATA_TFLAG_ISADDR) {
675 if (tf->flags & ATA_TFLAG_LBA48) {
676 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->hob_feature | WNB);
677 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect);
678 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->hob_lbal);
679 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->hob_lbam);
680 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->hob_lbah);
681 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature);
682 } else
683 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature | WNB);
684
685 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->nsect);
686 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->lbal);
687 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->lbam);
688 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->lbah);
689 }
690
691 if(tf->flags & ATA_TFLAG_DEVICE)
692 cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device);
693
694 cpb[idx++] = cpu_to_le16((ATA_REG_CMD << 8) | tf->command | CMDEND);
695
696 while(idx < 12)
697 cpb[idx++] = cpu_to_le16(IGN);
698
699 return idx;
700 }
701
702 static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
703 {
704 struct nv_adma_port_priv *pp = ap->private_data;
705 u8 flags = pp->cpb[cpb_num].resp_flags;
706
707 VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags);
708
709 if (unlikely((force_err ||
710 flags & (NV_CPB_RESP_ATA_ERR |
711 NV_CPB_RESP_CMD_ERR |
712 NV_CPB_RESP_CPB_ERR)))) {
713 struct ata_eh_info *ehi = &ap->eh_info;
714 int freeze = 0;
715
716 ata_ehi_clear_desc(ehi);
717 ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x", flags );
718 if (flags & NV_CPB_RESP_ATA_ERR) {
719 ata_ehi_push_desc(ehi, ": ATA error");
720 ehi->err_mask |= AC_ERR_DEV;
721 } else if (flags & NV_CPB_RESP_CMD_ERR) {
722 ata_ehi_push_desc(ehi, ": CMD error");
723 ehi->err_mask |= AC_ERR_DEV;
724 } else if (flags & NV_CPB_RESP_CPB_ERR) {
725 ata_ehi_push_desc(ehi, ": CPB error");
726 ehi->err_mask |= AC_ERR_SYSTEM;
727 freeze = 1;
728 } else {
729 /* notifier error, but no error in CPB flags? */
730 ehi->err_mask |= AC_ERR_OTHER;
731 freeze = 1;
732 }
733 /* Kill all commands. EH will determine what actually failed. */
734 if (freeze)
735 ata_port_freeze(ap);
736 else
737 ata_port_abort(ap);
738 return 1;
739 }
740
741 if (likely(flags & NV_CPB_RESP_DONE)) {
742 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, cpb_num);
743 VPRINTK("CPB flags done, flags=0x%x\n", flags);
744 if (likely(qc)) {
745 DPRINTK("Completing qc from tag %d\n",cpb_num);
746 ata_qc_complete(qc);
747 } else {
748 struct ata_eh_info *ehi = &ap->eh_info;
749 /* Notifier bits set without a command may indicate the drive
750 is misbehaving. Raise host state machine violation on this
751 condition. */
752 ata_port_printk(ap, KERN_ERR, "notifier for tag %d with no command?\n",
753 cpb_num);
754 ehi->err_mask |= AC_ERR_HSM;
755 ehi->action |= ATA_EH_SOFTRESET;
756 ata_port_freeze(ap);
757 return 1;
758 }
759 }
760 return 0;
761 }
762
763 static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
764 {
765 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
766
767 /* freeze if hotplugged */
768 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
769 ata_port_freeze(ap);
770 return 1;
771 }
772
773 /* bail out if not our interrupt */
774 if (!(irq_stat & NV_INT_DEV))
775 return 0;
776
777 /* DEV interrupt w/ no active qc? */
778 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
779 ata_check_status(ap);
780 return 1;
781 }
782
783 /* handle interrupt */
784 return ata_host_intr(ap, qc);
785 }
786
787 static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
788 {
789 struct ata_host *host = dev_instance;
790 int i, handled = 0;
791 u32 notifier_clears[2];
792
793 spin_lock(&host->lock);
794
795 for (i = 0; i < host->n_ports; i++) {
796 struct ata_port *ap = host->ports[i];
797 notifier_clears[i] = 0;
798
799 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
800 struct nv_adma_port_priv *pp = ap->private_data;
801 void __iomem *mmio = pp->ctl_block;
802 u16 status;
803 u32 gen_ctl;
804 u32 notifier, notifier_error;
805
806 /* if ADMA is disabled, use standard ata interrupt handler */
807 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
808 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
809 >> (NV_INT_PORT_SHIFT * i);
810 handled += nv_host_intr(ap, irq_stat);
811 continue;
812 }
813
814 /* if in ATA register mode, check for standard interrupts */
815 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
816 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
817 >> (NV_INT_PORT_SHIFT * i);
818 if(ata_tag_valid(ap->active_tag))
819 /** NV_INT_DEV indication seems unreliable at times
820 at least in ADMA mode. Force it on always when a
821 command is active, to prevent losing interrupts. */
822 irq_stat |= NV_INT_DEV;
823 handled += nv_host_intr(ap, irq_stat);
824 }
825
826 notifier = readl(mmio + NV_ADMA_NOTIFIER);
827 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
828 notifier_clears[i] = notifier | notifier_error;
829
830 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
831
832 if( !NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
833 !notifier_error)
834 /* Nothing to do */
835 continue;
836
837 status = readw(mmio + NV_ADMA_STAT);
838
839 /* Clear status. Ensure the controller sees the clearing before we start
840 looking at any of the CPB statuses, so that any CPB completions after
841 this point in the handler will raise another interrupt. */
842 writew(status, mmio + NV_ADMA_STAT);
843 readw(mmio + NV_ADMA_STAT); /* flush posted write */
844 rmb();
845
846 handled++; /* irq handled if we got here */
847
848 /* freeze if hotplugged or controller error */
849 if (unlikely(status & (NV_ADMA_STAT_HOTPLUG |
850 NV_ADMA_STAT_HOTUNPLUG |
851 NV_ADMA_STAT_TIMEOUT |
852 NV_ADMA_STAT_SERROR))) {
853 struct ata_eh_info *ehi = &ap->eh_info;
854
855 ata_ehi_clear_desc(ehi);
856 ata_ehi_push_desc(ehi, "ADMA status 0x%08x", status );
857 if (status & NV_ADMA_STAT_TIMEOUT) {
858 ehi->err_mask |= AC_ERR_SYSTEM;
859 ata_ehi_push_desc(ehi, ": timeout");
860 } else if (status & NV_ADMA_STAT_HOTPLUG) {
861 ata_ehi_hotplugged(ehi);
862 ata_ehi_push_desc(ehi, ": hotplug");
863 } else if (status & NV_ADMA_STAT_HOTUNPLUG) {
864 ata_ehi_hotplugged(ehi);
865 ata_ehi_push_desc(ehi, ": hot unplug");
866 } else if (status & NV_ADMA_STAT_SERROR) {
867 /* let libata analyze SError and figure out the cause */
868 ata_ehi_push_desc(ehi, ": SError");
869 }
870 ata_port_freeze(ap);
871 continue;
872 }
873
874 if (status & (NV_ADMA_STAT_DONE |
875 NV_ADMA_STAT_CPBERR)) {
876 u32 check_commands;
877 int pos, error = 0;
878
879 if(ata_tag_valid(ap->active_tag))
880 check_commands = 1 << ap->active_tag;
881 else
882 check_commands = ap->sactive;
883
884 /** Check CPBs for completed commands */
885 while ((pos = ffs(check_commands)) && !error) {
886 pos--;
887 error = nv_adma_check_cpb(ap, pos,
888 notifier_error & (1 << pos) );
889 check_commands &= ~(1 << pos );
890 }
891 }
892 }
893 }
894
895 if(notifier_clears[0] || notifier_clears[1]) {
896 /* Note: Both notifier clear registers must be written
897 if either is set, even if one is zero, according to NVIDIA. */
898 struct nv_adma_port_priv *pp = host->ports[0]->private_data;
899 writel(notifier_clears[0], pp->notifier_clear_block);
900 pp = host->ports[1]->private_data;
901 writel(notifier_clears[1], pp->notifier_clear_block);
902 }
903
904 spin_unlock(&host->lock);
905
906 return IRQ_RETVAL(handled);
907 }
908
909 static void nv_adma_freeze(struct ata_port *ap)
910 {
911 struct nv_adma_port_priv *pp = ap->private_data;
912 void __iomem *mmio = pp->ctl_block;
913 u16 tmp;
914
915 nv_ck804_freeze(ap);
916
917 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
918 return;
919
920 /* clear any outstanding CK804 notifications */
921 writeb( NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
922 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
923
924 /* Disable interrupt */
925 tmp = readw(mmio + NV_ADMA_CTL);
926 writew( tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
927 mmio + NV_ADMA_CTL);
928 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
929 }
930
931 static void nv_adma_thaw(struct ata_port *ap)
932 {
933 struct nv_adma_port_priv *pp = ap->private_data;
934 void __iomem *mmio = pp->ctl_block;
935 u16 tmp;
936
937 nv_ck804_thaw(ap);
938
939 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
940 return;
941
942 /* Enable interrupt */
943 tmp = readw(mmio + NV_ADMA_CTL);
944 writew( tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
945 mmio + NV_ADMA_CTL);
946 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
947 }
948
949 static void nv_adma_irq_clear(struct ata_port *ap)
950 {
951 struct nv_adma_port_priv *pp = ap->private_data;
952 void __iomem *mmio = pp->ctl_block;
953 u32 notifier_clears[2];
954
955 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
956 ata_bmdma_irq_clear(ap);
957 return;
958 }
959
960 /* clear any outstanding CK804 notifications */
961 writeb( NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
962 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
963
964 /* clear ADMA status */
965 writew(0xffff, mmio + NV_ADMA_STAT);
966
967 /* clear notifiers - note both ports need to be written with
968 something even though we are only clearing on one */
969 if (ap->port_no == 0) {
970 notifier_clears[0] = 0xFFFFFFFF;
971 notifier_clears[1] = 0;
972 } else {
973 notifier_clears[0] = 0;
974 notifier_clears[1] = 0xFFFFFFFF;
975 }
976 pp = ap->host->ports[0]->private_data;
977 writel(notifier_clears[0], pp->notifier_clear_block);
978 pp = ap->host->ports[1]->private_data;
979 writel(notifier_clears[1], pp->notifier_clear_block);
980 }
981
982 static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc)
983 {
984 struct nv_adma_port_priv *pp = qc->ap->private_data;
985
986 if(pp->flags & NV_ADMA_PORT_REGISTER_MODE)
987 ata_bmdma_post_internal_cmd(qc);
988 }
989
990 static int nv_adma_port_start(struct ata_port *ap)
991 {
992 struct device *dev = ap->host->dev;
993 struct nv_adma_port_priv *pp;
994 int rc;
995 void *mem;
996 dma_addr_t mem_dma;
997 void __iomem *mmio;
998 u16 tmp;
999
1000 VPRINTK("ENTER\n");
1001
1002 rc = ata_port_start(ap);
1003 if (rc)
1004 return rc;
1005
1006 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1007 if (!pp)
1008 return -ENOMEM;
1009
1010 mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT +
1011 ap->port_no * NV_ADMA_PORT_SIZE;
1012 pp->ctl_block = mmio;
1013 pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN;
1014 pp->notifier_clear_block = pp->gen_block +
1015 NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no);
1016
1017 mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
1018 &mem_dma, GFP_KERNEL);
1019 if (!mem)
1020 return -ENOMEM;
1021 memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ);
1022
1023 /*
1024 * First item in chunk of DMA memory:
1025 * 128-byte command parameter block (CPB)
1026 * one for each command tag
1027 */
1028 pp->cpb = mem;
1029 pp->cpb_dma = mem_dma;
1030
1031 writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
1032 writel((mem_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
1033
1034 mem += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1035 mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1036
1037 /*
1038 * Second item: block of ADMA_SGTBL_LEN s/g entries
1039 */
1040 pp->aprd = mem;
1041 pp->aprd_dma = mem_dma;
1042
1043 ap->private_data = pp;
1044
1045 /* clear any outstanding interrupt conditions */
1046 writew(0xffff, mmio + NV_ADMA_STAT);
1047
1048 /* initialize port variables */
1049 pp->flags = NV_ADMA_PORT_REGISTER_MODE;
1050
1051 /* clear CPB fetch count */
1052 writew(0, mmio + NV_ADMA_CPB_COUNT);
1053
1054 /* clear GO for register mode, enable interrupt */
1055 tmp = readw(mmio + NV_ADMA_CTL);
1056 writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1057 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
1058
1059 tmp = readw(mmio + NV_ADMA_CTL);
1060 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1061 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1062 udelay(1);
1063 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1064 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1065
1066 return 0;
1067 }
1068
1069 static void nv_adma_port_stop(struct ata_port *ap)
1070 {
1071 struct nv_adma_port_priv *pp = ap->private_data;
1072 void __iomem *mmio = pp->ctl_block;
1073
1074 VPRINTK("ENTER\n");
1075 writew(0, mmio + NV_ADMA_CTL);
1076 }
1077
1078 #ifdef CONFIG_PM
1079 static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg)
1080 {
1081 struct nv_adma_port_priv *pp = ap->private_data;
1082 void __iomem *mmio = pp->ctl_block;
1083
1084 /* Go to register mode - clears GO */
1085 nv_adma_register_mode(ap);
1086
1087 /* clear CPB fetch count */
1088 writew(0, mmio + NV_ADMA_CPB_COUNT);
1089
1090 /* disable interrupt, shut down port */
1091 writew(0, mmio + NV_ADMA_CTL);
1092
1093 return 0;
1094 }
1095
1096 static int nv_adma_port_resume(struct ata_port *ap)
1097 {
1098 struct nv_adma_port_priv *pp = ap->private_data;
1099 void __iomem *mmio = pp->ctl_block;
1100 u16 tmp;
1101
1102 /* set CPB block location */
1103 writel(pp->cpb_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
1104 writel((pp->cpb_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
1105
1106 /* clear any outstanding interrupt conditions */
1107 writew(0xffff, mmio + NV_ADMA_STAT);
1108
1109 /* initialize port variables */
1110 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
1111
1112 /* clear CPB fetch count */
1113 writew(0, mmio + NV_ADMA_CPB_COUNT);
1114
1115 /* clear GO for register mode, enable interrupt */
1116 tmp = readw(mmio + NV_ADMA_CTL);
1117 writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1118 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
1119
1120 tmp = readw(mmio + NV_ADMA_CTL);
1121 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1122 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1123 udelay(1);
1124 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1125 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1126
1127 return 0;
1128 }
1129 #endif
1130
1131 static void nv_adma_setup_port(struct ata_port *ap)
1132 {
1133 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1134 struct ata_ioports *ioport = &ap->ioaddr;
1135
1136 VPRINTK("ENTER\n");
1137
1138 mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE;
1139
1140 ioport->cmd_addr = mmio;
1141 ioport->data_addr = mmio + (ATA_REG_DATA * 4);
1142 ioport->error_addr =
1143 ioport->feature_addr = mmio + (ATA_REG_ERR * 4);
1144 ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4);
1145 ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4);
1146 ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4);
1147 ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4);
1148 ioport->device_addr = mmio + (ATA_REG_DEVICE * 4);
1149 ioport->status_addr =
1150 ioport->command_addr = mmio + (ATA_REG_STATUS * 4);
1151 ioport->altstatus_addr =
1152 ioport->ctl_addr = mmio + 0x20;
1153 }
1154
1155 static int nv_adma_host_init(struct ata_host *host)
1156 {
1157 struct pci_dev *pdev = to_pci_dev(host->dev);
1158 unsigned int i;
1159 u32 tmp32;
1160
1161 VPRINTK("ENTER\n");
1162
1163 /* enable ADMA on the ports */
1164 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1165 tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
1166 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1167 NV_MCP_SATA_CFG_20_PORT1_EN |
1168 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
1169
1170 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1171
1172 for (i = 0; i < host->n_ports; i++)
1173 nv_adma_setup_port(host->ports[i]);
1174
1175 return 0;
1176 }
1177
1178 static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
1179 struct scatterlist *sg,
1180 int idx,
1181 struct nv_adma_prd *aprd)
1182 {
1183 u8 flags = 0;
1184 if (qc->tf.flags & ATA_TFLAG_WRITE)
1185 flags |= NV_APRD_WRITE;
1186 if (idx == qc->n_elem - 1)
1187 flags |= NV_APRD_END;
1188 else if (idx != 4)
1189 flags |= NV_APRD_CONT;
1190
1191 aprd->addr = cpu_to_le64(((u64)sg_dma_address(sg)));
1192 aprd->len = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */
1193 aprd->flags = flags;
1194 aprd->packet_len = 0;
1195 }
1196
1197 static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
1198 {
1199 struct nv_adma_port_priv *pp = qc->ap->private_data;
1200 unsigned int idx;
1201 struct nv_adma_prd *aprd;
1202 struct scatterlist *sg;
1203
1204 VPRINTK("ENTER\n");
1205
1206 idx = 0;
1207
1208 ata_for_each_sg(sg, qc) {
1209 aprd = (idx < 5) ? &cpb->aprd[idx] : &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (idx-5)];
1210 nv_adma_fill_aprd(qc, sg, idx, aprd);
1211 idx++;
1212 }
1213 if (idx > 5)
1214 cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
1215 else
1216 cpb->next_aprd = cpu_to_le64(0);
1217 }
1218
1219 static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
1220 {
1221 struct nv_adma_port_priv *pp = qc->ap->private_data;
1222
1223 /* ADMA engine can only be used for non-ATAPI DMA commands,
1224 or interrupt-driven no-data commands, where a result taskfile
1225 is not required. */
1226 if((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
1227 (qc->tf.flags & ATA_TFLAG_POLLING) ||
1228 (qc->flags & ATA_QCFLAG_RESULT_TF))
1229 return 1;
1230
1231 if((qc->flags & ATA_QCFLAG_DMAMAP) ||
1232 (qc->tf.protocol == ATA_PROT_NODATA))
1233 return 0;
1234
1235 return 1;
1236 }
1237
1238 static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
1239 {
1240 struct nv_adma_port_priv *pp = qc->ap->private_data;
1241 struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
1242 u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
1243 NV_CPB_CTL_IEN;
1244
1245 if (nv_adma_use_reg_mode(qc)) {
1246 nv_adma_register_mode(qc->ap);
1247 ata_qc_prep(qc);
1248 return;
1249 }
1250
1251 cpb->resp_flags = NV_CPB_RESP_DONE;
1252 wmb();
1253 cpb->ctl_flags = 0;
1254 wmb();
1255
1256 cpb->len = 3;
1257 cpb->tag = qc->tag;
1258 cpb->next_cpb_idx = 0;
1259
1260 /* turn on NCQ flags for NCQ commands */
1261 if (qc->tf.protocol == ATA_PROT_NCQ)
1262 ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;
1263
1264 VPRINTK("qc->flags = 0x%lx\n", qc->flags);
1265
1266 nv_adma_tf_to_cpb(&qc->tf, cpb->tf);
1267
1268 if(qc->flags & ATA_QCFLAG_DMAMAP) {
1269 nv_adma_fill_sg(qc, cpb);
1270 ctl_flags |= NV_CPB_CTL_APRD_VALID;
1271 } else
1272 memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5);
1273
1274 /* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID until we are
1275 finished filling in all of the contents */
1276 wmb();
1277 cpb->ctl_flags = ctl_flags;
1278 wmb();
1279 cpb->resp_flags = 0;
1280 }
1281
1282 static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
1283 {
1284 struct nv_adma_port_priv *pp = qc->ap->private_data;
1285 void __iomem *mmio = pp->ctl_block;
1286 int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ);
1287
1288 VPRINTK("ENTER\n");
1289
1290 if (nv_adma_use_reg_mode(qc)) {
1291 /* use ATA register mode */
1292 VPRINTK("using ATA register mode: 0x%lx\n", qc->flags);
1293 nv_adma_register_mode(qc->ap);
1294 return ata_qc_issue_prot(qc);
1295 } else
1296 nv_adma_mode(qc->ap);
1297
1298 /* write append register, command tag in lower 8 bits
1299 and (number of cpbs to append -1) in top 8 bits */
1300 wmb();
1301
1302 if(curr_ncq != pp->last_issue_ncq) {
1303 /* Seems to need some delay before switching between NCQ and non-NCQ
1304 commands, else we get command timeouts and such. */
1305 udelay(20);
1306 pp->last_issue_ncq = curr_ncq;
1307 }
1308
1309 writew(qc->tag, mmio + NV_ADMA_APPEND);
1310
1311 DPRINTK("Issued tag %u\n",qc->tag);
1312
1313 return 0;
1314 }
1315
1316 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
1317 {
1318 struct ata_host *host = dev_instance;
1319 unsigned int i;
1320 unsigned int handled = 0;
1321 unsigned long flags;
1322
1323 spin_lock_irqsave(&host->lock, flags);
1324
1325 for (i = 0; i < host->n_ports; i++) {
1326 struct ata_port *ap;
1327
1328 ap = host->ports[i];
1329 if (ap &&
1330 !(ap->flags & ATA_FLAG_DISABLED)) {
1331 struct ata_queued_cmd *qc;
1332
1333 qc = ata_qc_from_tag(ap, ap->active_tag);
1334 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1335 handled += ata_host_intr(ap, qc);
1336 else
1337 // No request pending? Clear interrupt status
1338 // anyway, in case there's one pending.
1339 ap->ops->check_status(ap);
1340 }
1341
1342 }
1343
1344 spin_unlock_irqrestore(&host->lock, flags);
1345
1346 return IRQ_RETVAL(handled);
1347 }
1348
1349 static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
1350 {
1351 int i, handled = 0;
1352
1353 for (i = 0; i < host->n_ports; i++) {
1354 struct ata_port *ap = host->ports[i];
1355
1356 if (ap && !(ap->flags & ATA_FLAG_DISABLED))
1357 handled += nv_host_intr(ap, irq_stat);
1358
1359 irq_stat >>= NV_INT_PORT_SHIFT;
1360 }
1361
1362 return IRQ_RETVAL(handled);
1363 }
1364
1365 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance)
1366 {
1367 struct ata_host *host = dev_instance;
1368 u8 irq_stat;
1369 irqreturn_t ret;
1370
1371 spin_lock(&host->lock);
1372 irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
1373 ret = nv_do_interrupt(host, irq_stat);
1374 spin_unlock(&host->lock);
1375
1376 return ret;
1377 }
1378
1379 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance)
1380 {
1381 struct ata_host *host = dev_instance;
1382 u8 irq_stat;
1383 irqreturn_t ret;
1384
1385 spin_lock(&host->lock);
1386 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
1387 ret = nv_do_interrupt(host, irq_stat);
1388 spin_unlock(&host->lock);
1389
1390 return ret;
1391 }
1392
1393 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
1394 {
1395 if (sc_reg > SCR_CONTROL)
1396 return 0xffffffffU;
1397
1398 return ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
1399 }
1400
1401 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
1402 {
1403 if (sc_reg > SCR_CONTROL)
1404 return;
1405
1406 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
1407 }
1408
1409 static void nv_nf2_freeze(struct ata_port *ap)
1410 {
1411 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
1412 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1413 u8 mask;
1414
1415 mask = ioread8(scr_addr + NV_INT_ENABLE);
1416 mask &= ~(NV_INT_ALL << shift);
1417 iowrite8(mask, scr_addr + NV_INT_ENABLE);
1418 }
1419
1420 static void nv_nf2_thaw(struct ata_port *ap)
1421 {
1422 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
1423 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1424 u8 mask;
1425
1426 iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
1427
1428 mask = ioread8(scr_addr + NV_INT_ENABLE);
1429 mask |= (NV_INT_MASK << shift);
1430 iowrite8(mask, scr_addr + NV_INT_ENABLE);
1431 }
1432
1433 static void nv_ck804_freeze(struct ata_port *ap)
1434 {
1435 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1436 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1437 u8 mask;
1438
1439 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1440 mask &= ~(NV_INT_ALL << shift);
1441 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1442 }
1443
1444 static void nv_ck804_thaw(struct ata_port *ap)
1445 {
1446 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1447 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1448 u8 mask;
1449
1450 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
1451
1452 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1453 mask |= (NV_INT_MASK << shift);
1454 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1455 }
1456
1457 static int nv_hardreset(struct ata_port *ap, unsigned int *class,
1458 unsigned long deadline)
1459 {
1460 unsigned int dummy;
1461
1462 /* SATA hardreset fails to retrieve proper device signature on
1463 * some controllers. Don't classify on hardreset. For more
1464 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
1465 */
1466 return sata_std_hardreset(ap, &dummy, deadline);
1467 }
1468
1469 static void nv_error_handler(struct ata_port *ap)
1470 {
1471 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1472 nv_hardreset, ata_std_postreset);
1473 }
1474
1475 static void nv_adma_error_handler(struct ata_port *ap)
1476 {
1477 struct nv_adma_port_priv *pp = ap->private_data;
1478 if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
1479 void __iomem *mmio = pp->ctl_block;
1480 int i;
1481 u16 tmp;
1482
1483 if(ata_tag_valid(ap->active_tag) || ap->sactive) {
1484 u32 notifier = readl(mmio + NV_ADMA_NOTIFIER);
1485 u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
1486 u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
1487 u32 status = readw(mmio + NV_ADMA_STAT);
1488 u8 cpb_count = readb(mmio + NV_ADMA_CPB_COUNT);
1489 u8 next_cpb_idx = readb(mmio + NV_ADMA_NEXT_CPB_IDX);
1490
1491 ata_port_printk(ap, KERN_ERR, "EH in ADMA mode, notifier 0x%X "
1492 "notifier_error 0x%X gen_ctl 0x%X status 0x%X "
1493 "next cpb count 0x%X next cpb idx 0x%x\n",
1494 notifier, notifier_error, gen_ctl, status,
1495 cpb_count, next_cpb_idx);
1496
1497 for( i=0;i<NV_ADMA_MAX_CPBS;i++) {
1498 struct nv_adma_cpb *cpb = &pp->cpb[i];
1499 if( (ata_tag_valid(ap->active_tag) && i == ap->active_tag) ||
1500 ap->sactive & (1 << i) )
1501 ata_port_printk(ap, KERN_ERR,
1502 "CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n",
1503 i, cpb->ctl_flags, cpb->resp_flags);
1504 }
1505 }
1506
1507 /* Push us back into port register mode for error handling. */
1508 nv_adma_register_mode(ap);
1509
1510 /* Mark all of the CPBs as invalid to prevent them from being executed */
1511 for( i=0;i<NV_ADMA_MAX_CPBS;i++)
1512 pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID;
1513
1514 /* clear CPB fetch count */
1515 writew(0, mmio + NV_ADMA_CPB_COUNT);
1516
1517 /* Reset channel */
1518 tmp = readw(mmio + NV_ADMA_CTL);
1519 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1520 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1521 udelay(1);
1522 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1523 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1524 }
1525
1526 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1527 nv_hardreset, ata_std_postreset);
1528 }
1529
1530 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1531 {
1532 static int printed_version = 0;
1533 const struct ata_port_info *ppi[] = { NULL, NULL };
1534 struct ata_host *host;
1535 struct nv_host_priv *hpriv;
1536 int rc;
1537 u32 bar;
1538 void __iomem *base;
1539 unsigned long type = ent->driver_data;
1540
1541 // Make sure this is a SATA controller by counting the number of bars
1542 // (NVIDIA SATA controllers will always have six bars). Otherwise,
1543 // it's an IDE controller and we ignore it.
1544 for (bar=0; bar<6; bar++)
1545 if (pci_resource_start(pdev, bar) == 0)
1546 return -ENODEV;
1547
1548 if (!printed_version++)
1549 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1550
1551 rc = pcim_enable_device(pdev);
1552 if (rc)
1553 return rc;
1554
1555 /* determine type and allocate host */
1556 if (type >= CK804 && adma_enabled) {
1557 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
1558 type = ADMA;
1559 }
1560
1561 ppi[0] = &nv_port_info[type];
1562 rc = ata_pci_prepare_native_host(pdev, ppi, &host);
1563 if (rc)
1564 return rc;
1565
1566 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1567 if (!hpriv)
1568 return -ENOMEM;
1569 hpriv->type = type;
1570 host->private_data = hpriv;
1571
1572 /* set 64bit dma masks, may fail */
1573 if (type == ADMA) {
1574 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0)
1575 pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1576 }
1577
1578 /* request and iomap NV_MMIO_BAR */
1579 rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME);
1580 if (rc)
1581 return rc;
1582
1583 /* configure SCR access */
1584 base = host->iomap[NV_MMIO_BAR];
1585 host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
1586 host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
1587
1588 /* enable SATA space for CK804 */
1589 if (type >= CK804) {
1590 u8 regval;
1591
1592 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1593 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1594 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1595 }
1596
1597 /* init ADMA */
1598 if (type == ADMA) {
1599 rc = nv_adma_host_init(host);
1600 if (rc)
1601 return rc;
1602 }
1603
1604 pci_set_master(pdev);
1605 return ata_host_activate(host, pdev->irq, ppi[0]->irq_handler,
1606 IRQF_SHARED, ppi[0]->sht);
1607 }
1608
1609 #ifdef CONFIG_PM
1610 static int nv_pci_device_resume(struct pci_dev *pdev)
1611 {
1612 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1613 struct nv_host_priv *hpriv = host->private_data;
1614 int rc;
1615
1616 rc = ata_pci_device_do_resume(pdev);
1617 if(rc)
1618 return rc;
1619
1620 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1621 if(hpriv->type >= CK804) {
1622 u8 regval;
1623
1624 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1625 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1626 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1627 }
1628 if(hpriv->type == ADMA) {
1629 u32 tmp32;
1630 struct nv_adma_port_priv *pp;
1631 /* enable/disable ADMA on the ports appropriately */
1632 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1633
1634 pp = host->ports[0]->private_data;
1635 if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1636 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
1637 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
1638 else
1639 tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN |
1640 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
1641 pp = host->ports[1]->private_data;
1642 if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1643 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN |
1644 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1645 else
1646 tmp32 |= (NV_MCP_SATA_CFG_20_PORT1_EN |
1647 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1648
1649 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1650 }
1651 }
1652
1653 ata_host_resume(host);
1654
1655 return 0;
1656 }
1657 #endif
1658
1659 static void nv_ck804_host_stop(struct ata_host *host)
1660 {
1661 struct pci_dev *pdev = to_pci_dev(host->dev);
1662 u8 regval;
1663
1664 /* disable SATA space for CK804 */
1665 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1666 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1667 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1668 }
1669
1670 static void nv_adma_host_stop(struct ata_host *host)
1671 {
1672 struct pci_dev *pdev = to_pci_dev(host->dev);
1673 u32 tmp32;
1674
1675 /* disable ADMA on the ports */
1676 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1677 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
1678 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1679 NV_MCP_SATA_CFG_20_PORT1_EN |
1680 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1681
1682 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1683
1684 nv_ck804_host_stop(host);
1685 }
1686
1687 static int __init nv_init(void)
1688 {
1689 return pci_register_driver(&nv_pci_driver);
1690 }
1691
1692 static void __exit nv_exit(void)
1693 {
1694 pci_unregister_driver(&nv_pci_driver);
1695 }
1696
1697 module_init(nv_init);
1698 module_exit(nv_exit);
1699 module_param_named(adma, adma_enabled, bool, 0444);
1700 MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: true)");
Linux kernel - Deliverables
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