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[deliverable/linux.git] / drivers / ata / sata_qstor.c
1 /*
2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; see the file COPYING. If not, write to
22 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 *
25 * libata documentation is available via 'make {ps|pdf}docs',
26 * as Documentation/DocBook/libata.*
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/device.h>
38 #include <scsi/scsi_host.h>
39 #include <linux/libata.h>
40
41 #define DRV_NAME "sata_qstor"
42 #define DRV_VERSION "0.09"
43
44 enum {
45 QS_MMIO_BAR = 4,
46
47 QS_PORTS = 4,
48 QS_MAX_PRD = LIBATA_MAX_PRD,
49 QS_CPB_ORDER = 6,
50 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
51 QS_PRD_BYTES = QS_MAX_PRD * 16,
52 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
53
54 /* global register offsets */
55 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
56 QS_HID_HPHY = 0x0004, /* host physical interface info */
57 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
58 QS_HST_SFF = 0x0100, /* host status fifo offset */
59 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
60
61 /* global control bits */
62 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
63 QS_CNFG3_GSRST = 0x01, /* global chip reset */
64 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
65
66 /* per-channel register offsets */
67 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
68 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
69 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
70 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
71 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
72 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
73 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
74 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
75 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
76
77 /* channel control bits */
78 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
79 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
80 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
81 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
82 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
83
84 /* pkt sub-field headers */
85 QS_HCB_HDR = 0x01, /* Host Control Block header */
86 QS_DCB_HDR = 0x02, /* Device Control Block header */
87
88 /* pkt HCB flag bits */
89 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
90 QS_HF_DAT = (1 << 3), /* DATa pkt */
91 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
92 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
93
94 /* pkt DCB flag bits */
95 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
96 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
97
98 /* PCI device IDs */
99 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
100 };
101
102 enum {
103 QS_DMA_BOUNDARY = ~0UL
104 };
105
106 typedef enum { qs_state_mmio, qs_state_pkt } qs_state_t;
107
108 struct qs_port_priv {
109 u8 *pkt;
110 dma_addr_t pkt_dma;
111 qs_state_t state;
112 };
113
114 static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
115 static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
116 static int qs_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
117 static int qs_port_start(struct ata_port *ap);
118 static void qs_host_stop(struct ata_host *host);
119 static void qs_qc_prep(struct ata_queued_cmd *qc);
120 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
121 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
122 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
123 static u8 qs_bmdma_status(struct ata_port *ap);
124 static void qs_freeze(struct ata_port *ap);
125 static void qs_thaw(struct ata_port *ap);
126 static void qs_error_handler(struct ata_port *ap);
127
128 static struct scsi_host_template qs_ata_sht = {
129 .module = THIS_MODULE,
130 .name = DRV_NAME,
131 .ioctl = ata_scsi_ioctl,
132 .queuecommand = ata_scsi_queuecmd,
133 .can_queue = ATA_DEF_QUEUE,
134 .this_id = ATA_SHT_THIS_ID,
135 .sg_tablesize = QS_MAX_PRD,
136 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
137 .emulated = ATA_SHT_EMULATED,
138 .use_clustering = ENABLE_CLUSTERING,
139 .proc_name = DRV_NAME,
140 .dma_boundary = QS_DMA_BOUNDARY,
141 .slave_configure = ata_scsi_slave_config,
142 .slave_destroy = ata_scsi_slave_destroy,
143 .bios_param = ata_std_bios_param,
144 };
145
146 static const struct ata_port_operations qs_ata_ops = {
147 .tf_load = ata_tf_load,
148 .tf_read = ata_tf_read,
149 .check_status = ata_check_status,
150 .check_atapi_dma = qs_check_atapi_dma,
151 .exec_command = ata_exec_command,
152 .dev_select = ata_std_dev_select,
153 .qc_prep = qs_qc_prep,
154 .qc_issue = qs_qc_issue,
155 .data_xfer = ata_data_xfer,
156 .freeze = qs_freeze,
157 .thaw = qs_thaw,
158 .error_handler = qs_error_handler,
159 .irq_clear = ata_noop_irq_clear,
160 .irq_on = ata_irq_on,
161 .scr_read = qs_scr_read,
162 .scr_write = qs_scr_write,
163 .port_start = qs_port_start,
164 .host_stop = qs_host_stop,
165 .bmdma_stop = qs_bmdma_stop,
166 .bmdma_status = qs_bmdma_status,
167 };
168
169 static const struct ata_port_info qs_port_info[] = {
170 /* board_2068_idx */
171 {
172 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
173 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
174 .pio_mask = 0x10, /* pio4 */
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &qs_ata_ops,
177 },
178 };
179
180 static const struct pci_device_id qs_ata_pci_tbl[] = {
181 { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
182
183 { } /* terminate list */
184 };
185
186 static struct pci_driver qs_ata_pci_driver = {
187 .name = DRV_NAME,
188 .id_table = qs_ata_pci_tbl,
189 .probe = qs_ata_init_one,
190 .remove = ata_pci_remove_one,
191 };
192
193 static void __iomem *qs_mmio_base(struct ata_host *host)
194 {
195 return host->iomap[QS_MMIO_BAR];
196 }
197
198 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
199 {
200 return 1; /* ATAPI DMA not supported */
201 }
202
203 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
204 {
205 /* nothing */
206 }
207
208 static u8 qs_bmdma_status(struct ata_port *ap)
209 {
210 return 0;
211 }
212
213 static inline void qs_enter_reg_mode(struct ata_port *ap)
214 {
215 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
216 struct qs_port_priv *pp = ap->private_data;
217
218 pp->state = qs_state_mmio;
219 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
220 readb(chan + QS_CCT_CTR0); /* flush */
221 }
222
223 static inline void qs_reset_channel_logic(struct ata_port *ap)
224 {
225 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
226
227 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
228 readb(chan + QS_CCT_CTR0); /* flush */
229 qs_enter_reg_mode(ap);
230 }
231
232 static void qs_freeze(struct ata_port *ap)
233 {
234 u8 __iomem *mmio_base = qs_mmio_base(ap->host);
235
236 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
237 qs_enter_reg_mode(ap);
238 }
239
240 static void qs_thaw(struct ata_port *ap)
241 {
242 u8 __iomem *mmio_base = qs_mmio_base(ap->host);
243
244 qs_enter_reg_mode(ap);
245 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
246 }
247
248 static int qs_prereset(struct ata_link *link, unsigned long deadline)
249 {
250 struct ata_port *ap = link->ap;
251
252 qs_reset_channel_logic(ap);
253 return ata_std_prereset(link, deadline);
254 }
255
256 static int qs_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
257 {
258 if (sc_reg > SCR_CONTROL)
259 return -EINVAL;
260 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 8));
261 return 0;
262 }
263
264 static void qs_error_handler(struct ata_port *ap)
265 {
266 qs_enter_reg_mode(ap);
267 ata_do_eh(ap, qs_prereset, NULL, sata_std_hardreset,
268 ata_std_postreset);
269 }
270
271 static int qs_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
272 {
273 if (sc_reg > SCR_CONTROL)
274 return -EINVAL;
275 writel(val, ap->ioaddr.scr_addr + (sc_reg * 8));
276 return 0;
277 }
278
279 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
280 {
281 struct scatterlist *sg;
282 struct ata_port *ap = qc->ap;
283 struct qs_port_priv *pp = ap->private_data;
284 u8 *prd = pp->pkt + QS_CPB_BYTES;
285 unsigned int si;
286
287 for_each_sg(qc->sg, sg, qc->n_elem, si) {
288 u64 addr;
289 u32 len;
290
291 addr = sg_dma_address(sg);
292 *(__le64 *)prd = cpu_to_le64(addr);
293 prd += sizeof(u64);
294
295 len = sg_dma_len(sg);
296 *(__le32 *)prd = cpu_to_le32(len);
297 prd += sizeof(u64);
298
299 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", si,
300 (unsigned long long)addr, len);
301 }
302
303 return si;
304 }
305
306 static void qs_qc_prep(struct ata_queued_cmd *qc)
307 {
308 struct qs_port_priv *pp = qc->ap->private_data;
309 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
310 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
311 u64 addr;
312 unsigned int nelem;
313
314 VPRINTK("ENTER\n");
315
316 qs_enter_reg_mode(qc->ap);
317 if (qc->tf.protocol != ATA_PROT_DMA) {
318 ata_qc_prep(qc);
319 return;
320 }
321
322 nelem = qs_fill_sg(qc);
323
324 if ((qc->tf.flags & ATA_TFLAG_WRITE))
325 hflags |= QS_HF_DIRO;
326 if ((qc->tf.flags & ATA_TFLAG_LBA48))
327 dflags |= QS_DF_ELBA;
328
329 /* host control block (HCB) */
330 buf[ 0] = QS_HCB_HDR;
331 buf[ 1] = hflags;
332 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
333 *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
334 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
335 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
336
337 /* device control block (DCB) */
338 buf[24] = QS_DCB_HDR;
339 buf[28] = dflags;
340
341 /* frame information structure (FIS) */
342 ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);
343 }
344
345 static inline void qs_packet_start(struct ata_queued_cmd *qc)
346 {
347 struct ata_port *ap = qc->ap;
348 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
349
350 VPRINTK("ENTER, ap %p\n", ap);
351
352 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
353 wmb(); /* flush PRDs and pkt to memory */
354 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
355 readl(chan + QS_CCT_CFF); /* flush */
356 }
357
358 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
359 {
360 struct qs_port_priv *pp = qc->ap->private_data;
361
362 switch (qc->tf.protocol) {
363 case ATA_PROT_DMA:
364 pp->state = qs_state_pkt;
365 qs_packet_start(qc);
366 return 0;
367
368 case ATAPI_PROT_DMA:
369 BUG();
370 break;
371
372 default:
373 break;
374 }
375
376 pp->state = qs_state_mmio;
377 return ata_qc_issue_prot(qc);
378 }
379
380 static void qs_do_or_die(struct ata_queued_cmd *qc, u8 status)
381 {
382 qc->err_mask |= ac_err_mask(status);
383
384 if (!qc->err_mask) {
385 ata_qc_complete(qc);
386 } else {
387 struct ata_port *ap = qc->ap;
388 struct ata_eh_info *ehi = &ap->link.eh_info;
389
390 ata_ehi_clear_desc(ehi);
391 ata_ehi_push_desc(ehi, "status 0x%02X", status);
392
393 if (qc->err_mask == AC_ERR_DEV)
394 ata_port_abort(ap);
395 else
396 ata_port_freeze(ap);
397 }
398 }
399
400 static inline unsigned int qs_intr_pkt(struct ata_host *host)
401 {
402 unsigned int handled = 0;
403 u8 sFFE;
404 u8 __iomem *mmio_base = qs_mmio_base(host);
405
406 do {
407 u32 sff0 = readl(mmio_base + QS_HST_SFF);
408 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
409 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
410 sFFE = sff1 >> 31; /* empty flag */
411
412 if (sEVLD) {
413 u8 sDST = sff0 >> 16; /* dev status */
414 u8 sHST = sff1 & 0x3f; /* host status */
415 unsigned int port_no = (sff1 >> 8) & 0x03;
416 struct ata_port *ap = host->ports[port_no];
417
418 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
419 sff1, sff0, port_no, sHST, sDST);
420 handled = 1;
421 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
422 struct ata_queued_cmd *qc;
423 struct qs_port_priv *pp = ap->private_data;
424 if (!pp || pp->state != qs_state_pkt)
425 continue;
426 qc = ata_qc_from_tag(ap, ap->link.active_tag);
427 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
428 switch (sHST) {
429 case 0: /* successful CPB */
430 case 3: /* device error */
431 qs_enter_reg_mode(qc->ap);
432 qs_do_or_die(qc, sDST);
433 break;
434 default:
435 break;
436 }
437 }
438 }
439 }
440 } while (!sFFE);
441 return handled;
442 }
443
444 static inline unsigned int qs_intr_mmio(struct ata_host *host)
445 {
446 unsigned int handled = 0, port_no;
447
448 for (port_no = 0; port_no < host->n_ports; ++port_no) {
449 struct ata_port *ap;
450 ap = host->ports[port_no];
451 if (ap &&
452 !(ap->flags & ATA_FLAG_DISABLED)) {
453 struct ata_queued_cmd *qc;
454 struct qs_port_priv *pp;
455 qc = ata_qc_from_tag(ap, ap->link.active_tag);
456 if (!qc || !(qc->flags & ATA_QCFLAG_ACTIVE)) {
457 /*
458 * The qstor hardware generates spurious
459 * interrupts from time to time when switching
460 * in and out of packet mode.
461 * There's no obvious way to know if we're
462 * here now due to that, so just ack the irq
463 * and pretend we knew it was ours.. (ugh).
464 * This does not affect packet mode.
465 */
466 ata_check_status(ap);
467 handled = 1;
468 continue;
469 }
470 pp = ap->private_data;
471 if (!pp || pp->state != qs_state_mmio)
472 continue;
473 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
474 handled |= ata_host_intr(ap, qc);
475 }
476 }
477 return handled;
478 }
479
480 static irqreturn_t qs_intr(int irq, void *dev_instance)
481 {
482 struct ata_host *host = dev_instance;
483 unsigned int handled = 0;
484 unsigned long flags;
485
486 VPRINTK("ENTER\n");
487
488 spin_lock_irqsave(&host->lock, flags);
489 handled = qs_intr_pkt(host) | qs_intr_mmio(host);
490 spin_unlock_irqrestore(&host->lock, flags);
491
492 VPRINTK("EXIT\n");
493
494 return IRQ_RETVAL(handled);
495 }
496
497 static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
498 {
499 port->cmd_addr =
500 port->data_addr = base + 0x400;
501 port->error_addr =
502 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
503 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
504 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
505 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
506 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
507 port->device_addr = base + 0x430;
508 port->status_addr =
509 port->command_addr = base + 0x438;
510 port->altstatus_addr =
511 port->ctl_addr = base + 0x440;
512 port->scr_addr = base + 0xc00;
513 }
514
515 static int qs_port_start(struct ata_port *ap)
516 {
517 struct device *dev = ap->host->dev;
518 struct qs_port_priv *pp;
519 void __iomem *mmio_base = qs_mmio_base(ap->host);
520 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
521 u64 addr;
522 int rc;
523
524 rc = ata_port_start(ap);
525 if (rc)
526 return rc;
527 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
528 if (!pp)
529 return -ENOMEM;
530 pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
531 GFP_KERNEL);
532 if (!pp->pkt)
533 return -ENOMEM;
534 memset(pp->pkt, 0, QS_PKT_BYTES);
535 ap->private_data = pp;
536
537 qs_enter_reg_mode(ap);
538 addr = (u64)pp->pkt_dma;
539 writel((u32) addr, chan + QS_CCF_CPBA);
540 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
541 return 0;
542 }
543
544 static void qs_host_stop(struct ata_host *host)
545 {
546 void __iomem *mmio_base = qs_mmio_base(host);
547
548 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
549 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
550 }
551
552 static void qs_host_init(struct ata_host *host, unsigned int chip_id)
553 {
554 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
555 unsigned int port_no;
556
557 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
558 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
559
560 /* reset each channel in turn */
561 for (port_no = 0; port_no < host->n_ports; ++port_no) {
562 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
563 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
564 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
565 readb(chan + QS_CCT_CTR0); /* flush */
566 }
567 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
568
569 for (port_no = 0; port_no < host->n_ports; ++port_no) {
570 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
571 /* set FIFO depths to same settings as Windows driver */
572 writew(32, chan + QS_CFC_HUFT);
573 writew(32, chan + QS_CFC_HDFT);
574 writew(10, chan + QS_CFC_DUFT);
575 writew( 8, chan + QS_CFC_DDFT);
576 /* set CPB size in bytes, as a power of two */
577 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
578 }
579 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
580 }
581
582 /*
583 * The QStor understands 64-bit buses, and uses 64-bit fields
584 * for DMA pointers regardless of bus width. We just have to
585 * make sure our DMA masks are set appropriately for whatever
586 * bridge lies between us and the QStor, and then the DMA mapping
587 * code will ensure we only ever "see" appropriate buffer addresses.
588 * If we're 32-bit limited somewhere, then our 64-bit fields will
589 * just end up with zeros in the upper 32-bits, without any special
590 * logic required outside of this routine (below).
591 */
592 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
593 {
594 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
595 int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
596
597 if (have_64bit_bus &&
598 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
599 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
600 if (rc) {
601 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
602 if (rc) {
603 dev_printk(KERN_ERR, &pdev->dev,
604 "64-bit DMA enable failed\n");
605 return rc;
606 }
607 }
608 } else {
609 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
610 if (rc) {
611 dev_printk(KERN_ERR, &pdev->dev,
612 "32-bit DMA enable failed\n");
613 return rc;
614 }
615 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
616 if (rc) {
617 dev_printk(KERN_ERR, &pdev->dev,
618 "32-bit consistent DMA enable failed\n");
619 return rc;
620 }
621 }
622 return 0;
623 }
624
625 static int qs_ata_init_one(struct pci_dev *pdev,
626 const struct pci_device_id *ent)
627 {
628 static int printed_version;
629 unsigned int board_idx = (unsigned int) ent->driver_data;
630 const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
631 struct ata_host *host;
632 int rc, port_no;
633
634 if (!printed_version++)
635 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
636
637 /* alloc host */
638 host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
639 if (!host)
640 return -ENOMEM;
641
642 /* acquire resources and fill host */
643 rc = pcim_enable_device(pdev);
644 if (rc)
645 return rc;
646
647 if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
648 return -ENODEV;
649
650 rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
651 if (rc)
652 return rc;
653 host->iomap = pcim_iomap_table(pdev);
654
655 rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
656 if (rc)
657 return rc;
658
659 for (port_no = 0; port_no < host->n_ports; ++port_no) {
660 struct ata_port *ap = host->ports[port_no];
661 unsigned int offset = port_no * 0x4000;
662 void __iomem *chan = host->iomap[QS_MMIO_BAR] + offset;
663
664 qs_ata_setup_port(&ap->ioaddr, chan);
665
666 ata_port_pbar_desc(ap, QS_MMIO_BAR, -1, "mmio");
667 ata_port_pbar_desc(ap, QS_MMIO_BAR, offset, "port");
668 }
669
670 /* initialize adapter */
671 qs_host_init(host, board_idx);
672
673 pci_set_master(pdev);
674 return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
675 &qs_ata_sht);
676 }
677
678 static int __init qs_ata_init(void)
679 {
680 return pci_register_driver(&qs_ata_pci_driver);
681 }
682
683 static void __exit qs_ata_exit(void)
684 {
685 pci_unregister_driver(&qs_ata_pci_driver);
686 }
687
688 MODULE_AUTHOR("Mark Lord");
689 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
690 MODULE_LICENSE("GPL");
691 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
692 MODULE_VERSION(DRV_VERSION);
693
694 module_init(qs_ata_init);
695 module_exit(qs_ata_exit);
Linux kernel - Deliverables
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