projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'master' into 85xx
[deliverable/linux.git] / drivers / ata / sata_qstor.c
1 /*
2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; see the file COPYING. If not, write to
22 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 *
25 * libata documentation is available via 'make {ps|pdf}docs',
26 * as Documentation/DocBook/libata.*
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/sched.h>
38 #include <linux/device.h>
39 #include <scsi/scsi_host.h>
40 #include <linux/libata.h>
41
42 #define DRV_NAME "sata_qstor"
43 #define DRV_VERSION "0.06"
44
45 enum {
46 QS_MMIO_BAR = 4,
47
48 QS_PORTS = 4,
49 QS_MAX_PRD = LIBATA_MAX_PRD,
50 QS_CPB_ORDER = 6,
51 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
52 QS_PRD_BYTES = QS_MAX_PRD * 16,
53 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
54
55 /* global register offsets */
56 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
57 QS_HID_HPHY = 0x0004, /* host physical interface info */
58 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
59 QS_HST_SFF = 0x0100, /* host status fifo offset */
60 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
61
62 /* global control bits */
63 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
64 QS_CNFG3_GSRST = 0x01, /* global chip reset */
65 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
66
67 /* per-channel register offsets */
68 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
69 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
70 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
71 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
72 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
73 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
74 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
75 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
76 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
77
78 /* channel control bits */
79 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
80 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
81 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
82 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
83 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
84
85 /* pkt sub-field headers */
86 QS_HCB_HDR = 0x01, /* Host Control Block header */
87 QS_DCB_HDR = 0x02, /* Device Control Block header */
88
89 /* pkt HCB flag bits */
90 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
91 QS_HF_DAT = (1 << 3), /* DATa pkt */
92 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
93 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
94
95 /* pkt DCB flag bits */
96 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
97 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
98
99 /* PCI device IDs */
100 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
101 };
102
103 enum {
104 QS_DMA_BOUNDARY = ~0UL
105 };
106
107 typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t;
108
109 struct qs_port_priv {
110 u8 *pkt;
111 dma_addr_t pkt_dma;
112 qs_state_t state;
113 };
114
115 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg);
116 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
117 static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
118 static irqreturn_t qs_intr (int irq, void *dev_instance);
119 static int qs_port_start(struct ata_port *ap);
120 static void qs_host_stop(struct ata_host *host);
121 static void qs_phy_reset(struct ata_port *ap);
122 static void qs_qc_prep(struct ata_queued_cmd *qc);
123 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
124 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
125 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
126 static u8 qs_bmdma_status(struct ata_port *ap);
127 static void qs_irq_clear(struct ata_port *ap);
128 static void qs_eng_timeout(struct ata_port *ap);
129
130 static struct scsi_host_template qs_ata_sht = {
131 .module = THIS_MODULE,
132 .name = DRV_NAME,
133 .ioctl = ata_scsi_ioctl,
134 .queuecommand = ata_scsi_queuecmd,
135 .can_queue = ATA_DEF_QUEUE,
136 .this_id = ATA_SHT_THIS_ID,
137 .sg_tablesize = QS_MAX_PRD,
138 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
139 .emulated = ATA_SHT_EMULATED,
140 //FIXME .use_clustering = ATA_SHT_USE_CLUSTERING,
141 .use_clustering = ENABLE_CLUSTERING,
142 .proc_name = DRV_NAME,
143 .dma_boundary = QS_DMA_BOUNDARY,
144 .slave_configure = ata_scsi_slave_config,
145 .slave_destroy = ata_scsi_slave_destroy,
146 .bios_param = ata_std_bios_param,
147 };
148
149 static const struct ata_port_operations qs_ata_ops = {
150 .port_disable = ata_port_disable,
151 .tf_load = ata_tf_load,
152 .tf_read = ata_tf_read,
153 .check_status = ata_check_status,
154 .check_atapi_dma = qs_check_atapi_dma,
155 .exec_command = ata_exec_command,
156 .dev_select = ata_std_dev_select,
157 .phy_reset = qs_phy_reset,
158 .qc_prep = qs_qc_prep,
159 .qc_issue = qs_qc_issue,
160 .data_xfer = ata_data_xfer,
161 .eng_timeout = qs_eng_timeout,
162 .irq_handler = qs_intr,
163 .irq_clear = qs_irq_clear,
164 .irq_on = ata_irq_on,
165 .irq_ack = ata_irq_ack,
166 .scr_read = qs_scr_read,
167 .scr_write = qs_scr_write,
168 .port_start = qs_port_start,
169 .host_stop = qs_host_stop,
170 .bmdma_stop = qs_bmdma_stop,
171 .bmdma_status = qs_bmdma_status,
172 };
173
174 static const struct ata_port_info qs_port_info[] = {
175 /* board_2068_idx */
176 {
177 .sht = &qs_ata_sht,
178 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
179 ATA_FLAG_SATA_RESET |
180 //FIXME ATA_FLAG_SRST |
181 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
182 .pio_mask = 0x10, /* pio4 */
183 .udma_mask = 0x7f, /* udma0-6 */
184 .port_ops = &qs_ata_ops,
185 },
186 };
187
188 static const struct pci_device_id qs_ata_pci_tbl[] = {
189 { PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
190
191 { } /* terminate list */
192 };
193
194 static struct pci_driver qs_ata_pci_driver = {
195 .name = DRV_NAME,
196 .id_table = qs_ata_pci_tbl,
197 .probe = qs_ata_init_one,
198 .remove = ata_pci_remove_one,
199 };
200
201 static void __iomem *qs_mmio_base(struct ata_host *host)
202 {
203 return host->iomap[QS_MMIO_BAR];
204 }
205
206 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
207 {
208 return 1; /* ATAPI DMA not supported */
209 }
210
211 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
212 {
213 /* nothing */
214 }
215
216 static u8 qs_bmdma_status(struct ata_port *ap)
217 {
218 return 0;
219 }
220
221 static void qs_irq_clear(struct ata_port *ap)
222 {
223 /* nothing */
224 }
225
226 static inline void qs_enter_reg_mode(struct ata_port *ap)
227 {
228 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
229
230 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
231 readb(chan + QS_CCT_CTR0); /* flush */
232 }
233
234 static inline void qs_reset_channel_logic(struct ata_port *ap)
235 {
236 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
237
238 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
239 readb(chan + QS_CCT_CTR0); /* flush */
240 qs_enter_reg_mode(ap);
241 }
242
243 static void qs_phy_reset(struct ata_port *ap)
244 {
245 struct qs_port_priv *pp = ap->private_data;
246
247 pp->state = qs_state_idle;
248 qs_reset_channel_logic(ap);
249 sata_phy_reset(ap);
250 }
251
252 static void qs_eng_timeout(struct ata_port *ap)
253 {
254 struct qs_port_priv *pp = ap->private_data;
255
256 if (pp->state != qs_state_idle) /* healthy paranoia */
257 pp->state = qs_state_mmio;
258 qs_reset_channel_logic(ap);
259 ata_eng_timeout(ap);
260 }
261
262 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg)
263 {
264 if (sc_reg > SCR_CONTROL)
265 return ~0U;
266 return readl(ap->ioaddr.scr_addr + (sc_reg * 8));
267 }
268
269 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
270 {
271 if (sc_reg > SCR_CONTROL)
272 return;
273 writel(val, ap->ioaddr.scr_addr + (sc_reg * 8));
274 }
275
276 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
277 {
278 struct scatterlist *sg;
279 struct ata_port *ap = qc->ap;
280 struct qs_port_priv *pp = ap->private_data;
281 unsigned int nelem;
282 u8 *prd = pp->pkt + QS_CPB_BYTES;
283
284 WARN_ON(qc->__sg == NULL);
285 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
286
287 nelem = 0;
288 ata_for_each_sg(sg, qc) {
289 u64 addr;
290 u32 len;
291
292 addr = sg_dma_address(sg);
293 *(__le64 *)prd = cpu_to_le64(addr);
294 prd += sizeof(u64);
295
296 len = sg_dma_len(sg);
297 *(__le32 *)prd = cpu_to_le32(len);
298 prd += sizeof(u64);
299
300 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem,
301 (unsigned long long)addr, len);
302 nelem++;
303 }
304
305 return nelem;
306 }
307
308 static void qs_qc_prep(struct ata_queued_cmd *qc)
309 {
310 struct qs_port_priv *pp = qc->ap->private_data;
311 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
312 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
313 u64 addr;
314 unsigned int nelem;
315
316 VPRINTK("ENTER\n");
317
318 qs_enter_reg_mode(qc->ap);
319 if (qc->tf.protocol != ATA_PROT_DMA) {
320 ata_qc_prep(qc);
321 return;
322 }
323
324 nelem = qs_fill_sg(qc);
325
326 if ((qc->tf.flags & ATA_TFLAG_WRITE))
327 hflags |= QS_HF_DIRO;
328 if ((qc->tf.flags & ATA_TFLAG_LBA48))
329 dflags |= QS_DF_ELBA;
330
331 /* host control block (HCB) */
332 buf[ 0] = QS_HCB_HDR;
333 buf[ 1] = hflags;
334 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nbytes);
335 *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
336 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
337 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
338
339 /* device control block (DCB) */
340 buf[24] = QS_DCB_HDR;
341 buf[28] = dflags;
342
343 /* frame information structure (FIS) */
344 ata_tf_to_fis(&qc->tf, &buf[32], 0);
345 }
346
347 static inline void qs_packet_start(struct ata_queued_cmd *qc)
348 {
349 struct ata_port *ap = qc->ap;
350 u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);
351
352 VPRINTK("ENTER, ap %p\n", ap);
353
354 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
355 wmb(); /* flush PRDs and pkt to memory */
356 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
357 readl(chan + QS_CCT_CFF); /* flush */
358 }
359
360 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
361 {
362 struct qs_port_priv *pp = qc->ap->private_data;
363
364 switch (qc->tf.protocol) {
365 case ATA_PROT_DMA:
366
367 pp->state = qs_state_pkt;
368 qs_packet_start(qc);
369 return 0;
370
371 case ATA_PROT_ATAPI_DMA:
372 BUG();
373 break;
374
375 default:
376 break;
377 }
378
379 pp->state = qs_state_mmio;
380 return ata_qc_issue_prot(qc);
381 }
382
383 static inline unsigned int qs_intr_pkt(struct ata_host *host)
384 {
385 unsigned int handled = 0;
386 u8 sFFE;
387 u8 __iomem *mmio_base = qs_mmio_base(host);
388
389 do {
390 u32 sff0 = readl(mmio_base + QS_HST_SFF);
391 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
392 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
393 sFFE = sff1 >> 31; /* empty flag */
394
395 if (sEVLD) {
396 u8 sDST = sff0 >> 16; /* dev status */
397 u8 sHST = sff1 & 0x3f; /* host status */
398 unsigned int port_no = (sff1 >> 8) & 0x03;
399 struct ata_port *ap = host->ports[port_no];
400
401 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
402 sff1, sff0, port_no, sHST, sDST);
403 handled = 1;
404 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
405 struct ata_queued_cmd *qc;
406 struct qs_port_priv *pp = ap->private_data;
407 if (!pp || pp->state != qs_state_pkt)
408 continue;
409 qc = ata_qc_from_tag(ap, ap->active_tag);
410 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
411 switch (sHST) {
412 case 0: /* successful CPB */
413 case 3: /* device error */
414 pp->state = qs_state_idle;
415 qs_enter_reg_mode(qc->ap);
416 qc->err_mask |= ac_err_mask(sDST);
417 ata_qc_complete(qc);
418 break;
419 default:
420 break;
421 }
422 }
423 }
424 }
425 } while (!sFFE);
426 return handled;
427 }
428
429 static inline unsigned int qs_intr_mmio(struct ata_host *host)
430 {
431 unsigned int handled = 0, port_no;
432
433 for (port_no = 0; port_no < host->n_ports; ++port_no) {
434 struct ata_port *ap;
435 ap = host->ports[port_no];
436 if (ap &&
437 !(ap->flags & ATA_FLAG_DISABLED)) {
438 struct ata_queued_cmd *qc;
439 struct qs_port_priv *pp = ap->private_data;
440 if (!pp || pp->state != qs_state_mmio)
441 continue;
442 qc = ata_qc_from_tag(ap, ap->active_tag);
443 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
444
445 /* check main status, clearing INTRQ */
446 u8 status = ata_check_status(ap);
447 if ((status & ATA_BUSY))
448 continue;
449 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
450 ap->id, qc->tf.protocol, status);
451
452 /* complete taskfile transaction */
453 pp->state = qs_state_idle;
454 qc->err_mask |= ac_err_mask(status);
455 ata_qc_complete(qc);
456 handled = 1;
457 }
458 }
459 }
460 return handled;
461 }
462
463 static irqreturn_t qs_intr(int irq, void *dev_instance)
464 {
465 struct ata_host *host = dev_instance;
466 unsigned int handled = 0;
467
468 VPRINTK("ENTER\n");
469
470 spin_lock(&host->lock);
471 handled = qs_intr_pkt(host) | qs_intr_mmio(host);
472 spin_unlock(&host->lock);
473
474 VPRINTK("EXIT\n");
475
476 return IRQ_RETVAL(handled);
477 }
478
479 static void qs_ata_setup_port(struct ata_ioports *port, void __iomem *base)
480 {
481 port->cmd_addr =
482 port->data_addr = base + 0x400;
483 port->error_addr =
484 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
485 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
486 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
487 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
488 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
489 port->device_addr = base + 0x430;
490 port->status_addr =
491 port->command_addr = base + 0x438;
492 port->altstatus_addr =
493 port->ctl_addr = base + 0x440;
494 port->scr_addr = base + 0xc00;
495 }
496
497 static int qs_port_start(struct ata_port *ap)
498 {
499 struct device *dev = ap->host->dev;
500 struct qs_port_priv *pp;
501 void __iomem *mmio_base = qs_mmio_base(ap->host);
502 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
503 u64 addr;
504 int rc;
505
506 rc = ata_port_start(ap);
507 if (rc)
508 return rc;
509 qs_enter_reg_mode(ap);
510 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
511 if (!pp)
512 return -ENOMEM;
513 pp->pkt = dmam_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
514 GFP_KERNEL);
515 if (!pp->pkt)
516 return -ENOMEM;
517 memset(pp->pkt, 0, QS_PKT_BYTES);
518 ap->private_data = pp;
519
520 addr = (u64)pp->pkt_dma;
521 writel((u32) addr, chan + QS_CCF_CPBA);
522 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
523 return 0;
524 }
525
526 static void qs_host_stop(struct ata_host *host)
527 {
528 void __iomem *mmio_base = qs_mmio_base(host);
529
530 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
531 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
532 }
533
534 static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
535 {
536 void __iomem *mmio_base = pe->iomap[QS_MMIO_BAR];
537 unsigned int port_no;
538
539 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
540 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
541
542 /* reset each channel in turn */
543 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
544 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
545 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
546 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
547 readb(chan + QS_CCT_CTR0); /* flush */
548 }
549 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
550
551 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
552 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
553 /* set FIFO depths to same settings as Windows driver */
554 writew(32, chan + QS_CFC_HUFT);
555 writew(32, chan + QS_CFC_HDFT);
556 writew(10, chan + QS_CFC_DUFT);
557 writew( 8, chan + QS_CFC_DDFT);
558 /* set CPB size in bytes, as a power of two */
559 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
560 }
561 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
562 }
563
564 /*
565 * The QStor understands 64-bit buses, and uses 64-bit fields
566 * for DMA pointers regardless of bus width. We just have to
567 * make sure our DMA masks are set appropriately for whatever
568 * bridge lies between us and the QStor, and then the DMA mapping
569 * code will ensure we only ever "see" appropriate buffer addresses.
570 * If we're 32-bit limited somewhere, then our 64-bit fields will
571 * just end up with zeros in the upper 32-bits, without any special
572 * logic required outside of this routine (below).
573 */
574 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
575 {
576 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
577 int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
578
579 if (have_64bit_bus &&
580 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
581 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
582 if (rc) {
583 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
584 if (rc) {
585 dev_printk(KERN_ERR, &pdev->dev,
586 "64-bit DMA enable failed\n");
587 return rc;
588 }
589 }
590 } else {
591 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
592 if (rc) {
593 dev_printk(KERN_ERR, &pdev->dev,
594 "32-bit DMA enable failed\n");
595 return rc;
596 }
597 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
598 if (rc) {
599 dev_printk(KERN_ERR, &pdev->dev,
600 "32-bit consistent DMA enable failed\n");
601 return rc;
602 }
603 }
604 return 0;
605 }
606
607 static int qs_ata_init_one(struct pci_dev *pdev,
608 const struct pci_device_id *ent)
609 {
610 static int printed_version;
611 struct ata_probe_ent *probe_ent;
612 void __iomem * const *iomap;
613 unsigned int board_idx = (unsigned int) ent->driver_data;
614 int rc, port_no;
615
616 if (!printed_version++)
617 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
618
619 rc = pcim_enable_device(pdev);
620 if (rc)
621 return rc;
622
623 if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)
624 return -ENODEV;
625
626 rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
627 if (rc)
628 return rc;
629 iomap = pcim_iomap_table(pdev);
630
631 rc = qs_set_dma_masks(pdev, iomap[QS_MMIO_BAR]);
632 if (rc)
633 return rc;
634
635 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
636 if (probe_ent == NULL)
637 return -ENOMEM;
638
639 probe_ent->dev = pci_dev_to_dev(pdev);
640 INIT_LIST_HEAD(&probe_ent->node);
641
642 probe_ent->sht = qs_port_info[board_idx].sht;
643 probe_ent->port_flags = qs_port_info[board_idx].flags;
644 probe_ent->pio_mask = qs_port_info[board_idx].pio_mask;
645 probe_ent->mwdma_mask = qs_port_info[board_idx].mwdma_mask;
646 probe_ent->udma_mask = qs_port_info[board_idx].udma_mask;
647 probe_ent->port_ops = qs_port_info[board_idx].port_ops;
648
649 probe_ent->irq = pdev->irq;
650 probe_ent->irq_flags = IRQF_SHARED;
651 probe_ent->iomap = iomap;
652 probe_ent->n_ports = QS_PORTS;
653
654 for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
655 void __iomem *chan =
656 probe_ent->iomap[QS_MMIO_BAR] + (port_no * 0x4000);
657 qs_ata_setup_port(&probe_ent->port[port_no], chan);
658 }
659
660 pci_set_master(pdev);
661
662 /* initialize adapter */
663 qs_host_init(board_idx, probe_ent);
664
665 if (ata_device_add(probe_ent) != QS_PORTS)
666 return -EIO;
667
668 devm_kfree(&pdev->dev, probe_ent);
669 return 0;
670 }
671
672 static int __init qs_ata_init(void)
673 {
674 return pci_register_driver(&qs_ata_pci_driver);
675 }
676
677 static void __exit qs_ata_exit(void)
678 {
679 pci_unregister_driver(&qs_ata_pci_driver);
680 }
681
682 MODULE_AUTHOR("Mark Lord");
683 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
684 MODULE_LICENSE("GPL");
685 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
686 MODULE_VERSION(DRV_VERSION);
687
688 module_init(qs_ata_init);
689 module_exit(qs_ata_exit);
Linux kernel - Deliverables
This page took 0.045538 seconds and 6 git commands to generate.