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[deliverable/linux.git] / drivers / ata / sata_sil.c
1 /*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2005 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "sata_sil"
49 #define DRV_VERSION "2.3"
50
51 enum {
52 SIL_MMIO_BAR = 5,
53
54 /*
55 * host flags
56 */
57 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
58 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
59 SIL_FLAG_MOD15WRITE = (1 << 30),
60
61 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
62 ATA_FLAG_MMIO,
63
64 /*
65 * Controller IDs
66 */
67 sil_3112 = 0,
68 sil_3112_no_sata_irq = 1,
69 sil_3512 = 2,
70 sil_3114 = 3,
71
72 /*
73 * Register offsets
74 */
75 SIL_SYSCFG = 0x48,
76
77 /*
78 * Register bits
79 */
80 /* SYSCFG */
81 SIL_MASK_IDE0_INT = (1 << 22),
82 SIL_MASK_IDE1_INT = (1 << 23),
83 SIL_MASK_IDE2_INT = (1 << 24),
84 SIL_MASK_IDE3_INT = (1 << 25),
85 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
86 SIL_MASK_4PORT = SIL_MASK_2PORT |
87 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
88
89 /* BMDMA/BMDMA2 */
90 SIL_INTR_STEERING = (1 << 1),
91
92 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
93 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
94 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
95 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
96 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
97 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
98 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
99 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
100 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
101 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
102
103 /* SIEN */
104 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
105
106 /*
107 * Others
108 */
109 SIL_QUIRK_MOD15WRITE = (1 << 0),
110 SIL_QUIRK_UDMA5MAX = (1 << 1),
111 };
112
113 static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
114 #ifdef CONFIG_PM
115 static int sil_pci_device_resume(struct pci_dev *pdev);
116 #endif
117 static void sil_dev_config(struct ata_device *dev);
118 static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
119 static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
120 static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed);
121 static void sil_freeze(struct ata_port *ap);
122 static void sil_thaw(struct ata_port *ap);
123
124
125 static const struct pci_device_id sil_pci_tbl[] = {
126 { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
127 { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
128 { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
129 { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
130 { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
131 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
132 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
133
134 { } /* terminate list */
135 };
136
137
138 /* TODO firmware versions should be added - eric */
139 static const struct sil_drivelist {
140 const char *product;
141 unsigned int quirk;
142 } sil_blacklist [] = {
143 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
144 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
145 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
146 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
147 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
148 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
149 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
150 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
151 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
152 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
153 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
154 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
155 { }
156 };
157
158 static struct pci_driver sil_pci_driver = {
159 .name = DRV_NAME,
160 .id_table = sil_pci_tbl,
161 .probe = sil_init_one,
162 .remove = ata_pci_remove_one,
163 #ifdef CONFIG_PM
164 .suspend = ata_pci_device_suspend,
165 .resume = sil_pci_device_resume,
166 #endif
167 };
168
169 static struct scsi_host_template sil_sht = {
170 .module = THIS_MODULE,
171 .name = DRV_NAME,
172 .ioctl = ata_scsi_ioctl,
173 .queuecommand = ata_scsi_queuecmd,
174 .can_queue = ATA_DEF_QUEUE,
175 .this_id = ATA_SHT_THIS_ID,
176 .sg_tablesize = LIBATA_MAX_PRD,
177 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
178 .emulated = ATA_SHT_EMULATED,
179 .use_clustering = ATA_SHT_USE_CLUSTERING,
180 .proc_name = DRV_NAME,
181 .dma_boundary = ATA_DMA_BOUNDARY,
182 .slave_configure = ata_scsi_slave_config,
183 .slave_destroy = ata_scsi_slave_destroy,
184 .bios_param = ata_std_bios_param,
185 };
186
187 static const struct ata_port_operations sil_ops = {
188 .dev_config = sil_dev_config,
189 .tf_load = ata_tf_load,
190 .tf_read = ata_tf_read,
191 .check_status = ata_check_status,
192 .exec_command = ata_exec_command,
193 .dev_select = ata_std_dev_select,
194 .set_mode = sil_set_mode,
195 .bmdma_setup = ata_bmdma_setup,
196 .bmdma_start = ata_bmdma_start,
197 .bmdma_stop = ata_bmdma_stop,
198 .bmdma_status = ata_bmdma_status,
199 .qc_prep = ata_qc_prep,
200 .qc_issue = ata_qc_issue_prot,
201 .data_xfer = ata_data_xfer,
202 .freeze = sil_freeze,
203 .thaw = sil_thaw,
204 .error_handler = ata_bmdma_error_handler,
205 .post_internal_cmd = ata_bmdma_post_internal_cmd,
206 .irq_clear = ata_bmdma_irq_clear,
207 .irq_on = ata_irq_on,
208 .scr_read = sil_scr_read,
209 .scr_write = sil_scr_write,
210 .port_start = ata_port_start,
211 };
212
213 static const struct ata_port_info sil_port_info[] = {
214 /* sil_3112 */
215 {
216 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
217 .pio_mask = 0x1f, /* pio0-4 */
218 .mwdma_mask = 0x07, /* mwdma0-2 */
219 .udma_mask = ATA_UDMA5,
220 .port_ops = &sil_ops,
221 },
222 /* sil_3112_no_sata_irq */
223 {
224 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
225 SIL_FLAG_NO_SATA_IRQ,
226 .pio_mask = 0x1f, /* pio0-4 */
227 .mwdma_mask = 0x07, /* mwdma0-2 */
228 .udma_mask = ATA_UDMA5,
229 .port_ops = &sil_ops,
230 },
231 /* sil_3512 */
232 {
233 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
234 .pio_mask = 0x1f, /* pio0-4 */
235 .mwdma_mask = 0x07, /* mwdma0-2 */
236 .udma_mask = ATA_UDMA5,
237 .port_ops = &sil_ops,
238 },
239 /* sil_3114 */
240 {
241 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
242 .pio_mask = 0x1f, /* pio0-4 */
243 .mwdma_mask = 0x07, /* mwdma0-2 */
244 .udma_mask = ATA_UDMA5,
245 .port_ops = &sil_ops,
246 },
247 };
248
249 /* per-port register offsets */
250 /* TODO: we can probably calculate rather than use a table */
251 static const struct {
252 unsigned long tf; /* ATA taskfile register block */
253 unsigned long ctl; /* ATA control/altstatus register block */
254 unsigned long bmdma; /* DMA register block */
255 unsigned long bmdma2; /* DMA register block #2 */
256 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
257 unsigned long scr; /* SATA control register block */
258 unsigned long sien; /* SATA Interrupt Enable register */
259 unsigned long xfer_mode;/* data transfer mode register */
260 unsigned long sfis_cfg; /* SATA FIS reception config register */
261 } sil_port[] = {
262 /* port 0 ... */
263 /* tf ctl bmdma bmdma2 fifo scr sien mode sfis */
264 { 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
265 { 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
266 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
267 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
268 /* ... port 3 */
269 };
270
271 MODULE_AUTHOR("Jeff Garzik");
272 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
273 MODULE_LICENSE("GPL");
274 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
275 MODULE_VERSION(DRV_VERSION);
276
277 static int slow_down;
278 module_param(slow_down, int, 0444);
279 MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
280
281
282 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
283 {
284 u8 cache_line = 0;
285 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
286 return cache_line;
287 }
288
289 /**
290 * sil_set_mode - wrap set_mode functions
291 * @link: link to set up
292 * @r_failed: returned device when we fail
293 *
294 * Wrap the libata method for device setup as after the setup we need
295 * to inspect the results and do some configuration work
296 */
297
298 static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed)
299 {
300 struct ata_port *ap = link->ap;
301 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
302 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode;
303 struct ata_device *dev;
304 u32 tmp, dev_mode[2] = { };
305 int rc;
306
307 rc = ata_do_set_mode(link, r_failed);
308 if (rc)
309 return rc;
310
311 ata_link_for_each_dev(dev, link) {
312 if (!ata_dev_enabled(dev))
313 dev_mode[dev->devno] = 0; /* PIO0/1/2 */
314 else if (dev->flags & ATA_DFLAG_PIO)
315 dev_mode[dev->devno] = 1; /* PIO3/4 */
316 else
317 dev_mode[dev->devno] = 3; /* UDMA */
318 /* value 2 indicates MDMA */
319 }
320
321 tmp = readl(addr);
322 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
323 tmp |= dev_mode[0];
324 tmp |= (dev_mode[1] << 4);
325 writel(tmp, addr);
326 readl(addr); /* flush */
327 return 0;
328 }
329
330 static inline void __iomem *sil_scr_addr(struct ata_port *ap,
331 unsigned int sc_reg)
332 {
333 void __iomem *offset = ap->ioaddr.scr_addr;
334
335 switch (sc_reg) {
336 case SCR_STATUS:
337 return offset + 4;
338 case SCR_ERROR:
339 return offset + 8;
340 case SCR_CONTROL:
341 return offset;
342 default:
343 /* do nothing */
344 break;
345 }
346
347 return NULL;
348 }
349
350 static int sil_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
351 {
352 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
353
354 if (mmio) {
355 *val = readl(mmio);
356 return 0;
357 }
358 return -EINVAL;
359 }
360
361 static int sil_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
362 {
363 void __iomem *mmio = sil_scr_addr(ap, sc_reg);
364
365 if (mmio) {
366 writel(val, mmio);
367 return 0;
368 }
369 return -EINVAL;
370 }
371
372 static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
373 {
374 struct ata_eh_info *ehi = &ap->link.eh_info;
375 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
376 u8 status;
377
378 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
379 u32 serror;
380
381 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
382 * controllers continue to assert IRQ as long as
383 * SError bits are pending. Clear SError immediately.
384 */
385 sil_scr_read(ap, SCR_ERROR, &serror);
386 sil_scr_write(ap, SCR_ERROR, serror);
387
388 /* Sometimes spurious interrupts occur, double check
389 * it's PHYRDY CHG.
390 */
391 if (serror & SERR_PHYRDY_CHG) {
392 ap->link.eh_info.serror |= serror;
393 goto freeze;
394 }
395
396 if (!(bmdma2 & SIL_DMA_COMPLETE))
397 return;
398 }
399
400 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
401 /* this sometimes happens, just clear IRQ */
402 ata_chk_status(ap);
403 return;
404 }
405
406 /* Check whether we are expecting interrupt in this state */
407 switch (ap->hsm_task_state) {
408 case HSM_ST_FIRST:
409 /* Some pre-ATAPI-4 devices assert INTRQ
410 * at this state when ready to receive CDB.
411 */
412
413 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
414 * The flag was turned on only for atapi devices. No
415 * need to check ata_is_atapi(qc->tf.protocol) again.
416 */
417 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
418 goto err_hsm;
419 break;
420 case HSM_ST_LAST:
421 if (ata_is_dma(qc->tf.protocol)) {
422 /* clear DMA-Start bit */
423 ap->ops->bmdma_stop(qc);
424
425 if (bmdma2 & SIL_DMA_ERROR) {
426 qc->err_mask |= AC_ERR_HOST_BUS;
427 ap->hsm_task_state = HSM_ST_ERR;
428 }
429 }
430 break;
431 case HSM_ST:
432 break;
433 default:
434 goto err_hsm;
435 }
436
437 /* check main status, clearing INTRQ */
438 status = ata_chk_status(ap);
439 if (unlikely(status & ATA_BUSY))
440 goto err_hsm;
441
442 /* ack bmdma irq events */
443 ata_bmdma_irq_clear(ap);
444
445 /* kick HSM in the ass */
446 ata_hsm_move(ap, qc, status, 0);
447
448 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
449 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
450
451 return;
452
453 err_hsm:
454 qc->err_mask |= AC_ERR_HSM;
455 freeze:
456 ata_port_freeze(ap);
457 }
458
459 static irqreturn_t sil_interrupt(int irq, void *dev_instance)
460 {
461 struct ata_host *host = dev_instance;
462 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
463 int handled = 0;
464 int i;
465
466 spin_lock(&host->lock);
467
468 for (i = 0; i < host->n_ports; i++) {
469 struct ata_port *ap = host->ports[i];
470 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
471
472 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
473 continue;
474
475 /* turn off SATA_IRQ if not supported */
476 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
477 bmdma2 &= ~SIL_DMA_SATA_IRQ;
478
479 if (bmdma2 == 0xffffffff ||
480 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
481 continue;
482
483 sil_host_intr(ap, bmdma2);
484 handled = 1;
485 }
486
487 spin_unlock(&host->lock);
488
489 return IRQ_RETVAL(handled);
490 }
491
492 static void sil_freeze(struct ata_port *ap)
493 {
494 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
495 u32 tmp;
496
497 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
498 writel(0, mmio_base + sil_port[ap->port_no].sien);
499
500 /* plug IRQ */
501 tmp = readl(mmio_base + SIL_SYSCFG);
502 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
503 writel(tmp, mmio_base + SIL_SYSCFG);
504 readl(mmio_base + SIL_SYSCFG); /* flush */
505 }
506
507 static void sil_thaw(struct ata_port *ap)
508 {
509 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR];
510 u32 tmp;
511
512 /* clear IRQ */
513 ata_chk_status(ap);
514 ata_bmdma_irq_clear(ap);
515
516 /* turn on SATA IRQ if supported */
517 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
518 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
519
520 /* turn on IRQ */
521 tmp = readl(mmio_base + SIL_SYSCFG);
522 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
523 writel(tmp, mmio_base + SIL_SYSCFG);
524 }
525
526 /**
527 * sil_dev_config - Apply device/host-specific errata fixups
528 * @dev: Device to be examined
529 *
530 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
531 * device is known to be present, this function is called.
532 * We apply two errata fixups which are specific to Silicon Image,
533 * a Seagate and a Maxtor fixup.
534 *
535 * For certain Seagate devices, we must limit the maximum sectors
536 * to under 8K.
537 *
538 * For certain Maxtor devices, we must not program the drive
539 * beyond udma5.
540 *
541 * Both fixups are unfairly pessimistic. As soon as I get more
542 * information on these errata, I will create a more exhaustive
543 * list, and apply the fixups to only the specific
544 * devices/hosts/firmwares that need it.
545 *
546 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
547 * The Maxtor quirk is in the blacklist, but I'm keeping the original
548 * pessimistic fix for the following reasons...
549 * - There seems to be less info on it, only one device gleaned off the
550 * Windows driver, maybe only one is affected. More info would be greatly
551 * appreciated.
552 * - But then again UDMA5 is hardly anything to complain about
553 */
554 static void sil_dev_config(struct ata_device *dev)
555 {
556 struct ata_port *ap = dev->link->ap;
557 int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO;
558 unsigned int n, quirks = 0;
559 unsigned char model_num[ATA_ID_PROD_LEN + 1];
560
561 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
562
563 for (n = 0; sil_blacklist[n].product; n++)
564 if (!strcmp(sil_blacklist[n].product, model_num)) {
565 quirks = sil_blacklist[n].quirk;
566 break;
567 }
568
569 /* limit requests to 15 sectors */
570 if (slow_down ||
571 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
572 (quirks & SIL_QUIRK_MOD15WRITE))) {
573 if (print_info)
574 ata_dev_printk(dev, KERN_INFO, "applying Seagate "
575 "errata fix (mod15write workaround)\n");
576 dev->max_sectors = 15;
577 return;
578 }
579
580 /* limit to udma5 */
581 if (quirks & SIL_QUIRK_UDMA5MAX) {
582 if (print_info)
583 ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
584 "errata fix %s\n", model_num);
585 dev->udma_mask &= ATA_UDMA5;
586 return;
587 }
588 }
589
590 static void sil_init_controller(struct ata_host *host)
591 {
592 struct pci_dev *pdev = to_pci_dev(host->dev);
593 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
594 u8 cls;
595 u32 tmp;
596 int i;
597
598 /* Initialize FIFO PCI bus arbitration */
599 cls = sil_get_device_cache_line(pdev);
600 if (cls) {
601 cls >>= 3;
602 cls++; /* cls = (line_size/8)+1 */
603 for (i = 0; i < host->n_ports; i++)
604 writew(cls << 8 | cls,
605 mmio_base + sil_port[i].fifo_cfg);
606 } else
607 dev_printk(KERN_WARNING, &pdev->dev,
608 "cache line size not set. Driver may not function\n");
609
610 /* Apply R_ERR on DMA activate FIS errata workaround */
611 if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) {
612 int cnt;
613
614 for (i = 0, cnt = 0; i < host->n_ports; i++) {
615 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
616 if ((tmp & 0x3) != 0x01)
617 continue;
618 if (!cnt)
619 dev_printk(KERN_INFO, &pdev->dev,
620 "Applying R_ERR on DMA activate "
621 "FIS errata fix\n");
622 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
623 cnt++;
624 }
625 }
626
627 if (host->n_ports == 4) {
628 /* flip the magic "make 4 ports work" bit */
629 tmp = readl(mmio_base + sil_port[2].bmdma);
630 if ((tmp & SIL_INTR_STEERING) == 0)
631 writel(tmp | SIL_INTR_STEERING,
632 mmio_base + sil_port[2].bmdma);
633 }
634 }
635
636 static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
637 {
638 static int printed_version;
639 int board_id = ent->driver_data;
640 const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL };
641 struct ata_host *host;
642 void __iomem *mmio_base;
643 int n_ports, rc;
644 unsigned int i;
645
646 if (!printed_version++)
647 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
648
649 /* allocate host */
650 n_ports = 2;
651 if (board_id == sil_3114)
652 n_ports = 4;
653
654 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
655 if (!host)
656 return -ENOMEM;
657
658 /* acquire resources and fill host */
659 rc = pcim_enable_device(pdev);
660 if (rc)
661 return rc;
662
663 rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME);
664 if (rc == -EBUSY)
665 pcim_pin_device(pdev);
666 if (rc)
667 return rc;
668 host->iomap = pcim_iomap_table(pdev);
669
670 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
671 if (rc)
672 return rc;
673 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
674 if (rc)
675 return rc;
676
677 mmio_base = host->iomap[SIL_MMIO_BAR];
678
679 for (i = 0; i < host->n_ports; i++) {
680 struct ata_port *ap = host->ports[i];
681 struct ata_ioports *ioaddr = &ap->ioaddr;
682
683 ioaddr->cmd_addr = mmio_base + sil_port[i].tf;
684 ioaddr->altstatus_addr =
685 ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;
686 ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;
687 ioaddr->scr_addr = mmio_base + sil_port[i].scr;
688 ata_std_ports(ioaddr);
689
690 ata_port_pbar_desc(ap, SIL_MMIO_BAR, -1, "mmio");
691 ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf");
692 }
693
694 /* initialize and activate */
695 sil_init_controller(host);
696
697 pci_set_master(pdev);
698 return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED,
699 &sil_sht);
700 }
701
702 #ifdef CONFIG_PM
703 static int sil_pci_device_resume(struct pci_dev *pdev)
704 {
705 struct ata_host *host = dev_get_drvdata(&pdev->dev);
706 int rc;
707
708 rc = ata_pci_device_do_resume(pdev);
709 if (rc)
710 return rc;
711
712 sil_init_controller(host);
713 ata_host_resume(host);
714
715 return 0;
716 }
717 #endif
718
719 static int __init sil_init(void)
720 {
721 return pci_register_driver(&sil_pci_driver);
722 }
723
724 static void __exit sil_exit(void)
725 {
726 pci_unregister_driver(&sil_pci_driver);
727 }
728
729
730 module_init(sil_init);
731 module_exit(sil_exit);
Linux kernel - Deliverables
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