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libata: implement and use ata_noop_irq_clear()
[deliverable/linux.git] / drivers / ata / sata_sil24.c
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "1.1"
34
35 /*
36 * Port request block (PRB) 32 bytes
37 */
38 struct sil24_prb {
39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
42 u8 fis[6 * 4];
43 };
44
45 /*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48 struct sil24_sge {
49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
52 };
53
54 /*
55 * Port multiplier
56 */
57 struct sil24_port_multiplier {
58 __le32 diag;
59 __le32 sactive;
60 };
61
62 enum {
63 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
66 /* sil24 fetches in chunks of 64bytes. The first block
67 * contains the PRB and two SGEs. From the second block, it's
68 * consisted of four SGEs and called SGT. Calculate the
69 * number of SGTs that fit into one page.
70 */
71 SIL24_PRB_SZ = sizeof(struct sil24_prb)
72 + 2 * sizeof(struct sil24_sge),
73 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
74 / (4 * sizeof(struct sil24_sge)),
75
76 /* This will give us one unused SGEs for ATA. This extra SGE
77 * will be used to store CDB for ATAPI devices.
78 */
79 SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1,
80
81 /*
82 * Global controller registers (128 bytes @ BAR0)
83 */
84 /* 32 bit regs */
85 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
86 HOST_CTRL = 0x40,
87 HOST_IRQ_STAT = 0x44,
88 HOST_PHY_CFG = 0x48,
89 HOST_BIST_CTRL = 0x50,
90 HOST_BIST_PTRN = 0x54,
91 HOST_BIST_STAT = 0x58,
92 HOST_MEM_BIST_STAT = 0x5c,
93 HOST_FLASH_CMD = 0x70,
94 /* 8 bit regs */
95 HOST_FLASH_DATA = 0x74,
96 HOST_TRANSITION_DETECT = 0x75,
97 HOST_GPIO_CTRL = 0x76,
98 HOST_I2C_ADDR = 0x78, /* 32 bit */
99 HOST_I2C_DATA = 0x7c,
100 HOST_I2C_XFER_CNT = 0x7e,
101 HOST_I2C_CTRL = 0x7f,
102
103 /* HOST_SLOT_STAT bits */
104 HOST_SSTAT_ATTN = (1 << 31),
105
106 /* HOST_CTRL bits */
107 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
108 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
109 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
110 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
111 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
112 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
113
114 /*
115 * Port registers
116 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
117 */
118 PORT_REGS_SIZE = 0x2000,
119
120 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
121 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
122
123 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
124 PORT_PMP_STATUS = 0x0000, /* port device status offset */
125 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
126 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
127
128 /* 32 bit regs */
129 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
130 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
131 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
132 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
133 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
134 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
135 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
136 PORT_CMD_ERR = 0x1024, /* command error number */
137 PORT_FIS_CFG = 0x1028,
138 PORT_FIFO_THRES = 0x102c,
139 /* 16 bit regs */
140 PORT_DECODE_ERR_CNT = 0x1040,
141 PORT_DECODE_ERR_THRESH = 0x1042,
142 PORT_CRC_ERR_CNT = 0x1044,
143 PORT_CRC_ERR_THRESH = 0x1046,
144 PORT_HSHK_ERR_CNT = 0x1048,
145 PORT_HSHK_ERR_THRESH = 0x104a,
146 /* 32 bit regs */
147 PORT_PHY_CFG = 0x1050,
148 PORT_SLOT_STAT = 0x1800,
149 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
150 PORT_CONTEXT = 0x1e04,
151 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
152 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
153 PORT_SCONTROL = 0x1f00,
154 PORT_SSTATUS = 0x1f04,
155 PORT_SERROR = 0x1f08,
156 PORT_SACTIVE = 0x1f0c,
157
158 /* PORT_CTRL_STAT bits */
159 PORT_CS_PORT_RST = (1 << 0), /* port reset */
160 PORT_CS_DEV_RST = (1 << 1), /* device reset */
161 PORT_CS_INIT = (1 << 2), /* port initialize */
162 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
163 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
164 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
165 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
166 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
167 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
168
169 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
170 /* bits[11:0] are masked */
171 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
172 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
173 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
174 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
175 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
176 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
177 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
178 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
179 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
180 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
181 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
182 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
183
184 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
185 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
186 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
187
188 /* bits[27:16] are unmasked (raw) */
189 PORT_IRQ_RAW_SHIFT = 16,
190 PORT_IRQ_MASKED_MASK = 0x7ff,
191 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
192
193 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
194 PORT_IRQ_STEER_SHIFT = 30,
195 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
196
197 /* PORT_CMD_ERR constants */
198 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
199 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
200 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
201 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
202 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
203 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
204 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
205 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
206 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
207 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
208 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
209 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
210 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
211 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
212 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
213 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
214 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
215 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
216 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
217 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
218 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
219 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
220
221 /* bits of PRB control field */
222 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
223 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
224 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
225 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
226 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
227
228 /* PRB protocol field */
229 PRB_PROT_PACKET = (1 << 0),
230 PRB_PROT_TCQ = (1 << 1),
231 PRB_PROT_NCQ = (1 << 2),
232 PRB_PROT_READ = (1 << 3),
233 PRB_PROT_WRITE = (1 << 4),
234 PRB_PROT_TRANSPARENT = (1 << 5),
235
236 /*
237 * Other constants
238 */
239 SGE_TRM = (1 << 31), /* Last SGE in chain */
240 SGE_LNK = (1 << 30), /* linked list
241 Points to SGT, not SGE */
242 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
243 data address ignored */
244
245 SIL24_MAX_CMDS = 31,
246
247 /* board id */
248 BID_SIL3124 = 0,
249 BID_SIL3132 = 1,
250 BID_SIL3131 = 2,
251
252 /* host flags */
253 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
254 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
255 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
256 ATA_FLAG_AN | ATA_FLAG_PMP,
257 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
258
259 IRQ_STAT_4PORTS = 0xf,
260 };
261
262 struct sil24_ata_block {
263 struct sil24_prb prb;
264 struct sil24_sge sge[SIL24_MAX_SGE];
265 };
266
267 struct sil24_atapi_block {
268 struct sil24_prb prb;
269 u8 cdb[16];
270 struct sil24_sge sge[SIL24_MAX_SGE];
271 };
272
273 union sil24_cmd_block {
274 struct sil24_ata_block ata;
275 struct sil24_atapi_block atapi;
276 };
277
278 static struct sil24_cerr_info {
279 unsigned int err_mask, action;
280 const char *desc;
281 } sil24_cerr_db[] = {
282 [0] = { AC_ERR_DEV, 0,
283 "device error" },
284 [PORT_CERR_DEV] = { AC_ERR_DEV, 0,
285 "device error via D2H FIS" },
286 [PORT_CERR_SDB] = { AC_ERR_DEV, 0,
287 "device error via SDB FIS" },
288 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
289 "error in data FIS" },
290 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
291 "failed to transmit command FIS" },
292 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
293 "protocol mismatch" },
294 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
295 "data directon mismatch" },
296 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
297 "ran out of SGEs while writing" },
298 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
299 "ran out of SGEs while reading" },
300 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
301 "invalid data directon for ATAPI CDB" },
302 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
303 "SGT not on qword boundary" },
304 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
305 "PCI target abort while fetching SGT" },
306 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
307 "PCI master abort while fetching SGT" },
308 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
309 "PCI parity error while fetching SGT" },
310 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
311 "PRB not on qword boundary" },
312 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
313 "PCI target abort while fetching PRB" },
314 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
315 "PCI master abort while fetching PRB" },
316 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
317 "PCI parity error while fetching PRB" },
318 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
319 "undefined error while transferring data" },
320 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
321 "PCI target abort while transferring data" },
322 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
323 "PCI master abort while transferring data" },
324 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
325 "PCI parity error while transferring data" },
326 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
327 "FIS received while sending service FIS" },
328 };
329
330 /*
331 * ap->private_data
332 *
333 * The preview driver always returned 0 for status. We emulate it
334 * here from the previous interrupt.
335 */
336 struct sil24_port_priv {
337 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
338 dma_addr_t cmd_block_dma; /* DMA base addr for them */
339 struct ata_taskfile tf; /* Cached taskfile registers */
340 int do_port_rst;
341 };
342
343 static void sil24_dev_config(struct ata_device *dev);
344 static u8 sil24_check_status(struct ata_port *ap);
345 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
346 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
347 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
348 static int sil24_qc_defer(struct ata_queued_cmd *qc);
349 static void sil24_qc_prep(struct ata_queued_cmd *qc);
350 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
351 static void sil24_pmp_attach(struct ata_port *ap);
352 static void sil24_pmp_detach(struct ata_port *ap);
353 static void sil24_freeze(struct ata_port *ap);
354 static void sil24_thaw(struct ata_port *ap);
355 static void sil24_error_handler(struct ata_port *ap);
356 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
357 static int sil24_port_start(struct ata_port *ap);
358 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
359 #ifdef CONFIG_PM
360 static int sil24_pci_device_resume(struct pci_dev *pdev);
361 static int sil24_port_resume(struct ata_port *ap);
362 #endif
363
364 static const struct pci_device_id sil24_pci_tbl[] = {
365 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
366 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
367 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
368 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
369 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
370 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
371
372 { } /* terminate list */
373 };
374
375 static struct pci_driver sil24_pci_driver = {
376 .name = DRV_NAME,
377 .id_table = sil24_pci_tbl,
378 .probe = sil24_init_one,
379 .remove = ata_pci_remove_one,
380 #ifdef CONFIG_PM
381 .suspend = ata_pci_device_suspend,
382 .resume = sil24_pci_device_resume,
383 #endif
384 };
385
386 static struct scsi_host_template sil24_sht = {
387 .module = THIS_MODULE,
388 .name = DRV_NAME,
389 .ioctl = ata_scsi_ioctl,
390 .queuecommand = ata_scsi_queuecmd,
391 .change_queue_depth = ata_scsi_change_queue_depth,
392 .can_queue = SIL24_MAX_CMDS,
393 .this_id = ATA_SHT_THIS_ID,
394 .sg_tablesize = SIL24_MAX_SGE,
395 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
396 .emulated = ATA_SHT_EMULATED,
397 .use_clustering = ATA_SHT_USE_CLUSTERING,
398 .proc_name = DRV_NAME,
399 .dma_boundary = ATA_DMA_BOUNDARY,
400 .slave_configure = ata_scsi_slave_config,
401 .slave_destroy = ata_scsi_slave_destroy,
402 .bios_param = ata_std_bios_param,
403 };
404
405 static const struct ata_port_operations sil24_ops = {
406 .dev_config = sil24_dev_config,
407
408 .check_status = sil24_check_status,
409 .check_altstatus = sil24_check_status,
410 .dev_select = ata_noop_dev_select,
411
412 .tf_read = sil24_tf_read,
413
414 .qc_defer = sil24_qc_defer,
415 .qc_prep = sil24_qc_prep,
416 .qc_issue = sil24_qc_issue,
417
418 .irq_clear = ata_noop_irq_clear,
419
420 .scr_read = sil24_scr_read,
421 .scr_write = sil24_scr_write,
422
423 .pmp_attach = sil24_pmp_attach,
424 .pmp_detach = sil24_pmp_detach,
425
426 .freeze = sil24_freeze,
427 .thaw = sil24_thaw,
428 .error_handler = sil24_error_handler,
429 .post_internal_cmd = sil24_post_internal_cmd,
430
431 .port_start = sil24_port_start,
432
433 #ifdef CONFIG_PM
434 .port_resume = sil24_port_resume,
435 #endif
436 };
437
438 /*
439 * Use bits 30-31 of port_flags to encode available port numbers.
440 * Current maxium is 4.
441 */
442 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
443 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
444
445 static const struct ata_port_info sil24_port_info[] = {
446 /* sil_3124 */
447 {
448 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
449 SIL24_FLAG_PCIX_IRQ_WOC,
450 .pio_mask = 0x1f, /* pio0-4 */
451 .mwdma_mask = 0x07, /* mwdma0-2 */
452 .udma_mask = ATA_UDMA5, /* udma0-5 */
453 .port_ops = &sil24_ops,
454 },
455 /* sil_3132 */
456 {
457 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
458 .pio_mask = 0x1f, /* pio0-4 */
459 .mwdma_mask = 0x07, /* mwdma0-2 */
460 .udma_mask = ATA_UDMA5, /* udma0-5 */
461 .port_ops = &sil24_ops,
462 },
463 /* sil_3131/sil_3531 */
464 {
465 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
466 .pio_mask = 0x1f, /* pio0-4 */
467 .mwdma_mask = 0x07, /* mwdma0-2 */
468 .udma_mask = ATA_UDMA5, /* udma0-5 */
469 .port_ops = &sil24_ops,
470 },
471 };
472
473 static int sil24_tag(int tag)
474 {
475 if (unlikely(ata_tag_internal(tag)))
476 return 0;
477 return tag;
478 }
479
480 static void sil24_dev_config(struct ata_device *dev)
481 {
482 void __iomem *port = dev->link->ap->ioaddr.cmd_addr;
483
484 if (dev->cdb_len == 16)
485 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
486 else
487 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
488 }
489
490 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
491 {
492 void __iomem *port = ap->ioaddr.cmd_addr;
493 struct sil24_prb __iomem *prb;
494 u8 fis[6 * 4];
495
496 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
497 memcpy_fromio(fis, prb->fis, sizeof(fis));
498 ata_tf_from_fis(fis, tf);
499 }
500
501 static u8 sil24_check_status(struct ata_port *ap)
502 {
503 struct sil24_port_priv *pp = ap->private_data;
504 return pp->tf.command;
505 }
506
507 static int sil24_scr_map[] = {
508 [SCR_CONTROL] = 0,
509 [SCR_STATUS] = 1,
510 [SCR_ERROR] = 2,
511 [SCR_ACTIVE] = 3,
512 };
513
514 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
515 {
516 void __iomem *scr_addr = ap->ioaddr.scr_addr;
517
518 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
519 void __iomem *addr;
520 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
521 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
522 return 0;
523 }
524 return -EINVAL;
525 }
526
527 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
528 {
529 void __iomem *scr_addr = ap->ioaddr.scr_addr;
530
531 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
532 void __iomem *addr;
533 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
534 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
535 return 0;
536 }
537 return -EINVAL;
538 }
539
540 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
541 {
542 struct sil24_port_priv *pp = ap->private_data;
543 *tf = pp->tf;
544 }
545
546 static void sil24_config_port(struct ata_port *ap)
547 {
548 void __iomem *port = ap->ioaddr.cmd_addr;
549
550 /* configure IRQ WoC */
551 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
552 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
553 else
554 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
555
556 /* zero error counters. */
557 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
558 writel(0x8000, port + PORT_CRC_ERR_THRESH);
559 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
560 writel(0x0000, port + PORT_DECODE_ERR_CNT);
561 writel(0x0000, port + PORT_CRC_ERR_CNT);
562 writel(0x0000, port + PORT_HSHK_ERR_CNT);
563
564 /* always use 64bit activation */
565 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
566
567 /* clear port multiplier enable and resume bits */
568 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
569 }
570
571 static void sil24_config_pmp(struct ata_port *ap, int attached)
572 {
573 void __iomem *port = ap->ioaddr.cmd_addr;
574
575 if (attached)
576 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
577 else
578 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
579 }
580
581 static void sil24_clear_pmp(struct ata_port *ap)
582 {
583 void __iomem *port = ap->ioaddr.cmd_addr;
584 int i;
585
586 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
587
588 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
589 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
590
591 writel(0, pmp_base + PORT_PMP_STATUS);
592 writel(0, pmp_base + PORT_PMP_QACTIVE);
593 }
594 }
595
596 static int sil24_init_port(struct ata_port *ap)
597 {
598 void __iomem *port = ap->ioaddr.cmd_addr;
599 struct sil24_port_priv *pp = ap->private_data;
600 u32 tmp;
601
602 /* clear PMP error status */
603 if (ap->nr_pmp_links)
604 sil24_clear_pmp(ap);
605
606 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
607 ata_wait_register(port + PORT_CTRL_STAT,
608 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
609 tmp = ata_wait_register(port + PORT_CTRL_STAT,
610 PORT_CS_RDY, 0, 10, 100);
611
612 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
613 pp->do_port_rst = 1;
614 ap->link.eh_context.i.action |= ATA_EH_RESET;
615 return -EIO;
616 }
617
618 return 0;
619 }
620
621 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
622 const struct ata_taskfile *tf,
623 int is_cmd, u32 ctrl,
624 unsigned long timeout_msec)
625 {
626 void __iomem *port = ap->ioaddr.cmd_addr;
627 struct sil24_port_priv *pp = ap->private_data;
628 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
629 dma_addr_t paddr = pp->cmd_block_dma;
630 u32 irq_enabled, irq_mask, irq_stat;
631 int rc;
632
633 prb->ctrl = cpu_to_le16(ctrl);
634 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
635
636 /* temporarily plug completion and error interrupts */
637 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
638 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
639
640 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
641 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
642
643 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
644 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
645 10, timeout_msec);
646
647 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
648 irq_stat >>= PORT_IRQ_RAW_SHIFT;
649
650 if (irq_stat & PORT_IRQ_COMPLETE)
651 rc = 0;
652 else {
653 /* force port into known state */
654 sil24_init_port(ap);
655
656 if (irq_stat & PORT_IRQ_ERROR)
657 rc = -EIO;
658 else
659 rc = -EBUSY;
660 }
661
662 /* restore IRQ enabled */
663 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
664
665 return rc;
666 }
667
668 static int sil24_do_softreset(struct ata_link *link, unsigned int *class,
669 int pmp, unsigned long deadline)
670 {
671 struct ata_port *ap = link->ap;
672 unsigned long timeout_msec = 0;
673 struct ata_taskfile tf;
674 const char *reason;
675 int rc;
676
677 DPRINTK("ENTER\n");
678
679 if (ata_link_offline(link)) {
680 DPRINTK("PHY reports no device\n");
681 *class = ATA_DEV_NONE;
682 goto out;
683 }
684
685 /* put the port into known state */
686 if (sil24_init_port(ap)) {
687 reason = "port not ready";
688 goto err;
689 }
690
691 /* do SRST */
692 if (time_after(deadline, jiffies))
693 timeout_msec = jiffies_to_msecs(deadline - jiffies);
694
695 ata_tf_init(link->device, &tf); /* doesn't really matter */
696 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
697 timeout_msec);
698 if (rc == -EBUSY) {
699 reason = "timeout";
700 goto err;
701 } else if (rc) {
702 reason = "SRST command error";
703 goto err;
704 }
705
706 sil24_read_tf(ap, 0, &tf);
707 *class = ata_dev_classify(&tf);
708
709 if (*class == ATA_DEV_UNKNOWN)
710 *class = ATA_DEV_NONE;
711
712 out:
713 DPRINTK("EXIT, class=%u\n", *class);
714 return 0;
715
716 err:
717 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
718 return -EIO;
719 }
720
721 static int sil24_softreset(struct ata_link *link, unsigned int *class,
722 unsigned long deadline)
723 {
724 return sil24_do_softreset(link, class, SATA_PMP_CTRL_PORT, deadline);
725 }
726
727 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
728 unsigned long deadline)
729 {
730 struct ata_port *ap = link->ap;
731 void __iomem *port = ap->ioaddr.cmd_addr;
732 struct sil24_port_priv *pp = ap->private_data;
733 int did_port_rst = 0;
734 const char *reason;
735 int tout_msec, rc;
736 u32 tmp;
737
738 retry:
739 /* Sometimes, DEV_RST is not enough to recover the controller.
740 * This happens often after PM DMA CS errata.
741 */
742 if (pp->do_port_rst) {
743 ata_port_printk(ap, KERN_WARNING, "controller in dubious "
744 "state, performing PORT_RST\n");
745
746 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
747 msleep(10);
748 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
749 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
750 10, 5000);
751
752 /* restore port configuration */
753 sil24_config_port(ap);
754 sil24_config_pmp(ap, ap->nr_pmp_links);
755
756 pp->do_port_rst = 0;
757 did_port_rst = 1;
758 }
759
760 /* sil24 does the right thing(tm) without any protection */
761 sata_set_spd(link);
762
763 tout_msec = 100;
764 if (ata_link_online(link))
765 tout_msec = 5000;
766
767 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
768 tmp = ata_wait_register(port + PORT_CTRL_STAT,
769 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
770 tout_msec);
771
772 /* SStatus oscillates between zero and valid status after
773 * DEV_RST, debounce it.
774 */
775 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
776 if (rc) {
777 reason = "PHY debouncing failed";
778 goto err;
779 }
780
781 if (tmp & PORT_CS_DEV_RST) {
782 if (ata_link_offline(link))
783 return 0;
784 reason = "link not ready";
785 goto err;
786 }
787
788 /* Sil24 doesn't store signature FIS after hardreset, so we
789 * can't wait for BSY to clear. Some devices take a long time
790 * to get ready and those devices will choke if we don't wait
791 * for BSY clearance here. Tell libata to perform follow-up
792 * softreset.
793 */
794 return -EAGAIN;
795
796 err:
797 if (!did_port_rst) {
798 pp->do_port_rst = 1;
799 goto retry;
800 }
801
802 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
803 return -EIO;
804 }
805
806 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
807 struct sil24_sge *sge)
808 {
809 struct scatterlist *sg;
810 struct sil24_sge *last_sge = NULL;
811 unsigned int si;
812
813 for_each_sg(qc->sg, sg, qc->n_elem, si) {
814 sge->addr = cpu_to_le64(sg_dma_address(sg));
815 sge->cnt = cpu_to_le32(sg_dma_len(sg));
816 sge->flags = 0;
817
818 last_sge = sge;
819 sge++;
820 }
821
822 last_sge->flags = cpu_to_le32(SGE_TRM);
823 }
824
825 static int sil24_qc_defer(struct ata_queued_cmd *qc)
826 {
827 struct ata_link *link = qc->dev->link;
828 struct ata_port *ap = link->ap;
829 u8 prot = qc->tf.protocol;
830
831 /*
832 * There is a bug in the chip:
833 * Port LRAM Causes the PRB/SGT Data to be Corrupted
834 * If the host issues a read request for LRAM and SActive registers
835 * while active commands are available in the port, PRB/SGT data in
836 * the LRAM can become corrupted. This issue applies only when
837 * reading from, but not writing to, the LRAM.
838 *
839 * Therefore, reading LRAM when there is no particular error [and
840 * other commands may be outstanding] is prohibited.
841 *
842 * To avoid this bug there are two situations where a command must run
843 * exclusive of any other commands on the port:
844 *
845 * - ATAPI commands which check the sense data
846 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
847 * set.
848 *
849 */
850 int is_excl = (ata_is_atapi(prot) ||
851 (qc->flags & ATA_QCFLAG_RESULT_TF));
852
853 if (unlikely(ap->excl_link)) {
854 if (link == ap->excl_link) {
855 if (ap->nr_active_links)
856 return ATA_DEFER_PORT;
857 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
858 } else
859 return ATA_DEFER_PORT;
860 } else if (unlikely(is_excl)) {
861 ap->excl_link = link;
862 if (ap->nr_active_links)
863 return ATA_DEFER_PORT;
864 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
865 }
866
867 return ata_std_qc_defer(qc);
868 }
869
870 static void sil24_qc_prep(struct ata_queued_cmd *qc)
871 {
872 struct ata_port *ap = qc->ap;
873 struct sil24_port_priv *pp = ap->private_data;
874 union sil24_cmd_block *cb;
875 struct sil24_prb *prb;
876 struct sil24_sge *sge;
877 u16 ctrl = 0;
878
879 cb = &pp->cmd_block[sil24_tag(qc->tag)];
880
881 if (!ata_is_atapi(qc->tf.protocol)) {
882 prb = &cb->ata.prb;
883 sge = cb->ata.sge;
884 } else {
885 prb = &cb->atapi.prb;
886 sge = cb->atapi.sge;
887 memset(cb->atapi.cdb, 0, 32);
888 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
889
890 if (ata_is_data(qc->tf.protocol)) {
891 if (qc->tf.flags & ATA_TFLAG_WRITE)
892 ctrl = PRB_CTRL_PACKET_WRITE;
893 else
894 ctrl = PRB_CTRL_PACKET_READ;
895 }
896 }
897
898 prb->ctrl = cpu_to_le16(ctrl);
899 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
900
901 if (qc->flags & ATA_QCFLAG_DMAMAP)
902 sil24_fill_sg(qc, sge);
903 }
904
905 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
906 {
907 struct ata_port *ap = qc->ap;
908 struct sil24_port_priv *pp = ap->private_data;
909 void __iomem *port = ap->ioaddr.cmd_addr;
910 unsigned int tag = sil24_tag(qc->tag);
911 dma_addr_t paddr;
912 void __iomem *activate;
913
914 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
915 activate = port + PORT_CMD_ACTIVATE + tag * 8;
916
917 writel((u32)paddr, activate);
918 writel((u64)paddr >> 32, activate + 4);
919
920 return 0;
921 }
922
923 static void sil24_pmp_attach(struct ata_port *ap)
924 {
925 sil24_config_pmp(ap, 1);
926 sil24_init_port(ap);
927 }
928
929 static void sil24_pmp_detach(struct ata_port *ap)
930 {
931 sil24_init_port(ap);
932 sil24_config_pmp(ap, 0);
933 }
934
935 static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
936 unsigned long deadline)
937 {
938 return sil24_do_softreset(link, class, link->pmp, deadline);
939 }
940
941 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
942 unsigned long deadline)
943 {
944 int rc;
945
946 rc = sil24_init_port(link->ap);
947 if (rc) {
948 ata_link_printk(link, KERN_ERR,
949 "hardreset failed (port not ready)\n");
950 return rc;
951 }
952
953 return sata_pmp_std_hardreset(link, class, deadline);
954 }
955
956 static void sil24_freeze(struct ata_port *ap)
957 {
958 void __iomem *port = ap->ioaddr.cmd_addr;
959
960 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
961 * PORT_IRQ_ENABLE instead.
962 */
963 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
964 }
965
966 static void sil24_thaw(struct ata_port *ap)
967 {
968 void __iomem *port = ap->ioaddr.cmd_addr;
969 u32 tmp;
970
971 /* clear IRQ */
972 tmp = readl(port + PORT_IRQ_STAT);
973 writel(tmp, port + PORT_IRQ_STAT);
974
975 /* turn IRQ back on */
976 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
977 }
978
979 static void sil24_error_intr(struct ata_port *ap)
980 {
981 void __iomem *port = ap->ioaddr.cmd_addr;
982 struct sil24_port_priv *pp = ap->private_data;
983 struct ata_queued_cmd *qc = NULL;
984 struct ata_link *link;
985 struct ata_eh_info *ehi;
986 int abort = 0, freeze = 0;
987 u32 irq_stat;
988
989 /* on error, we need to clear IRQ explicitly */
990 irq_stat = readl(port + PORT_IRQ_STAT);
991 writel(irq_stat, port + PORT_IRQ_STAT);
992
993 /* first, analyze and record host port events */
994 link = &ap->link;
995 ehi = &link->eh_info;
996 ata_ehi_clear_desc(ehi);
997
998 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
999
1000 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
1001 ata_ehi_push_desc(ehi, "SDB notify");
1002 sata_async_notification(ap);
1003 }
1004
1005 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
1006 ata_ehi_hotplugged(ehi);
1007 ata_ehi_push_desc(ehi, "%s",
1008 irq_stat & PORT_IRQ_PHYRDY_CHG ?
1009 "PHY RDY changed" : "device exchanged");
1010 freeze = 1;
1011 }
1012
1013 if (irq_stat & PORT_IRQ_UNK_FIS) {
1014 ehi->err_mask |= AC_ERR_HSM;
1015 ehi->action |= ATA_EH_RESET;
1016 ata_ehi_push_desc(ehi, "unknown FIS");
1017 freeze = 1;
1018 }
1019
1020 /* deal with command error */
1021 if (irq_stat & PORT_IRQ_ERROR) {
1022 struct sil24_cerr_info *ci = NULL;
1023 unsigned int err_mask = 0, action = 0;
1024 u32 context, cerr;
1025 int pmp;
1026
1027 abort = 1;
1028
1029 /* DMA Context Switch Failure in Port Multiplier Mode
1030 * errata. If we have active commands to 3 or more
1031 * devices, any error condition on active devices can
1032 * corrupt DMA context switching.
1033 */
1034 if (ap->nr_active_links >= 3) {
1035 ehi->err_mask |= AC_ERR_OTHER;
1036 ehi->action |= ATA_EH_RESET;
1037 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1038 pp->do_port_rst = 1;
1039 freeze = 1;
1040 }
1041
1042 /* find out the offending link and qc */
1043 if (ap->nr_pmp_links) {
1044 context = readl(port + PORT_CONTEXT);
1045 pmp = (context >> 5) & 0xf;
1046
1047 if (pmp < ap->nr_pmp_links) {
1048 link = &ap->pmp_link[pmp];
1049 ehi = &link->eh_info;
1050 qc = ata_qc_from_tag(ap, link->active_tag);
1051
1052 ata_ehi_clear_desc(ehi);
1053 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1054 irq_stat);
1055 } else {
1056 err_mask |= AC_ERR_HSM;
1057 action |= ATA_EH_RESET;
1058 freeze = 1;
1059 }
1060 } else
1061 qc = ata_qc_from_tag(ap, link->active_tag);
1062
1063 /* analyze CMD_ERR */
1064 cerr = readl(port + PORT_CMD_ERR);
1065 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1066 ci = &sil24_cerr_db[cerr];
1067
1068 if (ci && ci->desc) {
1069 err_mask |= ci->err_mask;
1070 action |= ci->action;
1071 if (action & ATA_EH_RESET)
1072 freeze = 1;
1073 ata_ehi_push_desc(ehi, "%s", ci->desc);
1074 } else {
1075 err_mask |= AC_ERR_OTHER;
1076 action |= ATA_EH_RESET;
1077 freeze = 1;
1078 ata_ehi_push_desc(ehi, "unknown command error %d",
1079 cerr);
1080 }
1081
1082 /* record error info */
1083 if (qc) {
1084 sil24_read_tf(ap, qc->tag, &pp->tf);
1085 qc->err_mask |= err_mask;
1086 } else
1087 ehi->err_mask |= err_mask;
1088
1089 ehi->action |= action;
1090
1091 /* if PMP, resume */
1092 if (ap->nr_pmp_links)
1093 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1094 }
1095
1096 /* freeze or abort */
1097 if (freeze)
1098 ata_port_freeze(ap);
1099 else if (abort) {
1100 if (qc)
1101 ata_link_abort(qc->dev->link);
1102 else
1103 ata_port_abort(ap);
1104 }
1105 }
1106
1107 static void sil24_finish_qc(struct ata_queued_cmd *qc)
1108 {
1109 struct ata_port *ap = qc->ap;
1110 struct sil24_port_priv *pp = ap->private_data;
1111
1112 if (qc->flags & ATA_QCFLAG_RESULT_TF)
1113 sil24_read_tf(ap, qc->tag, &pp->tf);
1114 }
1115
1116 static inline void sil24_host_intr(struct ata_port *ap)
1117 {
1118 void __iomem *port = ap->ioaddr.cmd_addr;
1119 u32 slot_stat, qc_active;
1120 int rc;
1121
1122 /* If PCIX_IRQ_WOC, there's an inherent race window between
1123 * clearing IRQ pending status and reading PORT_SLOT_STAT
1124 * which may cause spurious interrupts afterwards. This is
1125 * unavoidable and much better than losing interrupts which
1126 * happens if IRQ pending is cleared after reading
1127 * PORT_SLOT_STAT.
1128 */
1129 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1130 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1131
1132 slot_stat = readl(port + PORT_SLOT_STAT);
1133
1134 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1135 sil24_error_intr(ap);
1136 return;
1137 }
1138
1139 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1140 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
1141 if (rc > 0)
1142 return;
1143 if (rc < 0) {
1144 struct ata_eh_info *ehi = &ap->link.eh_info;
1145 ehi->err_mask |= AC_ERR_HSM;
1146 ehi->action |= ATA_EH_RESET;
1147 ata_port_freeze(ap);
1148 return;
1149 }
1150
1151 /* spurious interrupts are expected if PCIX_IRQ_WOC */
1152 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1153 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1154 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
1155 slot_stat, ap->link.active_tag, ap->link.sactive);
1156 }
1157
1158 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1159 {
1160 struct ata_host *host = dev_instance;
1161 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1162 unsigned handled = 0;
1163 u32 status;
1164 int i;
1165
1166 status = readl(host_base + HOST_IRQ_STAT);
1167
1168 if (status == 0xffffffff) {
1169 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1170 "PCI fault or device removal?\n");
1171 goto out;
1172 }
1173
1174 if (!(status & IRQ_STAT_4PORTS))
1175 goto out;
1176
1177 spin_lock(&host->lock);
1178
1179 for (i = 0; i < host->n_ports; i++)
1180 if (status & (1 << i)) {
1181 struct ata_port *ap = host->ports[i];
1182 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
1183 sil24_host_intr(ap);
1184 handled++;
1185 } else
1186 printk(KERN_ERR DRV_NAME
1187 ": interrupt from disabled port %d\n", i);
1188 }
1189
1190 spin_unlock(&host->lock);
1191 out:
1192 return IRQ_RETVAL(handled);
1193 }
1194
1195 static void sil24_error_handler(struct ata_port *ap)
1196 {
1197 struct sil24_port_priv *pp = ap->private_data;
1198
1199 if (sil24_init_port(ap))
1200 ata_eh_freeze_port(ap);
1201
1202 /* perform recovery */
1203 sata_pmp_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
1204 ata_std_postreset, sata_pmp_std_prereset,
1205 sil24_pmp_softreset, sil24_pmp_hardreset,
1206 sata_pmp_std_postreset);
1207
1208 pp->do_port_rst = 0;
1209 }
1210
1211 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1212 {
1213 struct ata_port *ap = qc->ap;
1214
1215 /* make DMA engine forget about the failed command */
1216 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1217 ata_eh_freeze_port(ap);
1218 }
1219
1220 static int sil24_port_start(struct ata_port *ap)
1221 {
1222 struct device *dev = ap->host->dev;
1223 struct sil24_port_priv *pp;
1224 union sil24_cmd_block *cb;
1225 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1226 dma_addr_t cb_dma;
1227
1228 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1229 if (!pp)
1230 return -ENOMEM;
1231
1232 pp->tf.command = ATA_DRDY;
1233
1234 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1235 if (!cb)
1236 return -ENOMEM;
1237 memset(cb, 0, cb_size);
1238
1239 pp->cmd_block = cb;
1240 pp->cmd_block_dma = cb_dma;
1241
1242 ap->private_data = pp;
1243
1244 return 0;
1245 }
1246
1247 static void sil24_init_controller(struct ata_host *host)
1248 {
1249 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1250 u32 tmp;
1251 int i;
1252
1253 /* GPIO off */
1254 writel(0, host_base + HOST_FLASH_CMD);
1255
1256 /* clear global reset & mask interrupts during initialization */
1257 writel(0, host_base + HOST_CTRL);
1258
1259 /* init ports */
1260 for (i = 0; i < host->n_ports; i++) {
1261 struct ata_port *ap = host->ports[i];
1262 void __iomem *port = ap->ioaddr.cmd_addr;
1263
1264 /* Initial PHY setting */
1265 writel(0x20c, port + PORT_PHY_CFG);
1266
1267 /* Clear port RST */
1268 tmp = readl(port + PORT_CTRL_STAT);
1269 if (tmp & PORT_CS_PORT_RST) {
1270 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1271 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1272 PORT_CS_PORT_RST,
1273 PORT_CS_PORT_RST, 10, 100);
1274 if (tmp & PORT_CS_PORT_RST)
1275 dev_printk(KERN_ERR, host->dev,
1276 "failed to clear port RST\n");
1277 }
1278
1279 /* configure port */
1280 sil24_config_port(ap);
1281 }
1282
1283 /* Turn on interrupts */
1284 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1285 }
1286
1287 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1288 {
1289 extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
1290 static int printed_version;
1291 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1292 const struct ata_port_info *ppi[] = { &pi, NULL };
1293 void __iomem * const *iomap;
1294 struct ata_host *host;
1295 int i, rc;
1296 u32 tmp;
1297
1298 /* cause link error if sil24_cmd_block is sized wrongly */
1299 if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1300 __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1301
1302 if (!printed_version++)
1303 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1304
1305 /* acquire resources */
1306 rc = pcim_enable_device(pdev);
1307 if (rc)
1308 return rc;
1309
1310 rc = pcim_iomap_regions(pdev,
1311 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1312 DRV_NAME);
1313 if (rc)
1314 return rc;
1315 iomap = pcim_iomap_table(pdev);
1316
1317 /* apply workaround for completion IRQ loss on PCI-X errata */
1318 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1319 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1320 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1321 dev_printk(KERN_INFO, &pdev->dev,
1322 "Applying completion IRQ loss on PCI-X "
1323 "errata fix\n");
1324 else
1325 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1326 }
1327
1328 /* allocate and fill host */
1329 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1330 SIL24_FLAG2NPORTS(ppi[0]->flags));
1331 if (!host)
1332 return -ENOMEM;
1333 host->iomap = iomap;
1334
1335 for (i = 0; i < host->n_ports; i++) {
1336 struct ata_port *ap = host->ports[i];
1337 size_t offset = ap->port_no * PORT_REGS_SIZE;
1338 void __iomem *port = iomap[SIL24_PORT_BAR] + offset;
1339
1340 host->ports[i]->ioaddr.cmd_addr = port;
1341 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
1342
1343 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1344 ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port");
1345 }
1346
1347 /* configure and activate the device */
1348 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1349 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1350 if (rc) {
1351 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1352 if (rc) {
1353 dev_printk(KERN_ERR, &pdev->dev,
1354 "64-bit DMA enable failed\n");
1355 return rc;
1356 }
1357 }
1358 } else {
1359 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1360 if (rc) {
1361 dev_printk(KERN_ERR, &pdev->dev,
1362 "32-bit DMA enable failed\n");
1363 return rc;
1364 }
1365 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1366 if (rc) {
1367 dev_printk(KERN_ERR, &pdev->dev,
1368 "32-bit consistent DMA enable failed\n");
1369 return rc;
1370 }
1371 }
1372
1373 sil24_init_controller(host);
1374
1375 pci_set_master(pdev);
1376 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1377 &sil24_sht);
1378 }
1379
1380 #ifdef CONFIG_PM
1381 static int sil24_pci_device_resume(struct pci_dev *pdev)
1382 {
1383 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1384 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1385 int rc;
1386
1387 rc = ata_pci_device_do_resume(pdev);
1388 if (rc)
1389 return rc;
1390
1391 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1392 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1393
1394 sil24_init_controller(host);
1395
1396 ata_host_resume(host);
1397
1398 return 0;
1399 }
1400
1401 static int sil24_port_resume(struct ata_port *ap)
1402 {
1403 sil24_config_pmp(ap, ap->nr_pmp_links);
1404 return 0;
1405 }
1406 #endif
1407
1408 static int __init sil24_init(void)
1409 {
1410 return pci_register_driver(&sil24_pci_driver);
1411 }
1412
1413 static void __exit sil24_exit(void)
1414 {
1415 pci_unregister_driver(&sil24_pci_driver);
1416 }
1417
1418 MODULE_AUTHOR("Tejun Heo");
1419 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1420 MODULE_LICENSE("GPL");
1421 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1422
1423 module_init(sil24_init);
1424 module_exit(sil24_exit);
Linux kernel - Deliverables
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