2 * Broadcom specific AMBA
3 * ChipCommon core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
9 * Licensed under the GNU/GPL. See COPYING for details.
12 #include "bcma_private.h"
13 #include <linux/bcm47xx_wdt.h>
14 #include <linux/export.h>
15 #include <linux/platform_device.h>
16 #include <linux/bcma/bcma.h>
18 static inline u32
bcma_cc_write32_masked(struct bcma_drv_cc
*cc
, u16 offset
,
22 value
|= bcma_cc_read32(cc
, offset
) & ~mask
;
23 bcma_cc_write32(cc
, offset
, value
);
28 static u32
bcma_chipco_get_alp_clock(struct bcma_drv_cc
*cc
)
30 if (cc
->capabilities
& BCMA_CC_CAP_PMU
)
31 return bcma_pmu_get_alp_clock(cc
);
36 static u32
bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc
*cc
)
38 struct bcma_bus
*bus
= cc
->core
->bus
;
41 if (cc
->capabilities
& BCMA_CC_CAP_PMU
) {
42 if (bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM4706
)
44 else if (cc
->core
->id
.rev
< 26)
47 nb
= (cc
->core
->id
.rev
>= 37) ? 32 : 24;
57 static u32
bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt
*wdt
,
60 struct bcma_drv_cc
*cc
= bcm47xx_wdt_get_drvdata(wdt
);
62 return bcma_chipco_watchdog_timer_set(cc
, ticks
);
65 static u32
bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt
*wdt
,
68 struct bcma_drv_cc
*cc
= bcm47xx_wdt_get_drvdata(wdt
);
71 ticks
= bcma_chipco_watchdog_timer_set(cc
, cc
->ticks_per_ms
* ms
);
72 return ticks
/ cc
->ticks_per_ms
;
75 static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc
*cc
)
77 struct bcma_bus
*bus
= cc
->core
->bus
;
79 if (cc
->capabilities
& BCMA_CC_CAP_PMU
) {
80 if (bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM4706
)
81 /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
82 return bcma_chipco_get_alp_clock(cc
) / 4000;
84 /* based on 32KHz ILP clock */
87 return bcma_chipco_get_alp_clock(cc
) / 1000;
91 int bcma_chipco_watchdog_register(struct bcma_drv_cc
*cc
)
93 struct bcm47xx_wdt wdt
= {};
94 struct platform_device
*pdev
;
97 wdt
.timer_set
= bcma_chipco_watchdog_timer_set_wdt
;
98 wdt
.timer_set_ms
= bcma_chipco_watchdog_timer_set_ms_wdt
;
99 wdt
.max_timer_ms
= bcma_chipco_watchdog_get_max_timer(cc
) / cc
->ticks_per_ms
;
101 pdev
= platform_device_register_data(NULL
, "bcm47xx-wdt",
102 cc
->core
->bus
->num
, &wdt
,
105 return PTR_ERR(pdev
);
112 void bcma_core_chipcommon_early_init(struct bcma_drv_cc
*cc
)
114 if (cc
->early_setup_done
)
117 spin_lock_init(&cc
->gpio_lock
);
119 if (cc
->core
->id
.rev
>= 11)
120 cc
->status
= bcma_cc_read32(cc
, BCMA_CC_CHIPSTAT
);
121 cc
->capabilities
= bcma_cc_read32(cc
, BCMA_CC_CAP
);
122 if (cc
->core
->id
.rev
>= 35)
123 cc
->capabilities_ext
= bcma_cc_read32(cc
, BCMA_CC_CAP_EXT
);
125 if (cc
->capabilities
& BCMA_CC_CAP_PMU
)
126 bcma_pmu_early_init(cc
);
128 cc
->early_setup_done
= true;
131 void bcma_core_chipcommon_init(struct bcma_drv_cc
*cc
)
139 bcma_core_chipcommon_early_init(cc
);
141 if (cc
->core
->id
.rev
>= 20) {
142 bcma_cc_write32(cc
, BCMA_CC_GPIOPULLUP
, 0);
143 bcma_cc_write32(cc
, BCMA_CC_GPIOPULLDOWN
, 0);
146 if (cc
->capabilities
& BCMA_CC_CAP_PMU
)
148 if (cc
->capabilities
& BCMA_CC_CAP_PCTL
)
149 bcma_err(cc
->core
->bus
, "Power control not implemented!\n");
151 if (cc
->core
->id
.rev
>= 16) {
152 if (cc
->core
->bus
->sprom
.leddc_on_time
&&
153 cc
->core
->bus
->sprom
.leddc_off_time
) {
154 leddc_on
= cc
->core
->bus
->sprom
.leddc_on_time
;
155 leddc_off
= cc
->core
->bus
->sprom
.leddc_off_time
;
157 bcma_cc_write32(cc
, BCMA_CC_GPIOTIMER
,
158 ((leddc_on
<< BCMA_CC_GPIOTIMER_ONTIME_SHIFT
) |
159 (leddc_off
<< BCMA_CC_GPIOTIMER_OFFTIME_SHIFT
)));
161 cc
->ticks_per_ms
= bcma_chipco_watchdog_ticks_per_ms(cc
);
163 cc
->setup_done
= true;
166 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
167 u32
bcma_chipco_watchdog_timer_set(struct bcma_drv_cc
*cc
, u32 ticks
)
170 enum bcma_clkmode clkmode
;
172 maxt
= bcma_chipco_watchdog_get_max_timer(cc
);
173 if (cc
->capabilities
& BCMA_CC_CAP_PMU
) {
176 else if (ticks
> maxt
)
178 bcma_cc_write32(cc
, BCMA_CC_PMU_WATCHDOG
, ticks
);
180 clkmode
= ticks
? BCMA_CLKMODE_FAST
: BCMA_CLKMODE_DYNAMIC
;
181 bcma_core_set_clockmode(cc
->core
, clkmode
);
185 bcma_cc_write32(cc
, BCMA_CC_WATCHDOG
, ticks
);
190 void bcma_chipco_irq_mask(struct bcma_drv_cc
*cc
, u32 mask
, u32 value
)
192 bcma_cc_write32_masked(cc
, BCMA_CC_IRQMASK
, mask
, value
);
195 u32
bcma_chipco_irq_status(struct bcma_drv_cc
*cc
, u32 mask
)
197 return bcma_cc_read32(cc
, BCMA_CC_IRQSTAT
) & mask
;
200 u32
bcma_chipco_gpio_in(struct bcma_drv_cc
*cc
, u32 mask
)
202 return bcma_cc_read32(cc
, BCMA_CC_GPIOIN
) & mask
;
205 u32
bcma_chipco_gpio_out(struct bcma_drv_cc
*cc
, u32 mask
, u32 value
)
210 spin_lock_irqsave(&cc
->gpio_lock
, flags
);
211 res
= bcma_cc_write32_masked(cc
, BCMA_CC_GPIOOUT
, mask
, value
);
212 spin_unlock_irqrestore(&cc
->gpio_lock
, flags
);
217 u32
bcma_chipco_gpio_outen(struct bcma_drv_cc
*cc
, u32 mask
, u32 value
)
222 spin_lock_irqsave(&cc
->gpio_lock
, flags
);
223 res
= bcma_cc_write32_masked(cc
, BCMA_CC_GPIOOUTEN
, mask
, value
);
224 spin_unlock_irqrestore(&cc
->gpio_lock
, flags
);
230 * If the bit is set to 0, chipcommon controlls this GPIO,
231 * if the bit is set to 1, it is used by some part of the chip and not our code.
233 u32
bcma_chipco_gpio_control(struct bcma_drv_cc
*cc
, u32 mask
, u32 value
)
238 spin_lock_irqsave(&cc
->gpio_lock
, flags
);
239 res
= bcma_cc_write32_masked(cc
, BCMA_CC_GPIOCTL
, mask
, value
);
240 spin_unlock_irqrestore(&cc
->gpio_lock
, flags
);
244 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control
);
246 u32
bcma_chipco_gpio_intmask(struct bcma_drv_cc
*cc
, u32 mask
, u32 value
)
251 spin_lock_irqsave(&cc
->gpio_lock
, flags
);
252 res
= bcma_cc_write32_masked(cc
, BCMA_CC_GPIOIRQ
, mask
, value
);
253 spin_unlock_irqrestore(&cc
->gpio_lock
, flags
);
258 u32
bcma_chipco_gpio_polarity(struct bcma_drv_cc
*cc
, u32 mask
, u32 value
)
263 spin_lock_irqsave(&cc
->gpio_lock
, flags
);
264 res
= bcma_cc_write32_masked(cc
, BCMA_CC_GPIOPOL
, mask
, value
);
265 spin_unlock_irqrestore(&cc
->gpio_lock
, flags
);
270 u32
bcma_chipco_gpio_pullup(struct bcma_drv_cc
*cc
, u32 mask
, u32 value
)
275 if (cc
->core
->id
.rev
< 20)
278 spin_lock_irqsave(&cc
->gpio_lock
, flags
);
279 res
= bcma_cc_write32_masked(cc
, BCMA_CC_GPIOPULLUP
, mask
, value
);
280 spin_unlock_irqrestore(&cc
->gpio_lock
, flags
);
285 u32
bcma_chipco_gpio_pulldown(struct bcma_drv_cc
*cc
, u32 mask
, u32 value
)
290 if (cc
->core
->id
.rev
< 20)
293 spin_lock_irqsave(&cc
->gpio_lock
, flags
);
294 res
= bcma_cc_write32_masked(cc
, BCMA_CC_GPIOPULLDOWN
, mask
, value
);
295 spin_unlock_irqrestore(&cc
->gpio_lock
, flags
);
300 #ifdef CONFIG_BCMA_DRIVER_MIPS
301 void bcma_chipco_serial_init(struct bcma_drv_cc
*cc
)
306 unsigned int ccrev
= cc
->core
->id
.rev
;
307 struct bcma_serial_port
*ports
= cc
->serial_ports
;
309 if (ccrev
>= 11 && ccrev
!= 15) {
310 baud_base
= bcma_chipco_get_alp_clock(cc
);
312 /* Turn off UART clock before switching clocksource. */
313 bcma_cc_write32(cc
, BCMA_CC_CORECTL
,
314 bcma_cc_read32(cc
, BCMA_CC_CORECTL
)
315 & ~BCMA_CC_CORECTL_UARTCLKEN
);
317 /* Set the override bit so we don't divide it */
318 bcma_cc_write32(cc
, BCMA_CC_CORECTL
,
319 bcma_cc_read32(cc
, BCMA_CC_CORECTL
)
320 | BCMA_CC_CORECTL_UARTCLK0
);
322 /* Re-enable the UART clock. */
323 bcma_cc_write32(cc
, BCMA_CC_CORECTL
,
324 bcma_cc_read32(cc
, BCMA_CC_CORECTL
)
325 | BCMA_CC_CORECTL_UARTCLKEN
);
328 bcma_err(cc
->core
->bus
, "serial not supported on this device ccrev: 0x%x\n", ccrev
);
332 irq
= bcma_core_mips_irq(cc
->core
);
334 /* Determine the registers of the UARTs */
335 cc
->nr_serial_ports
= (cc
->capabilities
& BCMA_CC_CAP_NRUART
);
336 for (i
= 0; i
< cc
->nr_serial_ports
; i
++) {
337 ports
[i
].regs
= cc
->core
->io_addr
+ BCMA_CC_UART0_DATA
+
340 ports
[i
].baud_base
= baud_base
;
341 ports
[i
].reg_shift
= 0;
344 #endif /* CONFIG_BCMA_DRIVER_MIPS */