drivers/bcma/driver_chipcommon_pmu.c

   1 /*
   2  * Broadcom specific AMBA
   3  * ChipCommon Power Management Unit driver
   4  *
   5  * Copyright 2009, Michael Buesch <m@bues.ch>
   6  * Copyright 2007, Broadcom Corporation
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include "bcma_private.h"
  12 #include <linux/export.h>
  13 #include <linux/bcma/bcma.h>
  14
  15 static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
  16 {
  17         bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  18         bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  19         return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
  20 }
  21
  22 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
  23 {
  24         bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  25         bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  26         bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
  27 }
  28 EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
  29
  30 void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
  31                              u32 set)
  32 {
  33         bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  34         bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  35         bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
  36 }
  37 EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
  38
  39 void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
  40                                  u32 offset, u32 mask, u32 set)
  41 {
  42         bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
  43         bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
  44         bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
  45 }
  46 EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
  47
  48 void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
  49                                 u32 set)
  50 {
  51         bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
  52         bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
  53         bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
  54 }
  55 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
  56
  57 static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
  58 {
  59         struct bcma_bus *bus = cc->core->bus;
  60
  61         switch (bus->chipinfo.id) {
  62         case 0x4313:
  63         case 0x4331:
  64         case 43224:
  65         case 43225:
  66                 break;
  67         default:
  68                 pr_err("PLL init unknown for device 0x%04X\n",
  69                         bus->chipinfo.id);
  70         }
  71 }
  72
  73 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
  74 {
  75         struct bcma_bus *bus = cc->core->bus;
  76         u32 min_msk = 0, max_msk = 0;
  77
  78         switch (bus->chipinfo.id) {
  79         case 0x4313:
  80                 min_msk = 0x200D;
  81                 max_msk = 0xFFFF;
  82                 break;
  83         case 0x4331:
  84         case 43224:
  85         case 43225:
  86                 break;
  87         default:
  88                 pr_err("PMU resource config unknown for device 0x%04X\n",
  89                         bus->chipinfo.id);
  90         }
  91
  92         /* Set the resource masks. */
  93         if (min_msk)
  94                 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
  95         if (max_msk)
  96                 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
  97 }
  98
  99 void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
 100 {
 101         struct bcma_bus *bus = cc->core->bus;
 102
 103         switch (bus->chipinfo.id) {
 104         case 0x4313:
 105         case 0x4331:
 106         case 43224:
 107         case 43225:
 108                 break;
 109         default:
 110                 pr_err("PMU switch/regulators init unknown for device "
 111                         "0x%04X\n", bus->chipinfo.id);
 112         }
 113 }
 114
 115 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
 116 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
 117 {
 118         struct bcma_bus *bus = cc->core->bus;
 119         u32 val;
 120
 121         val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
 122         if (enable) {
 123                 val |= BCMA_CHIPCTL_4331_EXTPA_EN;
 124                 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
 125                         val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
 126         } else {
 127                 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
 128                 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
 129         }
 130         bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
 131 }
 132
 133 void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
 134 {
 135         struct bcma_bus *bus = cc->core->bus;
 136
 137         switch (bus->chipinfo.id) {
 138         case 0x4313:
 139                 bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
 140                 break;
 141         case 0x4331:
 142                 /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
 143                 break;
 144         case 43224:
 145                 if (bus->chipinfo.rev == 0) {
 146                         pr_err("Workarounds for 43224 rev 0 not fully "
 147                                 "implemented\n");
 148                         bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
 149                 } else {
 150                         bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
 151                 }
 152                 break;
 153         case 43225:
 154                 break;
 155         default:
 156                 pr_err("Workarounds unknown for device 0x%04X\n",
 157                         bus->chipinfo.id);
 158         }
 159 }
 160
 161 void bcma_pmu_init(struct bcma_drv_cc *cc)
 162 {
 163         u32 pmucap;
 164
 165         pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
 166         cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
 167
 168         pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
 169                  pmucap);
 170
 171         if (cc->pmu.rev == 1)
 172                 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
 173                               ~BCMA_CC_PMU_CTL_NOILPONW);
 174         else
 175                 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
 176                              BCMA_CC_PMU_CTL_NOILPONW);
 177
 178         if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
 179                 pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
 180
 181         bcma_pmu_pll_init(cc);
 182         bcma_pmu_resources_init(cc);
 183         bcma_pmu_swreg_init(cc);
 184         bcma_pmu_workarounds(cc);
 185 }
 186
 187 u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
 188 {
 189         struct bcma_bus *bus = cc->core->bus;
 190
 191         switch (bus->chipinfo.id) {
 192         case 0x4716:
 193         case 0x4748:
 194         case 47162:
 195         case 0x4313:
 196         case 0x5357:
 197         case 0x4749:
 198         case 53572:
 199                 /* always 20Mhz */
 200                 return 20000 * 1000;
 201         case 0x5356:
 202         case 0x5300:
 203                 /* always 25Mhz */
 204                 return 25000 * 1000;
 205         default:
 206                 pr_warn("No ALP clock specified for %04X device, "
 207                         "pmu rev. %d, using default %d Hz\n",
 208                         bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
 209         }
 210         return BCMA_CC_PMU_ALP_CLOCK;
 211 }
 212
 213 /* Find the output of the "m" pll divider given pll controls that start with
 214  * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
 215  */
 216 static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 217 {
 218         u32 tmp, div, ndiv, p1, p2, fc;
 219         struct bcma_bus *bus = cc->core->bus;
 220
 221         BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
 222
 223         BUG_ON(!m || m > 4);
 224
 225         if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
 226                 /* Detect failure in clock setting */
 227                 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
 228                 if (tmp & 0x40000)
 229                         return 133 * 1000000;
 230         }
 231
 232         tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
 233         p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
 234         p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
 235
 236         tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
 237         div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
 238                 BCMA_CC_PPL_MDIV_MASK;
 239
 240         tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
 241         ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
 242
 243         /* Do calculation in Mhz */
 244         fc = bcma_pmu_alp_clock(cc) / 1000000;
 245         fc = (p1 * ndiv * fc) / p2;
 246
 247         /* Return clock in Hertz */
 248         return (fc / div) * 1000000;
 249 }
 250
 251 /* query bus clock frequency for PMU-enabled chipcommon */
 252 u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
 253 {
 254         struct bcma_bus *bus = cc->core->bus;
 255
 256         switch (bus->chipinfo.id) {
 257         case 0x4716:
 258         case 0x4748:
 259         case 47162:
 260                 return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
 261                                       BCMA_CC_PMU5_MAINPLL_SSB);
 262         case 0x5356:
 263                 return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
 264                                       BCMA_CC_PMU5_MAINPLL_SSB);
 265         case 0x5357:
 266         case 0x4749:
 267                 return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
 268                                       BCMA_CC_PMU5_MAINPLL_SSB);
 269         case 0x5300:
 270                 return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
 271                                       BCMA_CC_PMU5_MAINPLL_SSB);
 272         case 53572:
 273                 return 75000000;
 274         default:
 275                 pr_warn("No backplane clock specified for %04X device, "
 276                         "pmu rev. %d, using default %d Hz\n",
 277                         bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
 278         }
 279         return BCMA_CC_PMU_HT_CLOCK;
 280 }
 281
 282 /* query cpu clock frequency for PMU-enabled chipcommon */
 283 u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
 284 {
 285         struct bcma_bus *bus = cc->core->bus;
 286
 287         if (bus->chipinfo.id == 53572)
 288                 return 300000000;
 289
 290         if (cc->pmu.rev >= 5) {
 291                 u32 pll;
 292                 switch (bus->chipinfo.id) {
 293                 case 0x5356:
 294                         pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
 295                         break;
 296                 case 0x5357:
 297                 case 0x4749:
 298                         pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
 299                         break;
 300                 default:
 301                         pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
 302                         break;
 303                 }
 304
 305                 /* TODO: if (bus->chipinfo.id == 0x5300)
 306                   return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
 307                 return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
 308         }
 309
 310         return bcma_pmu_get_clockcontrol(cc);
 311 }