2 * Broadcom specific AMBA
3 * ChipCommon Power Management Unit driver
5 * Copyright 2009, Michael Buesch <m@bues.ch>
6 * Copyright 2007, Broadcom Corporation
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include "bcma_private.h"
12 #include <linux/export.h>
13 #include <linux/bcma/bcma.h>
15 static u32
bcma_chipco_pll_read(struct bcma_drv_cc
*cc
, u32 offset
)
17 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
, offset
);
18 bcma_cc_read32(cc
, BCMA_CC_PLLCTL_ADDR
);
19 return bcma_cc_read32(cc
, BCMA_CC_PLLCTL_DATA
);
22 void bcma_chipco_pll_write(struct bcma_drv_cc
*cc
, u32 offset
, u32 value
)
24 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
, offset
);
25 bcma_cc_read32(cc
, BCMA_CC_PLLCTL_ADDR
);
26 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_DATA
, value
);
28 EXPORT_SYMBOL_GPL(bcma_chipco_pll_write
);
30 void bcma_chipco_pll_maskset(struct bcma_drv_cc
*cc
, u32 offset
, u32 mask
,
33 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
, offset
);
34 bcma_cc_read32(cc
, BCMA_CC_PLLCTL_ADDR
);
35 bcma_cc_maskset32(cc
, BCMA_CC_PLLCTL_DATA
, mask
, set
);
37 EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset
);
39 void bcma_chipco_chipctl_maskset(struct bcma_drv_cc
*cc
,
40 u32 offset
, u32 mask
, u32 set
)
42 bcma_cc_write32(cc
, BCMA_CC_CHIPCTL_ADDR
, offset
);
43 bcma_cc_read32(cc
, BCMA_CC_CHIPCTL_ADDR
);
44 bcma_cc_maskset32(cc
, BCMA_CC_CHIPCTL_DATA
, mask
, set
);
46 EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset
);
48 void bcma_chipco_regctl_maskset(struct bcma_drv_cc
*cc
, u32 offset
, u32 mask
,
51 bcma_cc_write32(cc
, BCMA_CC_REGCTL_ADDR
, offset
);
52 bcma_cc_read32(cc
, BCMA_CC_REGCTL_ADDR
);
53 bcma_cc_maskset32(cc
, BCMA_CC_REGCTL_DATA
, mask
, set
);
55 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset
);
57 static void bcma_pmu_pll_init(struct bcma_drv_cc
*cc
)
59 struct bcma_bus
*bus
= cc
->core
->bus
;
61 switch (bus
->chipinfo
.id
) {
68 pr_err("PLL init unknown for device 0x%04X\n",
73 static void bcma_pmu_resources_init(struct bcma_drv_cc
*cc
)
75 struct bcma_bus
*bus
= cc
->core
->bus
;
76 u32 min_msk
= 0, max_msk
= 0;
78 switch (bus
->chipinfo
.id
) {
88 pr_err("PMU resource config unknown for device 0x%04X\n",
92 /* Set the resource masks. */
94 bcma_cc_write32(cc
, BCMA_CC_PMU_MINRES_MSK
, min_msk
);
96 bcma_cc_write32(cc
, BCMA_CC_PMU_MAXRES_MSK
, max_msk
);
99 void bcma_pmu_swreg_init(struct bcma_drv_cc
*cc
)
101 struct bcma_bus
*bus
= cc
->core
->bus
;
103 switch (bus
->chipinfo
.id
) {
110 pr_err("PMU switch/regulators init unknown for device "
111 "0x%04X\n", bus
->chipinfo
.id
);
115 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
116 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc
*cc
, bool enable
)
118 struct bcma_bus
*bus
= cc
->core
->bus
;
121 val
= bcma_cc_read32(cc
, BCMA_CC_CHIPCTL
);
123 val
|= BCMA_CHIPCTL_4331_EXTPA_EN
;
124 if (bus
->chipinfo
.pkg
== 9 || bus
->chipinfo
.pkg
== 11)
125 val
|= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5
;
127 val
&= ~BCMA_CHIPCTL_4331_EXTPA_EN
;
128 val
&= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5
;
130 bcma_cc_write32(cc
, BCMA_CC_CHIPCTL
, val
);
133 void bcma_pmu_workarounds(struct bcma_drv_cc
*cc
)
135 struct bcma_bus
*bus
= cc
->core
->bus
;
137 switch (bus
->chipinfo
.id
) {
139 bcma_chipco_chipctl_maskset(cc
, 0, ~0, 0x7);
143 /* Ext PA lines must be enabled for tx on BCM4331 */
144 bcma_chipco_bcm4331_ext_pa_lines_ctl(cc
, true);
147 if (bus
->chipinfo
.rev
== 0) {
148 pr_err("Workarounds for 43224 rev 0 not fully "
150 bcma_chipco_chipctl_maskset(cc
, 0, ~0, 0x00F000F0);
152 bcma_chipco_chipctl_maskset(cc
, 0, ~0, 0xF0);
158 pr_err("Workarounds unknown for device 0x%04X\n",
163 void bcma_pmu_init(struct bcma_drv_cc
*cc
)
167 pmucap
= bcma_cc_read32(cc
, BCMA_CC_PMU_CAP
);
168 cc
->pmu
.rev
= (pmucap
& BCMA_CC_PMU_CAP_REVISION
);
170 pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc
->pmu
.rev
,
173 if (cc
->pmu
.rev
== 1)
174 bcma_cc_mask32(cc
, BCMA_CC_PMU_CTL
,
175 ~BCMA_CC_PMU_CTL_NOILPONW
);
177 bcma_cc_set32(cc
, BCMA_CC_PMU_CTL
,
178 BCMA_CC_PMU_CTL_NOILPONW
);
180 if (cc
->core
->id
.id
== 0x4329 && cc
->core
->id
.rev
== 2)
181 pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
183 bcma_pmu_pll_init(cc
);
184 bcma_pmu_resources_init(cc
);
185 bcma_pmu_swreg_init(cc
);
186 bcma_pmu_workarounds(cc
);
189 u32
bcma_pmu_alp_clock(struct bcma_drv_cc
*cc
)
191 struct bcma_bus
*bus
= cc
->core
->bus
;
193 switch (bus
->chipinfo
.id
) {
208 pr_warn("No ALP clock specified for %04X device, "
209 "pmu rev. %d, using default %d Hz\n",
210 bus
->chipinfo
.id
, cc
->pmu
.rev
, BCMA_CC_PMU_ALP_CLOCK
);
212 return BCMA_CC_PMU_ALP_CLOCK
;
215 /* Find the output of the "m" pll divider given pll controls that start with
216 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
218 static u32
bcma_pmu_clock(struct bcma_drv_cc
*cc
, u32 pll0
, u32 m
)
220 u32 tmp
, div
, ndiv
, p1
, p2
, fc
;
221 struct bcma_bus
*bus
= cc
->core
->bus
;
223 BUG_ON((pll0
& 3) || (pll0
> BCMA_CC_PMU4716_MAINPLL_PLL0
));
227 if (bus
->chipinfo
.id
== 0x5357 || bus
->chipinfo
.id
== 0x4749) {
228 /* Detect failure in clock setting */
229 tmp
= bcma_cc_read32(cc
, BCMA_CC_CHIPSTAT
);
231 return 133 * 1000000;
234 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PPL_P1P2_OFF
);
235 p1
= (tmp
& BCMA_CC_PPL_P1_MASK
) >> BCMA_CC_PPL_P1_SHIFT
;
236 p2
= (tmp
& BCMA_CC_PPL_P2_MASK
) >> BCMA_CC_PPL_P2_SHIFT
;
238 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PPL_M14_OFF
);
239 div
= (tmp
>> ((m
- 1) * BCMA_CC_PPL_MDIV_WIDTH
)) &
240 BCMA_CC_PPL_MDIV_MASK
;
242 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PPL_NM5_OFF
);
243 ndiv
= (tmp
& BCMA_CC_PPL_NDIV_MASK
) >> BCMA_CC_PPL_NDIV_SHIFT
;
245 /* Do calculation in Mhz */
246 fc
= bcma_pmu_alp_clock(cc
) / 1000000;
247 fc
= (p1
* ndiv
* fc
) / p2
;
249 /* Return clock in Hertz */
250 return (fc
/ div
) * 1000000;
253 /* query bus clock frequency for PMU-enabled chipcommon */
254 u32
bcma_pmu_get_clockcontrol(struct bcma_drv_cc
*cc
)
256 struct bcma_bus
*bus
= cc
->core
->bus
;
258 switch (bus
->chipinfo
.id
) {
262 return bcma_pmu_clock(cc
, BCMA_CC_PMU4716_MAINPLL_PLL0
,
263 BCMA_CC_PMU5_MAINPLL_SSB
);
265 return bcma_pmu_clock(cc
, BCMA_CC_PMU5356_MAINPLL_PLL0
,
266 BCMA_CC_PMU5_MAINPLL_SSB
);
269 return bcma_pmu_clock(cc
, BCMA_CC_PMU5357_MAINPLL_PLL0
,
270 BCMA_CC_PMU5_MAINPLL_SSB
);
272 return bcma_pmu_clock(cc
, BCMA_CC_PMU4706_MAINPLL_PLL0
,
273 BCMA_CC_PMU5_MAINPLL_SSB
);
277 pr_warn("No backplane clock specified for %04X device, "
278 "pmu rev. %d, using default %d Hz\n",
279 bus
->chipinfo
.id
, cc
->pmu
.rev
, BCMA_CC_PMU_HT_CLOCK
);
281 return BCMA_CC_PMU_HT_CLOCK
;
284 /* query cpu clock frequency for PMU-enabled chipcommon */
285 u32
bcma_pmu_get_clockcpu(struct bcma_drv_cc
*cc
)
287 struct bcma_bus
*bus
= cc
->core
->bus
;
289 if (bus
->chipinfo
.id
== 53572)
292 if (cc
->pmu
.rev
>= 5) {
294 switch (bus
->chipinfo
.id
) {
296 pll
= BCMA_CC_PMU5356_MAINPLL_PLL0
;
300 pll
= BCMA_CC_PMU5357_MAINPLL_PLL0
;
303 pll
= BCMA_CC_PMU4716_MAINPLL_PLL0
;
307 /* TODO: if (bus->chipinfo.id == 0x5300)
308 return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
309 return bcma_pmu_clock(cc
, pll
, BCMA_CC_PMU5_MAINPLL_CPU
);
312 return bcma_pmu_get_clockcontrol(cc
);