Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/borntraeger...
[deliverable/linux.git] / drivers / block / nvme-core.c
1 /*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/nvme.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
22 #include <linux/fs.h>
23 #include <linux/genhd.h>
24 #include <linux/hdreg.h>
25 #include <linux/idr.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/kdev_t.h>
30 #include <linux/kthread.h>
31 #include <linux/kernel.h>
32 #include <linux/mm.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/types.h>
41 #include <scsi/sg.h>
42 #include <asm-generic/io-64-nonatomic-lo-hi.h>
43
44 #define NVME_Q_DEPTH 1024
45 #define NVME_AQ_DEPTH 64
46 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
48 #define ADMIN_TIMEOUT (admin_timeout * HZ)
49 #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
50 #define IOD_TIMEOUT (retry_time * HZ)
51
52 static unsigned char admin_timeout = 60;
53 module_param(admin_timeout, byte, 0644);
54 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
55
56 unsigned char nvme_io_timeout = 30;
57 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
58 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
59
60 static unsigned char retry_time = 30;
61 module_param(retry_time, byte, 0644);
62 MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
63
64 static unsigned char shutdown_timeout = 5;
65 module_param(shutdown_timeout, byte, 0644);
66 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
67
68 static int nvme_major;
69 module_param(nvme_major, int, 0);
70
71 static int use_threaded_interrupts;
72 module_param(use_threaded_interrupts, int, 0);
73
74 static DEFINE_SPINLOCK(dev_list_lock);
75 static LIST_HEAD(dev_list);
76 static struct task_struct *nvme_thread;
77 static struct workqueue_struct *nvme_workq;
78 static wait_queue_head_t nvme_kthread_wait;
79 static struct notifier_block nvme_nb;
80
81 static void nvme_reset_failed_dev(struct work_struct *ws);
82 static int nvme_process_cq(struct nvme_queue *nvmeq);
83
84 struct async_cmd_info {
85 struct kthread_work work;
86 struct kthread_worker *worker;
87 struct request *req;
88 u32 result;
89 int status;
90 void *ctx;
91 };
92
93 /*
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
96 */
97 struct nvme_queue {
98 struct llist_node node;
99 struct device *q_dmadev;
100 struct nvme_dev *dev;
101 char irqname[24]; /* nvme4294967295-65535\0 */
102 spinlock_t q_lock;
103 struct nvme_command *sq_cmds;
104 volatile struct nvme_completion *cqes;
105 dma_addr_t sq_dma_addr;
106 dma_addr_t cq_dma_addr;
107 u32 __iomem *q_db;
108 u16 q_depth;
109 u16 cq_vector;
110 u16 sq_head;
111 u16 sq_tail;
112 u16 cq_head;
113 u16 qid;
114 u8 cq_phase;
115 u8 cqe_seen;
116 struct async_cmd_info cmdinfo;
117 struct blk_mq_hw_ctx *hctx;
118 };
119
120 /*
121 * Check we didin't inadvertently grow the command struct
122 */
123 static inline void _nvme_check_size(void)
124 {
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
137 }
138
139 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
140 struct nvme_completion *);
141
142 struct nvme_cmd_info {
143 nvme_completion_fn fn;
144 void *ctx;
145 int aborted;
146 struct nvme_queue *nvmeq;
147 };
148
149 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
150 unsigned int hctx_idx)
151 {
152 struct nvme_dev *dev = data;
153 struct nvme_queue *nvmeq = dev->queues[0];
154
155 WARN_ON(nvmeq->hctx);
156 nvmeq->hctx = hctx;
157 hctx->driver_data = nvmeq;
158 return 0;
159 }
160
161 static int nvme_admin_init_request(void *data, struct request *req,
162 unsigned int hctx_idx, unsigned int rq_idx,
163 unsigned int numa_node)
164 {
165 struct nvme_dev *dev = data;
166 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
167 struct nvme_queue *nvmeq = dev->queues[0];
168
169 BUG_ON(!nvmeq);
170 cmd->nvmeq = nvmeq;
171 return 0;
172 }
173
174 static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
175 {
176 struct nvme_queue *nvmeq = hctx->driver_data;
177
178 nvmeq->hctx = NULL;
179 }
180
181 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
182 unsigned int hctx_idx)
183 {
184 struct nvme_dev *dev = data;
185 struct nvme_queue *nvmeq = dev->queues[
186 (hctx_idx % dev->queue_count) + 1];
187
188 if (!nvmeq->hctx)
189 nvmeq->hctx = hctx;
190
191 /* nvmeq queues are shared between namespaces. We assume here that
192 * blk-mq map the tags so they match up with the nvme queue tags. */
193 WARN_ON(nvmeq->hctx->tags != hctx->tags);
194
195 hctx->driver_data = nvmeq;
196 return 0;
197 }
198
199 static int nvme_init_request(void *data, struct request *req,
200 unsigned int hctx_idx, unsigned int rq_idx,
201 unsigned int numa_node)
202 {
203 struct nvme_dev *dev = data;
204 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
205 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
206
207 BUG_ON(!nvmeq);
208 cmd->nvmeq = nvmeq;
209 return 0;
210 }
211
212 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
213 nvme_completion_fn handler)
214 {
215 cmd->fn = handler;
216 cmd->ctx = ctx;
217 cmd->aborted = 0;
218 }
219
220 /* Special values must be less than 0x1000 */
221 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
222 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
223 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
224 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
225
226 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
227 struct nvme_completion *cqe)
228 {
229 if (ctx == CMD_CTX_CANCELLED)
230 return;
231 if (ctx == CMD_CTX_COMPLETED) {
232 dev_warn(nvmeq->q_dmadev,
233 "completed id %d twice on queue %d\n",
234 cqe->command_id, le16_to_cpup(&cqe->sq_id));
235 return;
236 }
237 if (ctx == CMD_CTX_INVALID) {
238 dev_warn(nvmeq->q_dmadev,
239 "invalid id %d completed on queue %d\n",
240 cqe->command_id, le16_to_cpup(&cqe->sq_id));
241 return;
242 }
243 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
244 }
245
246 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
247 {
248 void *ctx;
249
250 if (fn)
251 *fn = cmd->fn;
252 ctx = cmd->ctx;
253 cmd->fn = special_completion;
254 cmd->ctx = CMD_CTX_CANCELLED;
255 return ctx;
256 }
257
258 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
259 struct nvme_completion *cqe)
260 {
261 struct request *req = ctx;
262
263 u32 result = le32_to_cpup(&cqe->result);
264 u16 status = le16_to_cpup(&cqe->status) >> 1;
265
266 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
267 ++nvmeq->dev->event_limit;
268 if (status == NVME_SC_SUCCESS)
269 dev_warn(nvmeq->q_dmadev,
270 "async event result %08x\n", result);
271
272 blk_mq_free_hctx_request(nvmeq->hctx, req);
273 }
274
275 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
276 struct nvme_completion *cqe)
277 {
278 struct request *req = ctx;
279
280 u16 status = le16_to_cpup(&cqe->status) >> 1;
281 u32 result = le32_to_cpup(&cqe->result);
282
283 blk_mq_free_hctx_request(nvmeq->hctx, req);
284
285 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
286 ++nvmeq->dev->abort_limit;
287 }
288
289 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
290 struct nvme_completion *cqe)
291 {
292 struct async_cmd_info *cmdinfo = ctx;
293 cmdinfo->result = le32_to_cpup(&cqe->result);
294 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
295 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
296 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
297 }
298
299 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
300 unsigned int tag)
301 {
302 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
303 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
304
305 return blk_mq_rq_to_pdu(req);
306 }
307
308 /*
309 * Called with local interrupts disabled and the q_lock held. May not sleep.
310 */
311 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
312 nvme_completion_fn *fn)
313 {
314 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
315 void *ctx;
316 if (tag >= nvmeq->q_depth) {
317 *fn = special_completion;
318 return CMD_CTX_INVALID;
319 }
320 if (fn)
321 *fn = cmd->fn;
322 ctx = cmd->ctx;
323 cmd->fn = special_completion;
324 cmd->ctx = CMD_CTX_COMPLETED;
325 return ctx;
326 }
327
328 /**
329 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
330 * @nvmeq: The queue to use
331 * @cmd: The command to send
332 *
333 * Safe to use from interrupt context
334 */
335 static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
336 {
337 u16 tail = nvmeq->sq_tail;
338
339 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
340 if (++tail == nvmeq->q_depth)
341 tail = 0;
342 writel(tail, nvmeq->q_db);
343 nvmeq->sq_tail = tail;
344
345 return 0;
346 }
347
348 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
349 {
350 unsigned long flags;
351 int ret;
352 spin_lock_irqsave(&nvmeq->q_lock, flags);
353 ret = __nvme_submit_cmd(nvmeq, cmd);
354 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
355 return ret;
356 }
357
358 static __le64 **iod_list(struct nvme_iod *iod)
359 {
360 return ((void *)iod) + iod->offset;
361 }
362
363 /*
364 * Will slightly overestimate the number of pages needed. This is OK
365 * as it only leads to a small amount of wasted memory for the lifetime of
366 * the I/O.
367 */
368 static int nvme_npages(unsigned size, struct nvme_dev *dev)
369 {
370 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
371 return DIV_ROUND_UP(8 * nprps, dev->page_size - 8);
372 }
373
374 static struct nvme_iod *
375 nvme_alloc_iod(unsigned nseg, unsigned nbytes, struct nvme_dev *dev, gfp_t gfp)
376 {
377 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
378 sizeof(__le64 *) * nvme_npages(nbytes, dev) +
379 sizeof(struct scatterlist) * nseg, gfp);
380
381 if (iod) {
382 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
383 iod->npages = -1;
384 iod->length = nbytes;
385 iod->nents = 0;
386 iod->first_dma = 0ULL;
387 }
388
389 return iod;
390 }
391
392 void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
393 {
394 const int last_prp = dev->page_size / 8 - 1;
395 int i;
396 __le64 **list = iod_list(iod);
397 dma_addr_t prp_dma = iod->first_dma;
398
399 if (iod->npages == 0)
400 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
401 for (i = 0; i < iod->npages; i++) {
402 __le64 *prp_list = list[i];
403 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
404 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
405 prp_dma = next_prp_dma;
406 }
407 kfree(iod);
408 }
409
410 static int nvme_error_status(u16 status)
411 {
412 switch (status & 0x7ff) {
413 case NVME_SC_SUCCESS:
414 return 0;
415 case NVME_SC_CAP_EXCEEDED:
416 return -ENOSPC;
417 default:
418 return -EIO;
419 }
420 }
421
422 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
423 struct nvme_completion *cqe)
424 {
425 struct nvme_iod *iod = ctx;
426 struct request *req = iod->private;
427 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
428
429 u16 status = le16_to_cpup(&cqe->status) >> 1;
430
431 if (unlikely(status)) {
432 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
433 && (jiffies - req->start_time) < req->timeout) {
434 blk_mq_requeue_request(req);
435 blk_mq_kick_requeue_list(req->q);
436 return;
437 }
438 req->errors = nvme_error_status(status);
439 } else
440 req->errors = 0;
441
442 if (cmd_rq->aborted)
443 dev_warn(&nvmeq->dev->pci_dev->dev,
444 "completing aborted command with status:%04x\n",
445 status);
446
447 if (iod->nents)
448 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
449 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
450 nvme_free_iod(nvmeq->dev, iod);
451
452 blk_mq_complete_request(req);
453 }
454
455 /* length is in bytes. gfp flags indicates whether we may sleep. */
456 int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
457 gfp_t gfp)
458 {
459 struct dma_pool *pool;
460 int length = total_len;
461 struct scatterlist *sg = iod->sg;
462 int dma_len = sg_dma_len(sg);
463 u64 dma_addr = sg_dma_address(sg);
464 int offset = offset_in_page(dma_addr);
465 __le64 *prp_list;
466 __le64 **list = iod_list(iod);
467 dma_addr_t prp_dma;
468 int nprps, i;
469 u32 page_size = dev->page_size;
470
471 length -= (page_size - offset);
472 if (length <= 0)
473 return total_len;
474
475 dma_len -= (page_size - offset);
476 if (dma_len) {
477 dma_addr += (page_size - offset);
478 } else {
479 sg = sg_next(sg);
480 dma_addr = sg_dma_address(sg);
481 dma_len = sg_dma_len(sg);
482 }
483
484 if (length <= page_size) {
485 iod->first_dma = dma_addr;
486 return total_len;
487 }
488
489 nprps = DIV_ROUND_UP(length, page_size);
490 if (nprps <= (256 / 8)) {
491 pool = dev->prp_small_pool;
492 iod->npages = 0;
493 } else {
494 pool = dev->prp_page_pool;
495 iod->npages = 1;
496 }
497
498 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
499 if (!prp_list) {
500 iod->first_dma = dma_addr;
501 iod->npages = -1;
502 return (total_len - length) + page_size;
503 }
504 list[0] = prp_list;
505 iod->first_dma = prp_dma;
506 i = 0;
507 for (;;) {
508 if (i == page_size >> 3) {
509 __le64 *old_prp_list = prp_list;
510 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
511 if (!prp_list)
512 return total_len - length;
513 list[iod->npages++] = prp_list;
514 prp_list[0] = old_prp_list[i - 1];
515 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
516 i = 1;
517 }
518 prp_list[i++] = cpu_to_le64(dma_addr);
519 dma_len -= page_size;
520 dma_addr += page_size;
521 length -= page_size;
522 if (length <= 0)
523 break;
524 if (dma_len > 0)
525 continue;
526 BUG_ON(dma_len < 0);
527 sg = sg_next(sg);
528 dma_addr = sg_dma_address(sg);
529 dma_len = sg_dma_len(sg);
530 }
531
532 return total_len;
533 }
534
535 /*
536 * We reuse the small pool to allocate the 16-byte range here as it is not
537 * worth having a special pool for these or additional cases to handle freeing
538 * the iod.
539 */
540 static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
541 struct request *req, struct nvme_iod *iod)
542 {
543 struct nvme_dsm_range *range =
544 (struct nvme_dsm_range *)iod_list(iod)[0];
545 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
546
547 range->cattr = cpu_to_le32(0);
548 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
549 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
550
551 memset(cmnd, 0, sizeof(*cmnd));
552 cmnd->dsm.opcode = nvme_cmd_dsm;
553 cmnd->dsm.command_id = req->tag;
554 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
555 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
556 cmnd->dsm.nr = 0;
557 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
558
559 if (++nvmeq->sq_tail == nvmeq->q_depth)
560 nvmeq->sq_tail = 0;
561 writel(nvmeq->sq_tail, nvmeq->q_db);
562 }
563
564 static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
565 int cmdid)
566 {
567 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
568
569 memset(cmnd, 0, sizeof(*cmnd));
570 cmnd->common.opcode = nvme_cmd_flush;
571 cmnd->common.command_id = cmdid;
572 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
573
574 if (++nvmeq->sq_tail == nvmeq->q_depth)
575 nvmeq->sq_tail = 0;
576 writel(nvmeq->sq_tail, nvmeq->q_db);
577 }
578
579 static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
580 struct nvme_ns *ns)
581 {
582 struct request *req = iod->private;
583 struct nvme_command *cmnd;
584 u16 control = 0;
585 u32 dsmgmt = 0;
586
587 if (req->cmd_flags & REQ_FUA)
588 control |= NVME_RW_FUA;
589 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
590 control |= NVME_RW_LR;
591
592 if (req->cmd_flags & REQ_RAHEAD)
593 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
594
595 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
596 memset(cmnd, 0, sizeof(*cmnd));
597
598 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
599 cmnd->rw.command_id = req->tag;
600 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
601 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
602 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
603 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
604 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
605 cmnd->rw.control = cpu_to_le16(control);
606 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
607
608 if (++nvmeq->sq_tail == nvmeq->q_depth)
609 nvmeq->sq_tail = 0;
610 writel(nvmeq->sq_tail, nvmeq->q_db);
611
612 return 0;
613 }
614
615 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
616 const struct blk_mq_queue_data *bd)
617 {
618 struct nvme_ns *ns = hctx->queue->queuedata;
619 struct nvme_queue *nvmeq = hctx->driver_data;
620 struct request *req = bd->rq;
621 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
622 struct nvme_iod *iod;
623 int psegs = req->nr_phys_segments;
624 enum dma_data_direction dma_dir;
625 unsigned size = !(req->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(req) :
626 sizeof(struct nvme_dsm_range);
627
628 iod = nvme_alloc_iod(psegs, size, ns->dev, GFP_ATOMIC);
629 if (!iod)
630 return BLK_MQ_RQ_QUEUE_BUSY;
631
632 iod->private = req;
633
634 if (req->cmd_flags & REQ_DISCARD) {
635 void *range;
636 /*
637 * We reuse the small pool to allocate the 16-byte range here
638 * as it is not worth having a special pool for these or
639 * additional cases to handle freeing the iod.
640 */
641 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
642 GFP_ATOMIC,
643 &iod->first_dma);
644 if (!range)
645 goto retry_cmd;
646 iod_list(iod)[0] = (__le64 *)range;
647 iod->npages = 0;
648 } else if (psegs) {
649 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
650
651 sg_init_table(iod->sg, psegs);
652 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
653 if (!iod->nents)
654 goto error_cmd;
655
656 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
657 goto retry_cmd;
658
659 if (blk_rq_bytes(req) !=
660 nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
661 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
662 iod->nents, dma_dir);
663 goto retry_cmd;
664 }
665 }
666
667 blk_mq_start_request(req);
668
669 nvme_set_info(cmd, iod, req_completion);
670 spin_lock_irq(&nvmeq->q_lock);
671 if (req->cmd_flags & REQ_DISCARD)
672 nvme_submit_discard(nvmeq, ns, req, iod);
673 else if (req->cmd_flags & REQ_FLUSH)
674 nvme_submit_flush(nvmeq, ns, req->tag);
675 else
676 nvme_submit_iod(nvmeq, iod, ns);
677
678 nvme_process_cq(nvmeq);
679 spin_unlock_irq(&nvmeq->q_lock);
680 return BLK_MQ_RQ_QUEUE_OK;
681
682 error_cmd:
683 nvme_free_iod(nvmeq->dev, iod);
684 return BLK_MQ_RQ_QUEUE_ERROR;
685 retry_cmd:
686 nvme_free_iod(nvmeq->dev, iod);
687 return BLK_MQ_RQ_QUEUE_BUSY;
688 }
689
690 static int nvme_process_cq(struct nvme_queue *nvmeq)
691 {
692 u16 head, phase;
693
694 head = nvmeq->cq_head;
695 phase = nvmeq->cq_phase;
696
697 for (;;) {
698 void *ctx;
699 nvme_completion_fn fn;
700 struct nvme_completion cqe = nvmeq->cqes[head];
701 if ((le16_to_cpu(cqe.status) & 1) != phase)
702 break;
703 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
704 if (++head == nvmeq->q_depth) {
705 head = 0;
706 phase = !phase;
707 }
708 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
709 fn(nvmeq, ctx, &cqe);
710 }
711
712 /* If the controller ignores the cq head doorbell and continuously
713 * writes to the queue, it is theoretically possible to wrap around
714 * the queue twice and mistakenly return IRQ_NONE. Linux only
715 * requires that 0.1% of your interrupts are handled, so this isn't
716 * a big problem.
717 */
718 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
719 return 0;
720
721 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
722 nvmeq->cq_head = head;
723 nvmeq->cq_phase = phase;
724
725 nvmeq->cqe_seen = 1;
726 return 1;
727 }
728
729 /* Admin queue isn't initialized as a request queue. If at some point this
730 * happens anyway, make sure to notify the user */
731 static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
732 const struct blk_mq_queue_data *bd)
733 {
734 WARN_ON_ONCE(1);
735 return BLK_MQ_RQ_QUEUE_ERROR;
736 }
737
738 static irqreturn_t nvme_irq(int irq, void *data)
739 {
740 irqreturn_t result;
741 struct nvme_queue *nvmeq = data;
742 spin_lock(&nvmeq->q_lock);
743 nvme_process_cq(nvmeq);
744 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
745 nvmeq->cqe_seen = 0;
746 spin_unlock(&nvmeq->q_lock);
747 return result;
748 }
749
750 static irqreturn_t nvme_irq_check(int irq, void *data)
751 {
752 struct nvme_queue *nvmeq = data;
753 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
754 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
755 return IRQ_NONE;
756 return IRQ_WAKE_THREAD;
757 }
758
759 static void nvme_abort_cmd_info(struct nvme_queue *nvmeq, struct nvme_cmd_info *
760 cmd_info)
761 {
762 spin_lock_irq(&nvmeq->q_lock);
763 cancel_cmd_info(cmd_info, NULL);
764 spin_unlock_irq(&nvmeq->q_lock);
765 }
766
767 struct sync_cmd_info {
768 struct task_struct *task;
769 u32 result;
770 int status;
771 };
772
773 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
774 struct nvme_completion *cqe)
775 {
776 struct sync_cmd_info *cmdinfo = ctx;
777 cmdinfo->result = le32_to_cpup(&cqe->result);
778 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
779 wake_up_process(cmdinfo->task);
780 }
781
782 /*
783 * Returns 0 on success. If the result is negative, it's a Linux error code;
784 * if the result is positive, it's an NVM Express status code
785 */
786 static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
787 u32 *result, unsigned timeout)
788 {
789 int ret;
790 struct sync_cmd_info cmdinfo;
791 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
792 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
793
794 cmdinfo.task = current;
795 cmdinfo.status = -EINTR;
796
797 cmd->common.command_id = req->tag;
798
799 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
800
801 set_current_state(TASK_KILLABLE);
802 ret = nvme_submit_cmd(nvmeq, cmd);
803 if (ret) {
804 nvme_finish_cmd(nvmeq, req->tag, NULL);
805 set_current_state(TASK_RUNNING);
806 }
807 ret = schedule_timeout(timeout);
808
809 /*
810 * Ensure that sync_completion has either run, or that it will
811 * never run.
812 */
813 nvme_abort_cmd_info(nvmeq, blk_mq_rq_to_pdu(req));
814
815 /*
816 * We never got the completion
817 */
818 if (cmdinfo.status == -EINTR)
819 return -EINTR;
820
821 if (result)
822 *result = cmdinfo.result;
823
824 return cmdinfo.status;
825 }
826
827 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
828 {
829 struct nvme_queue *nvmeq = dev->queues[0];
830 struct nvme_command c;
831 struct nvme_cmd_info *cmd_info;
832 struct request *req;
833
834 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false);
835 if (IS_ERR(req))
836 return PTR_ERR(req);
837
838 cmd_info = blk_mq_rq_to_pdu(req);
839 nvme_set_info(cmd_info, req, async_req_completion);
840
841 memset(&c, 0, sizeof(c));
842 c.common.opcode = nvme_admin_async_event;
843 c.common.command_id = req->tag;
844
845 return __nvme_submit_cmd(nvmeq, &c);
846 }
847
848 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
849 struct nvme_command *cmd,
850 struct async_cmd_info *cmdinfo, unsigned timeout)
851 {
852 struct nvme_queue *nvmeq = dev->queues[0];
853 struct request *req;
854 struct nvme_cmd_info *cmd_rq;
855
856 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
857 if (IS_ERR(req))
858 return PTR_ERR(req);
859
860 req->timeout = timeout;
861 cmd_rq = blk_mq_rq_to_pdu(req);
862 cmdinfo->req = req;
863 nvme_set_info(cmd_rq, cmdinfo, async_completion);
864 cmdinfo->status = -EINTR;
865
866 cmd->common.command_id = req->tag;
867
868 return nvme_submit_cmd(nvmeq, cmd);
869 }
870
871 static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
872 u32 *result, unsigned timeout)
873 {
874 int res;
875 struct request *req;
876
877 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
878 if (IS_ERR(req))
879 return PTR_ERR(req);
880 res = nvme_submit_sync_cmd(req, cmd, result, timeout);
881 blk_mq_free_request(req);
882 return res;
883 }
884
885 int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
886 u32 *result)
887 {
888 return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
889 }
890
891 int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
892 struct nvme_command *cmd, u32 *result)
893 {
894 int res;
895 struct request *req;
896
897 req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
898 false);
899 if (IS_ERR(req))
900 return PTR_ERR(req);
901 res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
902 blk_mq_free_request(req);
903 return res;
904 }
905
906 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
907 {
908 struct nvme_command c;
909
910 memset(&c, 0, sizeof(c));
911 c.delete_queue.opcode = opcode;
912 c.delete_queue.qid = cpu_to_le16(id);
913
914 return nvme_submit_admin_cmd(dev, &c, NULL);
915 }
916
917 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
918 struct nvme_queue *nvmeq)
919 {
920 struct nvme_command c;
921 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
922
923 memset(&c, 0, sizeof(c));
924 c.create_cq.opcode = nvme_admin_create_cq;
925 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
926 c.create_cq.cqid = cpu_to_le16(qid);
927 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
928 c.create_cq.cq_flags = cpu_to_le16(flags);
929 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
930
931 return nvme_submit_admin_cmd(dev, &c, NULL);
932 }
933
934 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
935 struct nvme_queue *nvmeq)
936 {
937 struct nvme_command c;
938 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
939
940 memset(&c, 0, sizeof(c));
941 c.create_sq.opcode = nvme_admin_create_sq;
942 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
943 c.create_sq.sqid = cpu_to_le16(qid);
944 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
945 c.create_sq.sq_flags = cpu_to_le16(flags);
946 c.create_sq.cqid = cpu_to_le16(qid);
947
948 return nvme_submit_admin_cmd(dev, &c, NULL);
949 }
950
951 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
952 {
953 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
954 }
955
956 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
957 {
958 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
959 }
960
961 int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
962 dma_addr_t dma_addr)
963 {
964 struct nvme_command c;
965
966 memset(&c, 0, sizeof(c));
967 c.identify.opcode = nvme_admin_identify;
968 c.identify.nsid = cpu_to_le32(nsid);
969 c.identify.prp1 = cpu_to_le64(dma_addr);
970 c.identify.cns = cpu_to_le32(cns);
971
972 return nvme_submit_admin_cmd(dev, &c, NULL);
973 }
974
975 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
976 dma_addr_t dma_addr, u32 *result)
977 {
978 struct nvme_command c;
979
980 memset(&c, 0, sizeof(c));
981 c.features.opcode = nvme_admin_get_features;
982 c.features.nsid = cpu_to_le32(nsid);
983 c.features.prp1 = cpu_to_le64(dma_addr);
984 c.features.fid = cpu_to_le32(fid);
985
986 return nvme_submit_admin_cmd(dev, &c, result);
987 }
988
989 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
990 dma_addr_t dma_addr, u32 *result)
991 {
992 struct nvme_command c;
993
994 memset(&c, 0, sizeof(c));
995 c.features.opcode = nvme_admin_set_features;
996 c.features.prp1 = cpu_to_le64(dma_addr);
997 c.features.fid = cpu_to_le32(fid);
998 c.features.dword11 = cpu_to_le32(dword11);
999
1000 return nvme_submit_admin_cmd(dev, &c, result);
1001 }
1002
1003 /**
1004 * nvme_abort_req - Attempt aborting a request
1005 *
1006 * Schedule controller reset if the command was already aborted once before and
1007 * still hasn't been returned to the driver, or if this is the admin queue.
1008 */
1009 static void nvme_abort_req(struct request *req)
1010 {
1011 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1012 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1013 struct nvme_dev *dev = nvmeq->dev;
1014 struct request *abort_req;
1015 struct nvme_cmd_info *abort_cmd;
1016 struct nvme_command cmd;
1017
1018 if (!nvmeq->qid || cmd_rq->aborted) {
1019 if (work_busy(&dev->reset_work))
1020 return;
1021 list_del_init(&dev->node);
1022 dev_warn(&dev->pci_dev->dev,
1023 "I/O %d QID %d timeout, reset controller\n",
1024 req->tag, nvmeq->qid);
1025 dev->reset_workfn = nvme_reset_failed_dev;
1026 queue_work(nvme_workq, &dev->reset_work);
1027 return;
1028 }
1029
1030 if (!dev->abort_limit)
1031 return;
1032
1033 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1034 false);
1035 if (IS_ERR(abort_req))
1036 return;
1037
1038 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1039 nvme_set_info(abort_cmd, abort_req, abort_completion);
1040
1041 memset(&cmd, 0, sizeof(cmd));
1042 cmd.abort.opcode = nvme_admin_abort_cmd;
1043 cmd.abort.cid = req->tag;
1044 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1045 cmd.abort.command_id = abort_req->tag;
1046
1047 --dev->abort_limit;
1048 cmd_rq->aborted = 1;
1049
1050 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
1051 nvmeq->qid);
1052 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1053 dev_warn(nvmeq->q_dmadev,
1054 "Could not abort I/O %d QID %d",
1055 req->tag, nvmeq->qid);
1056 blk_mq_free_request(abort_req);
1057 }
1058 }
1059
1060 static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1061 struct request *req, void *data, bool reserved)
1062 {
1063 struct nvme_queue *nvmeq = data;
1064 void *ctx;
1065 nvme_completion_fn fn;
1066 struct nvme_cmd_info *cmd;
1067 static struct nvme_completion cqe = {
1068 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
1069 };
1070
1071 cmd = blk_mq_rq_to_pdu(req);
1072
1073 if (cmd->ctx == CMD_CTX_CANCELLED)
1074 return;
1075
1076 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1077 req->tag, nvmeq->qid);
1078 ctx = cancel_cmd_info(cmd, &fn);
1079 fn(nvmeq, ctx, &cqe);
1080 }
1081
1082 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1083 {
1084 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1085 struct nvme_queue *nvmeq = cmd->nvmeq;
1086
1087 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1088 nvmeq->qid);
1089 if (nvmeq->dev->initialized)
1090 nvme_abort_req(req);
1091
1092 /*
1093 * The aborted req will be completed on receiving the abort req.
1094 * We enable the timer again. If hit twice, it'll cause a device reset,
1095 * as the device then is in a faulty state.
1096 */
1097 return BLK_EH_RESET_TIMER;
1098 }
1099
1100 static void nvme_free_queue(struct nvme_queue *nvmeq)
1101 {
1102 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1103 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1104 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1105 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1106 kfree(nvmeq);
1107 }
1108
1109 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1110 {
1111 LLIST_HEAD(q_list);
1112 struct nvme_queue *nvmeq, *next;
1113 struct llist_node *entry;
1114 int i;
1115
1116 for (i = dev->queue_count - 1; i >= lowest; i--) {
1117 struct nvme_queue *nvmeq = dev->queues[i];
1118 llist_add(&nvmeq->node, &q_list);
1119 dev->queue_count--;
1120 dev->queues[i] = NULL;
1121 }
1122 synchronize_rcu();
1123 entry = llist_del_all(&q_list);
1124 llist_for_each_entry_safe(nvmeq, next, entry, node)
1125 nvme_free_queue(nvmeq);
1126 }
1127
1128 /**
1129 * nvme_suspend_queue - put queue into suspended state
1130 * @nvmeq - queue to suspend
1131 */
1132 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1133 {
1134 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1135
1136 spin_lock_irq(&nvmeq->q_lock);
1137 nvmeq->dev->online_queues--;
1138 spin_unlock_irq(&nvmeq->q_lock);
1139
1140 irq_set_affinity_hint(vector, NULL);
1141 free_irq(vector, nvmeq);
1142
1143 return 0;
1144 }
1145
1146 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1147 {
1148 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1149
1150 spin_lock_irq(&nvmeq->q_lock);
1151 nvme_process_cq(nvmeq);
1152 if (hctx && hctx->tags)
1153 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
1154 spin_unlock_irq(&nvmeq->q_lock);
1155 }
1156
1157 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1158 {
1159 struct nvme_queue *nvmeq = dev->queues[qid];
1160
1161 if (!nvmeq)
1162 return;
1163 if (nvme_suspend_queue(nvmeq))
1164 return;
1165
1166 /* Don't tell the adapter to delete the admin queue.
1167 * Don't tell a removed adapter to delete IO queues. */
1168 if (qid && readl(&dev->bar->csts) != -1) {
1169 adapter_delete_sq(dev, qid);
1170 adapter_delete_cq(dev, qid);
1171 }
1172 nvme_clear_queue(nvmeq);
1173 }
1174
1175 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1176 int depth, int vector)
1177 {
1178 struct device *dmadev = &dev->pci_dev->dev;
1179 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1180 if (!nvmeq)
1181 return NULL;
1182
1183 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1184 &nvmeq->cq_dma_addr, GFP_KERNEL);
1185 if (!nvmeq->cqes)
1186 goto free_nvmeq;
1187
1188 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1189 &nvmeq->sq_dma_addr, GFP_KERNEL);
1190 if (!nvmeq->sq_cmds)
1191 goto free_cqdma;
1192
1193 nvmeq->q_dmadev = dmadev;
1194 nvmeq->dev = dev;
1195 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1196 dev->instance, qid);
1197 spin_lock_init(&nvmeq->q_lock);
1198 nvmeq->cq_head = 0;
1199 nvmeq->cq_phase = 1;
1200 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1201 nvmeq->q_depth = depth;
1202 nvmeq->cq_vector = vector;
1203 nvmeq->qid = qid;
1204 dev->queue_count++;
1205 dev->queues[qid] = nvmeq;
1206
1207 return nvmeq;
1208
1209 free_cqdma:
1210 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1211 nvmeq->cq_dma_addr);
1212 free_nvmeq:
1213 kfree(nvmeq);
1214 return NULL;
1215 }
1216
1217 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1218 const char *name)
1219 {
1220 if (use_threaded_interrupts)
1221 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1222 nvme_irq_check, nvme_irq, IRQF_SHARED,
1223 name, nvmeq);
1224 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1225 IRQF_SHARED, name, nvmeq);
1226 }
1227
1228 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1229 {
1230 struct nvme_dev *dev = nvmeq->dev;
1231
1232 spin_lock_irq(&nvmeq->q_lock);
1233 nvmeq->sq_tail = 0;
1234 nvmeq->cq_head = 0;
1235 nvmeq->cq_phase = 1;
1236 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1237 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1238 dev->online_queues++;
1239 spin_unlock_irq(&nvmeq->q_lock);
1240 }
1241
1242 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1243 {
1244 struct nvme_dev *dev = nvmeq->dev;
1245 int result;
1246
1247 result = adapter_alloc_cq(dev, qid, nvmeq);
1248 if (result < 0)
1249 return result;
1250
1251 result = adapter_alloc_sq(dev, qid, nvmeq);
1252 if (result < 0)
1253 goto release_cq;
1254
1255 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1256 if (result < 0)
1257 goto release_sq;
1258
1259 nvme_init_queue(nvmeq, qid);
1260 return result;
1261
1262 release_sq:
1263 adapter_delete_sq(dev, qid);
1264 release_cq:
1265 adapter_delete_cq(dev, qid);
1266 return result;
1267 }
1268
1269 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1270 {
1271 unsigned long timeout;
1272 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1273
1274 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1275
1276 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1277 msleep(100);
1278 if (fatal_signal_pending(current))
1279 return -EINTR;
1280 if (time_after(jiffies, timeout)) {
1281 dev_err(&dev->pci_dev->dev,
1282 "Device not ready; aborting %s\n", enabled ?
1283 "initialisation" : "reset");
1284 return -ENODEV;
1285 }
1286 }
1287
1288 return 0;
1289 }
1290
1291 /*
1292 * If the device has been passed off to us in an enabled state, just clear
1293 * the enabled bit. The spec says we should set the 'shutdown notification
1294 * bits', but doing so may cause the device to complete commands to the
1295 * admin queue ... and we don't know what memory that might be pointing at!
1296 */
1297 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1298 {
1299 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1300 dev->ctrl_config &= ~NVME_CC_ENABLE;
1301 writel(dev->ctrl_config, &dev->bar->cc);
1302
1303 return nvme_wait_ready(dev, cap, false);
1304 }
1305
1306 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1307 {
1308 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1309 dev->ctrl_config |= NVME_CC_ENABLE;
1310 writel(dev->ctrl_config, &dev->bar->cc);
1311
1312 return nvme_wait_ready(dev, cap, true);
1313 }
1314
1315 static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1316 {
1317 unsigned long timeout;
1318
1319 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1320 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1321
1322 writel(dev->ctrl_config, &dev->bar->cc);
1323
1324 timeout = SHUTDOWN_TIMEOUT + jiffies;
1325 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1326 NVME_CSTS_SHST_CMPLT) {
1327 msleep(100);
1328 if (fatal_signal_pending(current))
1329 return -EINTR;
1330 if (time_after(jiffies, timeout)) {
1331 dev_err(&dev->pci_dev->dev,
1332 "Device shutdown incomplete; abort shutdown\n");
1333 return -ENODEV;
1334 }
1335 }
1336
1337 return 0;
1338 }
1339
1340 static struct blk_mq_ops nvme_mq_admin_ops = {
1341 .queue_rq = nvme_admin_queue_rq,
1342 .map_queue = blk_mq_map_queue,
1343 .init_hctx = nvme_admin_init_hctx,
1344 .exit_hctx = nvme_exit_hctx,
1345 .init_request = nvme_admin_init_request,
1346 .timeout = nvme_timeout,
1347 };
1348
1349 static struct blk_mq_ops nvme_mq_ops = {
1350 .queue_rq = nvme_queue_rq,
1351 .map_queue = blk_mq_map_queue,
1352 .init_hctx = nvme_init_hctx,
1353 .exit_hctx = nvme_exit_hctx,
1354 .init_request = nvme_init_request,
1355 .timeout = nvme_timeout,
1356 };
1357
1358 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1359 {
1360 if (!dev->admin_q) {
1361 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1362 dev->admin_tagset.nr_hw_queues = 1;
1363 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1364 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1365 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
1366 dev->admin_tagset.cmd_size = sizeof(struct nvme_cmd_info);
1367 dev->admin_tagset.driver_data = dev;
1368
1369 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1370 return -ENOMEM;
1371
1372 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1373 if (!dev->admin_q) {
1374 blk_mq_free_tag_set(&dev->admin_tagset);
1375 return -ENOMEM;
1376 }
1377 }
1378
1379 return 0;
1380 }
1381
1382 static void nvme_free_admin_tags(struct nvme_dev *dev)
1383 {
1384 if (dev->admin_q)
1385 blk_mq_free_tag_set(&dev->admin_tagset);
1386 }
1387
1388 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1389 {
1390 int result;
1391 u32 aqa;
1392 u64 cap = readq(&dev->bar->cap);
1393 struct nvme_queue *nvmeq;
1394 unsigned page_shift = PAGE_SHIFT;
1395 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1396 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1397
1398 if (page_shift < dev_page_min) {
1399 dev_err(&dev->pci_dev->dev,
1400 "Minimum device page size (%u) too large for "
1401 "host (%u)\n", 1 << dev_page_min,
1402 1 << page_shift);
1403 return -ENODEV;
1404 }
1405 if (page_shift > dev_page_max) {
1406 dev_info(&dev->pci_dev->dev,
1407 "Device maximum page size (%u) smaller than "
1408 "host (%u); enabling work-around\n",
1409 1 << dev_page_max, 1 << page_shift);
1410 page_shift = dev_page_max;
1411 }
1412
1413 result = nvme_disable_ctrl(dev, cap);
1414 if (result < 0)
1415 return result;
1416
1417 nvmeq = dev->queues[0];
1418 if (!nvmeq) {
1419 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, 0);
1420 if (!nvmeq)
1421 return -ENOMEM;
1422 }
1423
1424 aqa = nvmeq->q_depth - 1;
1425 aqa |= aqa << 16;
1426
1427 dev->page_size = 1 << page_shift;
1428
1429 dev->ctrl_config = NVME_CC_CSS_NVM;
1430 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1431 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1432 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1433
1434 writel(aqa, &dev->bar->aqa);
1435 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1436 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1437
1438 result = nvme_enable_ctrl(dev, cap);
1439 if (result)
1440 goto free_nvmeq;
1441
1442 result = nvme_alloc_admin_tags(dev);
1443 if (result)
1444 goto free_nvmeq;
1445
1446 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1447 if (result)
1448 goto free_tags;
1449
1450 return result;
1451
1452 free_tags:
1453 nvme_free_admin_tags(dev);
1454 free_nvmeq:
1455 nvme_free_queues(dev, 0);
1456 return result;
1457 }
1458
1459 struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1460 unsigned long addr, unsigned length)
1461 {
1462 int i, err, count, nents, offset;
1463 struct scatterlist *sg;
1464 struct page **pages;
1465 struct nvme_iod *iod;
1466
1467 if (addr & 3)
1468 return ERR_PTR(-EINVAL);
1469 if (!length || length > INT_MAX - PAGE_SIZE)
1470 return ERR_PTR(-EINVAL);
1471
1472 offset = offset_in_page(addr);
1473 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1474 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1475 if (!pages)
1476 return ERR_PTR(-ENOMEM);
1477
1478 err = get_user_pages_fast(addr, count, 1, pages);
1479 if (err < count) {
1480 count = err;
1481 err = -EFAULT;
1482 goto put_pages;
1483 }
1484
1485 err = -ENOMEM;
1486 iod = nvme_alloc_iod(count, length, dev, GFP_KERNEL);
1487 if (!iod)
1488 goto put_pages;
1489
1490 sg = iod->sg;
1491 sg_init_table(sg, count);
1492 for (i = 0; i < count; i++) {
1493 sg_set_page(&sg[i], pages[i],
1494 min_t(unsigned, length, PAGE_SIZE - offset),
1495 offset);
1496 length -= (PAGE_SIZE - offset);
1497 offset = 0;
1498 }
1499 sg_mark_end(&sg[i - 1]);
1500 iod->nents = count;
1501
1502 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1503 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1504 if (!nents)
1505 goto free_iod;
1506
1507 kfree(pages);
1508 return iod;
1509
1510 free_iod:
1511 kfree(iod);
1512 put_pages:
1513 for (i = 0; i < count; i++)
1514 put_page(pages[i]);
1515 kfree(pages);
1516 return ERR_PTR(err);
1517 }
1518
1519 void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1520 struct nvme_iod *iod)
1521 {
1522 int i;
1523
1524 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1525 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1526
1527 for (i = 0; i < iod->nents; i++)
1528 put_page(sg_page(&iod->sg[i]));
1529 }
1530
1531 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1532 {
1533 struct nvme_dev *dev = ns->dev;
1534 struct nvme_user_io io;
1535 struct nvme_command c;
1536 unsigned length, meta_len;
1537 int status, i;
1538 struct nvme_iod *iod, *meta_iod = NULL;
1539 dma_addr_t meta_dma_addr;
1540 void *meta, *uninitialized_var(meta_mem);
1541
1542 if (copy_from_user(&io, uio, sizeof(io)))
1543 return -EFAULT;
1544 length = (io.nblocks + 1) << ns->lba_shift;
1545 meta_len = (io.nblocks + 1) * ns->ms;
1546
1547 if (meta_len && ((io.metadata & 3) || !io.metadata))
1548 return -EINVAL;
1549
1550 switch (io.opcode) {
1551 case nvme_cmd_write:
1552 case nvme_cmd_read:
1553 case nvme_cmd_compare:
1554 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
1555 break;
1556 default:
1557 return -EINVAL;
1558 }
1559
1560 if (IS_ERR(iod))
1561 return PTR_ERR(iod);
1562
1563 memset(&c, 0, sizeof(c));
1564 c.rw.opcode = io.opcode;
1565 c.rw.flags = io.flags;
1566 c.rw.nsid = cpu_to_le32(ns->ns_id);
1567 c.rw.slba = cpu_to_le64(io.slba);
1568 c.rw.length = cpu_to_le16(io.nblocks);
1569 c.rw.control = cpu_to_le16(io.control);
1570 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1571 c.rw.reftag = cpu_to_le32(io.reftag);
1572 c.rw.apptag = cpu_to_le16(io.apptag);
1573 c.rw.appmask = cpu_to_le16(io.appmask);
1574
1575 if (meta_len) {
1576 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1577 meta_len);
1578 if (IS_ERR(meta_iod)) {
1579 status = PTR_ERR(meta_iod);
1580 meta_iod = NULL;
1581 goto unmap;
1582 }
1583
1584 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1585 &meta_dma_addr, GFP_KERNEL);
1586 if (!meta_mem) {
1587 status = -ENOMEM;
1588 goto unmap;
1589 }
1590
1591 if (io.opcode & 1) {
1592 int meta_offset = 0;
1593
1594 for (i = 0; i < meta_iod->nents; i++) {
1595 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1596 meta_iod->sg[i].offset;
1597 memcpy(meta_mem + meta_offset, meta,
1598 meta_iod->sg[i].length);
1599 kunmap_atomic(meta);
1600 meta_offset += meta_iod->sg[i].length;
1601 }
1602 }
1603
1604 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1605 }
1606
1607 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1608 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1609 c.rw.prp2 = cpu_to_le64(iod->first_dma);
1610
1611 if (length != (io.nblocks + 1) << ns->lba_shift)
1612 status = -ENOMEM;
1613 else
1614 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
1615
1616 if (meta_len) {
1617 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1618 int meta_offset = 0;
1619
1620 for (i = 0; i < meta_iod->nents; i++) {
1621 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1622 meta_iod->sg[i].offset;
1623 memcpy(meta, meta_mem + meta_offset,
1624 meta_iod->sg[i].length);
1625 kunmap_atomic(meta);
1626 meta_offset += meta_iod->sg[i].length;
1627 }
1628 }
1629
1630 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1631 meta_dma_addr);
1632 }
1633
1634 unmap:
1635 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
1636 nvme_free_iod(dev, iod);
1637
1638 if (meta_iod) {
1639 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1640 nvme_free_iod(dev, meta_iod);
1641 }
1642
1643 return status;
1644 }
1645
1646 static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1647 struct nvme_passthru_cmd __user *ucmd)
1648 {
1649 struct nvme_passthru_cmd cmd;
1650 struct nvme_command c;
1651 int status, length;
1652 struct nvme_iod *uninitialized_var(iod);
1653 unsigned timeout;
1654
1655 if (!capable(CAP_SYS_ADMIN))
1656 return -EACCES;
1657 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1658 return -EFAULT;
1659
1660 memset(&c, 0, sizeof(c));
1661 c.common.opcode = cmd.opcode;
1662 c.common.flags = cmd.flags;
1663 c.common.nsid = cpu_to_le32(cmd.nsid);
1664 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1665 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1666 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1667 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1668 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1669 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1670 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1671 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1672
1673 length = cmd.data_len;
1674 if (cmd.data_len) {
1675 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1676 length);
1677 if (IS_ERR(iod))
1678 return PTR_ERR(iod);
1679 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1680 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1681 c.common.prp2 = cpu_to_le64(iod->first_dma);
1682 }
1683
1684 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1685 ADMIN_TIMEOUT;
1686
1687 if (length != cmd.data_len)
1688 status = -ENOMEM;
1689 else if (ns) {
1690 struct request *req;
1691
1692 req = blk_mq_alloc_request(ns->queue, WRITE,
1693 (GFP_KERNEL|__GFP_WAIT), false);
1694 if (IS_ERR(req))
1695 status = PTR_ERR(req);
1696 else {
1697 status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1698 timeout);
1699 blk_mq_free_request(req);
1700 }
1701 } else
1702 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
1703
1704 if (cmd.data_len) {
1705 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1706 nvme_free_iod(dev, iod);
1707 }
1708
1709 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
1710 sizeof(cmd.result)))
1711 status = -EFAULT;
1712
1713 return status;
1714 }
1715
1716 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1717 unsigned long arg)
1718 {
1719 struct nvme_ns *ns = bdev->bd_disk->private_data;
1720
1721 switch (cmd) {
1722 case NVME_IOCTL_ID:
1723 force_successful_syscall_return();
1724 return ns->ns_id;
1725 case NVME_IOCTL_ADMIN_CMD:
1726 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
1727 case NVME_IOCTL_IO_CMD:
1728 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
1729 case NVME_IOCTL_SUBMIT_IO:
1730 return nvme_submit_io(ns, (void __user *)arg);
1731 case SG_GET_VERSION_NUM:
1732 return nvme_sg_get_version_num((void __user *)arg);
1733 case SG_IO:
1734 return nvme_sg_io(ns, (void __user *)arg);
1735 default:
1736 return -ENOTTY;
1737 }
1738 }
1739
1740 #ifdef CONFIG_COMPAT
1741 static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1742 unsigned int cmd, unsigned long arg)
1743 {
1744 switch (cmd) {
1745 case SG_IO:
1746 return -ENOIOCTLCMD;
1747 }
1748 return nvme_ioctl(bdev, mode, cmd, arg);
1749 }
1750 #else
1751 #define nvme_compat_ioctl NULL
1752 #endif
1753
1754 static int nvme_open(struct block_device *bdev, fmode_t mode)
1755 {
1756 int ret = 0;
1757 struct nvme_ns *ns;
1758
1759 spin_lock(&dev_list_lock);
1760 ns = bdev->bd_disk->private_data;
1761 if (!ns)
1762 ret = -ENXIO;
1763 else if (!kref_get_unless_zero(&ns->dev->kref))
1764 ret = -ENXIO;
1765 spin_unlock(&dev_list_lock);
1766
1767 return ret;
1768 }
1769
1770 static void nvme_free_dev(struct kref *kref);
1771
1772 static void nvme_release(struct gendisk *disk, fmode_t mode)
1773 {
1774 struct nvme_ns *ns = disk->private_data;
1775 struct nvme_dev *dev = ns->dev;
1776
1777 kref_put(&dev->kref, nvme_free_dev);
1778 }
1779
1780 static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1781 {
1782 /* some standard values */
1783 geo->heads = 1 << 6;
1784 geo->sectors = 1 << 5;
1785 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1786 return 0;
1787 }
1788
1789 static int nvme_revalidate_disk(struct gendisk *disk)
1790 {
1791 struct nvme_ns *ns = disk->private_data;
1792 struct nvme_dev *dev = ns->dev;
1793 struct nvme_id_ns *id;
1794 dma_addr_t dma_addr;
1795 int lbaf;
1796
1797 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
1798 GFP_KERNEL);
1799 if (!id) {
1800 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
1801 __func__);
1802 return 0;
1803 }
1804
1805 if (nvme_identify(dev, ns->ns_id, 0, dma_addr))
1806 goto free;
1807
1808 lbaf = id->flbas & 0xf;
1809 ns->lba_shift = id->lbaf[lbaf].ds;
1810
1811 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1812 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1813 free:
1814 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1815 return 0;
1816 }
1817
1818 static const struct block_device_operations nvme_fops = {
1819 .owner = THIS_MODULE,
1820 .ioctl = nvme_ioctl,
1821 .compat_ioctl = nvme_compat_ioctl,
1822 .open = nvme_open,
1823 .release = nvme_release,
1824 .getgeo = nvme_getgeo,
1825 .revalidate_disk= nvme_revalidate_disk,
1826 };
1827
1828 static int nvme_kthread(void *data)
1829 {
1830 struct nvme_dev *dev, *next;
1831
1832 while (!kthread_should_stop()) {
1833 set_current_state(TASK_INTERRUPTIBLE);
1834 spin_lock(&dev_list_lock);
1835 list_for_each_entry_safe(dev, next, &dev_list, node) {
1836 int i;
1837 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1838 dev->initialized) {
1839 if (work_busy(&dev->reset_work))
1840 continue;
1841 list_del_init(&dev->node);
1842 dev_warn(&dev->pci_dev->dev,
1843 "Failed status: %x, reset controller\n",
1844 readl(&dev->bar->csts));
1845 dev->reset_workfn = nvme_reset_failed_dev;
1846 queue_work(nvme_workq, &dev->reset_work);
1847 continue;
1848 }
1849 for (i = 0; i < dev->queue_count; i++) {
1850 struct nvme_queue *nvmeq = dev->queues[i];
1851 if (!nvmeq)
1852 continue;
1853 spin_lock_irq(&nvmeq->q_lock);
1854 nvme_process_cq(nvmeq);
1855
1856 while ((i == 0) && (dev->event_limit > 0)) {
1857 if (nvme_submit_async_admin_req(dev))
1858 break;
1859 dev->event_limit--;
1860 }
1861 spin_unlock_irq(&nvmeq->q_lock);
1862 }
1863 }
1864 spin_unlock(&dev_list_lock);
1865 schedule_timeout(round_jiffies_relative(HZ));
1866 }
1867 return 0;
1868 }
1869
1870 static void nvme_config_discard(struct nvme_ns *ns)
1871 {
1872 u32 logical_block_size = queue_logical_block_size(ns->queue);
1873 ns->queue->limits.discard_zeroes_data = 0;
1874 ns->queue->limits.discard_alignment = logical_block_size;
1875 ns->queue->limits.discard_granularity = logical_block_size;
1876 ns->queue->limits.max_discard_sectors = 0xffffffff;
1877 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1878 }
1879
1880 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
1881 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1882 {
1883 struct nvme_ns *ns;
1884 struct gendisk *disk;
1885 int node = dev_to_node(&dev->pci_dev->dev);
1886 int lbaf;
1887
1888 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1889 return NULL;
1890
1891 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
1892 if (!ns)
1893 return NULL;
1894 ns->queue = blk_mq_init_queue(&dev->tagset);
1895 if (IS_ERR(ns->queue))
1896 goto out_free_ns;
1897 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1898 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1899 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
1900 ns->dev = dev;
1901 ns->queue->queuedata = ns;
1902
1903 disk = alloc_disk_node(0, node);
1904 if (!disk)
1905 goto out_free_queue;
1906
1907 ns->ns_id = nsid;
1908 ns->disk = disk;
1909 lbaf = id->flbas & 0xf;
1910 ns->lba_shift = id->lbaf[lbaf].ds;
1911 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
1912 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1913 if (dev->max_hw_sectors)
1914 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
1915 if (dev->stripe_size)
1916 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
1917 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
1918 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
1919
1920 disk->major = nvme_major;
1921 disk->first_minor = 0;
1922 disk->fops = &nvme_fops;
1923 disk->private_data = ns;
1924 disk->queue = ns->queue;
1925 disk->driverfs_dev = &dev->pci_dev->dev;
1926 disk->flags = GENHD_FL_EXT_DEVT;
1927 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1928 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1929
1930 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1931 nvme_config_discard(ns);
1932
1933 return ns;
1934
1935 out_free_queue:
1936 blk_cleanup_queue(ns->queue);
1937 out_free_ns:
1938 kfree(ns);
1939 return NULL;
1940 }
1941
1942 static void nvme_create_io_queues(struct nvme_dev *dev)
1943 {
1944 unsigned i;
1945
1946 for (i = dev->queue_count; i <= dev->max_qid; i++)
1947 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
1948 break;
1949
1950 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
1951 if (nvme_create_queue(dev->queues[i], i))
1952 break;
1953 }
1954
1955 static int set_queue_count(struct nvme_dev *dev, int count)
1956 {
1957 int status;
1958 u32 result;
1959 u32 q_count = (count - 1) | ((count - 1) << 16);
1960
1961 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1962 &result);
1963 if (status < 0)
1964 return status;
1965 if (status > 0) {
1966 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
1967 status);
1968 return 0;
1969 }
1970 return min(result & 0xffff, result >> 16) + 1;
1971 }
1972
1973 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1974 {
1975 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1976 }
1977
1978 static int nvme_setup_io_queues(struct nvme_dev *dev)
1979 {
1980 struct nvme_queue *adminq = dev->queues[0];
1981 struct pci_dev *pdev = dev->pci_dev;
1982 int result, i, vecs, nr_io_queues, size;
1983
1984 nr_io_queues = num_possible_cpus();
1985 result = set_queue_count(dev, nr_io_queues);
1986 if (result <= 0)
1987 return result;
1988 if (result < nr_io_queues)
1989 nr_io_queues = result;
1990
1991 size = db_bar_size(dev, nr_io_queues);
1992 if (size > 8192) {
1993 iounmap(dev->bar);
1994 do {
1995 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1996 if (dev->bar)
1997 break;
1998 if (!--nr_io_queues)
1999 return -ENOMEM;
2000 size = db_bar_size(dev, nr_io_queues);
2001 } while (1);
2002 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2003 adminq->q_db = dev->dbs;
2004 }
2005
2006 /* Deregister the admin queue's interrupt */
2007 free_irq(dev->entry[0].vector, adminq);
2008
2009 /*
2010 * If we enable msix early due to not intx, disable it again before
2011 * setting up the full range we need.
2012 */
2013 if (!pdev->irq)
2014 pci_disable_msix(pdev);
2015
2016 for (i = 0; i < nr_io_queues; i++)
2017 dev->entry[i].entry = i;
2018 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2019 if (vecs < 0) {
2020 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2021 if (vecs < 0) {
2022 vecs = 1;
2023 } else {
2024 for (i = 0; i < vecs; i++)
2025 dev->entry[i].vector = i + pdev->irq;
2026 }
2027 }
2028
2029 /*
2030 * Should investigate if there's a performance win from allocating
2031 * more queues than interrupt vectors; it might allow the submission
2032 * path to scale better, even if the receive path is limited by the
2033 * number of interrupts.
2034 */
2035 nr_io_queues = vecs;
2036 dev->max_qid = nr_io_queues;
2037
2038 result = queue_request_irq(dev, adminq, adminq->irqname);
2039 if (result)
2040 goto free_queues;
2041
2042 /* Free previously allocated queues that are no longer usable */
2043 nvme_free_queues(dev, nr_io_queues + 1);
2044 nvme_create_io_queues(dev);
2045
2046 return 0;
2047
2048 free_queues:
2049 nvme_free_queues(dev, 1);
2050 return result;
2051 }
2052
2053 /*
2054 * Return: error value if an error occurred setting up the queues or calling
2055 * Identify Device. 0 if these succeeded, even if adding some of the
2056 * namespaces failed. At the moment, these failures are silent. TBD which
2057 * failures should be reported.
2058 */
2059 static int nvme_dev_add(struct nvme_dev *dev)
2060 {
2061 struct pci_dev *pdev = dev->pci_dev;
2062 int res;
2063 unsigned nn, i;
2064 struct nvme_ns *ns;
2065 struct nvme_id_ctrl *ctrl;
2066 struct nvme_id_ns *id_ns;
2067 void *mem;
2068 dma_addr_t dma_addr;
2069 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
2070
2071 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
2072 if (!mem)
2073 return -ENOMEM;
2074
2075 res = nvme_identify(dev, 0, 1, dma_addr);
2076 if (res) {
2077 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
2078 res = -EIO;
2079 goto out;
2080 }
2081
2082 ctrl = mem;
2083 nn = le32_to_cpup(&ctrl->nn);
2084 dev->oncs = le16_to_cpup(&ctrl->oncs);
2085 dev->abort_limit = ctrl->acl + 1;
2086 dev->vwc = ctrl->vwc;
2087 dev->event_limit = min(ctrl->aerl + 1, 8);
2088 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2089 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2090 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
2091 if (ctrl->mdts)
2092 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
2093 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2094 (pdev->device == 0x0953) && ctrl->vs[3]) {
2095 unsigned int max_hw_sectors;
2096
2097 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
2098 max_hw_sectors = dev->stripe_size >> (shift - 9);
2099 if (dev->max_hw_sectors) {
2100 dev->max_hw_sectors = min(max_hw_sectors,
2101 dev->max_hw_sectors);
2102 } else
2103 dev->max_hw_sectors = max_hw_sectors;
2104 }
2105
2106 dev->tagset.ops = &nvme_mq_ops;
2107 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2108 dev->tagset.timeout = NVME_IO_TIMEOUT;
2109 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2110 dev->tagset.queue_depth =
2111 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2112 dev->tagset.cmd_size = sizeof(struct nvme_cmd_info);
2113 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2114 dev->tagset.driver_data = dev;
2115
2116 if (blk_mq_alloc_tag_set(&dev->tagset))
2117 goto out;
2118
2119 id_ns = mem;
2120 for (i = 1; i <= nn; i++) {
2121 res = nvme_identify(dev, i, 0, dma_addr);
2122 if (res)
2123 continue;
2124
2125 if (id_ns->ncap == 0)
2126 continue;
2127
2128 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
2129 dma_addr + 4096, NULL);
2130 if (res)
2131 memset(mem + 4096, 0, 4096);
2132
2133 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
2134 if (ns)
2135 list_add_tail(&ns->list, &dev->namespaces);
2136 }
2137 list_for_each_entry(ns, &dev->namespaces, list)
2138 add_disk(ns->disk);
2139 res = 0;
2140
2141 out:
2142 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
2143 return res;
2144 }
2145
2146 static int nvme_dev_map(struct nvme_dev *dev)
2147 {
2148 u64 cap;
2149 int bars, result = -ENOMEM;
2150 struct pci_dev *pdev = dev->pci_dev;
2151
2152 if (pci_enable_device_mem(pdev))
2153 return result;
2154
2155 dev->entry[0].vector = pdev->irq;
2156 pci_set_master(pdev);
2157 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2158 if (!bars)
2159 goto disable_pci;
2160
2161 if (pci_request_selected_regions(pdev, bars, "nvme"))
2162 goto disable_pci;
2163
2164 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2165 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2166 goto disable;
2167
2168 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2169 if (!dev->bar)
2170 goto disable;
2171
2172 if (readl(&dev->bar->csts) == -1) {
2173 result = -ENODEV;
2174 goto unmap;
2175 }
2176
2177 /*
2178 * Some devices don't advertse INTx interrupts, pre-enable a single
2179 * MSIX vec for setup. We'll adjust this later.
2180 */
2181 if (!pdev->irq) {
2182 result = pci_enable_msix(pdev, dev->entry, 1);
2183 if (result < 0)
2184 goto unmap;
2185 }
2186
2187 cap = readq(&dev->bar->cap);
2188 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2189 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
2190 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2191
2192 return 0;
2193
2194 unmap:
2195 iounmap(dev->bar);
2196 dev->bar = NULL;
2197 disable:
2198 pci_release_regions(pdev);
2199 disable_pci:
2200 pci_disable_device(pdev);
2201 return result;
2202 }
2203
2204 static void nvme_dev_unmap(struct nvme_dev *dev)
2205 {
2206 if (dev->pci_dev->msi_enabled)
2207 pci_disable_msi(dev->pci_dev);
2208 else if (dev->pci_dev->msix_enabled)
2209 pci_disable_msix(dev->pci_dev);
2210
2211 if (dev->bar) {
2212 iounmap(dev->bar);
2213 dev->bar = NULL;
2214 pci_release_regions(dev->pci_dev);
2215 }
2216
2217 if (pci_is_enabled(dev->pci_dev))
2218 pci_disable_device(dev->pci_dev);
2219 }
2220
2221 struct nvme_delq_ctx {
2222 struct task_struct *waiter;
2223 struct kthread_worker *worker;
2224 atomic_t refcount;
2225 };
2226
2227 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2228 {
2229 dq->waiter = current;
2230 mb();
2231
2232 for (;;) {
2233 set_current_state(TASK_KILLABLE);
2234 if (!atomic_read(&dq->refcount))
2235 break;
2236 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2237 fatal_signal_pending(current)) {
2238 set_current_state(TASK_RUNNING);
2239
2240 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2241 nvme_disable_queue(dev, 0);
2242
2243 send_sig(SIGKILL, dq->worker->task, 1);
2244 flush_kthread_worker(dq->worker);
2245 return;
2246 }
2247 }
2248 set_current_state(TASK_RUNNING);
2249 }
2250
2251 static void nvme_put_dq(struct nvme_delq_ctx *dq)
2252 {
2253 atomic_dec(&dq->refcount);
2254 if (dq->waiter)
2255 wake_up_process(dq->waiter);
2256 }
2257
2258 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2259 {
2260 atomic_inc(&dq->refcount);
2261 return dq;
2262 }
2263
2264 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2265 {
2266 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2267
2268 nvme_clear_queue(nvmeq);
2269 nvme_put_dq(dq);
2270 }
2271
2272 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2273 kthread_work_func_t fn)
2274 {
2275 struct nvme_command c;
2276
2277 memset(&c, 0, sizeof(c));
2278 c.delete_queue.opcode = opcode;
2279 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2280
2281 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2282 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2283 ADMIN_TIMEOUT);
2284 }
2285
2286 static void nvme_del_cq_work_handler(struct kthread_work *work)
2287 {
2288 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2289 cmdinfo.work);
2290 nvme_del_queue_end(nvmeq);
2291 }
2292
2293 static int nvme_delete_cq(struct nvme_queue *nvmeq)
2294 {
2295 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2296 nvme_del_cq_work_handler);
2297 }
2298
2299 static void nvme_del_sq_work_handler(struct kthread_work *work)
2300 {
2301 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2302 cmdinfo.work);
2303 int status = nvmeq->cmdinfo.status;
2304
2305 if (!status)
2306 status = nvme_delete_cq(nvmeq);
2307 if (status)
2308 nvme_del_queue_end(nvmeq);
2309 }
2310
2311 static int nvme_delete_sq(struct nvme_queue *nvmeq)
2312 {
2313 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2314 nvme_del_sq_work_handler);
2315 }
2316
2317 static void nvme_del_queue_start(struct kthread_work *work)
2318 {
2319 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2320 cmdinfo.work);
2321 allow_signal(SIGKILL);
2322 if (nvme_delete_sq(nvmeq))
2323 nvme_del_queue_end(nvmeq);
2324 }
2325
2326 static void nvme_disable_io_queues(struct nvme_dev *dev)
2327 {
2328 int i;
2329 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2330 struct nvme_delq_ctx dq;
2331 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2332 &worker, "nvme%d", dev->instance);
2333
2334 if (IS_ERR(kworker_task)) {
2335 dev_err(&dev->pci_dev->dev,
2336 "Failed to create queue del task\n");
2337 for (i = dev->queue_count - 1; i > 0; i--)
2338 nvme_disable_queue(dev, i);
2339 return;
2340 }
2341
2342 dq.waiter = NULL;
2343 atomic_set(&dq.refcount, 0);
2344 dq.worker = &worker;
2345 for (i = dev->queue_count - 1; i > 0; i--) {
2346 struct nvme_queue *nvmeq = dev->queues[i];
2347
2348 if (nvme_suspend_queue(nvmeq))
2349 continue;
2350 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2351 nvmeq->cmdinfo.worker = dq.worker;
2352 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2353 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2354 }
2355 nvme_wait_dq(&dq, dev);
2356 kthread_stop(kworker_task);
2357 }
2358
2359 /*
2360 * Remove the node from the device list and check
2361 * for whether or not we need to stop the nvme_thread.
2362 */
2363 static void nvme_dev_list_remove(struct nvme_dev *dev)
2364 {
2365 struct task_struct *tmp = NULL;
2366
2367 spin_lock(&dev_list_lock);
2368 list_del_init(&dev->node);
2369 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2370 tmp = nvme_thread;
2371 nvme_thread = NULL;
2372 }
2373 spin_unlock(&dev_list_lock);
2374
2375 if (tmp)
2376 kthread_stop(tmp);
2377 }
2378
2379 static void nvme_dev_shutdown(struct nvme_dev *dev)
2380 {
2381 int i;
2382 u32 csts = -1;
2383
2384 dev->initialized = 0;
2385 nvme_dev_list_remove(dev);
2386
2387 if (dev->bar)
2388 csts = readl(&dev->bar->csts);
2389 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2390 for (i = dev->queue_count - 1; i >= 0; i--) {
2391 struct nvme_queue *nvmeq = dev->queues[i];
2392 nvme_suspend_queue(nvmeq);
2393 nvme_clear_queue(nvmeq);
2394 }
2395 } else {
2396 nvme_disable_io_queues(dev);
2397 nvme_shutdown_ctrl(dev);
2398 nvme_disable_queue(dev, 0);
2399 }
2400 nvme_dev_unmap(dev);
2401 }
2402
2403 static void nvme_dev_remove_admin(struct nvme_dev *dev)
2404 {
2405 if (dev->admin_q && !blk_queue_dying(dev->admin_q))
2406 blk_cleanup_queue(dev->admin_q);
2407 }
2408
2409 static void nvme_dev_remove(struct nvme_dev *dev)
2410 {
2411 struct nvme_ns *ns;
2412
2413 list_for_each_entry(ns, &dev->namespaces, list) {
2414 if (ns->disk->flags & GENHD_FL_UP)
2415 del_gendisk(ns->disk);
2416 if (!blk_queue_dying(ns->queue))
2417 blk_cleanup_queue(ns->queue);
2418 }
2419 }
2420
2421 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2422 {
2423 struct device *dmadev = &dev->pci_dev->dev;
2424 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2425 PAGE_SIZE, PAGE_SIZE, 0);
2426 if (!dev->prp_page_pool)
2427 return -ENOMEM;
2428
2429 /* Optimisation for I/Os between 4k and 128k */
2430 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2431 256, 256, 0);
2432 if (!dev->prp_small_pool) {
2433 dma_pool_destroy(dev->prp_page_pool);
2434 return -ENOMEM;
2435 }
2436 return 0;
2437 }
2438
2439 static void nvme_release_prp_pools(struct nvme_dev *dev)
2440 {
2441 dma_pool_destroy(dev->prp_page_pool);
2442 dma_pool_destroy(dev->prp_small_pool);
2443 }
2444
2445 static DEFINE_IDA(nvme_instance_ida);
2446
2447 static int nvme_set_instance(struct nvme_dev *dev)
2448 {
2449 int instance, error;
2450
2451 do {
2452 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2453 return -ENODEV;
2454
2455 spin_lock(&dev_list_lock);
2456 error = ida_get_new(&nvme_instance_ida, &instance);
2457 spin_unlock(&dev_list_lock);
2458 } while (error == -EAGAIN);
2459
2460 if (error)
2461 return -ENODEV;
2462
2463 dev->instance = instance;
2464 return 0;
2465 }
2466
2467 static void nvme_release_instance(struct nvme_dev *dev)
2468 {
2469 spin_lock(&dev_list_lock);
2470 ida_remove(&nvme_instance_ida, dev->instance);
2471 spin_unlock(&dev_list_lock);
2472 }
2473
2474 static void nvme_free_namespaces(struct nvme_dev *dev)
2475 {
2476 struct nvme_ns *ns, *next;
2477
2478 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2479 list_del(&ns->list);
2480
2481 spin_lock(&dev_list_lock);
2482 ns->disk->private_data = NULL;
2483 spin_unlock(&dev_list_lock);
2484
2485 put_disk(ns->disk);
2486 kfree(ns);
2487 }
2488 }
2489
2490 static void nvme_free_dev(struct kref *kref)
2491 {
2492 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
2493
2494 pci_dev_put(dev->pci_dev);
2495 nvme_free_namespaces(dev);
2496 nvme_release_instance(dev);
2497 blk_mq_free_tag_set(&dev->tagset);
2498 kfree(dev->queues);
2499 kfree(dev->entry);
2500 kfree(dev);
2501 }
2502
2503 static int nvme_dev_open(struct inode *inode, struct file *f)
2504 {
2505 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2506 miscdev);
2507 kref_get(&dev->kref);
2508 f->private_data = dev;
2509 return 0;
2510 }
2511
2512 static int nvme_dev_release(struct inode *inode, struct file *f)
2513 {
2514 struct nvme_dev *dev = f->private_data;
2515 kref_put(&dev->kref, nvme_free_dev);
2516 return 0;
2517 }
2518
2519 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2520 {
2521 struct nvme_dev *dev = f->private_data;
2522 struct nvme_ns *ns;
2523
2524 switch (cmd) {
2525 case NVME_IOCTL_ADMIN_CMD:
2526 return nvme_user_cmd(dev, NULL, (void __user *)arg);
2527 case NVME_IOCTL_IO_CMD:
2528 if (list_empty(&dev->namespaces))
2529 return -ENOTTY;
2530 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2531 return nvme_user_cmd(dev, ns, (void __user *)arg);
2532 default:
2533 return -ENOTTY;
2534 }
2535 }
2536
2537 static const struct file_operations nvme_dev_fops = {
2538 .owner = THIS_MODULE,
2539 .open = nvme_dev_open,
2540 .release = nvme_dev_release,
2541 .unlocked_ioctl = nvme_dev_ioctl,
2542 .compat_ioctl = nvme_dev_ioctl,
2543 };
2544
2545 static void nvme_set_irq_hints(struct nvme_dev *dev)
2546 {
2547 struct nvme_queue *nvmeq;
2548 int i;
2549
2550 for (i = 0; i < dev->online_queues; i++) {
2551 nvmeq = dev->queues[i];
2552
2553 if (!nvmeq->hctx)
2554 continue;
2555
2556 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2557 nvmeq->hctx->cpumask);
2558 }
2559 }
2560
2561 static int nvme_dev_start(struct nvme_dev *dev)
2562 {
2563 int result;
2564 bool start_thread = false;
2565
2566 result = nvme_dev_map(dev);
2567 if (result)
2568 return result;
2569
2570 result = nvme_configure_admin_queue(dev);
2571 if (result)
2572 goto unmap;
2573
2574 spin_lock(&dev_list_lock);
2575 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2576 start_thread = true;
2577 nvme_thread = NULL;
2578 }
2579 list_add(&dev->node, &dev_list);
2580 spin_unlock(&dev_list_lock);
2581
2582 if (start_thread) {
2583 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2584 wake_up_all(&nvme_kthread_wait);
2585 } else
2586 wait_event_killable(nvme_kthread_wait, nvme_thread);
2587
2588 if (IS_ERR_OR_NULL(nvme_thread)) {
2589 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2590 goto disable;
2591 }
2592
2593 nvme_init_queue(dev->queues[0], 0);
2594
2595 result = nvme_setup_io_queues(dev);
2596 if (result)
2597 goto disable;
2598
2599 nvme_set_irq_hints(dev);
2600
2601 return result;
2602
2603 disable:
2604 nvme_disable_queue(dev, 0);
2605 nvme_dev_list_remove(dev);
2606 unmap:
2607 nvme_dev_unmap(dev);
2608 return result;
2609 }
2610
2611 static int nvme_remove_dead_ctrl(void *arg)
2612 {
2613 struct nvme_dev *dev = (struct nvme_dev *)arg;
2614 struct pci_dev *pdev = dev->pci_dev;
2615
2616 if (pci_get_drvdata(pdev))
2617 pci_stop_and_remove_bus_device_locked(pdev);
2618 kref_put(&dev->kref, nvme_free_dev);
2619 return 0;
2620 }
2621
2622 static void nvme_remove_disks(struct work_struct *ws)
2623 {
2624 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2625
2626 nvme_free_queues(dev, 1);
2627 nvme_dev_remove(dev);
2628 }
2629
2630 static int nvme_dev_resume(struct nvme_dev *dev)
2631 {
2632 int ret;
2633
2634 ret = nvme_dev_start(dev);
2635 if (ret)
2636 return ret;
2637 if (dev->online_queues < 2) {
2638 spin_lock(&dev_list_lock);
2639 dev->reset_workfn = nvme_remove_disks;
2640 queue_work(nvme_workq, &dev->reset_work);
2641 spin_unlock(&dev_list_lock);
2642 }
2643 dev->initialized = 1;
2644 return 0;
2645 }
2646
2647 static void nvme_dev_reset(struct nvme_dev *dev)
2648 {
2649 nvme_dev_shutdown(dev);
2650 if (nvme_dev_resume(dev)) {
2651 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
2652 kref_get(&dev->kref);
2653 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2654 dev->instance))) {
2655 dev_err(&dev->pci_dev->dev,
2656 "Failed to start controller remove task\n");
2657 kref_put(&dev->kref, nvme_free_dev);
2658 }
2659 }
2660 }
2661
2662 static void nvme_reset_failed_dev(struct work_struct *ws)
2663 {
2664 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2665 nvme_dev_reset(dev);
2666 }
2667
2668 static void nvme_reset_workfn(struct work_struct *work)
2669 {
2670 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2671 dev->reset_workfn(work);
2672 }
2673
2674 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2675 {
2676 int node, result = -ENOMEM;
2677 struct nvme_dev *dev;
2678
2679 node = dev_to_node(&pdev->dev);
2680 if (node == NUMA_NO_NODE)
2681 set_dev_node(&pdev->dev, 0);
2682
2683 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2684 if (!dev)
2685 return -ENOMEM;
2686 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2687 GFP_KERNEL, node);
2688 if (!dev->entry)
2689 goto free;
2690 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2691 GFP_KERNEL, node);
2692 if (!dev->queues)
2693 goto free;
2694
2695 INIT_LIST_HEAD(&dev->namespaces);
2696 dev->reset_workfn = nvme_reset_failed_dev;
2697 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
2698 dev->pci_dev = pci_dev_get(pdev);
2699 pci_set_drvdata(pdev, dev);
2700 result = nvme_set_instance(dev);
2701 if (result)
2702 goto put_pci;
2703
2704 result = nvme_setup_prp_pools(dev);
2705 if (result)
2706 goto release;
2707
2708 kref_init(&dev->kref);
2709 result = nvme_dev_start(dev);
2710 if (result)
2711 goto release_pools;
2712
2713 if (dev->online_queues > 1)
2714 result = nvme_dev_add(dev);
2715 if (result)
2716 goto shutdown;
2717
2718 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2719 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2720 dev->miscdev.parent = &pdev->dev;
2721 dev->miscdev.name = dev->name;
2722 dev->miscdev.fops = &nvme_dev_fops;
2723 result = misc_register(&dev->miscdev);
2724 if (result)
2725 goto remove;
2726
2727 nvme_set_irq_hints(dev);
2728
2729 dev->initialized = 1;
2730 return 0;
2731
2732 remove:
2733 nvme_dev_remove(dev);
2734 nvme_dev_remove_admin(dev);
2735 nvme_free_namespaces(dev);
2736 shutdown:
2737 nvme_dev_shutdown(dev);
2738 release_pools:
2739 nvme_free_queues(dev, 0);
2740 nvme_release_prp_pools(dev);
2741 release:
2742 nvme_release_instance(dev);
2743 put_pci:
2744 pci_dev_put(dev->pci_dev);
2745 free:
2746 kfree(dev->queues);
2747 kfree(dev->entry);
2748 kfree(dev);
2749 return result;
2750 }
2751
2752 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2753 {
2754 struct nvme_dev *dev = pci_get_drvdata(pdev);
2755
2756 if (prepare)
2757 nvme_dev_shutdown(dev);
2758 else
2759 nvme_dev_resume(dev);
2760 }
2761
2762 static void nvme_shutdown(struct pci_dev *pdev)
2763 {
2764 struct nvme_dev *dev = pci_get_drvdata(pdev);
2765 nvme_dev_shutdown(dev);
2766 }
2767
2768 static void nvme_remove(struct pci_dev *pdev)
2769 {
2770 struct nvme_dev *dev = pci_get_drvdata(pdev);
2771
2772 spin_lock(&dev_list_lock);
2773 list_del_init(&dev->node);
2774 spin_unlock(&dev_list_lock);
2775
2776 pci_set_drvdata(pdev, NULL);
2777 flush_work(&dev->reset_work);
2778 misc_deregister(&dev->miscdev);
2779 nvme_dev_remove(dev);
2780 nvme_dev_shutdown(dev);
2781 nvme_dev_remove_admin(dev);
2782 nvme_free_queues(dev, 0);
2783 nvme_free_admin_tags(dev);
2784 nvme_release_prp_pools(dev);
2785 kref_put(&dev->kref, nvme_free_dev);
2786 }
2787
2788 /* These functions are yet to be implemented */
2789 #define nvme_error_detected NULL
2790 #define nvme_dump_registers NULL
2791 #define nvme_link_reset NULL
2792 #define nvme_slot_reset NULL
2793 #define nvme_error_resume NULL
2794
2795 #ifdef CONFIG_PM_SLEEP
2796 static int nvme_suspend(struct device *dev)
2797 {
2798 struct pci_dev *pdev = to_pci_dev(dev);
2799 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2800
2801 nvme_dev_shutdown(ndev);
2802 return 0;
2803 }
2804
2805 static int nvme_resume(struct device *dev)
2806 {
2807 struct pci_dev *pdev = to_pci_dev(dev);
2808 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2809
2810 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
2811 ndev->reset_workfn = nvme_reset_failed_dev;
2812 queue_work(nvme_workq, &ndev->reset_work);
2813 }
2814 return 0;
2815 }
2816 #endif
2817
2818 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2819
2820 static const struct pci_error_handlers nvme_err_handler = {
2821 .error_detected = nvme_error_detected,
2822 .mmio_enabled = nvme_dump_registers,
2823 .link_reset = nvme_link_reset,
2824 .slot_reset = nvme_slot_reset,
2825 .resume = nvme_error_resume,
2826 .reset_notify = nvme_reset_notify,
2827 };
2828
2829 /* Move to pci_ids.h later */
2830 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2831
2832 static const struct pci_device_id nvme_id_table[] = {
2833 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2834 { 0, }
2835 };
2836 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2837
2838 static struct pci_driver nvme_driver = {
2839 .name = "nvme",
2840 .id_table = nvme_id_table,
2841 .probe = nvme_probe,
2842 .remove = nvme_remove,
2843 .shutdown = nvme_shutdown,
2844 .driver = {
2845 .pm = &nvme_dev_pm_ops,
2846 },
2847 .err_handler = &nvme_err_handler,
2848 };
2849
2850 static int __init nvme_init(void)
2851 {
2852 int result;
2853
2854 init_waitqueue_head(&nvme_kthread_wait);
2855
2856 nvme_workq = create_singlethread_workqueue("nvme");
2857 if (!nvme_workq)
2858 return -ENOMEM;
2859
2860 result = register_blkdev(nvme_major, "nvme");
2861 if (result < 0)
2862 goto kill_workq;
2863 else if (result > 0)
2864 nvme_major = result;
2865
2866 result = pci_register_driver(&nvme_driver);
2867 if (result)
2868 goto unregister_blkdev;
2869 return 0;
2870
2871 unregister_blkdev:
2872 unregister_blkdev(nvme_major, "nvme");
2873 kill_workq:
2874 destroy_workqueue(nvme_workq);
2875 return result;
2876 }
2877
2878 static void __exit nvme_exit(void)
2879 {
2880 pci_unregister_driver(&nvme_driver);
2881 unregister_hotcpu_notifier(&nvme_nb);
2882 unregister_blkdev(nvme_major, "nvme");
2883 destroy_workqueue(nvme_workq);
2884 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2885 _nvme_check_size();
2886 }
2887
2888 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2889 MODULE_LICENSE("GPL");
2890 MODULE_VERSION("1.0");
2891 module_init(nvme_init);
2892 module_exit(nvme_exit);
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