2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
43 #include <asm-generic/io-64-nonatomic-lo-hi.h>
45 #define NVME_Q_DEPTH 1024
46 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
48 #define NVME_MINORS 64
49 #define ADMIN_TIMEOUT (60 * HZ)
51 static int nvme_major
;
52 module_param(nvme_major
, int, 0);
54 static int use_threaded_interrupts
;
55 module_param(use_threaded_interrupts
, int, 0);
57 static DEFINE_SPINLOCK(dev_list_lock
);
58 static LIST_HEAD(dev_list
);
59 static struct task_struct
*nvme_thread
;
62 * An NVM Express queue. Each device has at least two (one for admin
63 * commands and one for I/O commands).
66 struct device
*q_dmadev
;
69 struct nvme_command
*sq_cmds
;
70 volatile struct nvme_completion
*cqes
;
71 dma_addr_t sq_dma_addr
;
72 dma_addr_t cq_dma_addr
;
73 wait_queue_head_t sq_full
;
74 wait_queue_t sq_cong_wait
;
75 struct bio_list sq_cong
;
83 unsigned long cmdid_data
[];
87 * Check we didin't inadvertently grow the command struct
89 static inline void _nvme_check_size(void)
91 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
92 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
93 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
94 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
95 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
96 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
97 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
98 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
99 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
100 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
101 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
104 typedef void (*nvme_completion_fn
)(struct nvme_dev
*, void *,
105 struct nvme_completion
*);
107 struct nvme_cmd_info
{
108 nvme_completion_fn fn
;
110 unsigned long timeout
;
113 static struct nvme_cmd_info
*nvme_cmd_info(struct nvme_queue
*nvmeq
)
115 return (void *)&nvmeq
->cmdid_data
[BITS_TO_LONGS(nvmeq
->q_depth
)];
119 * alloc_cmdid() - Allocate a Command ID
120 * @nvmeq: The queue that will be used for this command
121 * @ctx: A pointer that will be passed to the handler
122 * @handler: The function to call on completion
124 * Allocate a Command ID for a queue. The data passed in will
125 * be passed to the completion handler. This is implemented by using
126 * the bottom two bits of the ctx pointer to store the handler ID.
127 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
128 * We can change this if it becomes a problem.
130 * May be called with local interrupts disabled and the q_lock held,
131 * or with interrupts enabled and no locks held.
133 static int alloc_cmdid(struct nvme_queue
*nvmeq
, void *ctx
,
134 nvme_completion_fn handler
, unsigned timeout
)
136 int depth
= nvmeq
->q_depth
- 1;
137 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
141 cmdid
= find_first_zero_bit(nvmeq
->cmdid_data
, depth
);
144 } while (test_and_set_bit(cmdid
, nvmeq
->cmdid_data
));
146 info
[cmdid
].fn
= handler
;
147 info
[cmdid
].ctx
= ctx
;
148 info
[cmdid
].timeout
= jiffies
+ timeout
;
152 static int alloc_cmdid_killable(struct nvme_queue
*nvmeq
, void *ctx
,
153 nvme_completion_fn handler
, unsigned timeout
)
156 wait_event_killable(nvmeq
->sq_full
,
157 (cmdid
= alloc_cmdid(nvmeq
, ctx
, handler
, timeout
)) >= 0);
158 return (cmdid
< 0) ? -EINTR
: cmdid
;
161 /* Special values must be less than 0x1000 */
162 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
163 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
164 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
165 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
166 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
168 static void special_completion(struct nvme_dev
*dev
, void *ctx
,
169 struct nvme_completion
*cqe
)
171 if (ctx
== CMD_CTX_CANCELLED
)
173 if (ctx
== CMD_CTX_FLUSH
)
175 if (ctx
== CMD_CTX_COMPLETED
) {
176 dev_warn(&dev
->pci_dev
->dev
,
177 "completed id %d twice on queue %d\n",
178 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
181 if (ctx
== CMD_CTX_INVALID
) {
182 dev_warn(&dev
->pci_dev
->dev
,
183 "invalid id %d completed on queue %d\n",
184 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
188 dev_warn(&dev
->pci_dev
->dev
, "Unknown special completion %p\n", ctx
);
192 * Called with local interrupts disabled and the q_lock held. May not sleep.
194 static void *free_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
195 nvme_completion_fn
*fn
)
198 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
200 if (cmdid
>= nvmeq
->q_depth
) {
201 *fn
= special_completion
;
202 return CMD_CTX_INVALID
;
205 *fn
= info
[cmdid
].fn
;
206 ctx
= info
[cmdid
].ctx
;
207 info
[cmdid
].fn
= special_completion
;
208 info
[cmdid
].ctx
= CMD_CTX_COMPLETED
;
209 clear_bit(cmdid
, nvmeq
->cmdid_data
);
210 wake_up(&nvmeq
->sq_full
);
214 static void *cancel_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
215 nvme_completion_fn
*fn
)
218 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
220 *fn
= info
[cmdid
].fn
;
221 ctx
= info
[cmdid
].ctx
;
222 info
[cmdid
].fn
= special_completion
;
223 info
[cmdid
].ctx
= CMD_CTX_CANCELLED
;
227 struct nvme_queue
*get_nvmeq(struct nvme_dev
*dev
)
229 return dev
->queues
[get_cpu() + 1];
232 void put_nvmeq(struct nvme_queue
*nvmeq
)
238 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
239 * @nvmeq: The queue to use
240 * @cmd: The command to send
242 * Safe to use from interrupt context
244 static int nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
)
248 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
249 tail
= nvmeq
->sq_tail
;
250 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
251 if (++tail
== nvmeq
->q_depth
)
253 writel(tail
, nvmeq
->q_db
);
254 nvmeq
->sq_tail
= tail
;
255 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
260 static __le64
**iod_list(struct nvme_iod
*iod
)
262 return ((void *)iod
) + iod
->offset
;
266 * Will slightly overestimate the number of pages needed. This is OK
267 * as it only leads to a small amount of wasted memory for the lifetime of
270 static int nvme_npages(unsigned size
)
272 unsigned nprps
= DIV_ROUND_UP(size
+ PAGE_SIZE
, PAGE_SIZE
);
273 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
276 static struct nvme_iod
*
277 nvme_alloc_iod(unsigned nseg
, unsigned nbytes
, gfp_t gfp
)
279 struct nvme_iod
*iod
= kmalloc(sizeof(struct nvme_iod
) +
280 sizeof(__le64
*) * nvme_npages(nbytes
) +
281 sizeof(struct scatterlist
) * nseg
, gfp
);
284 iod
->offset
= offsetof(struct nvme_iod
, sg
[nseg
]);
286 iod
->length
= nbytes
;
293 void nvme_free_iod(struct nvme_dev
*dev
, struct nvme_iod
*iod
)
295 const int last_prp
= PAGE_SIZE
/ 8 - 1;
297 __le64
**list
= iod_list(iod
);
298 dma_addr_t prp_dma
= iod
->first_dma
;
300 if (iod
->npages
== 0)
301 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
302 for (i
= 0; i
< iod
->npages
; i
++) {
303 __le64
*prp_list
= list
[i
];
304 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
305 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
306 prp_dma
= next_prp_dma
;
311 static void bio_completion(struct nvme_dev
*dev
, void *ctx
,
312 struct nvme_completion
*cqe
)
314 struct nvme_iod
*iod
= ctx
;
315 struct bio
*bio
= iod
->private;
316 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
319 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
320 bio_data_dir(bio
) ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
321 nvme_free_iod(dev
, iod
);
323 bio_endio(bio
, -EIO
);
328 /* length is in bytes. gfp flags indicates whether we may sleep. */
329 int nvme_setup_prps(struct nvme_dev
*dev
, struct nvme_common_command
*cmd
,
330 struct nvme_iod
*iod
, int total_len
, gfp_t gfp
)
332 struct dma_pool
*pool
;
333 int length
= total_len
;
334 struct scatterlist
*sg
= iod
->sg
;
335 int dma_len
= sg_dma_len(sg
);
336 u64 dma_addr
= sg_dma_address(sg
);
337 int offset
= offset_in_page(dma_addr
);
339 __le64
**list
= iod_list(iod
);
343 cmd
->prp1
= cpu_to_le64(dma_addr
);
344 length
-= (PAGE_SIZE
- offset
);
348 dma_len
-= (PAGE_SIZE
- offset
);
350 dma_addr
+= (PAGE_SIZE
- offset
);
353 dma_addr
= sg_dma_address(sg
);
354 dma_len
= sg_dma_len(sg
);
357 if (length
<= PAGE_SIZE
) {
358 cmd
->prp2
= cpu_to_le64(dma_addr
);
362 nprps
= DIV_ROUND_UP(length
, PAGE_SIZE
);
363 if (nprps
<= (256 / 8)) {
364 pool
= dev
->prp_small_pool
;
367 pool
= dev
->prp_page_pool
;
371 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
373 cmd
->prp2
= cpu_to_le64(dma_addr
);
375 return (total_len
- length
) + PAGE_SIZE
;
378 iod
->first_dma
= prp_dma
;
379 cmd
->prp2
= cpu_to_le64(prp_dma
);
382 if (i
== PAGE_SIZE
/ 8) {
383 __le64
*old_prp_list
= prp_list
;
384 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
386 return total_len
- length
;
387 list
[iod
->npages
++] = prp_list
;
388 prp_list
[0] = old_prp_list
[i
- 1];
389 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
392 prp_list
[i
++] = cpu_to_le64(dma_addr
);
393 dma_len
-= PAGE_SIZE
;
394 dma_addr
+= PAGE_SIZE
;
402 dma_addr
= sg_dma_address(sg
);
403 dma_len
= sg_dma_len(sg
);
409 struct nvme_bio_pair
{
410 struct bio b1
, b2
, *parent
;
411 struct bio_vec
*bv1
, *bv2
;
416 static void nvme_bio_pair_endio(struct bio
*bio
, int err
)
418 struct nvme_bio_pair
*bp
= bio
->bi_private
;
423 if (atomic_dec_and_test(&bp
->cnt
)) {
424 bio_endio(bp
->parent
, bp
->err
);
433 static struct nvme_bio_pair
*nvme_bio_split(struct bio
*bio
, int idx
,
436 struct nvme_bio_pair
*bp
;
438 BUG_ON(len
> bio
->bi_size
);
439 BUG_ON(idx
> bio
->bi_vcnt
);
441 bp
= kmalloc(sizeof(*bp
), GFP_ATOMIC
);
449 bp
->b1
.bi_size
= len
;
450 bp
->b2
.bi_size
-= len
;
451 bp
->b1
.bi_vcnt
= idx
;
453 bp
->b2
.bi_sector
+= len
>> 9;
456 bp
->bv1
= kmalloc(bio
->bi_max_vecs
* sizeof(struct bio_vec
),
461 bp
->bv2
= kmalloc(bio
->bi_max_vecs
* sizeof(struct bio_vec
),
466 memcpy(bp
->bv1
, bio
->bi_io_vec
,
467 bio
->bi_max_vecs
* sizeof(struct bio_vec
));
468 memcpy(bp
->bv2
, bio
->bi_io_vec
,
469 bio
->bi_max_vecs
* sizeof(struct bio_vec
));
471 bp
->b1
.bi_io_vec
= bp
->bv1
;
472 bp
->b2
.bi_io_vec
= bp
->bv2
;
473 bp
->b2
.bi_io_vec
[idx
].bv_offset
+= offset
;
474 bp
->b2
.bi_io_vec
[idx
].bv_len
-= offset
;
475 bp
->b1
.bi_io_vec
[idx
].bv_len
= offset
;
478 bp
->bv1
= bp
->bv2
= NULL
;
480 bp
->b1
.bi_private
= bp
;
481 bp
->b2
.bi_private
= bp
;
483 bp
->b1
.bi_end_io
= nvme_bio_pair_endio
;
484 bp
->b2
.bi_end_io
= nvme_bio_pair_endio
;
487 atomic_set(&bp
->cnt
, 2);
498 static int nvme_split_and_submit(struct bio
*bio
, struct nvme_queue
*nvmeq
,
499 int idx
, int len
, int offset
)
501 struct nvme_bio_pair
*bp
= nvme_bio_split(bio
, idx
, len
, offset
);
505 if (bio_list_empty(&nvmeq
->sq_cong
))
506 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
507 bio_list_add(&nvmeq
->sq_cong
, &bp
->b1
);
508 bio_list_add(&nvmeq
->sq_cong
, &bp
->b2
);
513 /* NVMe scatterlists require no holes in the virtual address */
514 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
515 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
517 static int nvme_map_bio(struct nvme_queue
*nvmeq
, struct nvme_iod
*iod
,
518 struct bio
*bio
, enum dma_data_direction dma_dir
, int psegs
)
520 struct bio_vec
*bvec
, *bvprv
= NULL
;
521 struct scatterlist
*sg
= NULL
;
522 int i
, length
= 0, nsegs
= 0;
524 sg_init_table(iod
->sg
, psegs
);
525 bio_for_each_segment(bvec
, bio
, i
) {
526 if (bvprv
&& BIOVEC_PHYS_MERGEABLE(bvprv
, bvec
)) {
527 sg
->length
+= bvec
->bv_len
;
529 if (bvprv
&& BIOVEC_NOT_VIRT_MERGEABLE(bvprv
, bvec
))
530 return nvme_split_and_submit(bio
, nvmeq
, i
,
533 sg
= sg
? sg
+ 1 : iod
->sg
;
534 sg_set_page(sg
, bvec
->bv_page
, bvec
->bv_len
,
538 length
+= bvec
->bv_len
;
543 if (dma_map_sg(nvmeq
->q_dmadev
, iod
->sg
, iod
->nents
, dma_dir
) == 0)
550 * We reuse the small pool to allocate the 16-byte range here as it is not
551 * worth having a special pool for these or additional cases to handle freeing
554 static int nvme_submit_discard(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
555 struct bio
*bio
, struct nvme_iod
*iod
, int cmdid
)
557 struct nvme_dsm_range
*range
;
558 struct nvme_command
*cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
560 range
= dma_pool_alloc(nvmeq
->dev
->prp_small_pool
, GFP_ATOMIC
,
565 iod_list(iod
)[0] = (__le64
*)range
;
568 range
->cattr
= cpu_to_le32(0);
569 range
->nlb
= cpu_to_le32(bio
->bi_size
>> ns
->lba_shift
);
570 range
->slba
= cpu_to_le64(nvme_block_nr(ns
, bio
->bi_sector
));
572 memset(cmnd
, 0, sizeof(*cmnd
));
573 cmnd
->dsm
.opcode
= nvme_cmd_dsm
;
574 cmnd
->dsm
.command_id
= cmdid
;
575 cmnd
->dsm
.nsid
= cpu_to_le32(ns
->ns_id
);
576 cmnd
->dsm
.prp1
= cpu_to_le64(iod
->first_dma
);
578 cmnd
->dsm
.attributes
= cpu_to_le32(NVME_DSMGMT_AD
);
580 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
582 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
587 static int nvme_submit_flush(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
590 struct nvme_command
*cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
592 memset(cmnd
, 0, sizeof(*cmnd
));
593 cmnd
->common
.opcode
= nvme_cmd_flush
;
594 cmnd
->common
.command_id
= cmdid
;
595 cmnd
->common
.nsid
= cpu_to_le32(ns
->ns_id
);
597 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
599 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
604 int nvme_submit_flush_data(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
)
606 int cmdid
= alloc_cmdid(nvmeq
, (void *)CMD_CTX_FLUSH
,
607 special_completion
, NVME_IO_TIMEOUT
);
608 if (unlikely(cmdid
< 0))
611 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
615 * Called with local interrupts disabled and the q_lock held. May not sleep.
617 static int nvme_submit_bio_queue(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
620 struct nvme_command
*cmnd
;
621 struct nvme_iod
*iod
;
622 enum dma_data_direction dma_dir
;
623 int cmdid
, length
, result
= -ENOMEM
;
626 int psegs
= bio_phys_segments(ns
->queue
, bio
);
628 if ((bio
->bi_rw
& REQ_FLUSH
) && psegs
) {
629 result
= nvme_submit_flush_data(nvmeq
, ns
);
634 iod
= nvme_alloc_iod(psegs
, bio
->bi_size
, GFP_ATOMIC
);
640 cmdid
= alloc_cmdid(nvmeq
, iod
, bio_completion
, NVME_IO_TIMEOUT
);
641 if (unlikely(cmdid
< 0))
644 if (bio
->bi_rw
& REQ_DISCARD
) {
645 result
= nvme_submit_discard(nvmeq
, ns
, bio
, iod
, cmdid
);
650 if ((bio
->bi_rw
& REQ_FLUSH
) && !psegs
)
651 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
654 if (bio
->bi_rw
& REQ_FUA
)
655 control
|= NVME_RW_FUA
;
656 if (bio
->bi_rw
& (REQ_FAILFAST_DEV
| REQ_RAHEAD
))
657 control
|= NVME_RW_LR
;
660 if (bio
->bi_rw
& REQ_RAHEAD
)
661 dsmgmt
|= NVME_RW_DSM_FREQ_PREFETCH
;
663 cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
665 memset(cmnd
, 0, sizeof(*cmnd
));
666 if (bio_data_dir(bio
)) {
667 cmnd
->rw
.opcode
= nvme_cmd_write
;
668 dma_dir
= DMA_TO_DEVICE
;
670 cmnd
->rw
.opcode
= nvme_cmd_read
;
671 dma_dir
= DMA_FROM_DEVICE
;
674 result
= nvme_map_bio(nvmeq
, iod
, bio
, dma_dir
, psegs
);
679 cmnd
->rw
.command_id
= cmdid
;
680 cmnd
->rw
.nsid
= cpu_to_le32(ns
->ns_id
);
681 length
= nvme_setup_prps(nvmeq
->dev
, &cmnd
->common
, iod
, length
,
683 cmnd
->rw
.slba
= cpu_to_le64(nvme_block_nr(ns
, bio
->bi_sector
));
684 cmnd
->rw
.length
= cpu_to_le16((length
>> ns
->lba_shift
) - 1);
685 cmnd
->rw
.control
= cpu_to_le16(control
);
686 cmnd
->rw
.dsmgmt
= cpu_to_le32(dsmgmt
);
688 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
690 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
695 free_cmdid(nvmeq
, cmdid
, NULL
);
697 nvme_free_iod(nvmeq
->dev
, iod
);
702 static void nvme_make_request(struct request_queue
*q
, struct bio
*bio
)
704 struct nvme_ns
*ns
= q
->queuedata
;
705 struct nvme_queue
*nvmeq
= get_nvmeq(ns
->dev
);
708 spin_lock_irq(&nvmeq
->q_lock
);
709 if (bio_list_empty(&nvmeq
->sq_cong
))
710 result
= nvme_submit_bio_queue(nvmeq
, ns
, bio
);
711 if (unlikely(result
)) {
712 if (bio_list_empty(&nvmeq
->sq_cong
))
713 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
714 bio_list_add(&nvmeq
->sq_cong
, bio
);
717 spin_unlock_irq(&nvmeq
->q_lock
);
721 static irqreturn_t
nvme_process_cq(struct nvme_queue
*nvmeq
)
725 head
= nvmeq
->cq_head
;
726 phase
= nvmeq
->cq_phase
;
730 nvme_completion_fn fn
;
731 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
732 if ((le16_to_cpu(cqe
.status
) & 1) != phase
)
734 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
735 if (++head
== nvmeq
->q_depth
) {
740 ctx
= free_cmdid(nvmeq
, cqe
.command_id
, &fn
);
741 fn(nvmeq
->dev
, ctx
, &cqe
);
744 /* If the controller ignores the cq head doorbell and continuously
745 * writes to the queue, it is theoretically possible to wrap around
746 * the queue twice and mistakenly return IRQ_NONE. Linux only
747 * requires that 0.1% of your interrupts are handled, so this isn't
750 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
753 writel(head
, nvmeq
->q_db
+ (1 << nvmeq
->dev
->db_stride
));
754 nvmeq
->cq_head
= head
;
755 nvmeq
->cq_phase
= phase
;
760 static irqreturn_t
nvme_irq(int irq
, void *data
)
763 struct nvme_queue
*nvmeq
= data
;
764 spin_lock(&nvmeq
->q_lock
);
765 result
= nvme_process_cq(nvmeq
);
766 spin_unlock(&nvmeq
->q_lock
);
770 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
772 struct nvme_queue
*nvmeq
= data
;
773 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
774 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
776 return IRQ_WAKE_THREAD
;
779 static void nvme_abort_command(struct nvme_queue
*nvmeq
, int cmdid
)
781 spin_lock_irq(&nvmeq
->q_lock
);
782 cancel_cmdid(nvmeq
, cmdid
, NULL
);
783 spin_unlock_irq(&nvmeq
->q_lock
);
786 struct sync_cmd_info
{
787 struct task_struct
*task
;
792 static void sync_completion(struct nvme_dev
*dev
, void *ctx
,
793 struct nvme_completion
*cqe
)
795 struct sync_cmd_info
*cmdinfo
= ctx
;
796 cmdinfo
->result
= le32_to_cpup(&cqe
->result
);
797 cmdinfo
->status
= le16_to_cpup(&cqe
->status
) >> 1;
798 wake_up_process(cmdinfo
->task
);
802 * Returns 0 on success. If the result is negative, it's a Linux error code;
803 * if the result is positive, it's an NVM Express status code
805 int nvme_submit_sync_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
,
806 u32
*result
, unsigned timeout
)
809 struct sync_cmd_info cmdinfo
;
811 cmdinfo
.task
= current
;
812 cmdinfo
.status
= -EINTR
;
814 cmdid
= alloc_cmdid_killable(nvmeq
, &cmdinfo
, sync_completion
,
818 cmd
->common
.command_id
= cmdid
;
820 set_current_state(TASK_KILLABLE
);
821 nvme_submit_cmd(nvmeq
, cmd
);
824 if (cmdinfo
.status
== -EINTR
) {
825 nvme_abort_command(nvmeq
, cmdid
);
830 *result
= cmdinfo
.result
;
832 return cmdinfo
.status
;
835 int nvme_submit_admin_cmd(struct nvme_dev
*dev
, struct nvme_command
*cmd
,
838 return nvme_submit_sync_cmd(dev
->queues
[0], cmd
, result
, ADMIN_TIMEOUT
);
841 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
844 struct nvme_command c
;
846 memset(&c
, 0, sizeof(c
));
847 c
.delete_queue
.opcode
= opcode
;
848 c
.delete_queue
.qid
= cpu_to_le16(id
);
850 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
856 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
857 struct nvme_queue
*nvmeq
)
860 struct nvme_command c
;
861 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
863 memset(&c
, 0, sizeof(c
));
864 c
.create_cq
.opcode
= nvme_admin_create_cq
;
865 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
866 c
.create_cq
.cqid
= cpu_to_le16(qid
);
867 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
868 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
869 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
871 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
877 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
878 struct nvme_queue
*nvmeq
)
881 struct nvme_command c
;
882 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
884 memset(&c
, 0, sizeof(c
));
885 c
.create_sq
.opcode
= nvme_admin_create_sq
;
886 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
887 c
.create_sq
.sqid
= cpu_to_le16(qid
);
888 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
889 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
890 c
.create_sq
.cqid
= cpu_to_le16(qid
);
892 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
898 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
900 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
903 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
905 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
908 int nvme_identify(struct nvme_dev
*dev
, unsigned nsid
, unsigned cns
,
911 struct nvme_command c
;
913 memset(&c
, 0, sizeof(c
));
914 c
.identify
.opcode
= nvme_admin_identify
;
915 c
.identify
.nsid
= cpu_to_le32(nsid
);
916 c
.identify
.prp1
= cpu_to_le64(dma_addr
);
917 c
.identify
.cns
= cpu_to_le32(cns
);
919 return nvme_submit_admin_cmd(dev
, &c
, NULL
);
922 int nvme_get_features(struct nvme_dev
*dev
, unsigned fid
, unsigned nsid
,
923 dma_addr_t dma_addr
, u32
*result
)
925 struct nvme_command c
;
927 memset(&c
, 0, sizeof(c
));
928 c
.features
.opcode
= nvme_admin_get_features
;
929 c
.features
.nsid
= cpu_to_le32(nsid
);
930 c
.features
.prp1
= cpu_to_le64(dma_addr
);
931 c
.features
.fid
= cpu_to_le32(fid
);
933 return nvme_submit_admin_cmd(dev
, &c
, result
);
936 int nvme_set_features(struct nvme_dev
*dev
, unsigned fid
, unsigned dword11
,
937 dma_addr_t dma_addr
, u32
*result
)
939 struct nvme_command c
;
941 memset(&c
, 0, sizeof(c
));
942 c
.features
.opcode
= nvme_admin_set_features
;
943 c
.features
.prp1
= cpu_to_le64(dma_addr
);
944 c
.features
.fid
= cpu_to_le32(fid
);
945 c
.features
.dword11
= cpu_to_le32(dword11
);
947 return nvme_submit_admin_cmd(dev
, &c
, result
);
951 * nvme_cancel_ios - Cancel outstanding I/Os
952 * @queue: The queue to cancel I/Os on
953 * @timeout: True to only cancel I/Os which have timed out
955 static void nvme_cancel_ios(struct nvme_queue
*nvmeq
, bool timeout
)
957 int depth
= nvmeq
->q_depth
- 1;
958 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
959 unsigned long now
= jiffies
;
962 for_each_set_bit(cmdid
, nvmeq
->cmdid_data
, depth
) {
964 nvme_completion_fn fn
;
965 static struct nvme_completion cqe
= {
966 .status
= cpu_to_le16(NVME_SC_ABORT_REQ
<< 1),
969 if (timeout
&& !time_after(now
, info
[cmdid
].timeout
))
971 dev_warn(nvmeq
->q_dmadev
, "Cancelling I/O %d\n", cmdid
);
972 ctx
= cancel_cmdid(nvmeq
, cmdid
, &fn
);
973 fn(nvmeq
->dev
, ctx
, &cqe
);
977 static void nvme_free_queue_mem(struct nvme_queue
*nvmeq
)
979 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
980 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
981 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
982 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
986 static void nvme_free_queue(struct nvme_dev
*dev
, int qid
)
988 struct nvme_queue
*nvmeq
= dev
->queues
[qid
];
989 int vector
= dev
->entry
[nvmeq
->cq_vector
].vector
;
991 spin_lock_irq(&nvmeq
->q_lock
);
992 nvme_cancel_ios(nvmeq
, false);
993 while (bio_list_peek(&nvmeq
->sq_cong
)) {
994 struct bio
*bio
= bio_list_pop(&nvmeq
->sq_cong
);
995 bio_endio(bio
, -EIO
);
997 spin_unlock_irq(&nvmeq
->q_lock
);
999 irq_set_affinity_hint(vector
, NULL
);
1000 free_irq(vector
, nvmeq
);
1002 /* Don't tell the adapter to delete the admin queue */
1004 adapter_delete_sq(dev
, qid
);
1005 adapter_delete_cq(dev
, qid
);
1008 nvme_free_queue_mem(nvmeq
);
1011 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1012 int depth
, int vector
)
1014 struct device
*dmadev
= &dev
->pci_dev
->dev
;
1015 unsigned extra
= DIV_ROUND_UP(depth
, 8) + (depth
*
1016 sizeof(struct nvme_cmd_info
));
1017 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
) + extra
, GFP_KERNEL
);
1021 nvmeq
->cqes
= dma_alloc_coherent(dmadev
, CQ_SIZE(depth
),
1022 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1025 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(depth
));
1027 nvmeq
->sq_cmds
= dma_alloc_coherent(dmadev
, SQ_SIZE(depth
),
1028 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1029 if (!nvmeq
->sq_cmds
)
1032 nvmeq
->q_dmadev
= dmadev
;
1034 spin_lock_init(&nvmeq
->q_lock
);
1036 nvmeq
->cq_phase
= 1;
1037 init_waitqueue_head(&nvmeq
->sq_full
);
1038 init_waitqueue_entry(&nvmeq
->sq_cong_wait
, nvme_thread
);
1039 bio_list_init(&nvmeq
->sq_cong
);
1040 nvmeq
->q_db
= &dev
->dbs
[qid
<< (dev
->db_stride
+ 1)];
1041 nvmeq
->q_depth
= depth
;
1042 nvmeq
->cq_vector
= vector
;
1047 dma_free_coherent(dmadev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1048 nvmeq
->cq_dma_addr
);
1054 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1057 if (use_threaded_interrupts
)
1058 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
1059 nvme_irq_check
, nvme_irq
,
1060 IRQF_DISABLED
| IRQF_SHARED
,
1062 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
1063 IRQF_DISABLED
| IRQF_SHARED
, name
, nvmeq
);
1066 static struct nvme_queue
*nvme_create_queue(struct nvme_dev
*dev
, int qid
,
1067 int cq_size
, int vector
)
1070 struct nvme_queue
*nvmeq
= nvme_alloc_queue(dev
, qid
, cq_size
, vector
);
1073 return ERR_PTR(-ENOMEM
);
1075 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1079 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1083 result
= queue_request_irq(dev
, nvmeq
, "nvme");
1090 adapter_delete_sq(dev
, qid
);
1092 adapter_delete_cq(dev
, qid
);
1094 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1095 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1096 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1097 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1099 return ERR_PTR(result
);
1102 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1107 unsigned long timeout
;
1108 struct nvme_queue
*nvmeq
;
1110 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
1112 nvmeq
= nvme_alloc_queue(dev
, 0, 64, 0);
1116 aqa
= nvmeq
->q_depth
- 1;
1119 dev
->ctrl_config
= NVME_CC_ENABLE
| NVME_CC_CSS_NVM
;
1120 dev
->ctrl_config
|= (PAGE_SHIFT
- 12) << NVME_CC_MPS_SHIFT
;
1121 dev
->ctrl_config
|= NVME_CC_ARB_RR
| NVME_CC_SHN_NONE
;
1122 dev
->ctrl_config
|= NVME_CC_IOSQES
| NVME_CC_IOCQES
;
1124 writel(0, &dev
->bar
->cc
);
1125 writel(aqa
, &dev
->bar
->aqa
);
1126 writeq(nvmeq
->sq_dma_addr
, &dev
->bar
->asq
);
1127 writeq(nvmeq
->cq_dma_addr
, &dev
->bar
->acq
);
1128 writel(dev
->ctrl_config
, &dev
->bar
->cc
);
1130 cap
= readq(&dev
->bar
->cap
);
1131 timeout
= ((NVME_CAP_TIMEOUT(cap
) + 1) * HZ
/ 2) + jiffies
;
1132 dev
->db_stride
= NVME_CAP_STRIDE(cap
);
1134 while (!result
&& !(readl(&dev
->bar
->csts
) & NVME_CSTS_RDY
)) {
1136 if (fatal_signal_pending(current
))
1138 if (time_after(jiffies
, timeout
)) {
1139 dev_err(&dev
->pci_dev
->dev
,
1140 "Device not ready; aborting initialisation\n");
1148 result
= queue_request_irq(dev
, nvmeq
, "nvme admin");
1152 dev
->queues
[0] = nvmeq
;
1156 nvme_free_queue_mem(nvmeq
);
1160 struct nvme_iod
*nvme_map_user_pages(struct nvme_dev
*dev
, int write
,
1161 unsigned long addr
, unsigned length
)
1163 int i
, err
, count
, nents
, offset
;
1164 struct scatterlist
*sg
;
1165 struct page
**pages
;
1166 struct nvme_iod
*iod
;
1169 return ERR_PTR(-EINVAL
);
1171 return ERR_PTR(-EINVAL
);
1173 offset
= offset_in_page(addr
);
1174 count
= DIV_ROUND_UP(offset
+ length
, PAGE_SIZE
);
1175 pages
= kcalloc(count
, sizeof(*pages
), GFP_KERNEL
);
1177 return ERR_PTR(-ENOMEM
);
1179 err
= get_user_pages_fast(addr
, count
, 1, pages
);
1186 iod
= nvme_alloc_iod(count
, length
, GFP_KERNEL
);
1188 sg_init_table(sg
, count
);
1189 for (i
= 0; i
< count
; i
++) {
1190 sg_set_page(&sg
[i
], pages
[i
],
1191 min_t(int, length
, PAGE_SIZE
- offset
), offset
);
1192 length
-= (PAGE_SIZE
- offset
);
1195 sg_mark_end(&sg
[i
- 1]);
1199 nents
= dma_map_sg(&dev
->pci_dev
->dev
, sg
, count
,
1200 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1210 for (i
= 0; i
< count
; i
++)
1213 return ERR_PTR(err
);
1216 void nvme_unmap_user_pages(struct nvme_dev
*dev
, int write
,
1217 struct nvme_iod
*iod
)
1221 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
1222 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1224 for (i
= 0; i
< iod
->nents
; i
++)
1225 put_page(sg_page(&iod
->sg
[i
]));
1228 static int nvme_submit_io(struct nvme_ns
*ns
, struct nvme_user_io __user
*uio
)
1230 struct nvme_dev
*dev
= ns
->dev
;
1231 struct nvme_queue
*nvmeq
;
1232 struct nvme_user_io io
;
1233 struct nvme_command c
;
1236 struct nvme_iod
*iod
;
1238 if (copy_from_user(&io
, uio
, sizeof(io
)))
1240 length
= (io
.nblocks
+ 1) << ns
->lba_shift
;
1242 switch (io
.opcode
) {
1243 case nvme_cmd_write
:
1245 case nvme_cmd_compare
:
1246 iod
= nvme_map_user_pages(dev
, io
.opcode
& 1, io
.addr
, length
);
1253 return PTR_ERR(iod
);
1255 memset(&c
, 0, sizeof(c
));
1256 c
.rw
.opcode
= io
.opcode
;
1257 c
.rw
.flags
= io
.flags
;
1258 c
.rw
.nsid
= cpu_to_le32(ns
->ns_id
);
1259 c
.rw
.slba
= cpu_to_le64(io
.slba
);
1260 c
.rw
.length
= cpu_to_le16(io
.nblocks
);
1261 c
.rw
.control
= cpu_to_le16(io
.control
);
1262 c
.rw
.dsmgmt
= cpu_to_le32(io
.dsmgmt
);
1263 c
.rw
.reftag
= cpu_to_le32(io
.reftag
);
1264 c
.rw
.apptag
= cpu_to_le16(io
.apptag
);
1265 c
.rw
.appmask
= cpu_to_le16(io
.appmask
);
1267 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
, GFP_KERNEL
);
1269 nvmeq
= get_nvmeq(dev
);
1271 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1272 * disabled. We may be preempted at any point, and be rescheduled
1273 * to a different CPU. That will cause cacheline bouncing, but no
1274 * additional races since q_lock already protects against other CPUs.
1277 if (length
!= (io
.nblocks
+ 1) << ns
->lba_shift
)
1280 status
= nvme_submit_sync_cmd(nvmeq
, &c
, NULL
, NVME_IO_TIMEOUT
);
1282 nvme_unmap_user_pages(dev
, io
.opcode
& 1, iod
);
1283 nvme_free_iod(dev
, iod
);
1287 static int nvme_user_admin_cmd(struct nvme_dev
*dev
,
1288 struct nvme_admin_cmd __user
*ucmd
)
1290 struct nvme_admin_cmd cmd
;
1291 struct nvme_command c
;
1293 struct nvme_iod
*uninitialized_var(iod
);
1295 if (!capable(CAP_SYS_ADMIN
))
1297 if (copy_from_user(&cmd
, ucmd
, sizeof(cmd
)))
1300 memset(&c
, 0, sizeof(c
));
1301 c
.common
.opcode
= cmd
.opcode
;
1302 c
.common
.flags
= cmd
.flags
;
1303 c
.common
.nsid
= cpu_to_le32(cmd
.nsid
);
1304 c
.common
.cdw2
[0] = cpu_to_le32(cmd
.cdw2
);
1305 c
.common
.cdw2
[1] = cpu_to_le32(cmd
.cdw3
);
1306 c
.common
.cdw10
[0] = cpu_to_le32(cmd
.cdw10
);
1307 c
.common
.cdw10
[1] = cpu_to_le32(cmd
.cdw11
);
1308 c
.common
.cdw10
[2] = cpu_to_le32(cmd
.cdw12
);
1309 c
.common
.cdw10
[3] = cpu_to_le32(cmd
.cdw13
);
1310 c
.common
.cdw10
[4] = cpu_to_le32(cmd
.cdw14
);
1311 c
.common
.cdw10
[5] = cpu_to_le32(cmd
.cdw15
);
1313 length
= cmd
.data_len
;
1315 iod
= nvme_map_user_pages(dev
, cmd
.opcode
& 1, cmd
.addr
,
1318 return PTR_ERR(iod
);
1319 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
,
1323 if (length
!= cmd
.data_len
)
1326 status
= nvme_submit_admin_cmd(dev
, &c
, &cmd
.result
);
1329 nvme_unmap_user_pages(dev
, cmd
.opcode
& 1, iod
);
1330 nvme_free_iod(dev
, iod
);
1333 if (!status
&& copy_to_user(&ucmd
->result
, &cmd
.result
,
1334 sizeof(cmd
.result
)))
1340 static int nvme_ioctl(struct block_device
*bdev
, fmode_t mode
, unsigned int cmd
,
1343 struct nvme_ns
*ns
= bdev
->bd_disk
->private_data
;
1348 case NVME_IOCTL_ADMIN_CMD
:
1349 return nvme_user_admin_cmd(ns
->dev
, (void __user
*)arg
);
1350 case NVME_IOCTL_SUBMIT_IO
:
1351 return nvme_submit_io(ns
, (void __user
*)arg
);
1352 case SG_GET_VERSION_NUM
:
1353 return nvme_sg_get_version_num((void __user
*)arg
);
1355 return nvme_sg_io(ns
, (void __user
*)arg
);
1361 static const struct block_device_operations nvme_fops
= {
1362 .owner
= THIS_MODULE
,
1363 .ioctl
= nvme_ioctl
,
1364 .compat_ioctl
= nvme_ioctl
,
1367 static void nvme_resubmit_bios(struct nvme_queue
*nvmeq
)
1369 while (bio_list_peek(&nvmeq
->sq_cong
)) {
1370 struct bio
*bio
= bio_list_pop(&nvmeq
->sq_cong
);
1371 struct nvme_ns
*ns
= bio
->bi_bdev
->bd_disk
->private_data
;
1373 if (bio_list_empty(&nvmeq
->sq_cong
))
1374 remove_wait_queue(&nvmeq
->sq_full
,
1375 &nvmeq
->sq_cong_wait
);
1376 if (nvme_submit_bio_queue(nvmeq
, ns
, bio
)) {
1377 if (bio_list_empty(&nvmeq
->sq_cong
))
1378 add_wait_queue(&nvmeq
->sq_full
,
1379 &nvmeq
->sq_cong_wait
);
1380 bio_list_add_head(&nvmeq
->sq_cong
, bio
);
1386 static int nvme_kthread(void *data
)
1388 struct nvme_dev
*dev
;
1390 while (!kthread_should_stop()) {
1391 set_current_state(TASK_INTERRUPTIBLE
);
1392 spin_lock(&dev_list_lock
);
1393 list_for_each_entry(dev
, &dev_list
, node
) {
1395 for (i
= 0; i
< dev
->queue_count
; i
++) {
1396 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1399 spin_lock_irq(&nvmeq
->q_lock
);
1400 if (nvme_process_cq(nvmeq
))
1401 printk("process_cq did something\n");
1402 nvme_cancel_ios(nvmeq
, true);
1403 nvme_resubmit_bios(nvmeq
);
1404 spin_unlock_irq(&nvmeq
->q_lock
);
1407 spin_unlock(&dev_list_lock
);
1408 schedule_timeout(round_jiffies_relative(HZ
));
1413 static DEFINE_IDA(nvme_index_ida
);
1415 static int nvme_get_ns_idx(void)
1420 if (!ida_pre_get(&nvme_index_ida
, GFP_KERNEL
))
1423 spin_lock(&dev_list_lock
);
1424 error
= ida_get_new(&nvme_index_ida
, &index
);
1425 spin_unlock(&dev_list_lock
);
1426 } while (error
== -EAGAIN
);
1433 static void nvme_put_ns_idx(int index
)
1435 spin_lock(&dev_list_lock
);
1436 ida_remove(&nvme_index_ida
, index
);
1437 spin_unlock(&dev_list_lock
);
1440 static void nvme_config_discard(struct nvme_ns
*ns
)
1442 u32 logical_block_size
= queue_logical_block_size(ns
->queue
);
1443 ns
->queue
->limits
.discard_zeroes_data
= 0;
1444 ns
->queue
->limits
.discard_alignment
= logical_block_size
;
1445 ns
->queue
->limits
.discard_granularity
= logical_block_size
;
1446 ns
->queue
->limits
.max_discard_sectors
= 0xffffffff;
1447 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD
, ns
->queue
);
1450 static struct nvme_ns
*nvme_alloc_ns(struct nvme_dev
*dev
, int nsid
,
1451 struct nvme_id_ns
*id
, struct nvme_lba_range_type
*rt
)
1454 struct gendisk
*disk
;
1457 if (rt
->attributes
& NVME_LBART_ATTRIB_HIDE
)
1460 ns
= kzalloc(sizeof(*ns
), GFP_KERNEL
);
1463 ns
->queue
= blk_alloc_queue(GFP_KERNEL
);
1466 ns
->queue
->queue_flags
= QUEUE_FLAG_DEFAULT
;
1467 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES
, ns
->queue
);
1468 queue_flag_set_unlocked(QUEUE_FLAG_NONROT
, ns
->queue
);
1469 blk_queue_make_request(ns
->queue
, nvme_make_request
);
1471 ns
->queue
->queuedata
= ns
;
1473 disk
= alloc_disk(NVME_MINORS
);
1475 goto out_free_queue
;
1478 lbaf
= id
->flbas
& 0xf;
1479 ns
->lba_shift
= id
->lbaf
[lbaf
].ds
;
1480 blk_queue_logical_block_size(ns
->queue
, 1 << ns
->lba_shift
);
1481 if (dev
->max_hw_sectors
)
1482 blk_queue_max_hw_sectors(ns
->queue
, dev
->max_hw_sectors
);
1484 disk
->major
= nvme_major
;
1485 disk
->minors
= NVME_MINORS
;
1486 disk
->first_minor
= NVME_MINORS
* nvme_get_ns_idx();
1487 disk
->fops
= &nvme_fops
;
1488 disk
->private_data
= ns
;
1489 disk
->queue
= ns
->queue
;
1490 disk
->driverfs_dev
= &dev
->pci_dev
->dev
;
1491 sprintf(disk
->disk_name
, "nvme%dn%d", dev
->instance
, nsid
);
1492 set_capacity(disk
, le64_to_cpup(&id
->nsze
) << (ns
->lba_shift
- 9));
1494 if (dev
->oncs
& NVME_CTRL_ONCS_DSM
)
1495 nvme_config_discard(ns
);
1500 blk_cleanup_queue(ns
->queue
);
1506 static void nvme_ns_free(struct nvme_ns
*ns
)
1508 int index
= ns
->disk
->first_minor
/ NVME_MINORS
;
1510 nvme_put_ns_idx(index
);
1511 blk_cleanup_queue(ns
->queue
);
1515 static int set_queue_count(struct nvme_dev
*dev
, int count
)
1519 u32 q_count
= (count
- 1) | ((count
- 1) << 16);
1521 status
= nvme_set_features(dev
, NVME_FEAT_NUM_QUEUES
, q_count
, 0,
1525 return min(result
& 0xffff, result
>> 16) + 1;
1528 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1530 int result
, cpu
, i
, nr_io_queues
, db_bar_size
, q_depth
;
1532 nr_io_queues
= num_online_cpus();
1533 result
= set_queue_count(dev
, nr_io_queues
);
1536 if (result
< nr_io_queues
)
1537 nr_io_queues
= result
;
1539 /* Deregister the admin queue's interrupt */
1540 free_irq(dev
->entry
[0].vector
, dev
->queues
[0]);
1542 db_bar_size
= 4096 + ((nr_io_queues
+ 1) << (dev
->db_stride
+ 3));
1543 if (db_bar_size
> 8192) {
1545 dev
->bar
= ioremap(pci_resource_start(dev
->pci_dev
, 0),
1547 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
1548 dev
->queues
[0]->q_db
= dev
->dbs
;
1551 for (i
= 0; i
< nr_io_queues
; i
++)
1552 dev
->entry
[i
].entry
= i
;
1554 result
= pci_enable_msix(dev
->pci_dev
, dev
->entry
,
1558 } else if (result
> 0) {
1559 nr_io_queues
= result
;
1567 result
= queue_request_irq(dev
, dev
->queues
[0], "nvme admin");
1568 /* XXX: handle failure here */
1570 cpu
= cpumask_first(cpu_online_mask
);
1571 for (i
= 0; i
< nr_io_queues
; i
++) {
1572 irq_set_affinity_hint(dev
->entry
[i
].vector
, get_cpu_mask(cpu
));
1573 cpu
= cpumask_next(cpu
, cpu_online_mask
);
1576 q_depth
= min_t(int, NVME_CAP_MQES(readq(&dev
->bar
->cap
)) + 1,
1578 for (i
= 0; i
< nr_io_queues
; i
++) {
1579 dev
->queues
[i
+ 1] = nvme_create_queue(dev
, i
+ 1, q_depth
, i
);
1580 if (IS_ERR(dev
->queues
[i
+ 1]))
1581 return PTR_ERR(dev
->queues
[i
+ 1]);
1585 for (; i
< num_possible_cpus(); i
++) {
1586 int target
= i
% rounddown_pow_of_two(dev
->queue_count
- 1);
1587 dev
->queues
[i
+ 1] = dev
->queues
[target
+ 1];
1593 static void nvme_free_queues(struct nvme_dev
*dev
)
1597 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
1598 nvme_free_queue(dev
, i
);
1602 * Return: error value if an error occurred setting up the queues or calling
1603 * Identify Device. 0 if these succeeded, even if adding some of the
1604 * namespaces failed. At the moment, these failures are silent. TBD which
1605 * failures should be reported.
1607 static int nvme_dev_add(struct nvme_dev
*dev
)
1611 struct nvme_id_ctrl
*ctrl
;
1612 struct nvme_id_ns
*id_ns
;
1614 dma_addr_t dma_addr
;
1616 res
= nvme_setup_io_queues(dev
);
1620 mem
= dma_alloc_coherent(&dev
->pci_dev
->dev
, 8192, &dma_addr
,
1625 res
= nvme_identify(dev
, 0, 1, dma_addr
);
1632 nn
= le32_to_cpup(&ctrl
->nn
);
1633 dev
->oncs
= le16_to_cpup(&ctrl
->oncs
);
1634 memcpy(dev
->serial
, ctrl
->sn
, sizeof(ctrl
->sn
));
1635 memcpy(dev
->model
, ctrl
->mn
, sizeof(ctrl
->mn
));
1636 memcpy(dev
->firmware_rev
, ctrl
->fr
, sizeof(ctrl
->fr
));
1638 int shift
= NVME_CAP_MPSMIN(readq(&dev
->bar
->cap
)) + 12;
1639 dev
->max_hw_sectors
= 1 << (ctrl
->mdts
+ shift
- 9);
1643 for (i
= 1; i
<= nn
; i
++) {
1644 res
= nvme_identify(dev
, i
, 0, dma_addr
);
1648 if (id_ns
->ncap
== 0)
1651 res
= nvme_get_features(dev
, NVME_FEAT_LBA_RANGE
, i
,
1652 dma_addr
+ 4096, NULL
);
1654 memset(mem
+ 4096, 0, 4096);
1656 ns
= nvme_alloc_ns(dev
, i
, mem
, mem
+ 4096);
1658 list_add_tail(&ns
->list
, &dev
->namespaces
);
1660 list_for_each_entry(ns
, &dev
->namespaces
, list
)
1665 dma_free_coherent(&dev
->pci_dev
->dev
, 8192, mem
, dma_addr
);
1669 static int nvme_dev_remove(struct nvme_dev
*dev
)
1671 struct nvme_ns
*ns
, *next
;
1673 spin_lock(&dev_list_lock
);
1674 list_del(&dev
->node
);
1675 spin_unlock(&dev_list_lock
);
1677 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1678 list_del(&ns
->list
);
1679 del_gendisk(ns
->disk
);
1683 nvme_free_queues(dev
);
1688 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1690 struct device
*dmadev
= &dev
->pci_dev
->dev
;
1691 dev
->prp_page_pool
= dma_pool_create("prp list page", dmadev
,
1692 PAGE_SIZE
, PAGE_SIZE
, 0);
1693 if (!dev
->prp_page_pool
)
1696 /* Optimisation for I/Os between 4k and 128k */
1697 dev
->prp_small_pool
= dma_pool_create("prp list 256", dmadev
,
1699 if (!dev
->prp_small_pool
) {
1700 dma_pool_destroy(dev
->prp_page_pool
);
1706 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1708 dma_pool_destroy(dev
->prp_page_pool
);
1709 dma_pool_destroy(dev
->prp_small_pool
);
1712 static DEFINE_IDA(nvme_instance_ida
);
1714 static int nvme_set_instance(struct nvme_dev
*dev
)
1716 int instance
, error
;
1719 if (!ida_pre_get(&nvme_instance_ida
, GFP_KERNEL
))
1722 spin_lock(&dev_list_lock
);
1723 error
= ida_get_new(&nvme_instance_ida
, &instance
);
1724 spin_unlock(&dev_list_lock
);
1725 } while (error
== -EAGAIN
);
1730 dev
->instance
= instance
;
1734 static void nvme_release_instance(struct nvme_dev
*dev
)
1736 spin_lock(&dev_list_lock
);
1737 ida_remove(&nvme_instance_ida
, dev
->instance
);
1738 spin_unlock(&dev_list_lock
);
1741 static void nvme_free_dev(struct kref
*kref
)
1743 struct nvme_dev
*dev
= container_of(kref
, struct nvme_dev
, kref
);
1744 nvme_dev_remove(dev
);
1745 pci_disable_msix(dev
->pci_dev
);
1747 nvme_release_instance(dev
);
1748 nvme_release_prp_pools(dev
);
1749 pci_disable_device(dev
->pci_dev
);
1750 pci_release_regions(dev
->pci_dev
);
1756 static int nvme_dev_open(struct inode
*inode
, struct file
*f
)
1758 struct nvme_dev
*dev
= container_of(f
->private_data
, struct nvme_dev
,
1760 kref_get(&dev
->kref
);
1761 f
->private_data
= dev
;
1765 static int nvme_dev_release(struct inode
*inode
, struct file
*f
)
1767 struct nvme_dev
*dev
= f
->private_data
;
1768 kref_put(&dev
->kref
, nvme_free_dev
);
1772 static long nvme_dev_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
1774 struct nvme_dev
*dev
= f
->private_data
;
1776 case NVME_IOCTL_ADMIN_CMD
:
1777 return nvme_user_admin_cmd(dev
, (void __user
*)arg
);
1783 static const struct file_operations nvme_dev_fops
= {
1784 .owner
= THIS_MODULE
,
1785 .open
= nvme_dev_open
,
1786 .release
= nvme_dev_release
,
1787 .unlocked_ioctl
= nvme_dev_ioctl
,
1788 .compat_ioctl
= nvme_dev_ioctl
,
1791 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1793 int bars
, result
= -ENOMEM
;
1794 struct nvme_dev
*dev
;
1796 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1799 dev
->entry
= kcalloc(num_possible_cpus(), sizeof(*dev
->entry
),
1803 dev
->queues
= kcalloc(num_possible_cpus() + 1, sizeof(void *),
1808 if (pci_enable_device_mem(pdev
))
1810 pci_set_master(pdev
);
1811 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1812 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1815 INIT_LIST_HEAD(&dev
->namespaces
);
1816 dev
->pci_dev
= pdev
;
1817 pci_set_drvdata(pdev
, dev
);
1818 dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1819 dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1820 result
= nvme_set_instance(dev
);
1824 dev
->entry
[0].vector
= pdev
->irq
;
1826 result
= nvme_setup_prp_pools(dev
);
1830 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1836 result
= nvme_configure_admin_queue(dev
);
1841 spin_lock(&dev_list_lock
);
1842 list_add(&dev
->node
, &dev_list
);
1843 spin_unlock(&dev_list_lock
);
1845 result
= nvme_dev_add(dev
);
1849 scnprintf(dev
->name
, sizeof(dev
->name
), "nvme%d", dev
->instance
);
1850 dev
->miscdev
.minor
= MISC_DYNAMIC_MINOR
;
1851 dev
->miscdev
.parent
= &pdev
->dev
;
1852 dev
->miscdev
.name
= dev
->name
;
1853 dev
->miscdev
.fops
= &nvme_dev_fops
;
1854 result
= misc_register(&dev
->miscdev
);
1858 kref_init(&dev
->kref
);
1862 nvme_dev_remove(dev
);
1864 spin_lock(&dev_list_lock
);
1865 list_del(&dev
->node
);
1866 spin_unlock(&dev_list_lock
);
1868 nvme_free_queues(dev
);
1872 pci_disable_msix(pdev
);
1873 nvme_release_instance(dev
);
1874 nvme_release_prp_pools(dev
);
1876 pci_disable_device(pdev
);
1877 pci_release_regions(pdev
);
1885 static void nvme_remove(struct pci_dev
*pdev
)
1887 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
1888 misc_deregister(&dev
->miscdev
);
1889 kref_put(&dev
->kref
, nvme_free_dev
);
1892 /* These functions are yet to be implemented */
1893 #define nvme_error_detected NULL
1894 #define nvme_dump_registers NULL
1895 #define nvme_link_reset NULL
1896 #define nvme_slot_reset NULL
1897 #define nvme_error_resume NULL
1898 #define nvme_suspend NULL
1899 #define nvme_resume NULL
1901 static const struct pci_error_handlers nvme_err_handler
= {
1902 .error_detected
= nvme_error_detected
,
1903 .mmio_enabled
= nvme_dump_registers
,
1904 .link_reset
= nvme_link_reset
,
1905 .slot_reset
= nvme_slot_reset
,
1906 .resume
= nvme_error_resume
,
1909 /* Move to pci_ids.h later */
1910 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1912 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table
) = {
1913 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
1916 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
1918 static struct pci_driver nvme_driver
= {
1920 .id_table
= nvme_id_table
,
1921 .probe
= nvme_probe
,
1922 .remove
= nvme_remove
,
1923 .suspend
= nvme_suspend
,
1924 .resume
= nvme_resume
,
1925 .err_handler
= &nvme_err_handler
,
1928 static int __init
nvme_init(void)
1932 nvme_thread
= kthread_run(nvme_kthread
, NULL
, "nvme");
1933 if (IS_ERR(nvme_thread
))
1934 return PTR_ERR(nvme_thread
);
1936 result
= register_blkdev(nvme_major
, "nvme");
1939 else if (result
> 0)
1940 nvme_major
= result
;
1942 result
= pci_register_driver(&nvme_driver
);
1944 goto unregister_blkdev
;
1948 unregister_blkdev(nvme_major
, "nvme");
1950 kthread_stop(nvme_thread
);
1954 static void __exit
nvme_exit(void)
1956 pci_unregister_driver(&nvme_driver
);
1957 unregister_blkdev(nvme_major
, "nvme");
1958 kthread_stop(nvme_thread
);
1961 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1962 MODULE_LICENSE("GPL");
1963 MODULE_VERSION("0.8");
1964 module_init(nvme_init
);
1965 module_exit(nvme_exit
);