NVMe: Start and stop h/w queues on reset
[deliverable/linux.git] / drivers / block / nvme-core.c
1 /*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/nvme.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
22 #include <linux/fs.h>
23 #include <linux/genhd.h>
24 #include <linux/hdreg.h>
25 #include <linux/idr.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/kdev_t.h>
30 #include <linux/kthread.h>
31 #include <linux/kernel.h>
32 #include <linux/mm.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/types.h>
41 #include <scsi/sg.h>
42 #include <asm-generic/io-64-nonatomic-lo-hi.h>
43
44 #define NVME_Q_DEPTH 1024
45 #define NVME_AQ_DEPTH 64
46 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
48 #define ADMIN_TIMEOUT (admin_timeout * HZ)
49 #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
50 #define IOD_TIMEOUT (retry_time * HZ)
51
52 static unsigned char admin_timeout = 60;
53 module_param(admin_timeout, byte, 0644);
54 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
55
56 unsigned char nvme_io_timeout = 30;
57 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
58 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
59
60 static unsigned char retry_time = 30;
61 module_param(retry_time, byte, 0644);
62 MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
63
64 static unsigned char shutdown_timeout = 5;
65 module_param(shutdown_timeout, byte, 0644);
66 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
67
68 static int nvme_major;
69 module_param(nvme_major, int, 0);
70
71 static int use_threaded_interrupts;
72 module_param(use_threaded_interrupts, int, 0);
73
74 static DEFINE_SPINLOCK(dev_list_lock);
75 static LIST_HEAD(dev_list);
76 static struct task_struct *nvme_thread;
77 static struct workqueue_struct *nvme_workq;
78 static wait_queue_head_t nvme_kthread_wait;
79 static struct notifier_block nvme_nb;
80
81 static void nvme_reset_failed_dev(struct work_struct *ws);
82 static int nvme_process_cq(struct nvme_queue *nvmeq);
83
84 struct async_cmd_info {
85 struct kthread_work work;
86 struct kthread_worker *worker;
87 struct request *req;
88 u32 result;
89 int status;
90 void *ctx;
91 };
92
93 /*
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
96 */
97 struct nvme_queue {
98 struct llist_node node;
99 struct device *q_dmadev;
100 struct nvme_dev *dev;
101 char irqname[24]; /* nvme4294967295-65535\0 */
102 spinlock_t q_lock;
103 struct nvme_command *sq_cmds;
104 volatile struct nvme_completion *cqes;
105 dma_addr_t sq_dma_addr;
106 dma_addr_t cq_dma_addr;
107 u32 __iomem *q_db;
108 u16 q_depth;
109 u16 cq_vector;
110 u16 sq_head;
111 u16 sq_tail;
112 u16 cq_head;
113 u16 qid;
114 u8 cq_phase;
115 u8 cqe_seen;
116 struct async_cmd_info cmdinfo;
117 struct blk_mq_hw_ctx *hctx;
118 };
119
120 /*
121 * Check we didin't inadvertently grow the command struct
122 */
123 static inline void _nvme_check_size(void)
124 {
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
137 }
138
139 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
140 struct nvme_completion *);
141
142 struct nvme_cmd_info {
143 nvme_completion_fn fn;
144 void *ctx;
145 int aborted;
146 struct nvme_queue *nvmeq;
147 };
148
149 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
150 unsigned int hctx_idx)
151 {
152 struct nvme_dev *dev = data;
153 struct nvme_queue *nvmeq = dev->queues[0];
154
155 WARN_ON(nvmeq->hctx);
156 nvmeq->hctx = hctx;
157 hctx->driver_data = nvmeq;
158 return 0;
159 }
160
161 static int nvme_admin_init_request(void *data, struct request *req,
162 unsigned int hctx_idx, unsigned int rq_idx,
163 unsigned int numa_node)
164 {
165 struct nvme_dev *dev = data;
166 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
167 struct nvme_queue *nvmeq = dev->queues[0];
168
169 BUG_ON(!nvmeq);
170 cmd->nvmeq = nvmeq;
171 return 0;
172 }
173
174 static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
175 {
176 struct nvme_queue *nvmeq = hctx->driver_data;
177
178 nvmeq->hctx = NULL;
179 }
180
181 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
182 unsigned int hctx_idx)
183 {
184 struct nvme_dev *dev = data;
185 struct nvme_queue *nvmeq = dev->queues[
186 (hctx_idx % dev->queue_count) + 1];
187
188 if (!nvmeq->hctx)
189 nvmeq->hctx = hctx;
190
191 /* nvmeq queues are shared between namespaces. We assume here that
192 * blk-mq map the tags so they match up with the nvme queue tags. */
193 WARN_ON(nvmeq->hctx->tags != hctx->tags);
194
195 hctx->driver_data = nvmeq;
196 return 0;
197 }
198
199 static int nvme_init_request(void *data, struct request *req,
200 unsigned int hctx_idx, unsigned int rq_idx,
201 unsigned int numa_node)
202 {
203 struct nvme_dev *dev = data;
204 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
205 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
206
207 BUG_ON(!nvmeq);
208 cmd->nvmeq = nvmeq;
209 return 0;
210 }
211
212 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
213 nvme_completion_fn handler)
214 {
215 cmd->fn = handler;
216 cmd->ctx = ctx;
217 cmd->aborted = 0;
218 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
219 }
220
221 /* Special values must be less than 0x1000 */
222 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
223 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
224 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
225 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
226
227 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
228 struct nvme_completion *cqe)
229 {
230 if (ctx == CMD_CTX_CANCELLED)
231 return;
232 if (ctx == CMD_CTX_COMPLETED) {
233 dev_warn(nvmeq->q_dmadev,
234 "completed id %d twice on queue %d\n",
235 cqe->command_id, le16_to_cpup(&cqe->sq_id));
236 return;
237 }
238 if (ctx == CMD_CTX_INVALID) {
239 dev_warn(nvmeq->q_dmadev,
240 "invalid id %d completed on queue %d\n",
241 cqe->command_id, le16_to_cpup(&cqe->sq_id));
242 return;
243 }
244 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
245 }
246
247 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
248 {
249 void *ctx;
250
251 if (fn)
252 *fn = cmd->fn;
253 ctx = cmd->ctx;
254 cmd->fn = special_completion;
255 cmd->ctx = CMD_CTX_CANCELLED;
256 return ctx;
257 }
258
259 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
260 struct nvme_completion *cqe)
261 {
262 struct request *req = ctx;
263
264 u32 result = le32_to_cpup(&cqe->result);
265 u16 status = le16_to_cpup(&cqe->status) >> 1;
266
267 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
268 ++nvmeq->dev->event_limit;
269 if (status == NVME_SC_SUCCESS)
270 dev_warn(nvmeq->q_dmadev,
271 "async event result %08x\n", result);
272
273 blk_mq_free_hctx_request(nvmeq->hctx, req);
274 }
275
276 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
277 struct nvme_completion *cqe)
278 {
279 struct request *req = ctx;
280
281 u16 status = le16_to_cpup(&cqe->status) >> 1;
282 u32 result = le32_to_cpup(&cqe->result);
283
284 blk_mq_free_hctx_request(nvmeq->hctx, req);
285
286 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
287 ++nvmeq->dev->abort_limit;
288 }
289
290 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
291 struct nvme_completion *cqe)
292 {
293 struct async_cmd_info *cmdinfo = ctx;
294 cmdinfo->result = le32_to_cpup(&cqe->result);
295 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
296 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
297 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
298 }
299
300 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
301 unsigned int tag)
302 {
303 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
304 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
305
306 return blk_mq_rq_to_pdu(req);
307 }
308
309 /*
310 * Called with local interrupts disabled and the q_lock held. May not sleep.
311 */
312 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
313 nvme_completion_fn *fn)
314 {
315 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
316 void *ctx;
317 if (tag >= nvmeq->q_depth) {
318 *fn = special_completion;
319 return CMD_CTX_INVALID;
320 }
321 if (fn)
322 *fn = cmd->fn;
323 ctx = cmd->ctx;
324 cmd->fn = special_completion;
325 cmd->ctx = CMD_CTX_COMPLETED;
326 return ctx;
327 }
328
329 /**
330 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
331 * @nvmeq: The queue to use
332 * @cmd: The command to send
333 *
334 * Safe to use from interrupt context
335 */
336 static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
337 {
338 u16 tail = nvmeq->sq_tail;
339
340 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
341 if (++tail == nvmeq->q_depth)
342 tail = 0;
343 writel(tail, nvmeq->q_db);
344 nvmeq->sq_tail = tail;
345
346 return 0;
347 }
348
349 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
350 {
351 unsigned long flags;
352 int ret;
353 spin_lock_irqsave(&nvmeq->q_lock, flags);
354 ret = __nvme_submit_cmd(nvmeq, cmd);
355 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
356 return ret;
357 }
358
359 static __le64 **iod_list(struct nvme_iod *iod)
360 {
361 return ((void *)iod) + iod->offset;
362 }
363
364 /*
365 * Will slightly overestimate the number of pages needed. This is OK
366 * as it only leads to a small amount of wasted memory for the lifetime of
367 * the I/O.
368 */
369 static int nvme_npages(unsigned size, struct nvme_dev *dev)
370 {
371 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
372 return DIV_ROUND_UP(8 * nprps, dev->page_size - 8);
373 }
374
375 static struct nvme_iod *
376 nvme_alloc_iod(unsigned nseg, unsigned nbytes, struct nvme_dev *dev, gfp_t gfp)
377 {
378 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
379 sizeof(__le64 *) * nvme_npages(nbytes, dev) +
380 sizeof(struct scatterlist) * nseg, gfp);
381
382 if (iod) {
383 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
384 iod->npages = -1;
385 iod->length = nbytes;
386 iod->nents = 0;
387 iod->first_dma = 0ULL;
388 }
389
390 return iod;
391 }
392
393 void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
394 {
395 const int last_prp = dev->page_size / 8 - 1;
396 int i;
397 __le64 **list = iod_list(iod);
398 dma_addr_t prp_dma = iod->first_dma;
399
400 if (iod->npages == 0)
401 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
402 for (i = 0; i < iod->npages; i++) {
403 __le64 *prp_list = list[i];
404 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
405 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
406 prp_dma = next_prp_dma;
407 }
408 kfree(iod);
409 }
410
411 static int nvme_error_status(u16 status)
412 {
413 switch (status & 0x7ff) {
414 case NVME_SC_SUCCESS:
415 return 0;
416 case NVME_SC_CAP_EXCEEDED:
417 return -ENOSPC;
418 default:
419 return -EIO;
420 }
421 }
422
423 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
424 struct nvme_completion *cqe)
425 {
426 struct nvme_iod *iod = ctx;
427 struct request *req = iod->private;
428 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
429
430 u16 status = le16_to_cpup(&cqe->status) >> 1;
431
432 if (unlikely(status)) {
433 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
434 && (jiffies - req->start_time) < req->timeout) {
435 unsigned long flags;
436
437 blk_mq_requeue_request(req);
438 spin_lock_irqsave(req->q->queue_lock, flags);
439 if (!blk_queue_stopped(req->q))
440 blk_mq_kick_requeue_list(req->q);
441 spin_unlock_irqrestore(req->q->queue_lock, flags);
442 return;
443 }
444 req->errors = nvme_error_status(status);
445 } else
446 req->errors = 0;
447
448 if (cmd_rq->aborted)
449 dev_warn(&nvmeq->dev->pci_dev->dev,
450 "completing aborted command with status:%04x\n",
451 status);
452
453 if (iod->nents)
454 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
455 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
456 nvme_free_iod(nvmeq->dev, iod);
457
458 blk_mq_complete_request(req);
459 }
460
461 /* length is in bytes. gfp flags indicates whether we may sleep. */
462 int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
463 gfp_t gfp)
464 {
465 struct dma_pool *pool;
466 int length = total_len;
467 struct scatterlist *sg = iod->sg;
468 int dma_len = sg_dma_len(sg);
469 u64 dma_addr = sg_dma_address(sg);
470 int offset = offset_in_page(dma_addr);
471 __le64 *prp_list;
472 __le64 **list = iod_list(iod);
473 dma_addr_t prp_dma;
474 int nprps, i;
475 u32 page_size = dev->page_size;
476
477 length -= (page_size - offset);
478 if (length <= 0)
479 return total_len;
480
481 dma_len -= (page_size - offset);
482 if (dma_len) {
483 dma_addr += (page_size - offset);
484 } else {
485 sg = sg_next(sg);
486 dma_addr = sg_dma_address(sg);
487 dma_len = sg_dma_len(sg);
488 }
489
490 if (length <= page_size) {
491 iod->first_dma = dma_addr;
492 return total_len;
493 }
494
495 nprps = DIV_ROUND_UP(length, page_size);
496 if (nprps <= (256 / 8)) {
497 pool = dev->prp_small_pool;
498 iod->npages = 0;
499 } else {
500 pool = dev->prp_page_pool;
501 iod->npages = 1;
502 }
503
504 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
505 if (!prp_list) {
506 iod->first_dma = dma_addr;
507 iod->npages = -1;
508 return (total_len - length) + page_size;
509 }
510 list[0] = prp_list;
511 iod->first_dma = prp_dma;
512 i = 0;
513 for (;;) {
514 if (i == page_size >> 3) {
515 __le64 *old_prp_list = prp_list;
516 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
517 if (!prp_list)
518 return total_len - length;
519 list[iod->npages++] = prp_list;
520 prp_list[0] = old_prp_list[i - 1];
521 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
522 i = 1;
523 }
524 prp_list[i++] = cpu_to_le64(dma_addr);
525 dma_len -= page_size;
526 dma_addr += page_size;
527 length -= page_size;
528 if (length <= 0)
529 break;
530 if (dma_len > 0)
531 continue;
532 BUG_ON(dma_len < 0);
533 sg = sg_next(sg);
534 dma_addr = sg_dma_address(sg);
535 dma_len = sg_dma_len(sg);
536 }
537
538 return total_len;
539 }
540
541 /*
542 * We reuse the small pool to allocate the 16-byte range here as it is not
543 * worth having a special pool for these or additional cases to handle freeing
544 * the iod.
545 */
546 static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
547 struct request *req, struct nvme_iod *iod)
548 {
549 struct nvme_dsm_range *range =
550 (struct nvme_dsm_range *)iod_list(iod)[0];
551 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
552
553 range->cattr = cpu_to_le32(0);
554 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
555 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
556
557 memset(cmnd, 0, sizeof(*cmnd));
558 cmnd->dsm.opcode = nvme_cmd_dsm;
559 cmnd->dsm.command_id = req->tag;
560 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
561 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
562 cmnd->dsm.nr = 0;
563 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
564
565 if (++nvmeq->sq_tail == nvmeq->q_depth)
566 nvmeq->sq_tail = 0;
567 writel(nvmeq->sq_tail, nvmeq->q_db);
568 }
569
570 static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
571 int cmdid)
572 {
573 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
574
575 memset(cmnd, 0, sizeof(*cmnd));
576 cmnd->common.opcode = nvme_cmd_flush;
577 cmnd->common.command_id = cmdid;
578 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
579
580 if (++nvmeq->sq_tail == nvmeq->q_depth)
581 nvmeq->sq_tail = 0;
582 writel(nvmeq->sq_tail, nvmeq->q_db);
583 }
584
585 static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
586 struct nvme_ns *ns)
587 {
588 struct request *req = iod->private;
589 struct nvme_command *cmnd;
590 u16 control = 0;
591 u32 dsmgmt = 0;
592
593 if (req->cmd_flags & REQ_FUA)
594 control |= NVME_RW_FUA;
595 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
596 control |= NVME_RW_LR;
597
598 if (req->cmd_flags & REQ_RAHEAD)
599 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
600
601 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
602 memset(cmnd, 0, sizeof(*cmnd));
603
604 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
605 cmnd->rw.command_id = req->tag;
606 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
607 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
608 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
609 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
610 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
611 cmnd->rw.control = cpu_to_le16(control);
612 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
613
614 if (++nvmeq->sq_tail == nvmeq->q_depth)
615 nvmeq->sq_tail = 0;
616 writel(nvmeq->sq_tail, nvmeq->q_db);
617
618 return 0;
619 }
620
621 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
622 const struct blk_mq_queue_data *bd)
623 {
624 struct nvme_ns *ns = hctx->queue->queuedata;
625 struct nvme_queue *nvmeq = hctx->driver_data;
626 struct request *req = bd->rq;
627 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
628 struct nvme_iod *iod;
629 int psegs = req->nr_phys_segments;
630 enum dma_data_direction dma_dir;
631 unsigned size = !(req->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(req) :
632 sizeof(struct nvme_dsm_range);
633
634 iod = nvme_alloc_iod(psegs, size, ns->dev, GFP_ATOMIC);
635 if (!iod)
636 return BLK_MQ_RQ_QUEUE_BUSY;
637
638 iod->private = req;
639
640 if (req->cmd_flags & REQ_DISCARD) {
641 void *range;
642 /*
643 * We reuse the small pool to allocate the 16-byte range here
644 * as it is not worth having a special pool for these or
645 * additional cases to handle freeing the iod.
646 */
647 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
648 GFP_ATOMIC,
649 &iod->first_dma);
650 if (!range)
651 goto retry_cmd;
652 iod_list(iod)[0] = (__le64 *)range;
653 iod->npages = 0;
654 } else if (psegs) {
655 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
656
657 sg_init_table(iod->sg, psegs);
658 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
659 if (!iod->nents)
660 goto error_cmd;
661
662 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
663 goto retry_cmd;
664
665 if (blk_rq_bytes(req) !=
666 nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
667 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
668 iod->nents, dma_dir);
669 goto retry_cmd;
670 }
671 }
672
673 nvme_set_info(cmd, iod, req_completion);
674 spin_lock_irq(&nvmeq->q_lock);
675 if (req->cmd_flags & REQ_DISCARD)
676 nvme_submit_discard(nvmeq, ns, req, iod);
677 else if (req->cmd_flags & REQ_FLUSH)
678 nvme_submit_flush(nvmeq, ns, req->tag);
679 else
680 nvme_submit_iod(nvmeq, iod, ns);
681
682 nvme_process_cq(nvmeq);
683 spin_unlock_irq(&nvmeq->q_lock);
684 return BLK_MQ_RQ_QUEUE_OK;
685
686 error_cmd:
687 nvme_free_iod(nvmeq->dev, iod);
688 return BLK_MQ_RQ_QUEUE_ERROR;
689 retry_cmd:
690 nvme_free_iod(nvmeq->dev, iod);
691 return BLK_MQ_RQ_QUEUE_BUSY;
692 }
693
694 static int nvme_process_cq(struct nvme_queue *nvmeq)
695 {
696 u16 head, phase;
697
698 head = nvmeq->cq_head;
699 phase = nvmeq->cq_phase;
700
701 for (;;) {
702 void *ctx;
703 nvme_completion_fn fn;
704 struct nvme_completion cqe = nvmeq->cqes[head];
705 if ((le16_to_cpu(cqe.status) & 1) != phase)
706 break;
707 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
708 if (++head == nvmeq->q_depth) {
709 head = 0;
710 phase = !phase;
711 }
712 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
713 fn(nvmeq, ctx, &cqe);
714 }
715
716 /* If the controller ignores the cq head doorbell and continuously
717 * writes to the queue, it is theoretically possible to wrap around
718 * the queue twice and mistakenly return IRQ_NONE. Linux only
719 * requires that 0.1% of your interrupts are handled, so this isn't
720 * a big problem.
721 */
722 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
723 return 0;
724
725 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
726 nvmeq->cq_head = head;
727 nvmeq->cq_phase = phase;
728
729 nvmeq->cqe_seen = 1;
730 return 1;
731 }
732
733 /* Admin queue isn't initialized as a request queue. If at some point this
734 * happens anyway, make sure to notify the user */
735 static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
736 const struct blk_mq_queue_data *bd)
737 {
738 WARN_ON_ONCE(1);
739 return BLK_MQ_RQ_QUEUE_ERROR;
740 }
741
742 static irqreturn_t nvme_irq(int irq, void *data)
743 {
744 irqreturn_t result;
745 struct nvme_queue *nvmeq = data;
746 spin_lock(&nvmeq->q_lock);
747 nvme_process_cq(nvmeq);
748 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
749 nvmeq->cqe_seen = 0;
750 spin_unlock(&nvmeq->q_lock);
751 return result;
752 }
753
754 static irqreturn_t nvme_irq_check(int irq, void *data)
755 {
756 struct nvme_queue *nvmeq = data;
757 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
758 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
759 return IRQ_NONE;
760 return IRQ_WAKE_THREAD;
761 }
762
763 static void nvme_abort_cmd_info(struct nvme_queue *nvmeq, struct nvme_cmd_info *
764 cmd_info)
765 {
766 spin_lock_irq(&nvmeq->q_lock);
767 cancel_cmd_info(cmd_info, NULL);
768 spin_unlock_irq(&nvmeq->q_lock);
769 }
770
771 struct sync_cmd_info {
772 struct task_struct *task;
773 u32 result;
774 int status;
775 };
776
777 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
778 struct nvme_completion *cqe)
779 {
780 struct sync_cmd_info *cmdinfo = ctx;
781 cmdinfo->result = le32_to_cpup(&cqe->result);
782 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
783 wake_up_process(cmdinfo->task);
784 }
785
786 /*
787 * Returns 0 on success. If the result is negative, it's a Linux error code;
788 * if the result is positive, it's an NVM Express status code
789 */
790 static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
791 u32 *result, unsigned timeout)
792 {
793 int ret;
794 struct sync_cmd_info cmdinfo;
795 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
796 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
797
798 cmdinfo.task = current;
799 cmdinfo.status = -EINTR;
800
801 cmd->common.command_id = req->tag;
802
803 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
804
805 set_current_state(TASK_KILLABLE);
806 ret = nvme_submit_cmd(nvmeq, cmd);
807 if (ret) {
808 nvme_finish_cmd(nvmeq, req->tag, NULL);
809 set_current_state(TASK_RUNNING);
810 }
811 ret = schedule_timeout(timeout);
812
813 /*
814 * Ensure that sync_completion has either run, or that it will
815 * never run.
816 */
817 nvme_abort_cmd_info(nvmeq, blk_mq_rq_to_pdu(req));
818
819 /*
820 * We never got the completion
821 */
822 if (cmdinfo.status == -EINTR)
823 return -EINTR;
824
825 if (result)
826 *result = cmdinfo.result;
827
828 return cmdinfo.status;
829 }
830
831 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
832 {
833 struct nvme_queue *nvmeq = dev->queues[0];
834 struct nvme_command c;
835 struct nvme_cmd_info *cmd_info;
836 struct request *req;
837
838 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false);
839 if (IS_ERR(req))
840 return PTR_ERR(req);
841
842 req->cmd_flags |= REQ_NO_TIMEOUT;
843 cmd_info = blk_mq_rq_to_pdu(req);
844 nvme_set_info(cmd_info, req, async_req_completion);
845
846 memset(&c, 0, sizeof(c));
847 c.common.opcode = nvme_admin_async_event;
848 c.common.command_id = req->tag;
849
850 return __nvme_submit_cmd(nvmeq, &c);
851 }
852
853 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
854 struct nvme_command *cmd,
855 struct async_cmd_info *cmdinfo, unsigned timeout)
856 {
857 struct nvme_queue *nvmeq = dev->queues[0];
858 struct request *req;
859 struct nvme_cmd_info *cmd_rq;
860
861 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
862 if (IS_ERR(req))
863 return PTR_ERR(req);
864
865 req->timeout = timeout;
866 cmd_rq = blk_mq_rq_to_pdu(req);
867 cmdinfo->req = req;
868 nvme_set_info(cmd_rq, cmdinfo, async_completion);
869 cmdinfo->status = -EINTR;
870
871 cmd->common.command_id = req->tag;
872
873 return nvme_submit_cmd(nvmeq, cmd);
874 }
875
876 static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
877 u32 *result, unsigned timeout)
878 {
879 int res;
880 struct request *req;
881
882 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
883 if (IS_ERR(req))
884 return PTR_ERR(req);
885 res = nvme_submit_sync_cmd(req, cmd, result, timeout);
886 blk_mq_free_request(req);
887 return res;
888 }
889
890 int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
891 u32 *result)
892 {
893 return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
894 }
895
896 int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
897 struct nvme_command *cmd, u32 *result)
898 {
899 int res;
900 struct request *req;
901
902 req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
903 false);
904 if (IS_ERR(req))
905 return PTR_ERR(req);
906 res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
907 blk_mq_free_request(req);
908 return res;
909 }
910
911 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
912 {
913 struct nvme_command c;
914
915 memset(&c, 0, sizeof(c));
916 c.delete_queue.opcode = opcode;
917 c.delete_queue.qid = cpu_to_le16(id);
918
919 return nvme_submit_admin_cmd(dev, &c, NULL);
920 }
921
922 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
923 struct nvme_queue *nvmeq)
924 {
925 struct nvme_command c;
926 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
927
928 memset(&c, 0, sizeof(c));
929 c.create_cq.opcode = nvme_admin_create_cq;
930 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
931 c.create_cq.cqid = cpu_to_le16(qid);
932 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
933 c.create_cq.cq_flags = cpu_to_le16(flags);
934 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
935
936 return nvme_submit_admin_cmd(dev, &c, NULL);
937 }
938
939 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
940 struct nvme_queue *nvmeq)
941 {
942 struct nvme_command c;
943 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
944
945 memset(&c, 0, sizeof(c));
946 c.create_sq.opcode = nvme_admin_create_sq;
947 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
948 c.create_sq.sqid = cpu_to_le16(qid);
949 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
950 c.create_sq.sq_flags = cpu_to_le16(flags);
951 c.create_sq.cqid = cpu_to_le16(qid);
952
953 return nvme_submit_admin_cmd(dev, &c, NULL);
954 }
955
956 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
957 {
958 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
959 }
960
961 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
962 {
963 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
964 }
965
966 int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
967 dma_addr_t dma_addr)
968 {
969 struct nvme_command c;
970
971 memset(&c, 0, sizeof(c));
972 c.identify.opcode = nvme_admin_identify;
973 c.identify.nsid = cpu_to_le32(nsid);
974 c.identify.prp1 = cpu_to_le64(dma_addr);
975 c.identify.cns = cpu_to_le32(cns);
976
977 return nvme_submit_admin_cmd(dev, &c, NULL);
978 }
979
980 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
981 dma_addr_t dma_addr, u32 *result)
982 {
983 struct nvme_command c;
984
985 memset(&c, 0, sizeof(c));
986 c.features.opcode = nvme_admin_get_features;
987 c.features.nsid = cpu_to_le32(nsid);
988 c.features.prp1 = cpu_to_le64(dma_addr);
989 c.features.fid = cpu_to_le32(fid);
990
991 return nvme_submit_admin_cmd(dev, &c, result);
992 }
993
994 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
995 dma_addr_t dma_addr, u32 *result)
996 {
997 struct nvme_command c;
998
999 memset(&c, 0, sizeof(c));
1000 c.features.opcode = nvme_admin_set_features;
1001 c.features.prp1 = cpu_to_le64(dma_addr);
1002 c.features.fid = cpu_to_le32(fid);
1003 c.features.dword11 = cpu_to_le32(dword11);
1004
1005 return nvme_submit_admin_cmd(dev, &c, result);
1006 }
1007
1008 /**
1009 * nvme_abort_req - Attempt aborting a request
1010 *
1011 * Schedule controller reset if the command was already aborted once before and
1012 * still hasn't been returned to the driver, or if this is the admin queue.
1013 */
1014 static void nvme_abort_req(struct request *req)
1015 {
1016 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1017 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1018 struct nvme_dev *dev = nvmeq->dev;
1019 struct request *abort_req;
1020 struct nvme_cmd_info *abort_cmd;
1021 struct nvme_command cmd;
1022
1023 if (!nvmeq->qid || cmd_rq->aborted) {
1024 if (work_busy(&dev->reset_work))
1025 return;
1026 list_del_init(&dev->node);
1027 dev_warn(&dev->pci_dev->dev,
1028 "I/O %d QID %d timeout, reset controller\n",
1029 req->tag, nvmeq->qid);
1030 dev->reset_workfn = nvme_reset_failed_dev;
1031 queue_work(nvme_workq, &dev->reset_work);
1032 return;
1033 }
1034
1035 if (!dev->abort_limit)
1036 return;
1037
1038 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1039 false);
1040 if (IS_ERR(abort_req))
1041 return;
1042
1043 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1044 nvme_set_info(abort_cmd, abort_req, abort_completion);
1045
1046 memset(&cmd, 0, sizeof(cmd));
1047 cmd.abort.opcode = nvme_admin_abort_cmd;
1048 cmd.abort.cid = req->tag;
1049 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1050 cmd.abort.command_id = abort_req->tag;
1051
1052 --dev->abort_limit;
1053 cmd_rq->aborted = 1;
1054
1055 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
1056 nvmeq->qid);
1057 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1058 dev_warn(nvmeq->q_dmadev,
1059 "Could not abort I/O %d QID %d",
1060 req->tag, nvmeq->qid);
1061 blk_mq_free_request(abort_req);
1062 }
1063 }
1064
1065 static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1066 struct request *req, void *data, bool reserved)
1067 {
1068 struct nvme_queue *nvmeq = data;
1069 void *ctx;
1070 nvme_completion_fn fn;
1071 struct nvme_cmd_info *cmd;
1072 struct nvme_completion cqe;
1073
1074 if (!blk_mq_request_started(req))
1075 return;
1076
1077 cmd = blk_mq_rq_to_pdu(req);
1078
1079 if (cmd->ctx == CMD_CTX_CANCELLED)
1080 return;
1081
1082 if (blk_queue_dying(req->q))
1083 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1084 else
1085 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1086
1087
1088 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1089 req->tag, nvmeq->qid);
1090 ctx = cancel_cmd_info(cmd, &fn);
1091 fn(nvmeq, ctx, &cqe);
1092 }
1093
1094 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1095 {
1096 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1097 struct nvme_queue *nvmeq = cmd->nvmeq;
1098
1099 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1100 nvmeq->qid);
1101
1102 if (!nvmeq->dev->initialized) {
1103 /*
1104 * Force cancelled command frees the request, which requires we
1105 * return BLK_EH_NOT_HANDLED.
1106 */
1107 nvme_cancel_queue_ios(nvmeq->hctx, req, nvmeq, reserved);
1108 return BLK_EH_NOT_HANDLED;
1109 }
1110 nvme_abort_req(req);
1111
1112 /*
1113 * The aborted req will be completed on receiving the abort req.
1114 * We enable the timer again. If hit twice, it'll cause a device reset,
1115 * as the device then is in a faulty state.
1116 */
1117 return BLK_EH_RESET_TIMER;
1118 }
1119
1120 static void nvme_free_queue(struct nvme_queue *nvmeq)
1121 {
1122 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1123 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1124 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1125 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1126 kfree(nvmeq);
1127 }
1128
1129 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1130 {
1131 LLIST_HEAD(q_list);
1132 struct nvme_queue *nvmeq, *next;
1133 struct llist_node *entry;
1134 int i;
1135
1136 for (i = dev->queue_count - 1; i >= lowest; i--) {
1137 struct nvme_queue *nvmeq = dev->queues[i];
1138 llist_add(&nvmeq->node, &q_list);
1139 dev->queue_count--;
1140 dev->queues[i] = NULL;
1141 }
1142 synchronize_rcu();
1143 entry = llist_del_all(&q_list);
1144 llist_for_each_entry_safe(nvmeq, next, entry, node)
1145 nvme_free_queue(nvmeq);
1146 }
1147
1148 /**
1149 * nvme_suspend_queue - put queue into suspended state
1150 * @nvmeq - queue to suspend
1151 */
1152 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1153 {
1154 int vector;
1155
1156 spin_lock_irq(&nvmeq->q_lock);
1157 if (nvmeq->cq_vector == -1) {
1158 spin_unlock_irq(&nvmeq->q_lock);
1159 return 1;
1160 }
1161 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1162 nvmeq->dev->online_queues--;
1163 nvmeq->cq_vector = -1;
1164 spin_unlock_irq(&nvmeq->q_lock);
1165
1166 irq_set_affinity_hint(vector, NULL);
1167 free_irq(vector, nvmeq);
1168
1169 return 0;
1170 }
1171
1172 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1173 {
1174 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1175
1176 spin_lock_irq(&nvmeq->q_lock);
1177 nvme_process_cq(nvmeq);
1178 if (hctx && hctx->tags)
1179 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
1180 spin_unlock_irq(&nvmeq->q_lock);
1181 }
1182
1183 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1184 {
1185 struct nvme_queue *nvmeq = dev->queues[qid];
1186
1187 if (!nvmeq)
1188 return;
1189 if (nvme_suspend_queue(nvmeq))
1190 return;
1191
1192 /* Don't tell the adapter to delete the admin queue.
1193 * Don't tell a removed adapter to delete IO queues. */
1194 if (qid && readl(&dev->bar->csts) != -1) {
1195 adapter_delete_sq(dev, qid);
1196 adapter_delete_cq(dev, qid);
1197 }
1198 if (!qid && dev->admin_q)
1199 blk_mq_freeze_queue_start(dev->admin_q);
1200 nvme_clear_queue(nvmeq);
1201 }
1202
1203 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1204 int depth)
1205 {
1206 struct device *dmadev = &dev->pci_dev->dev;
1207 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1208 if (!nvmeq)
1209 return NULL;
1210
1211 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1212 &nvmeq->cq_dma_addr, GFP_KERNEL);
1213 if (!nvmeq->cqes)
1214 goto free_nvmeq;
1215
1216 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1217 &nvmeq->sq_dma_addr, GFP_KERNEL);
1218 if (!nvmeq->sq_cmds)
1219 goto free_cqdma;
1220
1221 nvmeq->q_dmadev = dmadev;
1222 nvmeq->dev = dev;
1223 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1224 dev->instance, qid);
1225 spin_lock_init(&nvmeq->q_lock);
1226 nvmeq->cq_head = 0;
1227 nvmeq->cq_phase = 1;
1228 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1229 nvmeq->q_depth = depth;
1230 nvmeq->qid = qid;
1231 dev->queue_count++;
1232 dev->queues[qid] = nvmeq;
1233
1234 return nvmeq;
1235
1236 free_cqdma:
1237 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1238 nvmeq->cq_dma_addr);
1239 free_nvmeq:
1240 kfree(nvmeq);
1241 return NULL;
1242 }
1243
1244 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1245 const char *name)
1246 {
1247 if (use_threaded_interrupts)
1248 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1249 nvme_irq_check, nvme_irq, IRQF_SHARED,
1250 name, nvmeq);
1251 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1252 IRQF_SHARED, name, nvmeq);
1253 }
1254
1255 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1256 {
1257 struct nvme_dev *dev = nvmeq->dev;
1258
1259 spin_lock_irq(&nvmeq->q_lock);
1260 nvmeq->sq_tail = 0;
1261 nvmeq->cq_head = 0;
1262 nvmeq->cq_phase = 1;
1263 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1264 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1265 dev->online_queues++;
1266 spin_unlock_irq(&nvmeq->q_lock);
1267 }
1268
1269 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1270 {
1271 struct nvme_dev *dev = nvmeq->dev;
1272 int result;
1273
1274 nvmeq->cq_vector = qid - 1;
1275 result = adapter_alloc_cq(dev, qid, nvmeq);
1276 if (result < 0)
1277 return result;
1278
1279 result = adapter_alloc_sq(dev, qid, nvmeq);
1280 if (result < 0)
1281 goto release_cq;
1282
1283 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1284 if (result < 0)
1285 goto release_sq;
1286
1287 nvme_init_queue(nvmeq, qid);
1288 return result;
1289
1290 release_sq:
1291 adapter_delete_sq(dev, qid);
1292 release_cq:
1293 adapter_delete_cq(dev, qid);
1294 return result;
1295 }
1296
1297 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1298 {
1299 unsigned long timeout;
1300 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1301
1302 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1303
1304 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1305 msleep(100);
1306 if (fatal_signal_pending(current))
1307 return -EINTR;
1308 if (time_after(jiffies, timeout)) {
1309 dev_err(&dev->pci_dev->dev,
1310 "Device not ready; aborting %s\n", enabled ?
1311 "initialisation" : "reset");
1312 return -ENODEV;
1313 }
1314 }
1315
1316 return 0;
1317 }
1318
1319 /*
1320 * If the device has been passed off to us in an enabled state, just clear
1321 * the enabled bit. The spec says we should set the 'shutdown notification
1322 * bits', but doing so may cause the device to complete commands to the
1323 * admin queue ... and we don't know what memory that might be pointing at!
1324 */
1325 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1326 {
1327 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1328 dev->ctrl_config &= ~NVME_CC_ENABLE;
1329 writel(dev->ctrl_config, &dev->bar->cc);
1330
1331 return nvme_wait_ready(dev, cap, false);
1332 }
1333
1334 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1335 {
1336 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1337 dev->ctrl_config |= NVME_CC_ENABLE;
1338 writel(dev->ctrl_config, &dev->bar->cc);
1339
1340 return nvme_wait_ready(dev, cap, true);
1341 }
1342
1343 static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1344 {
1345 unsigned long timeout;
1346
1347 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1348 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1349
1350 writel(dev->ctrl_config, &dev->bar->cc);
1351
1352 timeout = SHUTDOWN_TIMEOUT + jiffies;
1353 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1354 NVME_CSTS_SHST_CMPLT) {
1355 msleep(100);
1356 if (fatal_signal_pending(current))
1357 return -EINTR;
1358 if (time_after(jiffies, timeout)) {
1359 dev_err(&dev->pci_dev->dev,
1360 "Device shutdown incomplete; abort shutdown\n");
1361 return -ENODEV;
1362 }
1363 }
1364
1365 return 0;
1366 }
1367
1368 static struct blk_mq_ops nvme_mq_admin_ops = {
1369 .queue_rq = nvme_admin_queue_rq,
1370 .map_queue = blk_mq_map_queue,
1371 .init_hctx = nvme_admin_init_hctx,
1372 .exit_hctx = nvme_exit_hctx,
1373 .init_request = nvme_admin_init_request,
1374 .timeout = nvme_timeout,
1375 };
1376
1377 static struct blk_mq_ops nvme_mq_ops = {
1378 .queue_rq = nvme_queue_rq,
1379 .map_queue = blk_mq_map_queue,
1380 .init_hctx = nvme_init_hctx,
1381 .exit_hctx = nvme_exit_hctx,
1382 .init_request = nvme_init_request,
1383 .timeout = nvme_timeout,
1384 };
1385
1386 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1387 {
1388 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1389 blk_cleanup_queue(dev->admin_q);
1390 blk_mq_free_tag_set(&dev->admin_tagset);
1391 }
1392 }
1393
1394 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1395 {
1396 if (!dev->admin_q) {
1397 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1398 dev->admin_tagset.nr_hw_queues = 1;
1399 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1400 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1401 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
1402 dev->admin_tagset.cmd_size = sizeof(struct nvme_cmd_info);
1403 dev->admin_tagset.driver_data = dev;
1404
1405 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1406 return -ENOMEM;
1407
1408 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1409 if (IS_ERR(dev->admin_q)) {
1410 blk_mq_free_tag_set(&dev->admin_tagset);
1411 return -ENOMEM;
1412 }
1413 if (!blk_get_queue(dev->admin_q)) {
1414 nvme_dev_remove_admin(dev);
1415 return -ENODEV;
1416 }
1417 } else
1418 blk_mq_unfreeze_queue(dev->admin_q);
1419
1420 return 0;
1421 }
1422
1423 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1424 {
1425 int result;
1426 u32 aqa;
1427 u64 cap = readq(&dev->bar->cap);
1428 struct nvme_queue *nvmeq;
1429 unsigned page_shift = PAGE_SHIFT;
1430 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1431 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1432
1433 if (page_shift < dev_page_min) {
1434 dev_err(&dev->pci_dev->dev,
1435 "Minimum device page size (%u) too large for "
1436 "host (%u)\n", 1 << dev_page_min,
1437 1 << page_shift);
1438 return -ENODEV;
1439 }
1440 if (page_shift > dev_page_max) {
1441 dev_info(&dev->pci_dev->dev,
1442 "Device maximum page size (%u) smaller than "
1443 "host (%u); enabling work-around\n",
1444 1 << dev_page_max, 1 << page_shift);
1445 page_shift = dev_page_max;
1446 }
1447
1448 result = nvme_disable_ctrl(dev, cap);
1449 if (result < 0)
1450 return result;
1451
1452 nvmeq = dev->queues[0];
1453 if (!nvmeq) {
1454 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1455 if (!nvmeq)
1456 return -ENOMEM;
1457 }
1458
1459 aqa = nvmeq->q_depth - 1;
1460 aqa |= aqa << 16;
1461
1462 dev->page_size = 1 << page_shift;
1463
1464 dev->ctrl_config = NVME_CC_CSS_NVM;
1465 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1466 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1467 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1468
1469 writel(aqa, &dev->bar->aqa);
1470 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1471 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1472
1473 result = nvme_enable_ctrl(dev, cap);
1474 if (result)
1475 goto free_nvmeq;
1476
1477 nvmeq->cq_vector = 0;
1478 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1479 if (result)
1480 goto free_nvmeq;
1481
1482 return result;
1483
1484 free_nvmeq:
1485 nvme_free_queues(dev, 0);
1486 return result;
1487 }
1488
1489 struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1490 unsigned long addr, unsigned length)
1491 {
1492 int i, err, count, nents, offset;
1493 struct scatterlist *sg;
1494 struct page **pages;
1495 struct nvme_iod *iod;
1496
1497 if (addr & 3)
1498 return ERR_PTR(-EINVAL);
1499 if (!length || length > INT_MAX - PAGE_SIZE)
1500 return ERR_PTR(-EINVAL);
1501
1502 offset = offset_in_page(addr);
1503 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1504 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1505 if (!pages)
1506 return ERR_PTR(-ENOMEM);
1507
1508 err = get_user_pages_fast(addr, count, 1, pages);
1509 if (err < count) {
1510 count = err;
1511 err = -EFAULT;
1512 goto put_pages;
1513 }
1514
1515 err = -ENOMEM;
1516 iod = nvme_alloc_iod(count, length, dev, GFP_KERNEL);
1517 if (!iod)
1518 goto put_pages;
1519
1520 sg = iod->sg;
1521 sg_init_table(sg, count);
1522 for (i = 0; i < count; i++) {
1523 sg_set_page(&sg[i], pages[i],
1524 min_t(unsigned, length, PAGE_SIZE - offset),
1525 offset);
1526 length -= (PAGE_SIZE - offset);
1527 offset = 0;
1528 }
1529 sg_mark_end(&sg[i - 1]);
1530 iod->nents = count;
1531
1532 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1533 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1534 if (!nents)
1535 goto free_iod;
1536
1537 kfree(pages);
1538 return iod;
1539
1540 free_iod:
1541 kfree(iod);
1542 put_pages:
1543 for (i = 0; i < count; i++)
1544 put_page(pages[i]);
1545 kfree(pages);
1546 return ERR_PTR(err);
1547 }
1548
1549 void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1550 struct nvme_iod *iod)
1551 {
1552 int i;
1553
1554 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1555 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1556
1557 for (i = 0; i < iod->nents; i++)
1558 put_page(sg_page(&iod->sg[i]));
1559 }
1560
1561 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1562 {
1563 struct nvme_dev *dev = ns->dev;
1564 struct nvme_user_io io;
1565 struct nvme_command c;
1566 unsigned length, meta_len;
1567 int status, i;
1568 struct nvme_iod *iod, *meta_iod = NULL;
1569 dma_addr_t meta_dma_addr;
1570 void *meta, *uninitialized_var(meta_mem);
1571
1572 if (copy_from_user(&io, uio, sizeof(io)))
1573 return -EFAULT;
1574 length = (io.nblocks + 1) << ns->lba_shift;
1575 meta_len = (io.nblocks + 1) * ns->ms;
1576
1577 if (meta_len && ((io.metadata & 3) || !io.metadata))
1578 return -EINVAL;
1579
1580 switch (io.opcode) {
1581 case nvme_cmd_write:
1582 case nvme_cmd_read:
1583 case nvme_cmd_compare:
1584 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
1585 break;
1586 default:
1587 return -EINVAL;
1588 }
1589
1590 if (IS_ERR(iod))
1591 return PTR_ERR(iod);
1592
1593 memset(&c, 0, sizeof(c));
1594 c.rw.opcode = io.opcode;
1595 c.rw.flags = io.flags;
1596 c.rw.nsid = cpu_to_le32(ns->ns_id);
1597 c.rw.slba = cpu_to_le64(io.slba);
1598 c.rw.length = cpu_to_le16(io.nblocks);
1599 c.rw.control = cpu_to_le16(io.control);
1600 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1601 c.rw.reftag = cpu_to_le32(io.reftag);
1602 c.rw.apptag = cpu_to_le16(io.apptag);
1603 c.rw.appmask = cpu_to_le16(io.appmask);
1604
1605 if (meta_len) {
1606 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1607 meta_len);
1608 if (IS_ERR(meta_iod)) {
1609 status = PTR_ERR(meta_iod);
1610 meta_iod = NULL;
1611 goto unmap;
1612 }
1613
1614 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1615 &meta_dma_addr, GFP_KERNEL);
1616 if (!meta_mem) {
1617 status = -ENOMEM;
1618 goto unmap;
1619 }
1620
1621 if (io.opcode & 1) {
1622 int meta_offset = 0;
1623
1624 for (i = 0; i < meta_iod->nents; i++) {
1625 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1626 meta_iod->sg[i].offset;
1627 memcpy(meta_mem + meta_offset, meta,
1628 meta_iod->sg[i].length);
1629 kunmap_atomic(meta);
1630 meta_offset += meta_iod->sg[i].length;
1631 }
1632 }
1633
1634 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1635 }
1636
1637 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1638 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1639 c.rw.prp2 = cpu_to_le64(iod->first_dma);
1640
1641 if (length != (io.nblocks + 1) << ns->lba_shift)
1642 status = -ENOMEM;
1643 else
1644 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
1645
1646 if (meta_len) {
1647 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1648 int meta_offset = 0;
1649
1650 for (i = 0; i < meta_iod->nents; i++) {
1651 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1652 meta_iod->sg[i].offset;
1653 memcpy(meta, meta_mem + meta_offset,
1654 meta_iod->sg[i].length);
1655 kunmap_atomic(meta);
1656 meta_offset += meta_iod->sg[i].length;
1657 }
1658 }
1659
1660 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1661 meta_dma_addr);
1662 }
1663
1664 unmap:
1665 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
1666 nvme_free_iod(dev, iod);
1667
1668 if (meta_iod) {
1669 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1670 nvme_free_iod(dev, meta_iod);
1671 }
1672
1673 return status;
1674 }
1675
1676 static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1677 struct nvme_passthru_cmd __user *ucmd)
1678 {
1679 struct nvme_passthru_cmd cmd;
1680 struct nvme_command c;
1681 int status, length;
1682 struct nvme_iod *uninitialized_var(iod);
1683 unsigned timeout;
1684
1685 if (!capable(CAP_SYS_ADMIN))
1686 return -EACCES;
1687 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1688 return -EFAULT;
1689
1690 memset(&c, 0, sizeof(c));
1691 c.common.opcode = cmd.opcode;
1692 c.common.flags = cmd.flags;
1693 c.common.nsid = cpu_to_le32(cmd.nsid);
1694 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1695 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1696 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1697 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1698 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1699 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1700 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1701 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1702
1703 length = cmd.data_len;
1704 if (cmd.data_len) {
1705 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1706 length);
1707 if (IS_ERR(iod))
1708 return PTR_ERR(iod);
1709 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1710 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1711 c.common.prp2 = cpu_to_le64(iod->first_dma);
1712 }
1713
1714 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1715 ADMIN_TIMEOUT;
1716
1717 if (length != cmd.data_len)
1718 status = -ENOMEM;
1719 else if (ns) {
1720 struct request *req;
1721
1722 req = blk_mq_alloc_request(ns->queue, WRITE,
1723 (GFP_KERNEL|__GFP_WAIT), false);
1724 if (IS_ERR(req))
1725 status = PTR_ERR(req);
1726 else {
1727 status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1728 timeout);
1729 blk_mq_free_request(req);
1730 }
1731 } else
1732 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
1733
1734 if (cmd.data_len) {
1735 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1736 nvme_free_iod(dev, iod);
1737 }
1738
1739 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
1740 sizeof(cmd.result)))
1741 status = -EFAULT;
1742
1743 return status;
1744 }
1745
1746 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1747 unsigned long arg)
1748 {
1749 struct nvme_ns *ns = bdev->bd_disk->private_data;
1750
1751 switch (cmd) {
1752 case NVME_IOCTL_ID:
1753 force_successful_syscall_return();
1754 return ns->ns_id;
1755 case NVME_IOCTL_ADMIN_CMD:
1756 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
1757 case NVME_IOCTL_IO_CMD:
1758 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
1759 case NVME_IOCTL_SUBMIT_IO:
1760 return nvme_submit_io(ns, (void __user *)arg);
1761 case SG_GET_VERSION_NUM:
1762 return nvme_sg_get_version_num((void __user *)arg);
1763 case SG_IO:
1764 return nvme_sg_io(ns, (void __user *)arg);
1765 default:
1766 return -ENOTTY;
1767 }
1768 }
1769
1770 #ifdef CONFIG_COMPAT
1771 static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1772 unsigned int cmd, unsigned long arg)
1773 {
1774 switch (cmd) {
1775 case SG_IO:
1776 return -ENOIOCTLCMD;
1777 }
1778 return nvme_ioctl(bdev, mode, cmd, arg);
1779 }
1780 #else
1781 #define nvme_compat_ioctl NULL
1782 #endif
1783
1784 static int nvme_open(struct block_device *bdev, fmode_t mode)
1785 {
1786 int ret = 0;
1787 struct nvme_ns *ns;
1788
1789 spin_lock(&dev_list_lock);
1790 ns = bdev->bd_disk->private_data;
1791 if (!ns)
1792 ret = -ENXIO;
1793 else if (!kref_get_unless_zero(&ns->dev->kref))
1794 ret = -ENXIO;
1795 spin_unlock(&dev_list_lock);
1796
1797 return ret;
1798 }
1799
1800 static void nvme_free_dev(struct kref *kref);
1801
1802 static void nvme_release(struct gendisk *disk, fmode_t mode)
1803 {
1804 struct nvme_ns *ns = disk->private_data;
1805 struct nvme_dev *dev = ns->dev;
1806
1807 kref_put(&dev->kref, nvme_free_dev);
1808 }
1809
1810 static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1811 {
1812 /* some standard values */
1813 geo->heads = 1 << 6;
1814 geo->sectors = 1 << 5;
1815 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1816 return 0;
1817 }
1818
1819 static int nvme_revalidate_disk(struct gendisk *disk)
1820 {
1821 struct nvme_ns *ns = disk->private_data;
1822 struct nvme_dev *dev = ns->dev;
1823 struct nvme_id_ns *id;
1824 dma_addr_t dma_addr;
1825 int lbaf;
1826
1827 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
1828 GFP_KERNEL);
1829 if (!id) {
1830 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
1831 __func__);
1832 return 0;
1833 }
1834
1835 if (nvme_identify(dev, ns->ns_id, 0, dma_addr))
1836 goto free;
1837
1838 lbaf = id->flbas & 0xf;
1839 ns->lba_shift = id->lbaf[lbaf].ds;
1840
1841 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1842 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1843 free:
1844 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1845 return 0;
1846 }
1847
1848 static const struct block_device_operations nvme_fops = {
1849 .owner = THIS_MODULE,
1850 .ioctl = nvme_ioctl,
1851 .compat_ioctl = nvme_compat_ioctl,
1852 .open = nvme_open,
1853 .release = nvme_release,
1854 .getgeo = nvme_getgeo,
1855 .revalidate_disk= nvme_revalidate_disk,
1856 };
1857
1858 static int nvme_kthread(void *data)
1859 {
1860 struct nvme_dev *dev, *next;
1861
1862 while (!kthread_should_stop()) {
1863 set_current_state(TASK_INTERRUPTIBLE);
1864 spin_lock(&dev_list_lock);
1865 list_for_each_entry_safe(dev, next, &dev_list, node) {
1866 int i;
1867 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1868 dev->initialized) {
1869 if (work_busy(&dev->reset_work))
1870 continue;
1871 list_del_init(&dev->node);
1872 dev_warn(&dev->pci_dev->dev,
1873 "Failed status: %x, reset controller\n",
1874 readl(&dev->bar->csts));
1875 dev->reset_workfn = nvme_reset_failed_dev;
1876 queue_work(nvme_workq, &dev->reset_work);
1877 continue;
1878 }
1879 for (i = 0; i < dev->queue_count; i++) {
1880 struct nvme_queue *nvmeq = dev->queues[i];
1881 if (!nvmeq)
1882 continue;
1883 spin_lock_irq(&nvmeq->q_lock);
1884 nvme_process_cq(nvmeq);
1885
1886 while ((i == 0) && (dev->event_limit > 0)) {
1887 if (nvme_submit_async_admin_req(dev))
1888 break;
1889 dev->event_limit--;
1890 }
1891 spin_unlock_irq(&nvmeq->q_lock);
1892 }
1893 }
1894 spin_unlock(&dev_list_lock);
1895 schedule_timeout(round_jiffies_relative(HZ));
1896 }
1897 return 0;
1898 }
1899
1900 static void nvme_config_discard(struct nvme_ns *ns)
1901 {
1902 u32 logical_block_size = queue_logical_block_size(ns->queue);
1903 ns->queue->limits.discard_zeroes_data = 0;
1904 ns->queue->limits.discard_alignment = logical_block_size;
1905 ns->queue->limits.discard_granularity = logical_block_size;
1906 ns->queue->limits.max_discard_sectors = 0xffffffff;
1907 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1908 }
1909
1910 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
1911 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1912 {
1913 struct nvme_ns *ns;
1914 struct gendisk *disk;
1915 int node = dev_to_node(&dev->pci_dev->dev);
1916 int lbaf;
1917
1918 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1919 return NULL;
1920
1921 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
1922 if (!ns)
1923 return NULL;
1924 ns->queue = blk_mq_init_queue(&dev->tagset);
1925 if (IS_ERR(ns->queue))
1926 goto out_free_ns;
1927 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1928 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1929 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
1930 ns->dev = dev;
1931 ns->queue->queuedata = ns;
1932
1933 disk = alloc_disk_node(0, node);
1934 if (!disk)
1935 goto out_free_queue;
1936
1937 ns->ns_id = nsid;
1938 ns->disk = disk;
1939 lbaf = id->flbas & 0xf;
1940 ns->lba_shift = id->lbaf[lbaf].ds;
1941 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
1942 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1943 if (dev->max_hw_sectors)
1944 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
1945 if (dev->stripe_size)
1946 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
1947 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
1948 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
1949
1950 disk->major = nvme_major;
1951 disk->first_minor = 0;
1952 disk->fops = &nvme_fops;
1953 disk->private_data = ns;
1954 disk->queue = ns->queue;
1955 disk->driverfs_dev = &dev->pci_dev->dev;
1956 disk->flags = GENHD_FL_EXT_DEVT;
1957 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1958 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1959
1960 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1961 nvme_config_discard(ns);
1962
1963 return ns;
1964
1965 out_free_queue:
1966 blk_cleanup_queue(ns->queue);
1967 out_free_ns:
1968 kfree(ns);
1969 return NULL;
1970 }
1971
1972 static void nvme_create_io_queues(struct nvme_dev *dev)
1973 {
1974 unsigned i;
1975
1976 for (i = dev->queue_count; i <= dev->max_qid; i++)
1977 if (!nvme_alloc_queue(dev, i, dev->q_depth))
1978 break;
1979
1980 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
1981 if (nvme_create_queue(dev->queues[i], i))
1982 break;
1983 }
1984
1985 static int set_queue_count(struct nvme_dev *dev, int count)
1986 {
1987 int status;
1988 u32 result;
1989 u32 q_count = (count - 1) | ((count - 1) << 16);
1990
1991 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1992 &result);
1993 if (status < 0)
1994 return status;
1995 if (status > 0) {
1996 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
1997 status);
1998 return 0;
1999 }
2000 return min(result & 0xffff, result >> 16) + 1;
2001 }
2002
2003 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2004 {
2005 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
2006 }
2007
2008 static int nvme_setup_io_queues(struct nvme_dev *dev)
2009 {
2010 struct nvme_queue *adminq = dev->queues[0];
2011 struct pci_dev *pdev = dev->pci_dev;
2012 int result, i, vecs, nr_io_queues, size;
2013
2014 nr_io_queues = num_possible_cpus();
2015 result = set_queue_count(dev, nr_io_queues);
2016 if (result <= 0)
2017 return result;
2018 if (result < nr_io_queues)
2019 nr_io_queues = result;
2020
2021 size = db_bar_size(dev, nr_io_queues);
2022 if (size > 8192) {
2023 iounmap(dev->bar);
2024 do {
2025 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2026 if (dev->bar)
2027 break;
2028 if (!--nr_io_queues)
2029 return -ENOMEM;
2030 size = db_bar_size(dev, nr_io_queues);
2031 } while (1);
2032 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2033 adminq->q_db = dev->dbs;
2034 }
2035
2036 /* Deregister the admin queue's interrupt */
2037 free_irq(dev->entry[0].vector, adminq);
2038
2039 /*
2040 * If we enable msix early due to not intx, disable it again before
2041 * setting up the full range we need.
2042 */
2043 if (!pdev->irq)
2044 pci_disable_msix(pdev);
2045
2046 for (i = 0; i < nr_io_queues; i++)
2047 dev->entry[i].entry = i;
2048 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2049 if (vecs < 0) {
2050 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2051 if (vecs < 0) {
2052 vecs = 1;
2053 } else {
2054 for (i = 0; i < vecs; i++)
2055 dev->entry[i].vector = i + pdev->irq;
2056 }
2057 }
2058
2059 /*
2060 * Should investigate if there's a performance win from allocating
2061 * more queues than interrupt vectors; it might allow the submission
2062 * path to scale better, even if the receive path is limited by the
2063 * number of interrupts.
2064 */
2065 nr_io_queues = vecs;
2066 dev->max_qid = nr_io_queues;
2067
2068 result = queue_request_irq(dev, adminq, adminq->irqname);
2069 if (result)
2070 goto free_queues;
2071
2072 /* Free previously allocated queues that are no longer usable */
2073 nvme_free_queues(dev, nr_io_queues + 1);
2074 nvme_create_io_queues(dev);
2075
2076 return 0;
2077
2078 free_queues:
2079 nvme_free_queues(dev, 1);
2080 return result;
2081 }
2082
2083 /*
2084 * Return: error value if an error occurred setting up the queues or calling
2085 * Identify Device. 0 if these succeeded, even if adding some of the
2086 * namespaces failed. At the moment, these failures are silent. TBD which
2087 * failures should be reported.
2088 */
2089 static int nvme_dev_add(struct nvme_dev *dev)
2090 {
2091 struct pci_dev *pdev = dev->pci_dev;
2092 int res;
2093 unsigned nn, i;
2094 struct nvme_ns *ns;
2095 struct nvme_id_ctrl *ctrl;
2096 struct nvme_id_ns *id_ns;
2097 void *mem;
2098 dma_addr_t dma_addr;
2099 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
2100
2101 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
2102 if (!mem)
2103 return -ENOMEM;
2104
2105 res = nvme_identify(dev, 0, 1, dma_addr);
2106 if (res) {
2107 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
2108 res = -EIO;
2109 goto out;
2110 }
2111
2112 ctrl = mem;
2113 nn = le32_to_cpup(&ctrl->nn);
2114 dev->oncs = le16_to_cpup(&ctrl->oncs);
2115 dev->abort_limit = ctrl->acl + 1;
2116 dev->vwc = ctrl->vwc;
2117 dev->event_limit = min(ctrl->aerl + 1, 8);
2118 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2119 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2120 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
2121 if (ctrl->mdts)
2122 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
2123 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2124 (pdev->device == 0x0953) && ctrl->vs[3]) {
2125 unsigned int max_hw_sectors;
2126
2127 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
2128 max_hw_sectors = dev->stripe_size >> (shift - 9);
2129 if (dev->max_hw_sectors) {
2130 dev->max_hw_sectors = min(max_hw_sectors,
2131 dev->max_hw_sectors);
2132 } else
2133 dev->max_hw_sectors = max_hw_sectors;
2134 }
2135
2136 dev->tagset.ops = &nvme_mq_ops;
2137 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2138 dev->tagset.timeout = NVME_IO_TIMEOUT;
2139 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2140 dev->tagset.queue_depth =
2141 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2142 dev->tagset.cmd_size = sizeof(struct nvme_cmd_info);
2143 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2144 dev->tagset.driver_data = dev;
2145
2146 if (blk_mq_alloc_tag_set(&dev->tagset))
2147 goto out;
2148
2149 id_ns = mem;
2150 for (i = 1; i <= nn; i++) {
2151 res = nvme_identify(dev, i, 0, dma_addr);
2152 if (res)
2153 continue;
2154
2155 if (id_ns->ncap == 0)
2156 continue;
2157
2158 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
2159 dma_addr + 4096, NULL);
2160 if (res)
2161 memset(mem + 4096, 0, 4096);
2162
2163 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
2164 if (ns)
2165 list_add_tail(&ns->list, &dev->namespaces);
2166 }
2167 list_for_each_entry(ns, &dev->namespaces, list)
2168 add_disk(ns->disk);
2169 res = 0;
2170
2171 out:
2172 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
2173 return res;
2174 }
2175
2176 static int nvme_dev_map(struct nvme_dev *dev)
2177 {
2178 u64 cap;
2179 int bars, result = -ENOMEM;
2180 struct pci_dev *pdev = dev->pci_dev;
2181
2182 if (pci_enable_device_mem(pdev))
2183 return result;
2184
2185 dev->entry[0].vector = pdev->irq;
2186 pci_set_master(pdev);
2187 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2188 if (!bars)
2189 goto disable_pci;
2190
2191 if (pci_request_selected_regions(pdev, bars, "nvme"))
2192 goto disable_pci;
2193
2194 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2195 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2196 goto disable;
2197
2198 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2199 if (!dev->bar)
2200 goto disable;
2201
2202 if (readl(&dev->bar->csts) == -1) {
2203 result = -ENODEV;
2204 goto unmap;
2205 }
2206
2207 /*
2208 * Some devices don't advertse INTx interrupts, pre-enable a single
2209 * MSIX vec for setup. We'll adjust this later.
2210 */
2211 if (!pdev->irq) {
2212 result = pci_enable_msix(pdev, dev->entry, 1);
2213 if (result < 0)
2214 goto unmap;
2215 }
2216
2217 cap = readq(&dev->bar->cap);
2218 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2219 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
2220 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2221
2222 return 0;
2223
2224 unmap:
2225 iounmap(dev->bar);
2226 dev->bar = NULL;
2227 disable:
2228 pci_release_regions(pdev);
2229 disable_pci:
2230 pci_disable_device(pdev);
2231 return result;
2232 }
2233
2234 static void nvme_dev_unmap(struct nvme_dev *dev)
2235 {
2236 if (dev->pci_dev->msi_enabled)
2237 pci_disable_msi(dev->pci_dev);
2238 else if (dev->pci_dev->msix_enabled)
2239 pci_disable_msix(dev->pci_dev);
2240
2241 if (dev->bar) {
2242 iounmap(dev->bar);
2243 dev->bar = NULL;
2244 pci_release_regions(dev->pci_dev);
2245 }
2246
2247 if (pci_is_enabled(dev->pci_dev))
2248 pci_disable_device(dev->pci_dev);
2249 }
2250
2251 struct nvme_delq_ctx {
2252 struct task_struct *waiter;
2253 struct kthread_worker *worker;
2254 atomic_t refcount;
2255 };
2256
2257 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2258 {
2259 dq->waiter = current;
2260 mb();
2261
2262 for (;;) {
2263 set_current_state(TASK_KILLABLE);
2264 if (!atomic_read(&dq->refcount))
2265 break;
2266 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2267 fatal_signal_pending(current)) {
2268 /*
2269 * Disable the controller first since we can't trust it
2270 * at this point, but leave the admin queue enabled
2271 * until all queue deletion requests are flushed.
2272 * FIXME: This may take a while if there are more h/w
2273 * queues than admin tags.
2274 */
2275 set_current_state(TASK_RUNNING);
2276 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2277 nvme_clear_queue(dev->queues[0]);
2278 flush_kthread_worker(dq->worker);
2279 nvme_disable_queue(dev, 0);
2280 return;
2281 }
2282 }
2283 set_current_state(TASK_RUNNING);
2284 }
2285
2286 static void nvme_put_dq(struct nvme_delq_ctx *dq)
2287 {
2288 atomic_dec(&dq->refcount);
2289 if (dq->waiter)
2290 wake_up_process(dq->waiter);
2291 }
2292
2293 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2294 {
2295 atomic_inc(&dq->refcount);
2296 return dq;
2297 }
2298
2299 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2300 {
2301 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2302
2303 nvme_clear_queue(nvmeq);
2304 nvme_put_dq(dq);
2305 }
2306
2307 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2308 kthread_work_func_t fn)
2309 {
2310 struct nvme_command c;
2311
2312 memset(&c, 0, sizeof(c));
2313 c.delete_queue.opcode = opcode;
2314 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2315
2316 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2317 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2318 ADMIN_TIMEOUT);
2319 }
2320
2321 static void nvme_del_cq_work_handler(struct kthread_work *work)
2322 {
2323 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2324 cmdinfo.work);
2325 nvme_del_queue_end(nvmeq);
2326 }
2327
2328 static int nvme_delete_cq(struct nvme_queue *nvmeq)
2329 {
2330 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2331 nvme_del_cq_work_handler);
2332 }
2333
2334 static void nvme_del_sq_work_handler(struct kthread_work *work)
2335 {
2336 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2337 cmdinfo.work);
2338 int status = nvmeq->cmdinfo.status;
2339
2340 if (!status)
2341 status = nvme_delete_cq(nvmeq);
2342 if (status)
2343 nvme_del_queue_end(nvmeq);
2344 }
2345
2346 static int nvme_delete_sq(struct nvme_queue *nvmeq)
2347 {
2348 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2349 nvme_del_sq_work_handler);
2350 }
2351
2352 static void nvme_del_queue_start(struct kthread_work *work)
2353 {
2354 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2355 cmdinfo.work);
2356 if (nvme_delete_sq(nvmeq))
2357 nvme_del_queue_end(nvmeq);
2358 }
2359
2360 static void nvme_disable_io_queues(struct nvme_dev *dev)
2361 {
2362 int i;
2363 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2364 struct nvme_delq_ctx dq;
2365 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2366 &worker, "nvme%d", dev->instance);
2367
2368 if (IS_ERR(kworker_task)) {
2369 dev_err(&dev->pci_dev->dev,
2370 "Failed to create queue del task\n");
2371 for (i = dev->queue_count - 1; i > 0; i--)
2372 nvme_disable_queue(dev, i);
2373 return;
2374 }
2375
2376 dq.waiter = NULL;
2377 atomic_set(&dq.refcount, 0);
2378 dq.worker = &worker;
2379 for (i = dev->queue_count - 1; i > 0; i--) {
2380 struct nvme_queue *nvmeq = dev->queues[i];
2381
2382 if (nvme_suspend_queue(nvmeq))
2383 continue;
2384 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2385 nvmeq->cmdinfo.worker = dq.worker;
2386 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2387 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2388 }
2389 nvme_wait_dq(&dq, dev);
2390 kthread_stop(kworker_task);
2391 }
2392
2393 /*
2394 * Remove the node from the device list and check
2395 * for whether or not we need to stop the nvme_thread.
2396 */
2397 static void nvme_dev_list_remove(struct nvme_dev *dev)
2398 {
2399 struct task_struct *tmp = NULL;
2400
2401 spin_lock(&dev_list_lock);
2402 list_del_init(&dev->node);
2403 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2404 tmp = nvme_thread;
2405 nvme_thread = NULL;
2406 }
2407 spin_unlock(&dev_list_lock);
2408
2409 if (tmp)
2410 kthread_stop(tmp);
2411 }
2412
2413 static void nvme_freeze_queues(struct nvme_dev *dev)
2414 {
2415 struct nvme_ns *ns;
2416
2417 list_for_each_entry(ns, &dev->namespaces, list) {
2418 blk_mq_freeze_queue_start(ns->queue);
2419
2420 spin_lock(ns->queue->queue_lock);
2421 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2422 spin_unlock(ns->queue->queue_lock);
2423
2424 blk_mq_cancel_requeue_work(ns->queue);
2425 blk_mq_stop_hw_queues(ns->queue);
2426 }
2427 }
2428
2429 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2430 {
2431 struct nvme_ns *ns;
2432
2433 list_for_each_entry(ns, &dev->namespaces, list) {
2434 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2435 blk_mq_unfreeze_queue(ns->queue);
2436 blk_mq_start_stopped_hw_queues(ns->queue, true);
2437 blk_mq_kick_requeue_list(ns->queue);
2438 }
2439 }
2440
2441 static void nvme_dev_shutdown(struct nvme_dev *dev)
2442 {
2443 int i;
2444 u32 csts = -1;
2445
2446 dev->initialized = 0;
2447 nvme_dev_list_remove(dev);
2448
2449 if (dev->bar) {
2450 nvme_freeze_queues(dev);
2451 csts = readl(&dev->bar->csts);
2452 }
2453 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2454 for (i = dev->queue_count - 1; i >= 0; i--) {
2455 struct nvme_queue *nvmeq = dev->queues[i];
2456 nvme_suspend_queue(nvmeq);
2457 nvme_clear_queue(nvmeq);
2458 }
2459 } else {
2460 nvme_disable_io_queues(dev);
2461 nvme_shutdown_ctrl(dev);
2462 nvme_disable_queue(dev, 0);
2463 }
2464 nvme_dev_unmap(dev);
2465 }
2466
2467 static void nvme_dev_remove(struct nvme_dev *dev)
2468 {
2469 struct nvme_ns *ns;
2470
2471 list_for_each_entry(ns, &dev->namespaces, list) {
2472 if (ns->disk->flags & GENHD_FL_UP)
2473 del_gendisk(ns->disk);
2474 if (!blk_queue_dying(ns->queue)) {
2475 blk_mq_abort_requeue_list(ns->queue);
2476 blk_cleanup_queue(ns->queue);
2477 }
2478 }
2479 }
2480
2481 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2482 {
2483 struct device *dmadev = &dev->pci_dev->dev;
2484 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2485 PAGE_SIZE, PAGE_SIZE, 0);
2486 if (!dev->prp_page_pool)
2487 return -ENOMEM;
2488
2489 /* Optimisation for I/Os between 4k and 128k */
2490 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2491 256, 256, 0);
2492 if (!dev->prp_small_pool) {
2493 dma_pool_destroy(dev->prp_page_pool);
2494 return -ENOMEM;
2495 }
2496 return 0;
2497 }
2498
2499 static void nvme_release_prp_pools(struct nvme_dev *dev)
2500 {
2501 dma_pool_destroy(dev->prp_page_pool);
2502 dma_pool_destroy(dev->prp_small_pool);
2503 }
2504
2505 static DEFINE_IDA(nvme_instance_ida);
2506
2507 static int nvme_set_instance(struct nvme_dev *dev)
2508 {
2509 int instance, error;
2510
2511 do {
2512 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2513 return -ENODEV;
2514
2515 spin_lock(&dev_list_lock);
2516 error = ida_get_new(&nvme_instance_ida, &instance);
2517 spin_unlock(&dev_list_lock);
2518 } while (error == -EAGAIN);
2519
2520 if (error)
2521 return -ENODEV;
2522
2523 dev->instance = instance;
2524 return 0;
2525 }
2526
2527 static void nvme_release_instance(struct nvme_dev *dev)
2528 {
2529 spin_lock(&dev_list_lock);
2530 ida_remove(&nvme_instance_ida, dev->instance);
2531 spin_unlock(&dev_list_lock);
2532 }
2533
2534 static void nvme_free_namespaces(struct nvme_dev *dev)
2535 {
2536 struct nvme_ns *ns, *next;
2537
2538 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2539 list_del(&ns->list);
2540
2541 spin_lock(&dev_list_lock);
2542 ns->disk->private_data = NULL;
2543 spin_unlock(&dev_list_lock);
2544
2545 put_disk(ns->disk);
2546 kfree(ns);
2547 }
2548 }
2549
2550 static void nvme_free_dev(struct kref *kref)
2551 {
2552 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
2553
2554 pci_dev_put(dev->pci_dev);
2555 nvme_free_namespaces(dev);
2556 nvme_release_instance(dev);
2557 blk_mq_free_tag_set(&dev->tagset);
2558 blk_put_queue(dev->admin_q);
2559 kfree(dev->queues);
2560 kfree(dev->entry);
2561 kfree(dev);
2562 }
2563
2564 static int nvme_dev_open(struct inode *inode, struct file *f)
2565 {
2566 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2567 miscdev);
2568 kref_get(&dev->kref);
2569 f->private_data = dev;
2570 return 0;
2571 }
2572
2573 static int nvme_dev_release(struct inode *inode, struct file *f)
2574 {
2575 struct nvme_dev *dev = f->private_data;
2576 kref_put(&dev->kref, nvme_free_dev);
2577 return 0;
2578 }
2579
2580 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2581 {
2582 struct nvme_dev *dev = f->private_data;
2583 struct nvme_ns *ns;
2584
2585 switch (cmd) {
2586 case NVME_IOCTL_ADMIN_CMD:
2587 return nvme_user_cmd(dev, NULL, (void __user *)arg);
2588 case NVME_IOCTL_IO_CMD:
2589 if (list_empty(&dev->namespaces))
2590 return -ENOTTY;
2591 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2592 return nvme_user_cmd(dev, ns, (void __user *)arg);
2593 default:
2594 return -ENOTTY;
2595 }
2596 }
2597
2598 static const struct file_operations nvme_dev_fops = {
2599 .owner = THIS_MODULE,
2600 .open = nvme_dev_open,
2601 .release = nvme_dev_release,
2602 .unlocked_ioctl = nvme_dev_ioctl,
2603 .compat_ioctl = nvme_dev_ioctl,
2604 };
2605
2606 static void nvme_set_irq_hints(struct nvme_dev *dev)
2607 {
2608 struct nvme_queue *nvmeq;
2609 int i;
2610
2611 for (i = 0; i < dev->online_queues; i++) {
2612 nvmeq = dev->queues[i];
2613
2614 if (!nvmeq->hctx)
2615 continue;
2616
2617 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2618 nvmeq->hctx->cpumask);
2619 }
2620 }
2621
2622 static int nvme_dev_start(struct nvme_dev *dev)
2623 {
2624 int result;
2625 bool start_thread = false;
2626
2627 result = nvme_dev_map(dev);
2628 if (result)
2629 return result;
2630
2631 result = nvme_configure_admin_queue(dev);
2632 if (result)
2633 goto unmap;
2634
2635 spin_lock(&dev_list_lock);
2636 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2637 start_thread = true;
2638 nvme_thread = NULL;
2639 }
2640 list_add(&dev->node, &dev_list);
2641 spin_unlock(&dev_list_lock);
2642
2643 if (start_thread) {
2644 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2645 wake_up_all(&nvme_kthread_wait);
2646 } else
2647 wait_event_killable(nvme_kthread_wait, nvme_thread);
2648
2649 if (IS_ERR_OR_NULL(nvme_thread)) {
2650 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2651 goto disable;
2652 }
2653
2654 nvme_init_queue(dev->queues[0], 0);
2655 result = nvme_alloc_admin_tags(dev);
2656 if (result)
2657 goto disable;
2658
2659 result = nvme_setup_io_queues(dev);
2660 if (result)
2661 goto free_tags;
2662
2663 nvme_set_irq_hints(dev);
2664
2665 return result;
2666
2667 free_tags:
2668 nvme_dev_remove_admin(dev);
2669 disable:
2670 nvme_disable_queue(dev, 0);
2671 nvme_dev_list_remove(dev);
2672 unmap:
2673 nvme_dev_unmap(dev);
2674 return result;
2675 }
2676
2677 static int nvme_remove_dead_ctrl(void *arg)
2678 {
2679 struct nvme_dev *dev = (struct nvme_dev *)arg;
2680 struct pci_dev *pdev = dev->pci_dev;
2681
2682 if (pci_get_drvdata(pdev))
2683 pci_stop_and_remove_bus_device_locked(pdev);
2684 kref_put(&dev->kref, nvme_free_dev);
2685 return 0;
2686 }
2687
2688 static void nvme_remove_disks(struct work_struct *ws)
2689 {
2690 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2691
2692 nvme_free_queues(dev, 1);
2693 nvme_dev_remove(dev);
2694 }
2695
2696 static int nvme_dev_resume(struct nvme_dev *dev)
2697 {
2698 int ret;
2699
2700 ret = nvme_dev_start(dev);
2701 if (ret)
2702 return ret;
2703 if (dev->online_queues < 2) {
2704 spin_lock(&dev_list_lock);
2705 dev->reset_workfn = nvme_remove_disks;
2706 queue_work(nvme_workq, &dev->reset_work);
2707 spin_unlock(&dev_list_lock);
2708 } else {
2709 nvme_unfreeze_queues(dev);
2710 nvme_set_irq_hints(dev);
2711 }
2712 dev->initialized = 1;
2713 return 0;
2714 }
2715
2716 static void nvme_dev_reset(struct nvme_dev *dev)
2717 {
2718 nvme_dev_shutdown(dev);
2719 if (nvme_dev_resume(dev)) {
2720 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
2721 kref_get(&dev->kref);
2722 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2723 dev->instance))) {
2724 dev_err(&dev->pci_dev->dev,
2725 "Failed to start controller remove task\n");
2726 kref_put(&dev->kref, nvme_free_dev);
2727 }
2728 }
2729 }
2730
2731 static void nvme_reset_failed_dev(struct work_struct *ws)
2732 {
2733 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2734 nvme_dev_reset(dev);
2735 }
2736
2737 static void nvme_reset_workfn(struct work_struct *work)
2738 {
2739 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2740 dev->reset_workfn(work);
2741 }
2742
2743 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2744 {
2745 int node, result = -ENOMEM;
2746 struct nvme_dev *dev;
2747
2748 node = dev_to_node(&pdev->dev);
2749 if (node == NUMA_NO_NODE)
2750 set_dev_node(&pdev->dev, 0);
2751
2752 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2753 if (!dev)
2754 return -ENOMEM;
2755 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2756 GFP_KERNEL, node);
2757 if (!dev->entry)
2758 goto free;
2759 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2760 GFP_KERNEL, node);
2761 if (!dev->queues)
2762 goto free;
2763
2764 INIT_LIST_HEAD(&dev->namespaces);
2765 dev->reset_workfn = nvme_reset_failed_dev;
2766 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
2767 dev->pci_dev = pci_dev_get(pdev);
2768 pci_set_drvdata(pdev, dev);
2769 result = nvme_set_instance(dev);
2770 if (result)
2771 goto put_pci;
2772
2773 result = nvme_setup_prp_pools(dev);
2774 if (result)
2775 goto release;
2776
2777 kref_init(&dev->kref);
2778 result = nvme_dev_start(dev);
2779 if (result)
2780 goto release_pools;
2781
2782 if (dev->online_queues > 1)
2783 result = nvme_dev_add(dev);
2784 if (result)
2785 goto shutdown;
2786
2787 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2788 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2789 dev->miscdev.parent = &pdev->dev;
2790 dev->miscdev.name = dev->name;
2791 dev->miscdev.fops = &nvme_dev_fops;
2792 result = misc_register(&dev->miscdev);
2793 if (result)
2794 goto remove;
2795
2796 nvme_set_irq_hints(dev);
2797
2798 dev->initialized = 1;
2799 return 0;
2800
2801 remove:
2802 nvme_dev_remove(dev);
2803 nvme_dev_remove_admin(dev);
2804 nvme_free_namespaces(dev);
2805 shutdown:
2806 nvme_dev_shutdown(dev);
2807 release_pools:
2808 nvme_free_queues(dev, 0);
2809 nvme_release_prp_pools(dev);
2810 release:
2811 nvme_release_instance(dev);
2812 put_pci:
2813 pci_dev_put(dev->pci_dev);
2814 free:
2815 kfree(dev->queues);
2816 kfree(dev->entry);
2817 kfree(dev);
2818 return result;
2819 }
2820
2821 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2822 {
2823 struct nvme_dev *dev = pci_get_drvdata(pdev);
2824
2825 if (prepare)
2826 nvme_dev_shutdown(dev);
2827 else
2828 nvme_dev_resume(dev);
2829 }
2830
2831 static void nvme_shutdown(struct pci_dev *pdev)
2832 {
2833 struct nvme_dev *dev = pci_get_drvdata(pdev);
2834 nvme_dev_shutdown(dev);
2835 }
2836
2837 static void nvme_remove(struct pci_dev *pdev)
2838 {
2839 struct nvme_dev *dev = pci_get_drvdata(pdev);
2840
2841 spin_lock(&dev_list_lock);
2842 list_del_init(&dev->node);
2843 spin_unlock(&dev_list_lock);
2844
2845 pci_set_drvdata(pdev, NULL);
2846 flush_work(&dev->reset_work);
2847 misc_deregister(&dev->miscdev);
2848 nvme_dev_shutdown(dev);
2849 nvme_dev_remove(dev);
2850 nvme_dev_remove_admin(dev);
2851 nvme_free_queues(dev, 0);
2852 nvme_release_prp_pools(dev);
2853 kref_put(&dev->kref, nvme_free_dev);
2854 }
2855
2856 /* These functions are yet to be implemented */
2857 #define nvme_error_detected NULL
2858 #define nvme_dump_registers NULL
2859 #define nvme_link_reset NULL
2860 #define nvme_slot_reset NULL
2861 #define nvme_error_resume NULL
2862
2863 #ifdef CONFIG_PM_SLEEP
2864 static int nvme_suspend(struct device *dev)
2865 {
2866 struct pci_dev *pdev = to_pci_dev(dev);
2867 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2868
2869 nvme_dev_shutdown(ndev);
2870 return 0;
2871 }
2872
2873 static int nvme_resume(struct device *dev)
2874 {
2875 struct pci_dev *pdev = to_pci_dev(dev);
2876 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2877
2878 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
2879 ndev->reset_workfn = nvme_reset_failed_dev;
2880 queue_work(nvme_workq, &ndev->reset_work);
2881 }
2882 return 0;
2883 }
2884 #endif
2885
2886 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2887
2888 static const struct pci_error_handlers nvme_err_handler = {
2889 .error_detected = nvme_error_detected,
2890 .mmio_enabled = nvme_dump_registers,
2891 .link_reset = nvme_link_reset,
2892 .slot_reset = nvme_slot_reset,
2893 .resume = nvme_error_resume,
2894 .reset_notify = nvme_reset_notify,
2895 };
2896
2897 /* Move to pci_ids.h later */
2898 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2899
2900 static const struct pci_device_id nvme_id_table[] = {
2901 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2902 { 0, }
2903 };
2904 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2905
2906 static struct pci_driver nvme_driver = {
2907 .name = "nvme",
2908 .id_table = nvme_id_table,
2909 .probe = nvme_probe,
2910 .remove = nvme_remove,
2911 .shutdown = nvme_shutdown,
2912 .driver = {
2913 .pm = &nvme_dev_pm_ops,
2914 },
2915 .err_handler = &nvme_err_handler,
2916 };
2917
2918 static int __init nvme_init(void)
2919 {
2920 int result;
2921
2922 init_waitqueue_head(&nvme_kthread_wait);
2923
2924 nvme_workq = create_singlethread_workqueue("nvme");
2925 if (!nvme_workq)
2926 return -ENOMEM;
2927
2928 result = register_blkdev(nvme_major, "nvme");
2929 if (result < 0)
2930 goto kill_workq;
2931 else if (result > 0)
2932 nvme_major = result;
2933
2934 result = pci_register_driver(&nvme_driver);
2935 if (result)
2936 goto unregister_blkdev;
2937 return 0;
2938
2939 unregister_blkdev:
2940 unregister_blkdev(nvme_major, "nvme");
2941 kill_workq:
2942 destroy_workqueue(nvme_workq);
2943 return result;
2944 }
2945
2946 static void __exit nvme_exit(void)
2947 {
2948 pci_unregister_driver(&nvme_driver);
2949 unregister_hotcpu_notifier(&nvme_nb);
2950 unregister_blkdev(nvme_major, "nvme");
2951 destroy_workqueue(nvme_workq);
2952 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2953 _nvme_check_size();
2954 }
2955
2956 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2957 MODULE_LICENSE("GPL");
2958 MODULE_VERSION("1.0");
2959 module_init(nvme_init);
2960 module_exit(nvme_exit);
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