2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
43 #include <asm-generic/io-64-nonatomic-lo-hi.h>
45 #define NVME_Q_DEPTH 1024
46 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
48 #define NVME_MINORS 64
49 #define ADMIN_TIMEOUT (60 * HZ)
51 static int nvme_major
;
52 module_param(nvme_major
, int, 0);
54 static int use_threaded_interrupts
;
55 module_param(use_threaded_interrupts
, int, 0);
57 static DEFINE_SPINLOCK(dev_list_lock
);
58 static LIST_HEAD(dev_list
);
59 static struct task_struct
*nvme_thread
;
62 * An NVM Express queue. Each device has at least two (one for admin
63 * commands and one for I/O commands).
66 struct device
*q_dmadev
;
69 struct nvme_command
*sq_cmds
;
70 volatile struct nvme_completion
*cqes
;
71 dma_addr_t sq_dma_addr
;
72 dma_addr_t cq_dma_addr
;
73 wait_queue_head_t sq_full
;
74 wait_queue_t sq_cong_wait
;
75 struct bio_list sq_cong
;
83 unsigned long cmdid_data
[];
87 * Check we didin't inadvertently grow the command struct
89 static inline void _nvme_check_size(void)
91 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
92 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
93 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
94 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
95 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
96 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
97 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
98 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
99 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
100 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
101 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
104 typedef void (*nvme_completion_fn
)(struct nvme_dev
*, void *,
105 struct nvme_completion
*);
107 struct nvme_cmd_info
{
108 nvme_completion_fn fn
;
110 unsigned long timeout
;
113 static struct nvme_cmd_info
*nvme_cmd_info(struct nvme_queue
*nvmeq
)
115 return (void *)&nvmeq
->cmdid_data
[BITS_TO_LONGS(nvmeq
->q_depth
)];
119 * alloc_cmdid() - Allocate a Command ID
120 * @nvmeq: The queue that will be used for this command
121 * @ctx: A pointer that will be passed to the handler
122 * @handler: The function to call on completion
124 * Allocate a Command ID for a queue. The data passed in will
125 * be passed to the completion handler. This is implemented by using
126 * the bottom two bits of the ctx pointer to store the handler ID.
127 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
128 * We can change this if it becomes a problem.
130 * May be called with local interrupts disabled and the q_lock held,
131 * or with interrupts enabled and no locks held.
133 static int alloc_cmdid(struct nvme_queue
*nvmeq
, void *ctx
,
134 nvme_completion_fn handler
, unsigned timeout
)
136 int depth
= nvmeq
->q_depth
- 1;
137 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
141 cmdid
= find_first_zero_bit(nvmeq
->cmdid_data
, depth
);
144 } while (test_and_set_bit(cmdid
, nvmeq
->cmdid_data
));
146 info
[cmdid
].fn
= handler
;
147 info
[cmdid
].ctx
= ctx
;
148 info
[cmdid
].timeout
= jiffies
+ timeout
;
152 static int alloc_cmdid_killable(struct nvme_queue
*nvmeq
, void *ctx
,
153 nvme_completion_fn handler
, unsigned timeout
)
156 wait_event_killable(nvmeq
->sq_full
,
157 (cmdid
= alloc_cmdid(nvmeq
, ctx
, handler
, timeout
)) >= 0);
158 return (cmdid
< 0) ? -EINTR
: cmdid
;
161 /* Special values must be less than 0x1000 */
162 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
163 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
164 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
165 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
166 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
168 static void special_completion(struct nvme_dev
*dev
, void *ctx
,
169 struct nvme_completion
*cqe
)
171 if (ctx
== CMD_CTX_CANCELLED
)
173 if (ctx
== CMD_CTX_FLUSH
)
175 if (ctx
== CMD_CTX_COMPLETED
) {
176 dev_warn(&dev
->pci_dev
->dev
,
177 "completed id %d twice on queue %d\n",
178 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
181 if (ctx
== CMD_CTX_INVALID
) {
182 dev_warn(&dev
->pci_dev
->dev
,
183 "invalid id %d completed on queue %d\n",
184 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
188 dev_warn(&dev
->pci_dev
->dev
, "Unknown special completion %p\n", ctx
);
192 * Called with local interrupts disabled and the q_lock held. May not sleep.
194 static void *free_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
195 nvme_completion_fn
*fn
)
198 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
200 if (cmdid
>= nvmeq
->q_depth
) {
201 *fn
= special_completion
;
202 return CMD_CTX_INVALID
;
205 *fn
= info
[cmdid
].fn
;
206 ctx
= info
[cmdid
].ctx
;
207 info
[cmdid
].fn
= special_completion
;
208 info
[cmdid
].ctx
= CMD_CTX_COMPLETED
;
209 clear_bit(cmdid
, nvmeq
->cmdid_data
);
210 wake_up(&nvmeq
->sq_full
);
214 static void *cancel_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
215 nvme_completion_fn
*fn
)
218 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
220 *fn
= info
[cmdid
].fn
;
221 ctx
= info
[cmdid
].ctx
;
222 info
[cmdid
].fn
= special_completion
;
223 info
[cmdid
].ctx
= CMD_CTX_CANCELLED
;
227 struct nvme_queue
*get_nvmeq(struct nvme_dev
*dev
)
229 return dev
->queues
[get_cpu() + 1];
232 void put_nvmeq(struct nvme_queue
*nvmeq
)
238 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
239 * @nvmeq: The queue to use
240 * @cmd: The command to send
242 * Safe to use from interrupt context
244 static int nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
)
248 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
249 tail
= nvmeq
->sq_tail
;
250 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
251 if (++tail
== nvmeq
->q_depth
)
253 writel(tail
, nvmeq
->q_db
);
254 nvmeq
->sq_tail
= tail
;
255 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
260 static __le64
**iod_list(struct nvme_iod
*iod
)
262 return ((void *)iod
) + iod
->offset
;
266 * Will slightly overestimate the number of pages needed. This is OK
267 * as it only leads to a small amount of wasted memory for the lifetime of
270 static int nvme_npages(unsigned size
)
272 unsigned nprps
= DIV_ROUND_UP(size
+ PAGE_SIZE
, PAGE_SIZE
);
273 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
276 static struct nvme_iod
*
277 nvme_alloc_iod(unsigned nseg
, unsigned nbytes
, gfp_t gfp
)
279 struct nvme_iod
*iod
= kmalloc(sizeof(struct nvme_iod
) +
280 sizeof(__le64
*) * nvme_npages(nbytes
) +
281 sizeof(struct scatterlist
) * nseg
, gfp
);
284 iod
->offset
= offsetof(struct nvme_iod
, sg
[nseg
]);
286 iod
->length
= nbytes
;
293 void nvme_free_iod(struct nvme_dev
*dev
, struct nvme_iod
*iod
)
295 const int last_prp
= PAGE_SIZE
/ 8 - 1;
297 __le64
**list
= iod_list(iod
);
298 dma_addr_t prp_dma
= iod
->first_dma
;
300 if (iod
->npages
== 0)
301 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
302 for (i
= 0; i
< iod
->npages
; i
++) {
303 __le64
*prp_list
= list
[i
];
304 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
305 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
306 prp_dma
= next_prp_dma
;
311 static void bio_completion(struct nvme_dev
*dev
, void *ctx
,
312 struct nvme_completion
*cqe
)
314 struct nvme_iod
*iod
= ctx
;
315 struct bio
*bio
= iod
->private;
316 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
319 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
320 bio_data_dir(bio
) ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
321 nvme_free_iod(dev
, iod
);
323 bio_endio(bio
, -EIO
);
328 /* length is in bytes. gfp flags indicates whether we may sleep. */
329 int nvme_setup_prps(struct nvme_dev
*dev
, struct nvme_common_command
*cmd
,
330 struct nvme_iod
*iod
, int total_len
, gfp_t gfp
)
332 struct dma_pool
*pool
;
333 int length
= total_len
;
334 struct scatterlist
*sg
= iod
->sg
;
335 int dma_len
= sg_dma_len(sg
);
336 u64 dma_addr
= sg_dma_address(sg
);
337 int offset
= offset_in_page(dma_addr
);
339 __le64
**list
= iod_list(iod
);
343 cmd
->prp1
= cpu_to_le64(dma_addr
);
344 length
-= (PAGE_SIZE
- offset
);
348 dma_len
-= (PAGE_SIZE
- offset
);
350 dma_addr
+= (PAGE_SIZE
- offset
);
353 dma_addr
= sg_dma_address(sg
);
354 dma_len
= sg_dma_len(sg
);
357 if (length
<= PAGE_SIZE
) {
358 cmd
->prp2
= cpu_to_le64(dma_addr
);
362 nprps
= DIV_ROUND_UP(length
, PAGE_SIZE
);
363 if (nprps
<= (256 / 8)) {
364 pool
= dev
->prp_small_pool
;
367 pool
= dev
->prp_page_pool
;
371 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
373 cmd
->prp2
= cpu_to_le64(dma_addr
);
375 return (total_len
- length
) + PAGE_SIZE
;
378 iod
->first_dma
= prp_dma
;
379 cmd
->prp2
= cpu_to_le64(prp_dma
);
382 if (i
== PAGE_SIZE
/ 8) {
383 __le64
*old_prp_list
= prp_list
;
384 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
386 return total_len
- length
;
387 list
[iod
->npages
++] = prp_list
;
388 prp_list
[0] = old_prp_list
[i
- 1];
389 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
392 prp_list
[i
++] = cpu_to_le64(dma_addr
);
393 dma_len
-= PAGE_SIZE
;
394 dma_addr
+= PAGE_SIZE
;
402 dma_addr
= sg_dma_address(sg
);
403 dma_len
= sg_dma_len(sg
);
409 struct nvme_bio_pair
{
410 struct bio b1
, b2
, *parent
;
411 struct bio_vec
*bv1
, *bv2
;
416 static void nvme_bio_pair_endio(struct bio
*bio
, int err
)
418 struct nvme_bio_pair
*bp
= bio
->bi_private
;
423 if (atomic_dec_and_test(&bp
->cnt
)) {
424 bio_endio(bp
->parent
, bp
->err
);
433 static struct nvme_bio_pair
*nvme_bio_split(struct bio
*bio
, int idx
,
436 struct nvme_bio_pair
*bp
;
438 BUG_ON(len
> bio
->bi_size
);
439 BUG_ON(idx
> bio
->bi_vcnt
);
441 bp
= kmalloc(sizeof(*bp
), GFP_ATOMIC
);
449 bp
->b1
.bi_size
= len
;
450 bp
->b2
.bi_size
-= len
;
451 bp
->b1
.bi_vcnt
= idx
;
453 bp
->b2
.bi_sector
+= len
>> 9;
456 bp
->bv1
= kmalloc(bio
->bi_max_vecs
* sizeof(struct bio_vec
),
461 bp
->bv2
= kmalloc(bio
->bi_max_vecs
* sizeof(struct bio_vec
),
466 memcpy(bp
->bv1
, bio
->bi_io_vec
,
467 bio
->bi_max_vecs
* sizeof(struct bio_vec
));
468 memcpy(bp
->bv2
, bio
->bi_io_vec
,
469 bio
->bi_max_vecs
* sizeof(struct bio_vec
));
471 bp
->b1
.bi_io_vec
= bp
->bv1
;
472 bp
->b2
.bi_io_vec
= bp
->bv2
;
473 bp
->b2
.bi_io_vec
[idx
].bv_offset
+= offset
;
474 bp
->b2
.bi_io_vec
[idx
].bv_len
-= offset
;
475 bp
->b1
.bi_io_vec
[idx
].bv_len
= offset
;
478 bp
->bv1
= bp
->bv2
= NULL
;
480 bp
->b1
.bi_private
= bp
;
481 bp
->b2
.bi_private
= bp
;
483 bp
->b1
.bi_end_io
= nvme_bio_pair_endio
;
484 bp
->b2
.bi_end_io
= nvme_bio_pair_endio
;
487 atomic_set(&bp
->cnt
, 2);
498 static int nvme_split_and_submit(struct bio
*bio
, struct nvme_queue
*nvmeq
,
499 int idx
, int len
, int offset
)
501 struct nvme_bio_pair
*bp
= nvme_bio_split(bio
, idx
, len
, offset
);
505 if (bio_list_empty(&nvmeq
->sq_cong
))
506 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
507 bio_list_add(&nvmeq
->sq_cong
, &bp
->b1
);
508 bio_list_add(&nvmeq
->sq_cong
, &bp
->b2
);
513 /* NVMe scatterlists require no holes in the virtual address */
514 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
515 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
517 static int nvme_map_bio(struct nvme_queue
*nvmeq
, struct nvme_iod
*iod
,
518 struct bio
*bio
, enum dma_data_direction dma_dir
, int psegs
)
520 struct bio_vec
*bvec
, *bvprv
= NULL
;
521 struct scatterlist
*sg
= NULL
;
522 int i
, length
= 0, nsegs
= 0, split_len
= bio
->bi_size
;
524 if (nvmeq
->dev
->stripe_size
)
525 split_len
= nvmeq
->dev
->stripe_size
-
526 ((bio
->bi_sector
<< 9) & (nvmeq
->dev
->stripe_size
- 1));
528 sg_init_table(iod
->sg
, psegs
);
529 bio_for_each_segment(bvec
, bio
, i
) {
530 if (bvprv
&& BIOVEC_PHYS_MERGEABLE(bvprv
, bvec
)) {
531 sg
->length
+= bvec
->bv_len
;
533 if (bvprv
&& BIOVEC_NOT_VIRT_MERGEABLE(bvprv
, bvec
))
534 return nvme_split_and_submit(bio
, nvmeq
, i
,
537 sg
= sg
? sg
+ 1 : iod
->sg
;
538 sg_set_page(sg
, bvec
->bv_page
, bvec
->bv_len
,
543 if (split_len
- length
< bvec
->bv_len
)
544 return nvme_split_and_submit(bio
, nvmeq
, i
, split_len
,
546 length
+= bvec
->bv_len
;
551 if (dma_map_sg(nvmeq
->q_dmadev
, iod
->sg
, iod
->nents
, dma_dir
) == 0)
554 BUG_ON(length
!= bio
->bi_size
);
559 * We reuse the small pool to allocate the 16-byte range here as it is not
560 * worth having a special pool for these or additional cases to handle freeing
563 static int nvme_submit_discard(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
564 struct bio
*bio
, struct nvme_iod
*iod
, int cmdid
)
566 struct nvme_dsm_range
*range
;
567 struct nvme_command
*cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
569 range
= dma_pool_alloc(nvmeq
->dev
->prp_small_pool
, GFP_ATOMIC
,
574 iod_list(iod
)[0] = (__le64
*)range
;
577 range
->cattr
= cpu_to_le32(0);
578 range
->nlb
= cpu_to_le32(bio
->bi_size
>> ns
->lba_shift
);
579 range
->slba
= cpu_to_le64(nvme_block_nr(ns
, bio
->bi_sector
));
581 memset(cmnd
, 0, sizeof(*cmnd
));
582 cmnd
->dsm
.opcode
= nvme_cmd_dsm
;
583 cmnd
->dsm
.command_id
= cmdid
;
584 cmnd
->dsm
.nsid
= cpu_to_le32(ns
->ns_id
);
585 cmnd
->dsm
.prp1
= cpu_to_le64(iod
->first_dma
);
587 cmnd
->dsm
.attributes
= cpu_to_le32(NVME_DSMGMT_AD
);
589 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
591 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
596 static int nvme_submit_flush(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
599 struct nvme_command
*cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
601 memset(cmnd
, 0, sizeof(*cmnd
));
602 cmnd
->common
.opcode
= nvme_cmd_flush
;
603 cmnd
->common
.command_id
= cmdid
;
604 cmnd
->common
.nsid
= cpu_to_le32(ns
->ns_id
);
606 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
608 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
613 int nvme_submit_flush_data(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
)
615 int cmdid
= alloc_cmdid(nvmeq
, (void *)CMD_CTX_FLUSH
,
616 special_completion
, NVME_IO_TIMEOUT
);
617 if (unlikely(cmdid
< 0))
620 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
624 * Called with local interrupts disabled and the q_lock held. May not sleep.
626 static int nvme_submit_bio_queue(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
629 struct nvme_command
*cmnd
;
630 struct nvme_iod
*iod
;
631 enum dma_data_direction dma_dir
;
632 int cmdid
, length
, result
= -ENOMEM
;
635 int psegs
= bio_phys_segments(ns
->queue
, bio
);
637 if ((bio
->bi_rw
& REQ_FLUSH
) && psegs
) {
638 result
= nvme_submit_flush_data(nvmeq
, ns
);
643 iod
= nvme_alloc_iod(psegs
, bio
->bi_size
, GFP_ATOMIC
);
649 cmdid
= alloc_cmdid(nvmeq
, iod
, bio_completion
, NVME_IO_TIMEOUT
);
650 if (unlikely(cmdid
< 0))
653 if (bio
->bi_rw
& REQ_DISCARD
) {
654 result
= nvme_submit_discard(nvmeq
, ns
, bio
, iod
, cmdid
);
659 if ((bio
->bi_rw
& REQ_FLUSH
) && !psegs
)
660 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
663 if (bio
->bi_rw
& REQ_FUA
)
664 control
|= NVME_RW_FUA
;
665 if (bio
->bi_rw
& (REQ_FAILFAST_DEV
| REQ_RAHEAD
))
666 control
|= NVME_RW_LR
;
669 if (bio
->bi_rw
& REQ_RAHEAD
)
670 dsmgmt
|= NVME_RW_DSM_FREQ_PREFETCH
;
672 cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
674 memset(cmnd
, 0, sizeof(*cmnd
));
675 if (bio_data_dir(bio
)) {
676 cmnd
->rw
.opcode
= nvme_cmd_write
;
677 dma_dir
= DMA_TO_DEVICE
;
679 cmnd
->rw
.opcode
= nvme_cmd_read
;
680 dma_dir
= DMA_FROM_DEVICE
;
683 result
= nvme_map_bio(nvmeq
, iod
, bio
, dma_dir
, psegs
);
688 cmnd
->rw
.command_id
= cmdid
;
689 cmnd
->rw
.nsid
= cpu_to_le32(ns
->ns_id
);
690 length
= nvme_setup_prps(nvmeq
->dev
, &cmnd
->common
, iod
, length
,
692 cmnd
->rw
.slba
= cpu_to_le64(nvme_block_nr(ns
, bio
->bi_sector
));
693 cmnd
->rw
.length
= cpu_to_le16((length
>> ns
->lba_shift
) - 1);
694 cmnd
->rw
.control
= cpu_to_le16(control
);
695 cmnd
->rw
.dsmgmt
= cpu_to_le32(dsmgmt
);
697 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
699 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
704 free_cmdid(nvmeq
, cmdid
, NULL
);
706 nvme_free_iod(nvmeq
->dev
, iod
);
711 static void nvme_make_request(struct request_queue
*q
, struct bio
*bio
)
713 struct nvme_ns
*ns
= q
->queuedata
;
714 struct nvme_queue
*nvmeq
= get_nvmeq(ns
->dev
);
717 spin_lock_irq(&nvmeq
->q_lock
);
718 if (bio_list_empty(&nvmeq
->sq_cong
))
719 result
= nvme_submit_bio_queue(nvmeq
, ns
, bio
);
720 if (unlikely(result
)) {
721 if (bio_list_empty(&nvmeq
->sq_cong
))
722 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
723 bio_list_add(&nvmeq
->sq_cong
, bio
);
726 spin_unlock_irq(&nvmeq
->q_lock
);
730 static irqreturn_t
nvme_process_cq(struct nvme_queue
*nvmeq
)
734 head
= nvmeq
->cq_head
;
735 phase
= nvmeq
->cq_phase
;
739 nvme_completion_fn fn
;
740 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
741 if ((le16_to_cpu(cqe
.status
) & 1) != phase
)
743 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
744 if (++head
== nvmeq
->q_depth
) {
749 ctx
= free_cmdid(nvmeq
, cqe
.command_id
, &fn
);
750 fn(nvmeq
->dev
, ctx
, &cqe
);
753 /* If the controller ignores the cq head doorbell and continuously
754 * writes to the queue, it is theoretically possible to wrap around
755 * the queue twice and mistakenly return IRQ_NONE. Linux only
756 * requires that 0.1% of your interrupts are handled, so this isn't
759 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
762 writel(head
, nvmeq
->q_db
+ (1 << nvmeq
->dev
->db_stride
));
763 nvmeq
->cq_head
= head
;
764 nvmeq
->cq_phase
= phase
;
769 static irqreturn_t
nvme_irq(int irq
, void *data
)
772 struct nvme_queue
*nvmeq
= data
;
773 spin_lock(&nvmeq
->q_lock
);
774 result
= nvme_process_cq(nvmeq
);
775 spin_unlock(&nvmeq
->q_lock
);
779 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
781 struct nvme_queue
*nvmeq
= data
;
782 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
783 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
785 return IRQ_WAKE_THREAD
;
788 static void nvme_abort_command(struct nvme_queue
*nvmeq
, int cmdid
)
790 spin_lock_irq(&nvmeq
->q_lock
);
791 cancel_cmdid(nvmeq
, cmdid
, NULL
);
792 spin_unlock_irq(&nvmeq
->q_lock
);
795 struct sync_cmd_info
{
796 struct task_struct
*task
;
801 static void sync_completion(struct nvme_dev
*dev
, void *ctx
,
802 struct nvme_completion
*cqe
)
804 struct sync_cmd_info
*cmdinfo
= ctx
;
805 cmdinfo
->result
= le32_to_cpup(&cqe
->result
);
806 cmdinfo
->status
= le16_to_cpup(&cqe
->status
) >> 1;
807 wake_up_process(cmdinfo
->task
);
811 * Returns 0 on success. If the result is negative, it's a Linux error code;
812 * if the result is positive, it's an NVM Express status code
814 int nvme_submit_sync_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
,
815 u32
*result
, unsigned timeout
)
818 struct sync_cmd_info cmdinfo
;
820 cmdinfo
.task
= current
;
821 cmdinfo
.status
= -EINTR
;
823 cmdid
= alloc_cmdid_killable(nvmeq
, &cmdinfo
, sync_completion
,
827 cmd
->common
.command_id
= cmdid
;
829 set_current_state(TASK_KILLABLE
);
830 nvme_submit_cmd(nvmeq
, cmd
);
831 schedule_timeout(timeout
);
833 if (cmdinfo
.status
== -EINTR
) {
834 nvme_abort_command(nvmeq
, cmdid
);
839 *result
= cmdinfo
.result
;
841 return cmdinfo
.status
;
844 int nvme_submit_admin_cmd(struct nvme_dev
*dev
, struct nvme_command
*cmd
,
847 return nvme_submit_sync_cmd(dev
->queues
[0], cmd
, result
, ADMIN_TIMEOUT
);
850 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
853 struct nvme_command c
;
855 memset(&c
, 0, sizeof(c
));
856 c
.delete_queue
.opcode
= opcode
;
857 c
.delete_queue
.qid
= cpu_to_le16(id
);
859 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
865 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
866 struct nvme_queue
*nvmeq
)
869 struct nvme_command c
;
870 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
872 memset(&c
, 0, sizeof(c
));
873 c
.create_cq
.opcode
= nvme_admin_create_cq
;
874 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
875 c
.create_cq
.cqid
= cpu_to_le16(qid
);
876 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
877 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
878 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
880 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
886 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
887 struct nvme_queue
*nvmeq
)
890 struct nvme_command c
;
891 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
893 memset(&c
, 0, sizeof(c
));
894 c
.create_sq
.opcode
= nvme_admin_create_sq
;
895 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
896 c
.create_sq
.sqid
= cpu_to_le16(qid
);
897 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
898 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
899 c
.create_sq
.cqid
= cpu_to_le16(qid
);
901 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
907 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
909 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
912 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
914 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
917 int nvme_identify(struct nvme_dev
*dev
, unsigned nsid
, unsigned cns
,
920 struct nvme_command c
;
922 memset(&c
, 0, sizeof(c
));
923 c
.identify
.opcode
= nvme_admin_identify
;
924 c
.identify
.nsid
= cpu_to_le32(nsid
);
925 c
.identify
.prp1
= cpu_to_le64(dma_addr
);
926 c
.identify
.cns
= cpu_to_le32(cns
);
928 return nvme_submit_admin_cmd(dev
, &c
, NULL
);
931 int nvme_get_features(struct nvme_dev
*dev
, unsigned fid
, unsigned nsid
,
932 dma_addr_t dma_addr
, u32
*result
)
934 struct nvme_command c
;
936 memset(&c
, 0, sizeof(c
));
937 c
.features
.opcode
= nvme_admin_get_features
;
938 c
.features
.nsid
= cpu_to_le32(nsid
);
939 c
.features
.prp1
= cpu_to_le64(dma_addr
);
940 c
.features
.fid
= cpu_to_le32(fid
);
942 return nvme_submit_admin_cmd(dev
, &c
, result
);
945 int nvme_set_features(struct nvme_dev
*dev
, unsigned fid
, unsigned dword11
,
946 dma_addr_t dma_addr
, u32
*result
)
948 struct nvme_command c
;
950 memset(&c
, 0, sizeof(c
));
951 c
.features
.opcode
= nvme_admin_set_features
;
952 c
.features
.prp1
= cpu_to_le64(dma_addr
);
953 c
.features
.fid
= cpu_to_le32(fid
);
954 c
.features
.dword11
= cpu_to_le32(dword11
);
956 return nvme_submit_admin_cmd(dev
, &c
, result
);
960 * nvme_cancel_ios - Cancel outstanding I/Os
961 * @queue: The queue to cancel I/Os on
962 * @timeout: True to only cancel I/Os which have timed out
964 static void nvme_cancel_ios(struct nvme_queue
*nvmeq
, bool timeout
)
966 int depth
= nvmeq
->q_depth
- 1;
967 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
968 unsigned long now
= jiffies
;
971 for_each_set_bit(cmdid
, nvmeq
->cmdid_data
, depth
) {
973 nvme_completion_fn fn
;
974 static struct nvme_completion cqe
= {
975 .status
= cpu_to_le16(NVME_SC_ABORT_REQ
<< 1),
978 if (timeout
&& !time_after(now
, info
[cmdid
].timeout
))
980 dev_warn(nvmeq
->q_dmadev
, "Cancelling I/O %d\n", cmdid
);
981 ctx
= cancel_cmdid(nvmeq
, cmdid
, &fn
);
982 fn(nvmeq
->dev
, ctx
, &cqe
);
986 static void nvme_free_queue_mem(struct nvme_queue
*nvmeq
)
988 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
989 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
990 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
991 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
995 static void nvme_free_queue(struct nvme_dev
*dev
, int qid
)
997 struct nvme_queue
*nvmeq
= dev
->queues
[qid
];
998 int vector
= dev
->entry
[nvmeq
->cq_vector
].vector
;
1000 spin_lock_irq(&nvmeq
->q_lock
);
1001 nvme_cancel_ios(nvmeq
, false);
1002 while (bio_list_peek(&nvmeq
->sq_cong
)) {
1003 struct bio
*bio
= bio_list_pop(&nvmeq
->sq_cong
);
1004 bio_endio(bio
, -EIO
);
1006 spin_unlock_irq(&nvmeq
->q_lock
);
1008 irq_set_affinity_hint(vector
, NULL
);
1009 free_irq(vector
, nvmeq
);
1011 /* Don't tell the adapter to delete the admin queue */
1013 adapter_delete_sq(dev
, qid
);
1014 adapter_delete_cq(dev
, qid
);
1017 nvme_free_queue_mem(nvmeq
);
1020 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1021 int depth
, int vector
)
1023 struct device
*dmadev
= &dev
->pci_dev
->dev
;
1024 unsigned extra
= DIV_ROUND_UP(depth
, 8) + (depth
*
1025 sizeof(struct nvme_cmd_info
));
1026 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
) + extra
, GFP_KERNEL
);
1030 nvmeq
->cqes
= dma_alloc_coherent(dmadev
, CQ_SIZE(depth
),
1031 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1034 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(depth
));
1036 nvmeq
->sq_cmds
= dma_alloc_coherent(dmadev
, SQ_SIZE(depth
),
1037 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1038 if (!nvmeq
->sq_cmds
)
1041 nvmeq
->q_dmadev
= dmadev
;
1043 spin_lock_init(&nvmeq
->q_lock
);
1045 nvmeq
->cq_phase
= 1;
1046 init_waitqueue_head(&nvmeq
->sq_full
);
1047 init_waitqueue_entry(&nvmeq
->sq_cong_wait
, nvme_thread
);
1048 bio_list_init(&nvmeq
->sq_cong
);
1049 nvmeq
->q_db
= &dev
->dbs
[qid
<< (dev
->db_stride
+ 1)];
1050 nvmeq
->q_depth
= depth
;
1051 nvmeq
->cq_vector
= vector
;
1056 dma_free_coherent(dmadev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1057 nvmeq
->cq_dma_addr
);
1063 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1066 if (use_threaded_interrupts
)
1067 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
1068 nvme_irq_check
, nvme_irq
,
1069 IRQF_DISABLED
| IRQF_SHARED
,
1071 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
1072 IRQF_DISABLED
| IRQF_SHARED
, name
, nvmeq
);
1075 static struct nvme_queue
*nvme_create_queue(struct nvme_dev
*dev
, int qid
,
1076 int cq_size
, int vector
)
1079 struct nvme_queue
*nvmeq
= nvme_alloc_queue(dev
, qid
, cq_size
, vector
);
1082 return ERR_PTR(-ENOMEM
);
1084 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1088 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1092 result
= queue_request_irq(dev
, nvmeq
, "nvme");
1099 adapter_delete_sq(dev
, qid
);
1101 adapter_delete_cq(dev
, qid
);
1103 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1104 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1105 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1106 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1108 return ERR_PTR(result
);
1111 static int nvme_wait_ready(struct nvme_dev
*dev
, u64 cap
, bool enabled
)
1113 unsigned long timeout
;
1114 u32 bit
= enabled
? NVME_CSTS_RDY
: 0;
1116 timeout
= ((NVME_CAP_TIMEOUT(cap
) + 1) * HZ
/ 2) + jiffies
;
1118 while ((readl(&dev
->bar
->csts
) & NVME_CSTS_RDY
) != bit
) {
1120 if (fatal_signal_pending(current
))
1122 if (time_after(jiffies
, timeout
)) {
1123 dev_err(&dev
->pci_dev
->dev
,
1124 "Device not ready; aborting initialisation\n");
1133 * If the device has been passed off to us in an enabled state, just clear
1134 * the enabled bit. The spec says we should set the 'shutdown notification
1135 * bits', but doing so may cause the device to complete commands to the
1136 * admin queue ... and we don't know what memory that might be pointing at!
1138 static int nvme_disable_ctrl(struct nvme_dev
*dev
, u64 cap
)
1140 u32 cc
= readl(&dev
->bar
->cc
);
1142 if (cc
& NVME_CC_ENABLE
)
1143 writel(cc
& ~NVME_CC_ENABLE
, &dev
->bar
->cc
);
1144 return nvme_wait_ready(dev
, cap
, false);
1147 static int nvme_enable_ctrl(struct nvme_dev
*dev
, u64 cap
)
1149 return nvme_wait_ready(dev
, cap
, true);
1152 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1156 u64 cap
= readq(&dev
->bar
->cap
);
1157 struct nvme_queue
*nvmeq
;
1159 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
1160 dev
->db_stride
= NVME_CAP_STRIDE(cap
);
1162 result
= nvme_disable_ctrl(dev
, cap
);
1166 nvmeq
= nvme_alloc_queue(dev
, 0, 64, 0);
1170 aqa
= nvmeq
->q_depth
- 1;
1173 dev
->ctrl_config
= NVME_CC_ENABLE
| NVME_CC_CSS_NVM
;
1174 dev
->ctrl_config
|= (PAGE_SHIFT
- 12) << NVME_CC_MPS_SHIFT
;
1175 dev
->ctrl_config
|= NVME_CC_ARB_RR
| NVME_CC_SHN_NONE
;
1176 dev
->ctrl_config
|= NVME_CC_IOSQES
| NVME_CC_IOCQES
;
1178 writel(aqa
, &dev
->bar
->aqa
);
1179 writeq(nvmeq
->sq_dma_addr
, &dev
->bar
->asq
);
1180 writeq(nvmeq
->cq_dma_addr
, &dev
->bar
->acq
);
1181 writel(dev
->ctrl_config
, &dev
->bar
->cc
);
1183 result
= nvme_enable_ctrl(dev
, cap
);
1187 result
= queue_request_irq(dev
, nvmeq
, "nvme admin");
1191 dev
->queues
[0] = nvmeq
;
1195 nvme_free_queue_mem(nvmeq
);
1199 struct nvme_iod
*nvme_map_user_pages(struct nvme_dev
*dev
, int write
,
1200 unsigned long addr
, unsigned length
)
1202 int i
, err
, count
, nents
, offset
;
1203 struct scatterlist
*sg
;
1204 struct page
**pages
;
1205 struct nvme_iod
*iod
;
1208 return ERR_PTR(-EINVAL
);
1210 return ERR_PTR(-EINVAL
);
1212 offset
= offset_in_page(addr
);
1213 count
= DIV_ROUND_UP(offset
+ length
, PAGE_SIZE
);
1214 pages
= kcalloc(count
, sizeof(*pages
), GFP_KERNEL
);
1216 return ERR_PTR(-ENOMEM
);
1218 err
= get_user_pages_fast(addr
, count
, 1, pages
);
1225 iod
= nvme_alloc_iod(count
, length
, GFP_KERNEL
);
1227 sg_init_table(sg
, count
);
1228 for (i
= 0; i
< count
; i
++) {
1229 sg_set_page(&sg
[i
], pages
[i
],
1230 min_t(int, length
, PAGE_SIZE
- offset
), offset
);
1231 length
-= (PAGE_SIZE
- offset
);
1234 sg_mark_end(&sg
[i
- 1]);
1238 nents
= dma_map_sg(&dev
->pci_dev
->dev
, sg
, count
,
1239 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1249 for (i
= 0; i
< count
; i
++)
1252 return ERR_PTR(err
);
1255 void nvme_unmap_user_pages(struct nvme_dev
*dev
, int write
,
1256 struct nvme_iod
*iod
)
1260 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
1261 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1263 for (i
= 0; i
< iod
->nents
; i
++)
1264 put_page(sg_page(&iod
->sg
[i
]));
1267 static int nvme_submit_io(struct nvme_ns
*ns
, struct nvme_user_io __user
*uio
)
1269 struct nvme_dev
*dev
= ns
->dev
;
1270 struct nvme_queue
*nvmeq
;
1271 struct nvme_user_io io
;
1272 struct nvme_command c
;
1273 unsigned length
, meta_len
;
1275 struct nvme_iod
*iod
, *meta_iod
= NULL
;
1276 dma_addr_t meta_dma_addr
;
1277 void *meta
, *uninitialized_var(meta_mem
);
1279 if (copy_from_user(&io
, uio
, sizeof(io
)))
1281 length
= (io
.nblocks
+ 1) << ns
->lba_shift
;
1282 meta_len
= (io
.nblocks
+ 1) * ns
->ms
;
1284 if (meta_len
&& ((io
.metadata
& 3) || !io
.metadata
))
1287 switch (io
.opcode
) {
1288 case nvme_cmd_write
:
1290 case nvme_cmd_compare
:
1291 iod
= nvme_map_user_pages(dev
, io
.opcode
& 1, io
.addr
, length
);
1298 return PTR_ERR(iod
);
1300 memset(&c
, 0, sizeof(c
));
1301 c
.rw
.opcode
= io
.opcode
;
1302 c
.rw
.flags
= io
.flags
;
1303 c
.rw
.nsid
= cpu_to_le32(ns
->ns_id
);
1304 c
.rw
.slba
= cpu_to_le64(io
.slba
);
1305 c
.rw
.length
= cpu_to_le16(io
.nblocks
);
1306 c
.rw
.control
= cpu_to_le16(io
.control
);
1307 c
.rw
.dsmgmt
= cpu_to_le32(io
.dsmgmt
);
1308 c
.rw
.reftag
= cpu_to_le32(io
.reftag
);
1309 c
.rw
.apptag
= cpu_to_le16(io
.apptag
);
1310 c
.rw
.appmask
= cpu_to_le16(io
.appmask
);
1313 meta_iod
= nvme_map_user_pages(dev
, io
.opcode
& 1, io
.metadata
, meta_len
);
1314 if (IS_ERR(meta_iod
)) {
1315 status
= PTR_ERR(meta_iod
);
1320 meta_mem
= dma_alloc_coherent(&dev
->pci_dev
->dev
, meta_len
,
1321 &meta_dma_addr
, GFP_KERNEL
);
1327 if (io
.opcode
& 1) {
1328 int meta_offset
= 0;
1330 for (i
= 0; i
< meta_iod
->nents
; i
++) {
1331 meta
= kmap_atomic(sg_page(&meta_iod
->sg
[i
])) +
1332 meta_iod
->sg
[i
].offset
;
1333 memcpy(meta_mem
+ meta_offset
, meta
,
1334 meta_iod
->sg
[i
].length
);
1335 kunmap_atomic(meta
);
1336 meta_offset
+= meta_iod
->sg
[i
].length
;
1340 c
.rw
.metadata
= cpu_to_le64(meta_dma_addr
);
1343 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
, GFP_KERNEL
);
1345 nvmeq
= get_nvmeq(dev
);
1347 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1348 * disabled. We may be preempted at any point, and be rescheduled
1349 * to a different CPU. That will cause cacheline bouncing, but no
1350 * additional races since q_lock already protects against other CPUs.
1353 if (length
!= (io
.nblocks
+ 1) << ns
->lba_shift
)
1356 status
= nvme_submit_sync_cmd(nvmeq
, &c
, NULL
, NVME_IO_TIMEOUT
);
1359 if (status
== NVME_SC_SUCCESS
&& !(io
.opcode
& 1)) {
1360 int meta_offset
= 0;
1362 for (i
= 0; i
< meta_iod
->nents
; i
++) {
1363 meta
= kmap_atomic(sg_page(&meta_iod
->sg
[i
])) +
1364 meta_iod
->sg
[i
].offset
;
1365 memcpy(meta
, meta_mem
+ meta_offset
,
1366 meta_iod
->sg
[i
].length
);
1367 kunmap_atomic(meta
);
1368 meta_offset
+= meta_iod
->sg
[i
].length
;
1372 dma_free_coherent(&dev
->pci_dev
->dev
, meta_len
, meta_mem
,
1377 nvme_unmap_user_pages(dev
, io
.opcode
& 1, iod
);
1378 nvme_free_iod(dev
, iod
);
1381 nvme_unmap_user_pages(dev
, io
.opcode
& 1, meta_iod
);
1382 nvme_free_iod(dev
, meta_iod
);
1388 static int nvme_user_admin_cmd(struct nvme_dev
*dev
,
1389 struct nvme_admin_cmd __user
*ucmd
)
1391 struct nvme_admin_cmd cmd
;
1392 struct nvme_command c
;
1394 struct nvme_iod
*uninitialized_var(iod
);
1397 if (!capable(CAP_SYS_ADMIN
))
1399 if (copy_from_user(&cmd
, ucmd
, sizeof(cmd
)))
1402 memset(&c
, 0, sizeof(c
));
1403 c
.common
.opcode
= cmd
.opcode
;
1404 c
.common
.flags
= cmd
.flags
;
1405 c
.common
.nsid
= cpu_to_le32(cmd
.nsid
);
1406 c
.common
.cdw2
[0] = cpu_to_le32(cmd
.cdw2
);
1407 c
.common
.cdw2
[1] = cpu_to_le32(cmd
.cdw3
);
1408 c
.common
.cdw10
[0] = cpu_to_le32(cmd
.cdw10
);
1409 c
.common
.cdw10
[1] = cpu_to_le32(cmd
.cdw11
);
1410 c
.common
.cdw10
[2] = cpu_to_le32(cmd
.cdw12
);
1411 c
.common
.cdw10
[3] = cpu_to_le32(cmd
.cdw13
);
1412 c
.common
.cdw10
[4] = cpu_to_le32(cmd
.cdw14
);
1413 c
.common
.cdw10
[5] = cpu_to_le32(cmd
.cdw15
);
1415 length
= cmd
.data_len
;
1417 iod
= nvme_map_user_pages(dev
, cmd
.opcode
& 1, cmd
.addr
,
1420 return PTR_ERR(iod
);
1421 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
,
1425 timeout
= cmd
.timeout_ms
? msecs_to_jiffies(cmd
.timeout_ms
) :
1427 if (length
!= cmd
.data_len
)
1430 status
= nvme_submit_sync_cmd(dev
->queues
[0], &c
, &cmd
.result
,
1434 nvme_unmap_user_pages(dev
, cmd
.opcode
& 1, iod
);
1435 nvme_free_iod(dev
, iod
);
1438 if (!status
&& copy_to_user(&ucmd
->result
, &cmd
.result
,
1439 sizeof(cmd
.result
)))
1445 static int nvme_ioctl(struct block_device
*bdev
, fmode_t mode
, unsigned int cmd
,
1448 struct nvme_ns
*ns
= bdev
->bd_disk
->private_data
;
1453 case NVME_IOCTL_ADMIN_CMD
:
1454 return nvme_user_admin_cmd(ns
->dev
, (void __user
*)arg
);
1455 case NVME_IOCTL_SUBMIT_IO
:
1456 return nvme_submit_io(ns
, (void __user
*)arg
);
1457 case SG_GET_VERSION_NUM
:
1458 return nvme_sg_get_version_num((void __user
*)arg
);
1460 return nvme_sg_io(ns
, (void __user
*)arg
);
1466 static const struct block_device_operations nvme_fops
= {
1467 .owner
= THIS_MODULE
,
1468 .ioctl
= nvme_ioctl
,
1469 .compat_ioctl
= nvme_ioctl
,
1472 static void nvme_resubmit_bios(struct nvme_queue
*nvmeq
)
1474 while (bio_list_peek(&nvmeq
->sq_cong
)) {
1475 struct bio
*bio
= bio_list_pop(&nvmeq
->sq_cong
);
1476 struct nvme_ns
*ns
= bio
->bi_bdev
->bd_disk
->private_data
;
1478 if (bio_list_empty(&nvmeq
->sq_cong
))
1479 remove_wait_queue(&nvmeq
->sq_full
,
1480 &nvmeq
->sq_cong_wait
);
1481 if (nvme_submit_bio_queue(nvmeq
, ns
, bio
)) {
1482 if (bio_list_empty(&nvmeq
->sq_cong
))
1483 add_wait_queue(&nvmeq
->sq_full
,
1484 &nvmeq
->sq_cong_wait
);
1485 bio_list_add_head(&nvmeq
->sq_cong
, bio
);
1491 static int nvme_kthread(void *data
)
1493 struct nvme_dev
*dev
;
1495 while (!kthread_should_stop()) {
1496 set_current_state(TASK_INTERRUPTIBLE
);
1497 spin_lock(&dev_list_lock
);
1498 list_for_each_entry(dev
, &dev_list
, node
) {
1500 for (i
= 0; i
< dev
->queue_count
; i
++) {
1501 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1504 spin_lock_irq(&nvmeq
->q_lock
);
1505 if (nvme_process_cq(nvmeq
))
1506 printk("process_cq did something\n");
1507 nvme_cancel_ios(nvmeq
, true);
1508 nvme_resubmit_bios(nvmeq
);
1509 spin_unlock_irq(&nvmeq
->q_lock
);
1512 spin_unlock(&dev_list_lock
);
1513 schedule_timeout(round_jiffies_relative(HZ
));
1518 static DEFINE_IDA(nvme_index_ida
);
1520 static int nvme_get_ns_idx(void)
1525 if (!ida_pre_get(&nvme_index_ida
, GFP_KERNEL
))
1528 spin_lock(&dev_list_lock
);
1529 error
= ida_get_new(&nvme_index_ida
, &index
);
1530 spin_unlock(&dev_list_lock
);
1531 } while (error
== -EAGAIN
);
1538 static void nvme_put_ns_idx(int index
)
1540 spin_lock(&dev_list_lock
);
1541 ida_remove(&nvme_index_ida
, index
);
1542 spin_unlock(&dev_list_lock
);
1545 static void nvme_config_discard(struct nvme_ns
*ns
)
1547 u32 logical_block_size
= queue_logical_block_size(ns
->queue
);
1548 ns
->queue
->limits
.discard_zeroes_data
= 0;
1549 ns
->queue
->limits
.discard_alignment
= logical_block_size
;
1550 ns
->queue
->limits
.discard_granularity
= logical_block_size
;
1551 ns
->queue
->limits
.max_discard_sectors
= 0xffffffff;
1552 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD
, ns
->queue
);
1555 static struct nvme_ns
*nvme_alloc_ns(struct nvme_dev
*dev
, int nsid
,
1556 struct nvme_id_ns
*id
, struct nvme_lba_range_type
*rt
)
1559 struct gendisk
*disk
;
1562 if (rt
->attributes
& NVME_LBART_ATTRIB_HIDE
)
1565 ns
= kzalloc(sizeof(*ns
), GFP_KERNEL
);
1568 ns
->queue
= blk_alloc_queue(GFP_KERNEL
);
1571 ns
->queue
->queue_flags
= QUEUE_FLAG_DEFAULT
;
1572 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES
, ns
->queue
);
1573 queue_flag_set_unlocked(QUEUE_FLAG_NONROT
, ns
->queue
);
1574 blk_queue_make_request(ns
->queue
, nvme_make_request
);
1576 ns
->queue
->queuedata
= ns
;
1578 disk
= alloc_disk(NVME_MINORS
);
1580 goto out_free_queue
;
1583 lbaf
= id
->flbas
& 0xf;
1584 ns
->lba_shift
= id
->lbaf
[lbaf
].ds
;
1585 ns
->ms
= le16_to_cpu(id
->lbaf
[lbaf
].ms
);
1586 blk_queue_logical_block_size(ns
->queue
, 1 << ns
->lba_shift
);
1587 if (dev
->max_hw_sectors
)
1588 blk_queue_max_hw_sectors(ns
->queue
, dev
->max_hw_sectors
);
1590 disk
->major
= nvme_major
;
1591 disk
->minors
= NVME_MINORS
;
1592 disk
->first_minor
= NVME_MINORS
* nvme_get_ns_idx();
1593 disk
->fops
= &nvme_fops
;
1594 disk
->private_data
= ns
;
1595 disk
->queue
= ns
->queue
;
1596 disk
->driverfs_dev
= &dev
->pci_dev
->dev
;
1597 sprintf(disk
->disk_name
, "nvme%dn%d", dev
->instance
, nsid
);
1598 set_capacity(disk
, le64_to_cpup(&id
->nsze
) << (ns
->lba_shift
- 9));
1600 if (dev
->oncs
& NVME_CTRL_ONCS_DSM
)
1601 nvme_config_discard(ns
);
1606 blk_cleanup_queue(ns
->queue
);
1612 static void nvme_ns_free(struct nvme_ns
*ns
)
1614 int index
= ns
->disk
->first_minor
/ NVME_MINORS
;
1616 nvme_put_ns_idx(index
);
1617 blk_cleanup_queue(ns
->queue
);
1621 static int set_queue_count(struct nvme_dev
*dev
, int count
)
1625 u32 q_count
= (count
- 1) | ((count
- 1) << 16);
1627 status
= nvme_set_features(dev
, NVME_FEAT_NUM_QUEUES
, q_count
, 0,
1631 return min(result
& 0xffff, result
>> 16) + 1;
1634 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1636 int result
, cpu
, i
, nr_io_queues
, db_bar_size
, q_depth
;
1638 nr_io_queues
= num_online_cpus();
1639 result
= set_queue_count(dev
, nr_io_queues
);
1642 if (result
< nr_io_queues
)
1643 nr_io_queues
= result
;
1645 /* Deregister the admin queue's interrupt */
1646 free_irq(dev
->entry
[0].vector
, dev
->queues
[0]);
1648 db_bar_size
= 4096 + ((nr_io_queues
+ 1) << (dev
->db_stride
+ 3));
1649 if (db_bar_size
> 8192) {
1651 dev
->bar
= ioremap(pci_resource_start(dev
->pci_dev
, 0),
1653 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
1654 dev
->queues
[0]->q_db
= dev
->dbs
;
1657 for (i
= 0; i
< nr_io_queues
; i
++)
1658 dev
->entry
[i
].entry
= i
;
1660 result
= pci_enable_msix(dev
->pci_dev
, dev
->entry
,
1664 } else if (result
> 0) {
1665 nr_io_queues
= result
;
1673 result
= queue_request_irq(dev
, dev
->queues
[0], "nvme admin");
1674 /* XXX: handle failure here */
1676 cpu
= cpumask_first(cpu_online_mask
);
1677 for (i
= 0; i
< nr_io_queues
; i
++) {
1678 irq_set_affinity_hint(dev
->entry
[i
].vector
, get_cpu_mask(cpu
));
1679 cpu
= cpumask_next(cpu
, cpu_online_mask
);
1682 q_depth
= min_t(int, NVME_CAP_MQES(readq(&dev
->bar
->cap
)) + 1,
1684 for (i
= 0; i
< nr_io_queues
; i
++) {
1685 dev
->queues
[i
+ 1] = nvme_create_queue(dev
, i
+ 1, q_depth
, i
);
1686 if (IS_ERR(dev
->queues
[i
+ 1]))
1687 return PTR_ERR(dev
->queues
[i
+ 1]);
1691 for (; i
< num_possible_cpus(); i
++) {
1692 int target
= i
% rounddown_pow_of_two(dev
->queue_count
- 1);
1693 dev
->queues
[i
+ 1] = dev
->queues
[target
+ 1];
1699 static void nvme_free_queues(struct nvme_dev
*dev
)
1703 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
1704 nvme_free_queue(dev
, i
);
1708 * Return: error value if an error occurred setting up the queues or calling
1709 * Identify Device. 0 if these succeeded, even if adding some of the
1710 * namespaces failed. At the moment, these failures are silent. TBD which
1711 * failures should be reported.
1713 static int nvme_dev_add(struct nvme_dev
*dev
)
1717 struct nvme_id_ctrl
*ctrl
;
1718 struct nvme_id_ns
*id_ns
;
1720 dma_addr_t dma_addr
;
1721 int shift
= NVME_CAP_MPSMIN(readq(&dev
->bar
->cap
)) + 12;
1723 res
= nvme_setup_io_queues(dev
);
1727 mem
= dma_alloc_coherent(&dev
->pci_dev
->dev
, 8192, &dma_addr
,
1732 res
= nvme_identify(dev
, 0, 1, dma_addr
);
1739 nn
= le32_to_cpup(&ctrl
->nn
);
1740 dev
->oncs
= le16_to_cpup(&ctrl
->oncs
);
1741 memcpy(dev
->serial
, ctrl
->sn
, sizeof(ctrl
->sn
));
1742 memcpy(dev
->model
, ctrl
->mn
, sizeof(ctrl
->mn
));
1743 memcpy(dev
->firmware_rev
, ctrl
->fr
, sizeof(ctrl
->fr
));
1745 dev
->max_hw_sectors
= 1 << (ctrl
->mdts
+ shift
- 9);
1746 if ((dev
->pci_dev
->vendor
== PCI_VENDOR_ID_INTEL
) &&
1747 (dev
->pci_dev
->device
== 0x0953) && ctrl
->vs
[3])
1748 dev
->stripe_size
= 1 << (ctrl
->vs
[3] + shift
);
1751 for (i
= 1; i
<= nn
; i
++) {
1752 res
= nvme_identify(dev
, i
, 0, dma_addr
);
1756 if (id_ns
->ncap
== 0)
1759 res
= nvme_get_features(dev
, NVME_FEAT_LBA_RANGE
, i
,
1760 dma_addr
+ 4096, NULL
);
1762 memset(mem
+ 4096, 0, 4096);
1764 ns
= nvme_alloc_ns(dev
, i
, mem
, mem
+ 4096);
1766 list_add_tail(&ns
->list
, &dev
->namespaces
);
1768 list_for_each_entry(ns
, &dev
->namespaces
, list
)
1773 dma_free_coherent(&dev
->pci_dev
->dev
, 8192, mem
, dma_addr
);
1777 static int nvme_dev_remove(struct nvme_dev
*dev
)
1779 struct nvme_ns
*ns
, *next
;
1781 spin_lock(&dev_list_lock
);
1782 list_del(&dev
->node
);
1783 spin_unlock(&dev_list_lock
);
1785 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1786 list_del(&ns
->list
);
1787 del_gendisk(ns
->disk
);
1791 nvme_free_queues(dev
);
1796 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1798 struct device
*dmadev
= &dev
->pci_dev
->dev
;
1799 dev
->prp_page_pool
= dma_pool_create("prp list page", dmadev
,
1800 PAGE_SIZE
, PAGE_SIZE
, 0);
1801 if (!dev
->prp_page_pool
)
1804 /* Optimisation for I/Os between 4k and 128k */
1805 dev
->prp_small_pool
= dma_pool_create("prp list 256", dmadev
,
1807 if (!dev
->prp_small_pool
) {
1808 dma_pool_destroy(dev
->prp_page_pool
);
1814 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1816 dma_pool_destroy(dev
->prp_page_pool
);
1817 dma_pool_destroy(dev
->prp_small_pool
);
1820 static DEFINE_IDA(nvme_instance_ida
);
1822 static int nvme_set_instance(struct nvme_dev
*dev
)
1824 int instance
, error
;
1827 if (!ida_pre_get(&nvme_instance_ida
, GFP_KERNEL
))
1830 spin_lock(&dev_list_lock
);
1831 error
= ida_get_new(&nvme_instance_ida
, &instance
);
1832 spin_unlock(&dev_list_lock
);
1833 } while (error
== -EAGAIN
);
1838 dev
->instance
= instance
;
1842 static void nvme_release_instance(struct nvme_dev
*dev
)
1844 spin_lock(&dev_list_lock
);
1845 ida_remove(&nvme_instance_ida
, dev
->instance
);
1846 spin_unlock(&dev_list_lock
);
1849 static void nvme_free_dev(struct kref
*kref
)
1851 struct nvme_dev
*dev
= container_of(kref
, struct nvme_dev
, kref
);
1852 nvme_dev_remove(dev
);
1853 pci_disable_msix(dev
->pci_dev
);
1855 nvme_release_instance(dev
);
1856 nvme_release_prp_pools(dev
);
1857 pci_disable_device(dev
->pci_dev
);
1858 pci_release_regions(dev
->pci_dev
);
1864 static int nvme_dev_open(struct inode
*inode
, struct file
*f
)
1866 struct nvme_dev
*dev
= container_of(f
->private_data
, struct nvme_dev
,
1868 kref_get(&dev
->kref
);
1869 f
->private_data
= dev
;
1873 static int nvme_dev_release(struct inode
*inode
, struct file
*f
)
1875 struct nvme_dev
*dev
= f
->private_data
;
1876 kref_put(&dev
->kref
, nvme_free_dev
);
1880 static long nvme_dev_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
1882 struct nvme_dev
*dev
= f
->private_data
;
1884 case NVME_IOCTL_ADMIN_CMD
:
1885 return nvme_user_admin_cmd(dev
, (void __user
*)arg
);
1891 static const struct file_operations nvme_dev_fops
= {
1892 .owner
= THIS_MODULE
,
1893 .open
= nvme_dev_open
,
1894 .release
= nvme_dev_release
,
1895 .unlocked_ioctl
= nvme_dev_ioctl
,
1896 .compat_ioctl
= nvme_dev_ioctl
,
1899 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1901 int bars
, result
= -ENOMEM
;
1902 struct nvme_dev
*dev
;
1904 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1907 dev
->entry
= kcalloc(num_possible_cpus(), sizeof(*dev
->entry
),
1911 dev
->queues
= kcalloc(num_possible_cpus() + 1, sizeof(void *),
1916 if (pci_enable_device_mem(pdev
))
1918 pci_set_master(pdev
);
1919 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1920 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1923 INIT_LIST_HEAD(&dev
->namespaces
);
1924 dev
->pci_dev
= pdev
;
1925 pci_set_drvdata(pdev
, dev
);
1926 dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1927 dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1928 result
= nvme_set_instance(dev
);
1932 dev
->entry
[0].vector
= pdev
->irq
;
1934 result
= nvme_setup_prp_pools(dev
);
1938 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1944 result
= nvme_configure_admin_queue(dev
);
1949 spin_lock(&dev_list_lock
);
1950 list_add(&dev
->node
, &dev_list
);
1951 spin_unlock(&dev_list_lock
);
1953 result
= nvme_dev_add(dev
);
1957 scnprintf(dev
->name
, sizeof(dev
->name
), "nvme%d", dev
->instance
);
1958 dev
->miscdev
.minor
= MISC_DYNAMIC_MINOR
;
1959 dev
->miscdev
.parent
= &pdev
->dev
;
1960 dev
->miscdev
.name
= dev
->name
;
1961 dev
->miscdev
.fops
= &nvme_dev_fops
;
1962 result
= misc_register(&dev
->miscdev
);
1966 kref_init(&dev
->kref
);
1970 nvme_dev_remove(dev
);
1972 spin_lock(&dev_list_lock
);
1973 list_del(&dev
->node
);
1974 spin_unlock(&dev_list_lock
);
1976 nvme_free_queues(dev
);
1980 pci_disable_msix(pdev
);
1981 nvme_release_instance(dev
);
1982 nvme_release_prp_pools(dev
);
1984 pci_disable_device(pdev
);
1985 pci_release_regions(pdev
);
1993 static void nvme_remove(struct pci_dev
*pdev
)
1995 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
1996 misc_deregister(&dev
->miscdev
);
1997 kref_put(&dev
->kref
, nvme_free_dev
);
2000 /* These functions are yet to be implemented */
2001 #define nvme_error_detected NULL
2002 #define nvme_dump_registers NULL
2003 #define nvme_link_reset NULL
2004 #define nvme_slot_reset NULL
2005 #define nvme_error_resume NULL
2006 #define nvme_suspend NULL
2007 #define nvme_resume NULL
2009 static const struct pci_error_handlers nvme_err_handler
= {
2010 .error_detected
= nvme_error_detected
,
2011 .mmio_enabled
= nvme_dump_registers
,
2012 .link_reset
= nvme_link_reset
,
2013 .slot_reset
= nvme_slot_reset
,
2014 .resume
= nvme_error_resume
,
2017 /* Move to pci_ids.h later */
2018 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2020 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table
) = {
2021 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2024 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2026 static struct pci_driver nvme_driver
= {
2028 .id_table
= nvme_id_table
,
2029 .probe
= nvme_probe
,
2030 .remove
= nvme_remove
,
2031 .suspend
= nvme_suspend
,
2032 .resume
= nvme_resume
,
2033 .err_handler
= &nvme_err_handler
,
2036 static int __init
nvme_init(void)
2040 nvme_thread
= kthread_run(nvme_kthread
, NULL
, "nvme");
2041 if (IS_ERR(nvme_thread
))
2042 return PTR_ERR(nvme_thread
);
2044 result
= register_blkdev(nvme_major
, "nvme");
2047 else if (result
> 0)
2048 nvme_major
= result
;
2050 result
= pci_register_driver(&nvme_driver
);
2052 goto unregister_blkdev
;
2056 unregister_blkdev(nvme_major
, "nvme");
2058 kthread_stop(nvme_thread
);
2062 static void __exit
nvme_exit(void)
2064 pci_unregister_driver(&nvme_driver
);
2065 unregister_blkdev(nvme_major
, "nvme");
2066 kthread_stop(nvme_thread
);
2069 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2070 MODULE_LICENSE("GPL");
2071 MODULE_VERSION("0.8");
2072 module_init(nvme_init
);
2073 module_exit(nvme_exit
);