2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/version.h>
44 #define NVME_Q_DEPTH 1024
45 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
46 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
47 #define NVME_MINORS 64
48 #define NVME_IO_TIMEOUT (5 * HZ)
49 #define ADMIN_TIMEOUT (60 * HZ)
51 static int nvme_major
;
52 module_param(nvme_major
, int, 0);
54 static int use_threaded_interrupts
;
55 module_param(use_threaded_interrupts
, int, 0);
57 static DEFINE_SPINLOCK(dev_list_lock
);
58 static LIST_HEAD(dev_list
);
59 static struct task_struct
*nvme_thread
;
62 * Represents an NVM Express device. Each nvme_dev is a PCI function.
65 struct list_head node
;
66 struct nvme_queue
**queues
;
68 struct pci_dev
*pci_dev
;
69 struct dma_pool
*prp_page_pool
;
70 struct dma_pool
*prp_small_pool
;
75 struct msix_entry
*entry
;
76 struct nvme_bar __iomem
*bar
;
77 struct list_head namespaces
;
85 * An NVM Express namespace is equivalent to a SCSI LUN
88 struct list_head list
;
91 struct request_queue
*queue
;
99 * An NVM Express queue. Each device has at least two (one for admin
100 * commands and one for I/O commands).
103 struct device
*q_dmadev
;
104 struct nvme_dev
*dev
;
106 struct nvme_command
*sq_cmds
;
107 volatile struct nvme_completion
*cqes
;
108 dma_addr_t sq_dma_addr
;
109 dma_addr_t cq_dma_addr
;
110 wait_queue_head_t sq_full
;
111 wait_queue_t sq_cong_wait
;
112 struct bio_list sq_cong
;
120 unsigned long cmdid_data
[];
124 * Check we didin't inadvertently grow the command struct
126 static inline void _nvme_check_size(void)
128 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
132 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
136 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
139 typedef void (*nvme_completion_fn
)(struct nvme_dev
*, void *,
140 struct nvme_completion
*);
142 struct nvme_cmd_info
{
143 nvme_completion_fn fn
;
145 unsigned long timeout
;
148 static struct nvme_cmd_info
*nvme_cmd_info(struct nvme_queue
*nvmeq
)
150 return (void *)&nvmeq
->cmdid_data
[BITS_TO_LONGS(nvmeq
->q_depth
)];
154 * alloc_cmdid() - Allocate a Command ID
155 * @nvmeq: The queue that will be used for this command
156 * @ctx: A pointer that will be passed to the handler
157 * @handler: The function to call on completion
159 * Allocate a Command ID for a queue. The data passed in will
160 * be passed to the completion handler. This is implemented by using
161 * the bottom two bits of the ctx pointer to store the handler ID.
162 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
163 * We can change this if it becomes a problem.
165 * May be called with local interrupts disabled and the q_lock held,
166 * or with interrupts enabled and no locks held.
168 static int alloc_cmdid(struct nvme_queue
*nvmeq
, void *ctx
,
169 nvme_completion_fn handler
, unsigned timeout
)
171 int depth
= nvmeq
->q_depth
- 1;
172 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
176 cmdid
= find_first_zero_bit(nvmeq
->cmdid_data
, depth
);
179 } while (test_and_set_bit(cmdid
, nvmeq
->cmdid_data
));
181 info
[cmdid
].fn
= handler
;
182 info
[cmdid
].ctx
= ctx
;
183 info
[cmdid
].timeout
= jiffies
+ timeout
;
187 static int alloc_cmdid_killable(struct nvme_queue
*nvmeq
, void *ctx
,
188 nvme_completion_fn handler
, unsigned timeout
)
191 wait_event_killable(nvmeq
->sq_full
,
192 (cmdid
= alloc_cmdid(nvmeq
, ctx
, handler
, timeout
)) >= 0);
193 return (cmdid
< 0) ? -EINTR
: cmdid
;
196 /* Special values must be less than 0x1000 */
197 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
198 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
199 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
200 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
201 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
203 static void special_completion(struct nvme_dev
*dev
, void *ctx
,
204 struct nvme_completion
*cqe
)
206 if (ctx
== CMD_CTX_CANCELLED
)
208 if (ctx
== CMD_CTX_FLUSH
)
210 if (ctx
== CMD_CTX_COMPLETED
) {
211 dev_warn(&dev
->pci_dev
->dev
,
212 "completed id %d twice on queue %d\n",
213 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
216 if (ctx
== CMD_CTX_INVALID
) {
217 dev_warn(&dev
->pci_dev
->dev
,
218 "invalid id %d completed on queue %d\n",
219 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
223 dev_warn(&dev
->pci_dev
->dev
, "Unknown special completion %p\n", ctx
);
227 * Called with local interrupts disabled and the q_lock held. May not sleep.
229 static void *free_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
230 nvme_completion_fn
*fn
)
233 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
235 if (cmdid
>= nvmeq
->q_depth
) {
236 *fn
= special_completion
;
237 return CMD_CTX_INVALID
;
239 *fn
= info
[cmdid
].fn
;
240 ctx
= info
[cmdid
].ctx
;
241 info
[cmdid
].fn
= special_completion
;
242 info
[cmdid
].ctx
= CMD_CTX_COMPLETED
;
243 clear_bit(cmdid
, nvmeq
->cmdid_data
);
244 wake_up(&nvmeq
->sq_full
);
248 static void *cancel_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
249 nvme_completion_fn
*fn
)
252 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
254 *fn
= info
[cmdid
].fn
;
255 ctx
= info
[cmdid
].ctx
;
256 info
[cmdid
].fn
= special_completion
;
257 info
[cmdid
].ctx
= CMD_CTX_CANCELLED
;
261 static struct nvme_queue
*get_nvmeq(struct nvme_dev
*dev
)
263 return dev
->queues
[get_cpu() + 1];
266 static void put_nvmeq(struct nvme_queue
*nvmeq
)
272 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
273 * @nvmeq: The queue to use
274 * @cmd: The command to send
276 * Safe to use from interrupt context
278 static int nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
)
282 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
283 tail
= nvmeq
->sq_tail
;
284 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
285 if (++tail
== nvmeq
->q_depth
)
287 writel(tail
, nvmeq
->q_db
);
288 nvmeq
->sq_tail
= tail
;
289 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
295 * The nvme_iod describes the data in an I/O, including the list of PRP
296 * entries. You can't see it in this data structure because C doesn't let
297 * me express that. Use nvme_alloc_iod to ensure there's enough space
298 * allocated to store the PRP list.
301 void *private; /* For the use of the submitter of the I/O */
302 int npages
; /* In the PRP list. 0 means small pool in use */
303 int offset
; /* Of PRP list */
304 int nents
; /* Used in scatterlist */
305 int length
; /* Of data, in bytes */
306 dma_addr_t first_dma
;
307 struct scatterlist sg
[0];
310 static __le64
**iod_list(struct nvme_iod
*iod
)
312 return ((void *)iod
) + iod
->offset
;
316 * Will slightly overestimate the number of pages needed. This is OK
317 * as it only leads to a small amount of wasted memory for the lifetime of
320 static int nvme_npages(unsigned size
)
322 unsigned nprps
= DIV_ROUND_UP(size
+ PAGE_SIZE
, PAGE_SIZE
);
323 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
326 static struct nvme_iod
*
327 nvme_alloc_iod(unsigned nseg
, unsigned nbytes
, gfp_t gfp
)
329 struct nvme_iod
*iod
= kmalloc(sizeof(struct nvme_iod
) +
330 sizeof(__le64
*) * nvme_npages(nbytes
) +
331 sizeof(struct scatterlist
) * nseg
, gfp
);
334 iod
->offset
= offsetof(struct nvme_iod
, sg
[nseg
]);
336 iod
->length
= nbytes
;
342 static void nvme_free_iod(struct nvme_dev
*dev
, struct nvme_iod
*iod
)
344 const int last_prp
= PAGE_SIZE
/ 8 - 1;
346 __le64
**list
= iod_list(iod
);
347 dma_addr_t prp_dma
= iod
->first_dma
;
349 if (iod
->npages
== 0)
350 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
351 for (i
= 0; i
< iod
->npages
; i
++) {
352 __le64
*prp_list
= list
[i
];
353 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
354 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
355 prp_dma
= next_prp_dma
;
360 static void requeue_bio(struct nvme_dev
*dev
, struct bio
*bio
)
362 struct nvme_queue
*nvmeq
= get_nvmeq(dev
);
363 if (bio_list_empty(&nvmeq
->sq_cong
))
364 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
365 bio_list_add(&nvmeq
->sq_cong
, bio
);
367 wake_up_process(nvme_thread
);
370 static void bio_completion(struct nvme_dev
*dev
, void *ctx
,
371 struct nvme_completion
*cqe
)
373 struct nvme_iod
*iod
= ctx
;
374 struct bio
*bio
= iod
->private;
375 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
377 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
378 bio_data_dir(bio
) ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
379 nvme_free_iod(dev
, iod
);
381 bio_endio(bio
, -EIO
);
382 } else if (bio
->bi_vcnt
> bio
->bi_idx
) {
383 requeue_bio(dev
, bio
);
389 /* length is in bytes. gfp flags indicates whether we may sleep. */
390 static int nvme_setup_prps(struct nvme_dev
*dev
,
391 struct nvme_common_command
*cmd
, struct nvme_iod
*iod
,
392 int total_len
, gfp_t gfp
)
394 struct dma_pool
*pool
;
395 int length
= total_len
;
396 struct scatterlist
*sg
= iod
->sg
;
397 int dma_len
= sg_dma_len(sg
);
398 u64 dma_addr
= sg_dma_address(sg
);
399 int offset
= offset_in_page(dma_addr
);
401 __le64
**list
= iod_list(iod
);
405 cmd
->prp1
= cpu_to_le64(dma_addr
);
406 length
-= (PAGE_SIZE
- offset
);
410 dma_len
-= (PAGE_SIZE
- offset
);
412 dma_addr
+= (PAGE_SIZE
- offset
);
415 dma_addr
= sg_dma_address(sg
);
416 dma_len
= sg_dma_len(sg
);
419 if (length
<= PAGE_SIZE
) {
420 cmd
->prp2
= cpu_to_le64(dma_addr
);
424 nprps
= DIV_ROUND_UP(length
, PAGE_SIZE
);
425 if (nprps
<= (256 / 8)) {
426 pool
= dev
->prp_small_pool
;
429 pool
= dev
->prp_page_pool
;
433 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
435 cmd
->prp2
= cpu_to_le64(dma_addr
);
437 return (total_len
- length
) + PAGE_SIZE
;
440 iod
->first_dma
= prp_dma
;
441 cmd
->prp2
= cpu_to_le64(prp_dma
);
444 if (i
== PAGE_SIZE
/ 8) {
445 __le64
*old_prp_list
= prp_list
;
446 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
448 return total_len
- length
;
449 list
[iod
->npages
++] = prp_list
;
450 prp_list
[0] = old_prp_list
[i
- 1];
451 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
454 prp_list
[i
++] = cpu_to_le64(dma_addr
);
455 dma_len
-= PAGE_SIZE
;
456 dma_addr
+= PAGE_SIZE
;
464 dma_addr
= sg_dma_address(sg
);
465 dma_len
= sg_dma_len(sg
);
471 /* NVMe scatterlists require no holes in the virtual address */
472 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
473 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
475 static int nvme_map_bio(struct device
*dev
, struct nvme_iod
*iod
,
476 struct bio
*bio
, enum dma_data_direction dma_dir
, int psegs
)
478 struct bio_vec
*bvec
, *bvprv
= NULL
;
479 struct scatterlist
*sg
= NULL
;
480 int i
, old_idx
, length
= 0, nsegs
= 0;
482 sg_init_table(iod
->sg
, psegs
);
483 old_idx
= bio
->bi_idx
;
484 bio_for_each_segment(bvec
, bio
, i
) {
485 if (bvprv
&& BIOVEC_PHYS_MERGEABLE(bvprv
, bvec
)) {
486 sg
->length
+= bvec
->bv_len
;
488 if (bvprv
&& BIOVEC_NOT_VIRT_MERGEABLE(bvprv
, bvec
))
490 sg
= sg
? sg
+ 1 : iod
->sg
;
491 sg_set_page(sg
, bvec
->bv_page
, bvec
->bv_len
,
495 length
+= bvec
->bv_len
;
501 if (dma_map_sg(dev
, iod
->sg
, iod
->nents
, dma_dir
) == 0) {
502 bio
->bi_idx
= old_idx
;
508 static int nvme_submit_flush(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
511 struct nvme_command
*cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
513 memset(cmnd
, 0, sizeof(*cmnd
));
514 cmnd
->common
.opcode
= nvme_cmd_flush
;
515 cmnd
->common
.command_id
= cmdid
;
516 cmnd
->common
.nsid
= cpu_to_le32(ns
->ns_id
);
518 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
520 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
525 static int nvme_submit_flush_data(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
)
527 int cmdid
= alloc_cmdid(nvmeq
, (void *)CMD_CTX_FLUSH
,
528 special_completion
, NVME_IO_TIMEOUT
);
529 if (unlikely(cmdid
< 0))
532 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
536 * Called with local interrupts disabled and the q_lock held. May not sleep.
538 static int nvme_submit_bio_queue(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
541 struct nvme_command
*cmnd
;
542 struct nvme_iod
*iod
;
543 enum dma_data_direction dma_dir
;
544 int cmdid
, length
, result
= -ENOMEM
;
547 int psegs
= bio_phys_segments(ns
->queue
, bio
);
549 if ((bio
->bi_rw
& REQ_FLUSH
) && psegs
) {
550 result
= nvme_submit_flush_data(nvmeq
, ns
);
555 iod
= nvme_alloc_iod(psegs
, bio
->bi_size
, GFP_ATOMIC
);
561 cmdid
= alloc_cmdid(nvmeq
, iod
, bio_completion
, NVME_IO_TIMEOUT
);
562 if (unlikely(cmdid
< 0))
565 if ((bio
->bi_rw
& REQ_FLUSH
) && !psegs
)
566 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
569 if (bio
->bi_rw
& REQ_FUA
)
570 control
|= NVME_RW_FUA
;
571 if (bio
->bi_rw
& (REQ_FAILFAST_DEV
| REQ_RAHEAD
))
572 control
|= NVME_RW_LR
;
575 if (bio
->bi_rw
& REQ_RAHEAD
)
576 dsmgmt
|= NVME_RW_DSM_FREQ_PREFETCH
;
578 cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
580 memset(cmnd
, 0, sizeof(*cmnd
));
581 if (bio_data_dir(bio
)) {
582 cmnd
->rw
.opcode
= nvme_cmd_write
;
583 dma_dir
= DMA_TO_DEVICE
;
585 cmnd
->rw
.opcode
= nvme_cmd_read
;
586 dma_dir
= DMA_FROM_DEVICE
;
589 result
= nvme_map_bio(nvmeq
->q_dmadev
, iod
, bio
, dma_dir
, psegs
);
594 cmnd
->rw
.command_id
= cmdid
;
595 cmnd
->rw
.nsid
= cpu_to_le32(ns
->ns_id
);
596 length
= nvme_setup_prps(nvmeq
->dev
, &cmnd
->common
, iod
, length
,
598 cmnd
->rw
.slba
= cpu_to_le64(bio
->bi_sector
>> (ns
->lba_shift
- 9));
599 cmnd
->rw
.length
= cpu_to_le16((length
>> ns
->lba_shift
) - 1);
600 cmnd
->rw
.control
= cpu_to_le16(control
);
601 cmnd
->rw
.dsmgmt
= cpu_to_le32(dsmgmt
);
603 bio
->bi_sector
+= length
>> 9;
605 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
607 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
612 nvme_free_iod(nvmeq
->dev
, iod
);
618 * NB: return value of non-zero would mean that we were a stacking driver.
619 * make_request must always succeed.
621 static int nvme_make_request(struct request_queue
*q
, struct bio
*bio
)
623 struct nvme_ns
*ns
= q
->queuedata
;
624 struct nvme_queue
*nvmeq
= get_nvmeq(ns
->dev
);
627 spin_lock_irq(&nvmeq
->q_lock
);
628 if (bio_list_empty(&nvmeq
->sq_cong
))
629 result
= nvme_submit_bio_queue(nvmeq
, ns
, bio
);
630 if (unlikely(result
)) {
631 if (bio_list_empty(&nvmeq
->sq_cong
))
632 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
633 bio_list_add(&nvmeq
->sq_cong
, bio
);
636 spin_unlock_irq(&nvmeq
->q_lock
);
642 static irqreturn_t
nvme_process_cq(struct nvme_queue
*nvmeq
)
646 head
= nvmeq
->cq_head
;
647 phase
= nvmeq
->cq_phase
;
651 nvme_completion_fn fn
;
652 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
653 if ((le16_to_cpu(cqe
.status
) & 1) != phase
)
655 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
656 if (++head
== nvmeq
->q_depth
) {
661 ctx
= free_cmdid(nvmeq
, cqe
.command_id
, &fn
);
662 fn(nvmeq
->dev
, ctx
, &cqe
);
665 /* If the controller ignores the cq head doorbell and continuously
666 * writes to the queue, it is theoretically possible to wrap around
667 * the queue twice and mistakenly return IRQ_NONE. Linux only
668 * requires that 0.1% of your interrupts are handled, so this isn't
671 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
674 writel(head
, nvmeq
->q_db
+ (1 << nvmeq
->dev
->db_stride
));
675 nvmeq
->cq_head
= head
;
676 nvmeq
->cq_phase
= phase
;
681 static irqreturn_t
nvme_irq(int irq
, void *data
)
684 struct nvme_queue
*nvmeq
= data
;
685 spin_lock(&nvmeq
->q_lock
);
686 result
= nvme_process_cq(nvmeq
);
687 spin_unlock(&nvmeq
->q_lock
);
691 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
693 struct nvme_queue
*nvmeq
= data
;
694 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
695 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
697 return IRQ_WAKE_THREAD
;
700 static void nvme_abort_command(struct nvme_queue
*nvmeq
, int cmdid
)
702 spin_lock_irq(&nvmeq
->q_lock
);
703 cancel_cmdid(nvmeq
, cmdid
, NULL
);
704 spin_unlock_irq(&nvmeq
->q_lock
);
707 struct sync_cmd_info
{
708 struct task_struct
*task
;
713 static void sync_completion(struct nvme_dev
*dev
, void *ctx
,
714 struct nvme_completion
*cqe
)
716 struct sync_cmd_info
*cmdinfo
= ctx
;
717 cmdinfo
->result
= le32_to_cpup(&cqe
->result
);
718 cmdinfo
->status
= le16_to_cpup(&cqe
->status
) >> 1;
719 wake_up_process(cmdinfo
->task
);
723 * Returns 0 on success. If the result is negative, it's a Linux error code;
724 * if the result is positive, it's an NVM Express status code
726 static int nvme_submit_sync_cmd(struct nvme_queue
*nvmeq
,
727 struct nvme_command
*cmd
, u32
*result
, unsigned timeout
)
730 struct sync_cmd_info cmdinfo
;
732 cmdinfo
.task
= current
;
733 cmdinfo
.status
= -EINTR
;
735 cmdid
= alloc_cmdid_killable(nvmeq
, &cmdinfo
, sync_completion
,
739 cmd
->common
.command_id
= cmdid
;
741 set_current_state(TASK_KILLABLE
);
742 nvme_submit_cmd(nvmeq
, cmd
);
745 if (cmdinfo
.status
== -EINTR
) {
746 nvme_abort_command(nvmeq
, cmdid
);
751 *result
= cmdinfo
.result
;
753 return cmdinfo
.status
;
756 static int nvme_submit_admin_cmd(struct nvme_dev
*dev
, struct nvme_command
*cmd
,
759 return nvme_submit_sync_cmd(dev
->queues
[0], cmd
, result
, ADMIN_TIMEOUT
);
762 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
765 struct nvme_command c
;
767 memset(&c
, 0, sizeof(c
));
768 c
.delete_queue
.opcode
= opcode
;
769 c
.delete_queue
.qid
= cpu_to_le16(id
);
771 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
777 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
778 struct nvme_queue
*nvmeq
)
781 struct nvme_command c
;
782 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
784 memset(&c
, 0, sizeof(c
));
785 c
.create_cq
.opcode
= nvme_admin_create_cq
;
786 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
787 c
.create_cq
.cqid
= cpu_to_le16(qid
);
788 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
789 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
790 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
792 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
798 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
799 struct nvme_queue
*nvmeq
)
802 struct nvme_command c
;
803 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
805 memset(&c
, 0, sizeof(c
));
806 c
.create_sq
.opcode
= nvme_admin_create_sq
;
807 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
808 c
.create_sq
.sqid
= cpu_to_le16(qid
);
809 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
810 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
811 c
.create_sq
.cqid
= cpu_to_le16(qid
);
813 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
819 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
821 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
824 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
826 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
829 static int nvme_identify(struct nvme_dev
*dev
, unsigned nsid
, unsigned cns
,
832 struct nvme_command c
;
834 memset(&c
, 0, sizeof(c
));
835 c
.identify
.opcode
= nvme_admin_identify
;
836 c
.identify
.nsid
= cpu_to_le32(nsid
);
837 c
.identify
.prp1
= cpu_to_le64(dma_addr
);
838 c
.identify
.cns
= cpu_to_le32(cns
);
840 return nvme_submit_admin_cmd(dev
, &c
, NULL
);
843 static int nvme_get_features(struct nvme_dev
*dev
, unsigned fid
,
844 unsigned nsid
, dma_addr_t dma_addr
)
846 struct nvme_command c
;
848 memset(&c
, 0, sizeof(c
));
849 c
.features
.opcode
= nvme_admin_get_features
;
850 c
.features
.nsid
= cpu_to_le32(nsid
);
851 c
.features
.prp1
= cpu_to_le64(dma_addr
);
852 c
.features
.fid
= cpu_to_le32(fid
);
854 return nvme_submit_admin_cmd(dev
, &c
, NULL
);
857 static int nvme_set_features(struct nvme_dev
*dev
, unsigned fid
,
858 unsigned dword11
, dma_addr_t dma_addr
, u32
*result
)
860 struct nvme_command c
;
862 memset(&c
, 0, sizeof(c
));
863 c
.features
.opcode
= nvme_admin_set_features
;
864 c
.features
.prp1
= cpu_to_le64(dma_addr
);
865 c
.features
.fid
= cpu_to_le32(fid
);
866 c
.features
.dword11
= cpu_to_le32(dword11
);
868 return nvme_submit_admin_cmd(dev
, &c
, result
);
871 static void nvme_free_queue(struct nvme_dev
*dev
, int qid
)
873 struct nvme_queue
*nvmeq
= dev
->queues
[qid
];
874 int vector
= dev
->entry
[nvmeq
->cq_vector
].vector
;
876 irq_set_affinity_hint(vector
, NULL
);
877 free_irq(vector
, nvmeq
);
879 /* Don't tell the adapter to delete the admin queue */
881 adapter_delete_sq(dev
, qid
);
882 adapter_delete_cq(dev
, qid
);
885 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
886 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
887 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
888 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
892 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
893 int depth
, int vector
)
895 struct device
*dmadev
= &dev
->pci_dev
->dev
;
896 unsigned extra
= DIV_ROUND_UP(depth
, 8) + (depth
*
897 sizeof(struct nvme_cmd_info
));
898 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
) + extra
, GFP_KERNEL
);
902 nvmeq
->cqes
= dma_alloc_coherent(dmadev
, CQ_SIZE(depth
),
903 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
906 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(depth
));
908 nvmeq
->sq_cmds
= dma_alloc_coherent(dmadev
, SQ_SIZE(depth
),
909 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
913 nvmeq
->q_dmadev
= dmadev
;
915 spin_lock_init(&nvmeq
->q_lock
);
918 init_waitqueue_head(&nvmeq
->sq_full
);
919 init_waitqueue_entry(&nvmeq
->sq_cong_wait
, nvme_thread
);
920 bio_list_init(&nvmeq
->sq_cong
);
921 nvmeq
->q_db
= &dev
->dbs
[qid
<< (dev
->db_stride
+ 1)];
922 nvmeq
->q_depth
= depth
;
923 nvmeq
->cq_vector
= vector
;
928 dma_free_coherent(dmadev
, CQ_SIZE(nvmeq
->q_depth
), (void *)nvmeq
->cqes
,
935 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
938 if (use_threaded_interrupts
)
939 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
940 nvme_irq_check
, nvme_irq
,
941 IRQF_DISABLED
| IRQF_SHARED
,
943 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
944 IRQF_DISABLED
| IRQF_SHARED
, name
, nvmeq
);
947 static __devinit
struct nvme_queue
*nvme_create_queue(struct nvme_dev
*dev
,
948 int qid
, int cq_size
, int vector
)
951 struct nvme_queue
*nvmeq
= nvme_alloc_queue(dev
, qid
, cq_size
, vector
);
954 return ERR_PTR(-ENOMEM
);
956 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
960 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
964 result
= queue_request_irq(dev
, nvmeq
, "nvme");
971 adapter_delete_sq(dev
, qid
);
973 adapter_delete_cq(dev
, qid
);
975 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
976 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
977 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
978 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
980 return ERR_PTR(result
);
983 static int __devinit
nvme_configure_admin_queue(struct nvme_dev
*dev
)
988 unsigned long timeout
;
989 struct nvme_queue
*nvmeq
;
991 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
993 nvmeq
= nvme_alloc_queue(dev
, 0, 64, 0);
997 aqa
= nvmeq
->q_depth
- 1;
1000 dev
->ctrl_config
= NVME_CC_ENABLE
| NVME_CC_CSS_NVM
;
1001 dev
->ctrl_config
|= (PAGE_SHIFT
- 12) << NVME_CC_MPS_SHIFT
;
1002 dev
->ctrl_config
|= NVME_CC_ARB_RR
| NVME_CC_SHN_NONE
;
1003 dev
->ctrl_config
|= NVME_CC_IOSQES
| NVME_CC_IOCQES
;
1005 writel(0, &dev
->bar
->cc
);
1006 writel(aqa
, &dev
->bar
->aqa
);
1007 writeq(nvmeq
->sq_dma_addr
, &dev
->bar
->asq
);
1008 writeq(nvmeq
->cq_dma_addr
, &dev
->bar
->acq
);
1009 writel(dev
->ctrl_config
, &dev
->bar
->cc
);
1011 cap
= readq(&dev
->bar
->cap
);
1012 timeout
= ((NVME_CAP_TIMEOUT(cap
) + 1) * HZ
/ 2) + jiffies
;
1013 dev
->db_stride
= NVME_CAP_STRIDE(cap
);
1015 while (!(readl(&dev
->bar
->csts
) & NVME_CSTS_RDY
)) {
1017 if (fatal_signal_pending(current
))
1019 if (time_after(jiffies
, timeout
)) {
1020 dev_err(&dev
->pci_dev
->dev
,
1021 "Device not ready; aborting initialisation\n");
1026 result
= queue_request_irq(dev
, nvmeq
, "nvme admin");
1027 dev
->queues
[0] = nvmeq
;
1031 static struct nvme_iod
*nvme_map_user_pages(struct nvme_dev
*dev
, int write
,
1032 unsigned long addr
, unsigned length
)
1034 int i
, err
, count
, nents
, offset
;
1035 struct scatterlist
*sg
;
1036 struct page
**pages
;
1037 struct nvme_iod
*iod
;
1040 return ERR_PTR(-EINVAL
);
1042 return ERR_PTR(-EINVAL
);
1044 offset
= offset_in_page(addr
);
1045 count
= DIV_ROUND_UP(offset
+ length
, PAGE_SIZE
);
1046 pages
= kcalloc(count
, sizeof(*pages
), GFP_KERNEL
);
1048 err
= get_user_pages_fast(addr
, count
, 1, pages
);
1055 iod
= nvme_alloc_iod(count
, length
, GFP_KERNEL
);
1057 sg_init_table(sg
, count
);
1058 for (i
= 0; i
< count
; i
++) {
1059 sg_set_page(&sg
[i
], pages
[i
],
1060 min_t(int, length
, PAGE_SIZE
- offset
), offset
);
1061 length
-= (PAGE_SIZE
- offset
);
1064 sg_mark_end(&sg
[i
- 1]);
1068 nents
= dma_map_sg(&dev
->pci_dev
->dev
, sg
, count
,
1069 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1079 for (i
= 0; i
< count
; i
++)
1082 return ERR_PTR(err
);
1085 static void nvme_unmap_user_pages(struct nvme_dev
*dev
, int write
,
1086 struct nvme_iod
*iod
)
1090 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
1091 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1093 for (i
= 0; i
< iod
->nents
; i
++)
1094 put_page(sg_page(&iod
->sg
[i
]));
1097 static int nvme_submit_io(struct nvme_ns
*ns
, struct nvme_user_io __user
*uio
)
1099 struct nvme_dev
*dev
= ns
->dev
;
1100 struct nvme_queue
*nvmeq
;
1101 struct nvme_user_io io
;
1102 struct nvme_command c
;
1105 struct nvme_iod
*iod
;
1107 if (copy_from_user(&io
, uio
, sizeof(io
)))
1109 length
= (io
.nblocks
+ 1) << ns
->lba_shift
;
1111 switch (io
.opcode
) {
1112 case nvme_cmd_write
:
1114 case nvme_cmd_compare
:
1115 iod
= nvme_map_user_pages(dev
, io
.opcode
& 1, io
.addr
, length
);
1122 return PTR_ERR(iod
);
1124 memset(&c
, 0, sizeof(c
));
1125 c
.rw
.opcode
= io
.opcode
;
1126 c
.rw
.flags
= io
.flags
;
1127 c
.rw
.nsid
= cpu_to_le32(ns
->ns_id
);
1128 c
.rw
.slba
= cpu_to_le64(io
.slba
);
1129 c
.rw
.length
= cpu_to_le16(io
.nblocks
);
1130 c
.rw
.control
= cpu_to_le16(io
.control
);
1131 c
.rw
.dsmgmt
= cpu_to_le16(io
.dsmgmt
);
1132 c
.rw
.reftag
= io
.reftag
;
1133 c
.rw
.apptag
= io
.apptag
;
1134 c
.rw
.appmask
= io
.appmask
;
1136 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
, GFP_KERNEL
);
1138 nvmeq
= get_nvmeq(dev
);
1140 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1141 * disabled. We may be preempted at any point, and be rescheduled
1142 * to a different CPU. That will cause cacheline bouncing, but no
1143 * additional races since q_lock already protects against other CPUs.
1146 if (length
!= (io
.nblocks
+ 1) << ns
->lba_shift
)
1149 status
= nvme_submit_sync_cmd(nvmeq
, &c
, NULL
, NVME_IO_TIMEOUT
);
1151 nvme_unmap_user_pages(dev
, io
.opcode
& 1, iod
);
1152 nvme_free_iod(dev
, iod
);
1156 static int nvme_user_admin_cmd(struct nvme_dev
*dev
,
1157 struct nvme_admin_cmd __user
*ucmd
)
1159 struct nvme_admin_cmd cmd
;
1160 struct nvme_command c
;
1162 struct nvme_iod
*uninitialized_var(iod
);
1164 if (!capable(CAP_SYS_ADMIN
))
1166 if (copy_from_user(&cmd
, ucmd
, sizeof(cmd
)))
1169 memset(&c
, 0, sizeof(c
));
1170 c
.common
.opcode
= cmd
.opcode
;
1171 c
.common
.flags
= cmd
.flags
;
1172 c
.common
.nsid
= cpu_to_le32(cmd
.nsid
);
1173 c
.common
.cdw2
[0] = cpu_to_le32(cmd
.cdw2
);
1174 c
.common
.cdw2
[1] = cpu_to_le32(cmd
.cdw3
);
1175 c
.common
.cdw10
[0] = cpu_to_le32(cmd
.cdw10
);
1176 c
.common
.cdw10
[1] = cpu_to_le32(cmd
.cdw11
);
1177 c
.common
.cdw10
[2] = cpu_to_le32(cmd
.cdw12
);
1178 c
.common
.cdw10
[3] = cpu_to_le32(cmd
.cdw13
);
1179 c
.common
.cdw10
[4] = cpu_to_le32(cmd
.cdw14
);
1180 c
.common
.cdw10
[5] = cpu_to_le32(cmd
.cdw15
);
1182 length
= cmd
.data_len
;
1184 iod
= nvme_map_user_pages(dev
, cmd
.opcode
& 1, cmd
.addr
,
1187 return PTR_ERR(iod
);
1188 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
,
1192 if (length
!= cmd
.data_len
)
1195 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
1198 nvme_unmap_user_pages(dev
, cmd
.opcode
& 1, iod
);
1199 nvme_free_iod(dev
, iod
);
1204 static int nvme_ioctl(struct block_device
*bdev
, fmode_t mode
, unsigned int cmd
,
1207 struct nvme_ns
*ns
= bdev
->bd_disk
->private_data
;
1212 case NVME_IOCTL_ADMIN_CMD
:
1213 return nvme_user_admin_cmd(ns
->dev
, (void __user
*)arg
);
1214 case NVME_IOCTL_SUBMIT_IO
:
1215 return nvme_submit_io(ns
, (void __user
*)arg
);
1221 static const struct block_device_operations nvme_fops
= {
1222 .owner
= THIS_MODULE
,
1223 .ioctl
= nvme_ioctl
,
1224 .compat_ioctl
= nvme_ioctl
,
1227 static void nvme_timeout_ios(struct nvme_queue
*nvmeq
)
1229 int depth
= nvmeq
->q_depth
- 1;
1230 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
1231 unsigned long now
= jiffies
;
1234 for_each_set_bit(cmdid
, nvmeq
->cmdid_data
, depth
) {
1236 nvme_completion_fn fn
;
1237 static struct nvme_completion cqe
= { .status
= cpu_to_le16(NVME_SC_ABORT_REQ
) << 1, };
1239 if (!time_after(now
, info
[cmdid
].timeout
))
1241 dev_warn(nvmeq
->q_dmadev
, "Timing out I/O %d\n", cmdid
);
1242 ctx
= cancel_cmdid(nvmeq
, cmdid
, &fn
);
1243 fn(nvmeq
->dev
, ctx
, &cqe
);
1247 static void nvme_resubmit_bios(struct nvme_queue
*nvmeq
)
1249 while (bio_list_peek(&nvmeq
->sq_cong
)) {
1250 struct bio
*bio
= bio_list_pop(&nvmeq
->sq_cong
);
1251 struct nvme_ns
*ns
= bio
->bi_bdev
->bd_disk
->private_data
;
1252 if (nvme_submit_bio_queue(nvmeq
, ns
, bio
)) {
1253 bio_list_add_head(&nvmeq
->sq_cong
, bio
);
1256 if (bio_list_empty(&nvmeq
->sq_cong
))
1257 remove_wait_queue(&nvmeq
->sq_full
,
1258 &nvmeq
->sq_cong_wait
);
1262 static int nvme_kthread(void *data
)
1264 struct nvme_dev
*dev
;
1266 while (!kthread_should_stop()) {
1267 __set_current_state(TASK_RUNNING
);
1268 spin_lock(&dev_list_lock
);
1269 list_for_each_entry(dev
, &dev_list
, node
) {
1271 for (i
= 0; i
< dev
->queue_count
; i
++) {
1272 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1275 spin_lock_irq(&nvmeq
->q_lock
);
1276 if (nvme_process_cq(nvmeq
))
1277 printk("process_cq did something\n");
1278 nvme_timeout_ios(nvmeq
);
1279 nvme_resubmit_bios(nvmeq
);
1280 spin_unlock_irq(&nvmeq
->q_lock
);
1283 spin_unlock(&dev_list_lock
);
1284 set_current_state(TASK_INTERRUPTIBLE
);
1285 schedule_timeout(HZ
);
1290 static DEFINE_IDA(nvme_index_ida
);
1292 static int nvme_get_ns_idx(void)
1297 if (!ida_pre_get(&nvme_index_ida
, GFP_KERNEL
))
1300 spin_lock(&dev_list_lock
);
1301 error
= ida_get_new(&nvme_index_ida
, &index
);
1302 spin_unlock(&dev_list_lock
);
1303 } while (error
== -EAGAIN
);
1310 static void nvme_put_ns_idx(int index
)
1312 spin_lock(&dev_list_lock
);
1313 ida_remove(&nvme_index_ida
, index
);
1314 spin_unlock(&dev_list_lock
);
1317 static struct nvme_ns
*nvme_alloc_ns(struct nvme_dev
*dev
, int nsid
,
1318 struct nvme_id_ns
*id
, struct nvme_lba_range_type
*rt
)
1321 struct gendisk
*disk
;
1324 if (rt
->attributes
& NVME_LBART_ATTRIB_HIDE
)
1327 ns
= kzalloc(sizeof(*ns
), GFP_KERNEL
);
1330 ns
->queue
= blk_alloc_queue(GFP_KERNEL
);
1333 ns
->queue
->queue_flags
= QUEUE_FLAG_DEFAULT
;
1334 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES
, ns
->queue
);
1335 queue_flag_set_unlocked(QUEUE_FLAG_NONROT
, ns
->queue
);
1336 /* queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); */
1337 blk_queue_make_request(ns
->queue
, nvme_make_request
);
1339 ns
->queue
->queuedata
= ns
;
1341 disk
= alloc_disk(NVME_MINORS
);
1343 goto out_free_queue
;
1346 lbaf
= id
->flbas
& 0xf;
1347 ns
->lba_shift
= id
->lbaf
[lbaf
].ds
;
1348 blk_queue_logical_block_size(ns
->queue
, 1 << ns
->lba_shift
);
1349 if (dev
->max_hw_sectors
)
1350 blk_queue_max_hw_sectors(ns
->queue
, dev
->max_hw_sectors
);
1352 disk
->major
= nvme_major
;
1353 disk
->minors
= NVME_MINORS
;
1354 disk
->first_minor
= NVME_MINORS
* nvme_get_ns_idx();
1355 disk
->fops
= &nvme_fops
;
1356 disk
->private_data
= ns
;
1357 disk
->queue
= ns
->queue
;
1358 disk
->driverfs_dev
= &dev
->pci_dev
->dev
;
1359 sprintf(disk
->disk_name
, "nvme%dn%d", dev
->instance
, nsid
);
1360 set_capacity(disk
, le64_to_cpup(&id
->nsze
) << (ns
->lba_shift
- 9));
1365 blk_cleanup_queue(ns
->queue
);
1371 static void nvme_ns_free(struct nvme_ns
*ns
)
1373 int index
= ns
->disk
->first_minor
/ NVME_MINORS
;
1375 nvme_put_ns_idx(index
);
1376 blk_cleanup_queue(ns
->queue
);
1380 static int set_queue_count(struct nvme_dev
*dev
, int count
)
1384 u32 q_count
= (count
- 1) | ((count
- 1) << 16);
1386 status
= nvme_set_features(dev
, NVME_FEAT_NUM_QUEUES
, q_count
, 0,
1390 return min(result
& 0xffff, result
>> 16) + 1;
1393 static int __devinit
nvme_setup_io_queues(struct nvme_dev
*dev
)
1395 int result
, cpu
, i
, nr_io_queues
, db_bar_size
, q_depth
;
1397 nr_io_queues
= num_online_cpus();
1398 result
= set_queue_count(dev
, nr_io_queues
);
1401 if (result
< nr_io_queues
)
1402 nr_io_queues
= result
;
1404 /* Deregister the admin queue's interrupt */
1405 free_irq(dev
->entry
[0].vector
, dev
->queues
[0]);
1407 db_bar_size
= 4096 + ((nr_io_queues
+ 1) << (dev
->db_stride
+ 3));
1408 if (db_bar_size
> 8192) {
1410 dev
->bar
= ioremap(pci_resource_start(dev
->pci_dev
, 0),
1412 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
1413 dev
->queues
[0]->q_db
= dev
->dbs
;
1416 for (i
= 0; i
< nr_io_queues
; i
++)
1417 dev
->entry
[i
].entry
= i
;
1419 result
= pci_enable_msix(dev
->pci_dev
, dev
->entry
,
1423 } else if (result
> 0) {
1424 nr_io_queues
= result
;
1432 result
= queue_request_irq(dev
, dev
->queues
[0], "nvme admin");
1433 /* XXX: handle failure here */
1435 cpu
= cpumask_first(cpu_online_mask
);
1436 for (i
= 0; i
< nr_io_queues
; i
++) {
1437 irq_set_affinity_hint(dev
->entry
[i
].vector
, get_cpu_mask(cpu
));
1438 cpu
= cpumask_next(cpu
, cpu_online_mask
);
1441 q_depth
= min_t(int, NVME_CAP_MQES(readq(&dev
->bar
->cap
)) + 1,
1443 for (i
= 0; i
< nr_io_queues
; i
++) {
1444 dev
->queues
[i
+ 1] = nvme_create_queue(dev
, i
+ 1, q_depth
, i
);
1445 if (IS_ERR(dev
->queues
[i
+ 1]))
1446 return PTR_ERR(dev
->queues
[i
+ 1]);
1450 for (; i
< num_possible_cpus(); i
++) {
1451 int target
= i
% rounddown_pow_of_two(dev
->queue_count
- 1);
1452 dev
->queues
[i
+ 1] = dev
->queues
[target
+ 1];
1458 static void nvme_free_queues(struct nvme_dev
*dev
)
1462 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
1463 nvme_free_queue(dev
, i
);
1466 static int __devinit
nvme_dev_add(struct nvme_dev
*dev
)
1469 struct nvme_ns
*ns
, *next
;
1470 struct nvme_id_ctrl
*ctrl
;
1471 struct nvme_id_ns
*id_ns
;
1473 dma_addr_t dma_addr
;
1475 res
= nvme_setup_io_queues(dev
);
1479 mem
= dma_alloc_coherent(&dev
->pci_dev
->dev
, 8192, &dma_addr
,
1482 res
= nvme_identify(dev
, 0, 1, dma_addr
);
1489 nn
= le32_to_cpup(&ctrl
->nn
);
1490 memcpy(dev
->serial
, ctrl
->sn
, sizeof(ctrl
->sn
));
1491 memcpy(dev
->model
, ctrl
->mn
, sizeof(ctrl
->mn
));
1492 memcpy(dev
->firmware_rev
, ctrl
->fr
, sizeof(ctrl
->fr
));
1494 int shift
= NVME_CAP_MPSMIN(readq(&dev
->bar
->cap
)) + 12;
1495 dev
->max_hw_sectors
= 1 << (ctrl
->mdts
+ shift
- 9);
1499 for (i
= 1; i
<= nn
; i
++) {
1500 res
= nvme_identify(dev
, i
, 0, dma_addr
);
1504 if (id_ns
->ncap
== 0)
1507 res
= nvme_get_features(dev
, NVME_FEAT_LBA_RANGE
, i
,
1512 ns
= nvme_alloc_ns(dev
, i
, mem
, mem
+ 4096);
1514 list_add_tail(&ns
->list
, &dev
->namespaces
);
1516 list_for_each_entry(ns
, &dev
->namespaces
, list
)
1522 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1523 list_del(&ns
->list
);
1528 dma_free_coherent(&dev
->pci_dev
->dev
, 8192, mem
, dma_addr
);
1532 static int nvme_dev_remove(struct nvme_dev
*dev
)
1534 struct nvme_ns
*ns
, *next
;
1536 spin_lock(&dev_list_lock
);
1537 list_del(&dev
->node
);
1538 spin_unlock(&dev_list_lock
);
1540 /* TODO: wait all I/O finished or cancel them */
1542 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1543 list_del(&ns
->list
);
1544 del_gendisk(ns
->disk
);
1548 nvme_free_queues(dev
);
1553 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1555 struct device
*dmadev
= &dev
->pci_dev
->dev
;
1556 dev
->prp_page_pool
= dma_pool_create("prp list page", dmadev
,
1557 PAGE_SIZE
, PAGE_SIZE
, 0);
1558 if (!dev
->prp_page_pool
)
1561 /* Optimisation for I/Os between 4k and 128k */
1562 dev
->prp_small_pool
= dma_pool_create("prp list 256", dmadev
,
1564 if (!dev
->prp_small_pool
) {
1565 dma_pool_destroy(dev
->prp_page_pool
);
1571 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1573 dma_pool_destroy(dev
->prp_page_pool
);
1574 dma_pool_destroy(dev
->prp_small_pool
);
1577 /* XXX: Use an ida or something to let remove / add work correctly */
1578 static void nvme_set_instance(struct nvme_dev
*dev
)
1580 static int instance
;
1581 dev
->instance
= instance
++;
1584 static void nvme_release_instance(struct nvme_dev
*dev
)
1588 static int __devinit
nvme_probe(struct pci_dev
*pdev
,
1589 const struct pci_device_id
*id
)
1591 int bars
, result
= -ENOMEM
;
1592 struct nvme_dev
*dev
;
1594 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1597 dev
->entry
= kcalloc(num_possible_cpus(), sizeof(*dev
->entry
),
1601 dev
->queues
= kcalloc(num_possible_cpus() + 1, sizeof(void *),
1606 if (pci_enable_device_mem(pdev
))
1608 pci_set_master(pdev
);
1609 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1610 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1613 INIT_LIST_HEAD(&dev
->namespaces
);
1614 dev
->pci_dev
= pdev
;
1615 pci_set_drvdata(pdev
, dev
);
1616 dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1617 dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1618 nvme_set_instance(dev
);
1619 dev
->entry
[0].vector
= pdev
->irq
;
1621 result
= nvme_setup_prp_pools(dev
);
1625 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1631 result
= nvme_configure_admin_queue(dev
);
1636 spin_lock(&dev_list_lock
);
1637 list_add(&dev
->node
, &dev_list
);
1638 spin_unlock(&dev_list_lock
);
1640 result
= nvme_dev_add(dev
);
1647 spin_lock(&dev_list_lock
);
1648 list_del(&dev
->node
);
1649 spin_unlock(&dev_list_lock
);
1651 nvme_free_queues(dev
);
1655 pci_disable_msix(pdev
);
1656 nvme_release_instance(dev
);
1657 nvme_release_prp_pools(dev
);
1659 pci_disable_device(pdev
);
1660 pci_release_regions(pdev
);
1668 static void __devexit
nvme_remove(struct pci_dev
*pdev
)
1670 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
1671 nvme_dev_remove(dev
);
1672 pci_disable_msix(pdev
);
1674 nvme_release_instance(dev
);
1675 nvme_release_prp_pools(dev
);
1676 pci_disable_device(pdev
);
1677 pci_release_regions(pdev
);
1683 /* These functions are yet to be implemented */
1684 #define nvme_error_detected NULL
1685 #define nvme_dump_registers NULL
1686 #define nvme_link_reset NULL
1687 #define nvme_slot_reset NULL
1688 #define nvme_error_resume NULL
1689 #define nvme_suspend NULL
1690 #define nvme_resume NULL
1692 static struct pci_error_handlers nvme_err_handler
= {
1693 .error_detected
= nvme_error_detected
,
1694 .mmio_enabled
= nvme_dump_registers
,
1695 .link_reset
= nvme_link_reset
,
1696 .slot_reset
= nvme_slot_reset
,
1697 .resume
= nvme_error_resume
,
1700 /* Move to pci_ids.h later */
1701 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1703 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table
) = {
1704 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
1707 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
1709 static struct pci_driver nvme_driver
= {
1711 .id_table
= nvme_id_table
,
1712 .probe
= nvme_probe
,
1713 .remove
= __devexit_p(nvme_remove
),
1714 .suspend
= nvme_suspend
,
1715 .resume
= nvme_resume
,
1716 .err_handler
= &nvme_err_handler
,
1719 static int __init
nvme_init(void)
1721 int result
= -EBUSY
;
1723 nvme_thread
= kthread_run(nvme_kthread
, NULL
, "nvme");
1724 if (IS_ERR(nvme_thread
))
1725 return PTR_ERR(nvme_thread
);
1727 result
= register_blkdev(nvme_major
, "nvme");
1730 else if (result
> 0)
1731 nvme_major
= result
;
1733 result
= pci_register_driver(&nvme_driver
);
1735 goto unregister_blkdev
;
1739 unregister_blkdev(nvme_major
, "nvme");
1741 kthread_stop(nvme_thread
);
1745 static void __exit
nvme_exit(void)
1747 pci_unregister_driver(&nvme_driver
);
1748 unregister_blkdev(nvme_major
, "nvme");
1749 kthread_stop(nvme_thread
);
1752 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1753 MODULE_LICENSE("GPL");
1754 MODULE_VERSION("0.8");
1755 module_init(nvme_init
);
1756 module_exit(nvme_exit
);