2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
43 #include <asm-generic/io-64-nonatomic-lo-hi.h>
45 #define NVME_Q_DEPTH 1024
46 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
48 #define NVME_MINORS 64
49 #define NVME_IO_TIMEOUT (5 * HZ)
50 #define ADMIN_TIMEOUT (60 * HZ)
52 static int nvme_major
;
53 module_param(nvme_major
, int, 0);
55 static int use_threaded_interrupts
;
56 module_param(use_threaded_interrupts
, int, 0);
58 static DEFINE_SPINLOCK(dev_list_lock
);
59 static LIST_HEAD(dev_list
);
60 static struct task_struct
*nvme_thread
;
63 * Represents an NVM Express device. Each nvme_dev is a PCI function.
66 struct list_head node
;
67 struct nvme_queue
**queues
;
69 struct pci_dev
*pci_dev
;
70 struct dma_pool
*prp_page_pool
;
71 struct dma_pool
*prp_small_pool
;
76 struct msix_entry
*entry
;
77 struct nvme_bar __iomem
*bar
;
78 struct list_head namespaces
;
86 * An NVM Express namespace is equivalent to a SCSI LUN
89 struct list_head list
;
92 struct request_queue
*queue
;
100 * An NVM Express queue. Each device has at least two (one for admin
101 * commands and one for I/O commands).
104 struct device
*q_dmadev
;
105 struct nvme_dev
*dev
;
107 struct nvme_command
*sq_cmds
;
108 volatile struct nvme_completion
*cqes
;
109 dma_addr_t sq_dma_addr
;
110 dma_addr_t cq_dma_addr
;
111 wait_queue_head_t sq_full
;
112 wait_queue_t sq_cong_wait
;
113 struct bio_list sq_cong
;
121 unsigned long cmdid_data
[];
125 * Check we didin't inadvertently grow the command struct
127 static inline void _nvme_check_size(void)
129 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
132 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
134 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
135 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
136 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
137 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
140 typedef void (*nvme_completion_fn
)(struct nvme_dev
*, void *,
141 struct nvme_completion
*);
143 struct nvme_cmd_info
{
144 nvme_completion_fn fn
;
146 unsigned long timeout
;
149 static struct nvme_cmd_info
*nvme_cmd_info(struct nvme_queue
*nvmeq
)
151 return (void *)&nvmeq
->cmdid_data
[BITS_TO_LONGS(nvmeq
->q_depth
)];
155 * alloc_cmdid() - Allocate a Command ID
156 * @nvmeq: The queue that will be used for this command
157 * @ctx: A pointer that will be passed to the handler
158 * @handler: The function to call on completion
160 * Allocate a Command ID for a queue. The data passed in will
161 * be passed to the completion handler. This is implemented by using
162 * the bottom two bits of the ctx pointer to store the handler ID.
163 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
164 * We can change this if it becomes a problem.
166 * May be called with local interrupts disabled and the q_lock held,
167 * or with interrupts enabled and no locks held.
169 static int alloc_cmdid(struct nvme_queue
*nvmeq
, void *ctx
,
170 nvme_completion_fn handler
, unsigned timeout
)
172 int depth
= nvmeq
->q_depth
- 1;
173 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
177 cmdid
= find_first_zero_bit(nvmeq
->cmdid_data
, depth
);
180 } while (test_and_set_bit(cmdid
, nvmeq
->cmdid_data
));
182 info
[cmdid
].fn
= handler
;
183 info
[cmdid
].ctx
= ctx
;
184 info
[cmdid
].timeout
= jiffies
+ timeout
;
188 static int alloc_cmdid_killable(struct nvme_queue
*nvmeq
, void *ctx
,
189 nvme_completion_fn handler
, unsigned timeout
)
192 wait_event_killable(nvmeq
->sq_full
,
193 (cmdid
= alloc_cmdid(nvmeq
, ctx
, handler
, timeout
)) >= 0);
194 return (cmdid
< 0) ? -EINTR
: cmdid
;
197 /* Special values must be less than 0x1000 */
198 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
199 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
200 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
201 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
202 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
204 static void special_completion(struct nvme_dev
*dev
, void *ctx
,
205 struct nvme_completion
*cqe
)
207 if (ctx
== CMD_CTX_CANCELLED
)
209 if (ctx
== CMD_CTX_FLUSH
)
211 if (ctx
== CMD_CTX_COMPLETED
) {
212 dev_warn(&dev
->pci_dev
->dev
,
213 "completed id %d twice on queue %d\n",
214 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
217 if (ctx
== CMD_CTX_INVALID
) {
218 dev_warn(&dev
->pci_dev
->dev
,
219 "invalid id %d completed on queue %d\n",
220 cqe
->command_id
, le16_to_cpup(&cqe
->sq_id
));
224 dev_warn(&dev
->pci_dev
->dev
, "Unknown special completion %p\n", ctx
);
228 * Called with local interrupts disabled and the q_lock held. May not sleep.
230 static void *free_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
231 nvme_completion_fn
*fn
)
234 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
236 if (cmdid
>= nvmeq
->q_depth
) {
237 *fn
= special_completion
;
238 return CMD_CTX_INVALID
;
241 *fn
= info
[cmdid
].fn
;
242 ctx
= info
[cmdid
].ctx
;
243 info
[cmdid
].fn
= special_completion
;
244 info
[cmdid
].ctx
= CMD_CTX_COMPLETED
;
245 clear_bit(cmdid
, nvmeq
->cmdid_data
);
246 wake_up(&nvmeq
->sq_full
);
250 static void *cancel_cmdid(struct nvme_queue
*nvmeq
, int cmdid
,
251 nvme_completion_fn
*fn
)
254 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
256 *fn
= info
[cmdid
].fn
;
257 ctx
= info
[cmdid
].ctx
;
258 info
[cmdid
].fn
= special_completion
;
259 info
[cmdid
].ctx
= CMD_CTX_CANCELLED
;
263 static struct nvme_queue
*get_nvmeq(struct nvme_dev
*dev
)
265 return dev
->queues
[get_cpu() + 1];
268 static void put_nvmeq(struct nvme_queue
*nvmeq
)
274 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
275 * @nvmeq: The queue to use
276 * @cmd: The command to send
278 * Safe to use from interrupt context
280 static int nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
)
284 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
285 tail
= nvmeq
->sq_tail
;
286 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
287 if (++tail
== nvmeq
->q_depth
)
289 writel(tail
, nvmeq
->q_db
);
290 nvmeq
->sq_tail
= tail
;
291 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
297 * The nvme_iod describes the data in an I/O, including the list of PRP
298 * entries. You can't see it in this data structure because C doesn't let
299 * me express that. Use nvme_alloc_iod to ensure there's enough space
300 * allocated to store the PRP list.
303 void *private; /* For the use of the submitter of the I/O */
304 int npages
; /* In the PRP list. 0 means small pool in use */
305 int offset
; /* Of PRP list */
306 int nents
; /* Used in scatterlist */
307 int length
; /* Of data, in bytes */
308 dma_addr_t first_dma
;
309 struct scatterlist sg
[0];
312 static __le64
**iod_list(struct nvme_iod
*iod
)
314 return ((void *)iod
) + iod
->offset
;
318 * Will slightly overestimate the number of pages needed. This is OK
319 * as it only leads to a small amount of wasted memory for the lifetime of
322 static int nvme_npages(unsigned size
)
324 unsigned nprps
= DIV_ROUND_UP(size
+ PAGE_SIZE
, PAGE_SIZE
);
325 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
328 static struct nvme_iod
*
329 nvme_alloc_iod(unsigned nseg
, unsigned nbytes
, gfp_t gfp
)
331 struct nvme_iod
*iod
= kmalloc(sizeof(struct nvme_iod
) +
332 sizeof(__le64
*) * nvme_npages(nbytes
) +
333 sizeof(struct scatterlist
) * nseg
, gfp
);
336 iod
->offset
= offsetof(struct nvme_iod
, sg
[nseg
]);
338 iod
->length
= nbytes
;
344 static void nvme_free_iod(struct nvme_dev
*dev
, struct nvme_iod
*iod
)
346 const int last_prp
= PAGE_SIZE
/ 8 - 1;
348 __le64
**list
= iod_list(iod
);
349 dma_addr_t prp_dma
= iod
->first_dma
;
351 if (iod
->npages
== 0)
352 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
353 for (i
= 0; i
< iod
->npages
; i
++) {
354 __le64
*prp_list
= list
[i
];
355 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
356 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
357 prp_dma
= next_prp_dma
;
362 static void requeue_bio(struct nvme_dev
*dev
, struct bio
*bio
)
364 struct nvme_queue
*nvmeq
= get_nvmeq(dev
);
365 if (bio_list_empty(&nvmeq
->sq_cong
))
366 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
367 bio_list_add(&nvmeq
->sq_cong
, bio
);
369 wake_up_process(nvme_thread
);
372 static void bio_completion(struct nvme_dev
*dev
, void *ctx
,
373 struct nvme_completion
*cqe
)
375 struct nvme_iod
*iod
= ctx
;
376 struct bio
*bio
= iod
->private;
377 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
379 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
380 bio_data_dir(bio
) ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
381 nvme_free_iod(dev
, iod
);
383 bio_endio(bio
, -EIO
);
384 } else if (bio
->bi_vcnt
> bio
->bi_idx
) {
385 requeue_bio(dev
, bio
);
391 /* length is in bytes. gfp flags indicates whether we may sleep. */
392 static int nvme_setup_prps(struct nvme_dev
*dev
,
393 struct nvme_common_command
*cmd
, struct nvme_iod
*iod
,
394 int total_len
, gfp_t gfp
)
396 struct dma_pool
*pool
;
397 int length
= total_len
;
398 struct scatterlist
*sg
= iod
->sg
;
399 int dma_len
= sg_dma_len(sg
);
400 u64 dma_addr
= sg_dma_address(sg
);
401 int offset
= offset_in_page(dma_addr
);
403 __le64
**list
= iod_list(iod
);
407 cmd
->prp1
= cpu_to_le64(dma_addr
);
408 length
-= (PAGE_SIZE
- offset
);
412 dma_len
-= (PAGE_SIZE
- offset
);
414 dma_addr
+= (PAGE_SIZE
- offset
);
417 dma_addr
= sg_dma_address(sg
);
418 dma_len
= sg_dma_len(sg
);
421 if (length
<= PAGE_SIZE
) {
422 cmd
->prp2
= cpu_to_le64(dma_addr
);
426 nprps
= DIV_ROUND_UP(length
, PAGE_SIZE
);
427 if (nprps
<= (256 / 8)) {
428 pool
= dev
->prp_small_pool
;
431 pool
= dev
->prp_page_pool
;
435 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
437 cmd
->prp2
= cpu_to_le64(dma_addr
);
439 return (total_len
- length
) + PAGE_SIZE
;
442 iod
->first_dma
= prp_dma
;
443 cmd
->prp2
= cpu_to_le64(prp_dma
);
446 if (i
== PAGE_SIZE
/ 8) {
447 __le64
*old_prp_list
= prp_list
;
448 prp_list
= dma_pool_alloc(pool
, gfp
, &prp_dma
);
450 return total_len
- length
;
451 list
[iod
->npages
++] = prp_list
;
452 prp_list
[0] = old_prp_list
[i
- 1];
453 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
456 prp_list
[i
++] = cpu_to_le64(dma_addr
);
457 dma_len
-= PAGE_SIZE
;
458 dma_addr
+= PAGE_SIZE
;
466 dma_addr
= sg_dma_address(sg
);
467 dma_len
= sg_dma_len(sg
);
473 /* NVMe scatterlists require no holes in the virtual address */
474 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
475 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
477 static int nvme_map_bio(struct device
*dev
, struct nvme_iod
*iod
,
478 struct bio
*bio
, enum dma_data_direction dma_dir
, int psegs
)
480 struct bio_vec
*bvec
, *bvprv
= NULL
;
481 struct scatterlist
*sg
= NULL
;
482 int i
, old_idx
, length
= 0, nsegs
= 0;
484 sg_init_table(iod
->sg
, psegs
);
485 old_idx
= bio
->bi_idx
;
486 bio_for_each_segment(bvec
, bio
, i
) {
487 if (bvprv
&& BIOVEC_PHYS_MERGEABLE(bvprv
, bvec
)) {
488 sg
->length
+= bvec
->bv_len
;
490 if (bvprv
&& BIOVEC_NOT_VIRT_MERGEABLE(bvprv
, bvec
))
492 sg
= sg
? sg
+ 1 : iod
->sg
;
493 sg_set_page(sg
, bvec
->bv_page
, bvec
->bv_len
,
497 length
+= bvec
->bv_len
;
503 if (dma_map_sg(dev
, iod
->sg
, iod
->nents
, dma_dir
) == 0) {
504 bio
->bi_idx
= old_idx
;
510 static int nvme_submit_flush(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
513 struct nvme_command
*cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
515 memset(cmnd
, 0, sizeof(*cmnd
));
516 cmnd
->common
.opcode
= nvme_cmd_flush
;
517 cmnd
->common
.command_id
= cmdid
;
518 cmnd
->common
.nsid
= cpu_to_le32(ns
->ns_id
);
520 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
522 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
527 static int nvme_submit_flush_data(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
)
529 int cmdid
= alloc_cmdid(nvmeq
, (void *)CMD_CTX_FLUSH
,
530 special_completion
, NVME_IO_TIMEOUT
);
531 if (unlikely(cmdid
< 0))
534 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
538 * Called with local interrupts disabled and the q_lock held. May not sleep.
540 static int nvme_submit_bio_queue(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
543 struct nvme_command
*cmnd
;
544 struct nvme_iod
*iod
;
545 enum dma_data_direction dma_dir
;
546 int cmdid
, length
, result
= -ENOMEM
;
549 int psegs
= bio_phys_segments(ns
->queue
, bio
);
551 if ((bio
->bi_rw
& REQ_FLUSH
) && psegs
) {
552 result
= nvme_submit_flush_data(nvmeq
, ns
);
557 iod
= nvme_alloc_iod(psegs
, bio
->bi_size
, GFP_ATOMIC
);
563 cmdid
= alloc_cmdid(nvmeq
, iod
, bio_completion
, NVME_IO_TIMEOUT
);
564 if (unlikely(cmdid
< 0))
567 if ((bio
->bi_rw
& REQ_FLUSH
) && !psegs
)
568 return nvme_submit_flush(nvmeq
, ns
, cmdid
);
571 if (bio
->bi_rw
& REQ_FUA
)
572 control
|= NVME_RW_FUA
;
573 if (bio
->bi_rw
& (REQ_FAILFAST_DEV
| REQ_RAHEAD
))
574 control
|= NVME_RW_LR
;
577 if (bio
->bi_rw
& REQ_RAHEAD
)
578 dsmgmt
|= NVME_RW_DSM_FREQ_PREFETCH
;
580 cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
582 memset(cmnd
, 0, sizeof(*cmnd
));
583 if (bio_data_dir(bio
)) {
584 cmnd
->rw
.opcode
= nvme_cmd_write
;
585 dma_dir
= DMA_TO_DEVICE
;
587 cmnd
->rw
.opcode
= nvme_cmd_read
;
588 dma_dir
= DMA_FROM_DEVICE
;
591 result
= nvme_map_bio(nvmeq
->q_dmadev
, iod
, bio
, dma_dir
, psegs
);
596 cmnd
->rw
.command_id
= cmdid
;
597 cmnd
->rw
.nsid
= cpu_to_le32(ns
->ns_id
);
598 length
= nvme_setup_prps(nvmeq
->dev
, &cmnd
->common
, iod
, length
,
600 cmnd
->rw
.slba
= cpu_to_le64(bio
->bi_sector
>> (ns
->lba_shift
- 9));
601 cmnd
->rw
.length
= cpu_to_le16((length
>> ns
->lba_shift
) - 1);
602 cmnd
->rw
.control
= cpu_to_le16(control
);
603 cmnd
->rw
.dsmgmt
= cpu_to_le32(dsmgmt
);
605 bio
->bi_sector
+= length
>> 9;
607 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
609 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
614 free_cmdid(nvmeq
, cmdid
, NULL
);
616 nvme_free_iod(nvmeq
->dev
, iod
);
621 static void nvme_make_request(struct request_queue
*q
, struct bio
*bio
)
623 struct nvme_ns
*ns
= q
->queuedata
;
624 struct nvme_queue
*nvmeq
= get_nvmeq(ns
->dev
);
627 spin_lock_irq(&nvmeq
->q_lock
);
628 if (bio_list_empty(&nvmeq
->sq_cong
))
629 result
= nvme_submit_bio_queue(nvmeq
, ns
, bio
);
630 if (unlikely(result
)) {
631 if (bio_list_empty(&nvmeq
->sq_cong
))
632 add_wait_queue(&nvmeq
->sq_full
, &nvmeq
->sq_cong_wait
);
633 bio_list_add(&nvmeq
->sq_cong
, bio
);
636 spin_unlock_irq(&nvmeq
->q_lock
);
640 static irqreturn_t
nvme_process_cq(struct nvme_queue
*nvmeq
)
644 head
= nvmeq
->cq_head
;
645 phase
= nvmeq
->cq_phase
;
649 nvme_completion_fn fn
;
650 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
651 if ((le16_to_cpu(cqe
.status
) & 1) != phase
)
653 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
654 if (++head
== nvmeq
->q_depth
) {
659 ctx
= free_cmdid(nvmeq
, cqe
.command_id
, &fn
);
660 fn(nvmeq
->dev
, ctx
, &cqe
);
663 /* If the controller ignores the cq head doorbell and continuously
664 * writes to the queue, it is theoretically possible to wrap around
665 * the queue twice and mistakenly return IRQ_NONE. Linux only
666 * requires that 0.1% of your interrupts are handled, so this isn't
669 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
672 writel(head
, nvmeq
->q_db
+ (1 << nvmeq
->dev
->db_stride
));
673 nvmeq
->cq_head
= head
;
674 nvmeq
->cq_phase
= phase
;
679 static irqreturn_t
nvme_irq(int irq
, void *data
)
682 struct nvme_queue
*nvmeq
= data
;
683 spin_lock(&nvmeq
->q_lock
);
684 result
= nvme_process_cq(nvmeq
);
685 spin_unlock(&nvmeq
->q_lock
);
689 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
691 struct nvme_queue
*nvmeq
= data
;
692 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
693 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
695 return IRQ_WAKE_THREAD
;
698 static void nvme_abort_command(struct nvme_queue
*nvmeq
, int cmdid
)
700 spin_lock_irq(&nvmeq
->q_lock
);
701 cancel_cmdid(nvmeq
, cmdid
, NULL
);
702 spin_unlock_irq(&nvmeq
->q_lock
);
705 struct sync_cmd_info
{
706 struct task_struct
*task
;
711 static void sync_completion(struct nvme_dev
*dev
, void *ctx
,
712 struct nvme_completion
*cqe
)
714 struct sync_cmd_info
*cmdinfo
= ctx
;
715 cmdinfo
->result
= le32_to_cpup(&cqe
->result
);
716 cmdinfo
->status
= le16_to_cpup(&cqe
->status
) >> 1;
717 wake_up_process(cmdinfo
->task
);
721 * Returns 0 on success. If the result is negative, it's a Linux error code;
722 * if the result is positive, it's an NVM Express status code
724 static int nvme_submit_sync_cmd(struct nvme_queue
*nvmeq
,
725 struct nvme_command
*cmd
, u32
*result
, unsigned timeout
)
728 struct sync_cmd_info cmdinfo
;
730 cmdinfo
.task
= current
;
731 cmdinfo
.status
= -EINTR
;
733 cmdid
= alloc_cmdid_killable(nvmeq
, &cmdinfo
, sync_completion
,
737 cmd
->common
.command_id
= cmdid
;
739 set_current_state(TASK_KILLABLE
);
740 nvme_submit_cmd(nvmeq
, cmd
);
743 if (cmdinfo
.status
== -EINTR
) {
744 nvme_abort_command(nvmeq
, cmdid
);
749 *result
= cmdinfo
.result
;
751 return cmdinfo
.status
;
754 static int nvme_submit_admin_cmd(struct nvme_dev
*dev
, struct nvme_command
*cmd
,
757 return nvme_submit_sync_cmd(dev
->queues
[0], cmd
, result
, ADMIN_TIMEOUT
);
760 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
763 struct nvme_command c
;
765 memset(&c
, 0, sizeof(c
));
766 c
.delete_queue
.opcode
= opcode
;
767 c
.delete_queue
.qid
= cpu_to_le16(id
);
769 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
775 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
776 struct nvme_queue
*nvmeq
)
779 struct nvme_command c
;
780 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
782 memset(&c
, 0, sizeof(c
));
783 c
.create_cq
.opcode
= nvme_admin_create_cq
;
784 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
785 c
.create_cq
.cqid
= cpu_to_le16(qid
);
786 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
787 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
788 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
790 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
796 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
797 struct nvme_queue
*nvmeq
)
800 struct nvme_command c
;
801 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
803 memset(&c
, 0, sizeof(c
));
804 c
.create_sq
.opcode
= nvme_admin_create_sq
;
805 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
806 c
.create_sq
.sqid
= cpu_to_le16(qid
);
807 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
808 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
809 c
.create_sq
.cqid
= cpu_to_le16(qid
);
811 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
817 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
819 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
822 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
824 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
827 static int nvme_identify(struct nvme_dev
*dev
, unsigned nsid
, unsigned cns
,
830 struct nvme_command c
;
832 memset(&c
, 0, sizeof(c
));
833 c
.identify
.opcode
= nvme_admin_identify
;
834 c
.identify
.nsid
= cpu_to_le32(nsid
);
835 c
.identify
.prp1
= cpu_to_le64(dma_addr
);
836 c
.identify
.cns
= cpu_to_le32(cns
);
838 return nvme_submit_admin_cmd(dev
, &c
, NULL
);
841 static int nvme_get_features(struct nvme_dev
*dev
, unsigned fid
,
842 unsigned nsid
, dma_addr_t dma_addr
)
844 struct nvme_command c
;
846 memset(&c
, 0, sizeof(c
));
847 c
.features
.opcode
= nvme_admin_get_features
;
848 c
.features
.nsid
= cpu_to_le32(nsid
);
849 c
.features
.prp1
= cpu_to_le64(dma_addr
);
850 c
.features
.fid
= cpu_to_le32(fid
);
852 return nvme_submit_admin_cmd(dev
, &c
, NULL
);
855 static int nvme_set_features(struct nvme_dev
*dev
, unsigned fid
,
856 unsigned dword11
, dma_addr_t dma_addr
, u32
*result
)
858 struct nvme_command c
;
860 memset(&c
, 0, sizeof(c
));
861 c
.features
.opcode
= nvme_admin_set_features
;
862 c
.features
.prp1
= cpu_to_le64(dma_addr
);
863 c
.features
.fid
= cpu_to_le32(fid
);
864 c
.features
.dword11
= cpu_to_le32(dword11
);
866 return nvme_submit_admin_cmd(dev
, &c
, result
);
870 * nvme_cancel_ios - Cancel outstanding I/Os
871 * @queue: The queue to cancel I/Os on
872 * @timeout: True to only cancel I/Os which have timed out
874 static void nvme_cancel_ios(struct nvme_queue
*nvmeq
, bool timeout
)
876 int depth
= nvmeq
->q_depth
- 1;
877 struct nvme_cmd_info
*info
= nvme_cmd_info(nvmeq
);
878 unsigned long now
= jiffies
;
881 for_each_set_bit(cmdid
, nvmeq
->cmdid_data
, depth
) {
883 nvme_completion_fn fn
;
884 static struct nvme_completion cqe
= {
885 .status
= cpu_to_le16(NVME_SC_ABORT_REQ
) << 1,
888 if (timeout
&& !time_after(now
, info
[cmdid
].timeout
))
890 dev_warn(nvmeq
->q_dmadev
, "Cancelling I/O %d\n", cmdid
);
891 ctx
= cancel_cmdid(nvmeq
, cmdid
, &fn
);
892 fn(nvmeq
->dev
, ctx
, &cqe
);
896 static void nvme_free_queue_mem(struct nvme_queue
*nvmeq
)
898 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
899 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
900 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
901 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
905 static void nvme_free_queue(struct nvme_dev
*dev
, int qid
)
907 struct nvme_queue
*nvmeq
= dev
->queues
[qid
];
908 int vector
= dev
->entry
[nvmeq
->cq_vector
].vector
;
910 spin_lock_irq(&nvmeq
->q_lock
);
911 nvme_cancel_ios(nvmeq
, false);
912 spin_unlock_irq(&nvmeq
->q_lock
);
914 irq_set_affinity_hint(vector
, NULL
);
915 free_irq(vector
, nvmeq
);
917 /* Don't tell the adapter to delete the admin queue */
919 adapter_delete_sq(dev
, qid
);
920 adapter_delete_cq(dev
, qid
);
923 nvme_free_queue_mem(nvmeq
);
926 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
927 int depth
, int vector
)
929 struct device
*dmadev
= &dev
->pci_dev
->dev
;
930 unsigned extra
= DIV_ROUND_UP(depth
, 8) + (depth
*
931 sizeof(struct nvme_cmd_info
));
932 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
) + extra
, GFP_KERNEL
);
936 nvmeq
->cqes
= dma_alloc_coherent(dmadev
, CQ_SIZE(depth
),
937 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
940 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(depth
));
942 nvmeq
->sq_cmds
= dma_alloc_coherent(dmadev
, SQ_SIZE(depth
),
943 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
947 nvmeq
->q_dmadev
= dmadev
;
949 spin_lock_init(&nvmeq
->q_lock
);
952 init_waitqueue_head(&nvmeq
->sq_full
);
953 init_waitqueue_entry(&nvmeq
->sq_cong_wait
, nvme_thread
);
954 bio_list_init(&nvmeq
->sq_cong
);
955 nvmeq
->q_db
= &dev
->dbs
[qid
<< (dev
->db_stride
+ 1)];
956 nvmeq
->q_depth
= depth
;
957 nvmeq
->cq_vector
= vector
;
962 dma_free_coherent(dmadev
, CQ_SIZE(nvmeq
->q_depth
), (void *)nvmeq
->cqes
,
969 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
972 if (use_threaded_interrupts
)
973 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
974 nvme_irq_check
, nvme_irq
,
975 IRQF_DISABLED
| IRQF_SHARED
,
977 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
978 IRQF_DISABLED
| IRQF_SHARED
, name
, nvmeq
);
981 static __devinit
struct nvme_queue
*nvme_create_queue(struct nvme_dev
*dev
,
982 int qid
, int cq_size
, int vector
)
985 struct nvme_queue
*nvmeq
= nvme_alloc_queue(dev
, qid
, cq_size
, vector
);
988 return ERR_PTR(-ENOMEM
);
990 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
994 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
998 result
= queue_request_irq(dev
, nvmeq
, "nvme");
1005 adapter_delete_sq(dev
, qid
);
1007 adapter_delete_cq(dev
, qid
);
1009 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1010 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1011 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1012 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1014 return ERR_PTR(result
);
1017 static int __devinit
nvme_configure_admin_queue(struct nvme_dev
*dev
)
1022 unsigned long timeout
;
1023 struct nvme_queue
*nvmeq
;
1025 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
1027 nvmeq
= nvme_alloc_queue(dev
, 0, 64, 0);
1031 aqa
= nvmeq
->q_depth
- 1;
1034 dev
->ctrl_config
= NVME_CC_ENABLE
| NVME_CC_CSS_NVM
;
1035 dev
->ctrl_config
|= (PAGE_SHIFT
- 12) << NVME_CC_MPS_SHIFT
;
1036 dev
->ctrl_config
|= NVME_CC_ARB_RR
| NVME_CC_SHN_NONE
;
1037 dev
->ctrl_config
|= NVME_CC_IOSQES
| NVME_CC_IOCQES
;
1039 writel(0, &dev
->bar
->cc
);
1040 writel(aqa
, &dev
->bar
->aqa
);
1041 writeq(nvmeq
->sq_dma_addr
, &dev
->bar
->asq
);
1042 writeq(nvmeq
->cq_dma_addr
, &dev
->bar
->acq
);
1043 writel(dev
->ctrl_config
, &dev
->bar
->cc
);
1045 cap
= readq(&dev
->bar
->cap
);
1046 timeout
= ((NVME_CAP_TIMEOUT(cap
) + 1) * HZ
/ 2) + jiffies
;
1047 dev
->db_stride
= NVME_CAP_STRIDE(cap
);
1049 while (!result
&& !(readl(&dev
->bar
->csts
) & NVME_CSTS_RDY
)) {
1051 if (fatal_signal_pending(current
))
1053 if (time_after(jiffies
, timeout
)) {
1054 dev_err(&dev
->pci_dev
->dev
,
1055 "Device not ready; aborting initialisation\n");
1061 nvme_free_queue_mem(nvmeq
);
1065 result
= queue_request_irq(dev
, nvmeq
, "nvme admin");
1066 dev
->queues
[0] = nvmeq
;
1070 static struct nvme_iod
*nvme_map_user_pages(struct nvme_dev
*dev
, int write
,
1071 unsigned long addr
, unsigned length
)
1073 int i
, err
, count
, nents
, offset
;
1074 struct scatterlist
*sg
;
1075 struct page
**pages
;
1076 struct nvme_iod
*iod
;
1079 return ERR_PTR(-EINVAL
);
1081 return ERR_PTR(-EINVAL
);
1083 offset
= offset_in_page(addr
);
1084 count
= DIV_ROUND_UP(offset
+ length
, PAGE_SIZE
);
1085 pages
= kcalloc(count
, sizeof(*pages
), GFP_KERNEL
);
1087 return ERR_PTR(-ENOMEM
);
1089 err
= get_user_pages_fast(addr
, count
, 1, pages
);
1096 iod
= nvme_alloc_iod(count
, length
, GFP_KERNEL
);
1098 sg_init_table(sg
, count
);
1099 for (i
= 0; i
< count
; i
++) {
1100 sg_set_page(&sg
[i
], pages
[i
],
1101 min_t(int, length
, PAGE_SIZE
- offset
), offset
);
1102 length
-= (PAGE_SIZE
- offset
);
1105 sg_mark_end(&sg
[i
- 1]);
1109 nents
= dma_map_sg(&dev
->pci_dev
->dev
, sg
, count
,
1110 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1120 for (i
= 0; i
< count
; i
++)
1123 return ERR_PTR(err
);
1126 static void nvme_unmap_user_pages(struct nvme_dev
*dev
, int write
,
1127 struct nvme_iod
*iod
)
1131 dma_unmap_sg(&dev
->pci_dev
->dev
, iod
->sg
, iod
->nents
,
1132 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1134 for (i
= 0; i
< iod
->nents
; i
++)
1135 put_page(sg_page(&iod
->sg
[i
]));
1138 static int nvme_submit_io(struct nvme_ns
*ns
, struct nvme_user_io __user
*uio
)
1140 struct nvme_dev
*dev
= ns
->dev
;
1141 struct nvme_queue
*nvmeq
;
1142 struct nvme_user_io io
;
1143 struct nvme_command c
;
1146 struct nvme_iod
*iod
;
1148 if (copy_from_user(&io
, uio
, sizeof(io
)))
1150 length
= (io
.nblocks
+ 1) << ns
->lba_shift
;
1152 switch (io
.opcode
) {
1153 case nvme_cmd_write
:
1155 case nvme_cmd_compare
:
1156 iod
= nvme_map_user_pages(dev
, io
.opcode
& 1, io
.addr
, length
);
1163 return PTR_ERR(iod
);
1165 memset(&c
, 0, sizeof(c
));
1166 c
.rw
.opcode
= io
.opcode
;
1167 c
.rw
.flags
= io
.flags
;
1168 c
.rw
.nsid
= cpu_to_le32(ns
->ns_id
);
1169 c
.rw
.slba
= cpu_to_le64(io
.slba
);
1170 c
.rw
.length
= cpu_to_le16(io
.nblocks
);
1171 c
.rw
.control
= cpu_to_le16(io
.control
);
1172 c
.rw
.dsmgmt
= cpu_to_le16(io
.dsmgmt
);
1173 c
.rw
.reftag
= io
.reftag
;
1174 c
.rw
.apptag
= io
.apptag
;
1175 c
.rw
.appmask
= io
.appmask
;
1177 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
, GFP_KERNEL
);
1179 nvmeq
= get_nvmeq(dev
);
1181 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1182 * disabled. We may be preempted at any point, and be rescheduled
1183 * to a different CPU. That will cause cacheline bouncing, but no
1184 * additional races since q_lock already protects against other CPUs.
1187 if (length
!= (io
.nblocks
+ 1) << ns
->lba_shift
)
1190 status
= nvme_submit_sync_cmd(nvmeq
, &c
, NULL
, NVME_IO_TIMEOUT
);
1192 nvme_unmap_user_pages(dev
, io
.opcode
& 1, iod
);
1193 nvme_free_iod(dev
, iod
);
1197 static int nvme_user_admin_cmd(struct nvme_dev
*dev
,
1198 struct nvme_admin_cmd __user
*ucmd
)
1200 struct nvme_admin_cmd cmd
;
1201 struct nvme_command c
;
1203 struct nvme_iod
*uninitialized_var(iod
);
1205 if (!capable(CAP_SYS_ADMIN
))
1207 if (copy_from_user(&cmd
, ucmd
, sizeof(cmd
)))
1210 memset(&c
, 0, sizeof(c
));
1211 c
.common
.opcode
= cmd
.opcode
;
1212 c
.common
.flags
= cmd
.flags
;
1213 c
.common
.nsid
= cpu_to_le32(cmd
.nsid
);
1214 c
.common
.cdw2
[0] = cpu_to_le32(cmd
.cdw2
);
1215 c
.common
.cdw2
[1] = cpu_to_le32(cmd
.cdw3
);
1216 c
.common
.cdw10
[0] = cpu_to_le32(cmd
.cdw10
);
1217 c
.common
.cdw10
[1] = cpu_to_le32(cmd
.cdw11
);
1218 c
.common
.cdw10
[2] = cpu_to_le32(cmd
.cdw12
);
1219 c
.common
.cdw10
[3] = cpu_to_le32(cmd
.cdw13
);
1220 c
.common
.cdw10
[4] = cpu_to_le32(cmd
.cdw14
);
1221 c
.common
.cdw10
[5] = cpu_to_le32(cmd
.cdw15
);
1223 length
= cmd
.data_len
;
1225 iod
= nvme_map_user_pages(dev
, cmd
.opcode
& 1, cmd
.addr
,
1228 return PTR_ERR(iod
);
1229 length
= nvme_setup_prps(dev
, &c
.common
, iod
, length
,
1233 if (length
!= cmd
.data_len
)
1236 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
1239 nvme_unmap_user_pages(dev
, cmd
.opcode
& 1, iod
);
1240 nvme_free_iod(dev
, iod
);
1245 static int nvme_ioctl(struct block_device
*bdev
, fmode_t mode
, unsigned int cmd
,
1248 struct nvme_ns
*ns
= bdev
->bd_disk
->private_data
;
1253 case NVME_IOCTL_ADMIN_CMD
:
1254 return nvme_user_admin_cmd(ns
->dev
, (void __user
*)arg
);
1255 case NVME_IOCTL_SUBMIT_IO
:
1256 return nvme_submit_io(ns
, (void __user
*)arg
);
1262 static const struct block_device_operations nvme_fops
= {
1263 .owner
= THIS_MODULE
,
1264 .ioctl
= nvme_ioctl
,
1265 .compat_ioctl
= nvme_ioctl
,
1268 static void nvme_resubmit_bios(struct nvme_queue
*nvmeq
)
1270 while (bio_list_peek(&nvmeq
->sq_cong
)) {
1271 struct bio
*bio
= bio_list_pop(&nvmeq
->sq_cong
);
1272 struct nvme_ns
*ns
= bio
->bi_bdev
->bd_disk
->private_data
;
1273 if (nvme_submit_bio_queue(nvmeq
, ns
, bio
)) {
1274 bio_list_add_head(&nvmeq
->sq_cong
, bio
);
1277 if (bio_list_empty(&nvmeq
->sq_cong
))
1278 remove_wait_queue(&nvmeq
->sq_full
,
1279 &nvmeq
->sq_cong_wait
);
1283 static int nvme_kthread(void *data
)
1285 struct nvme_dev
*dev
;
1287 while (!kthread_should_stop()) {
1288 __set_current_state(TASK_RUNNING
);
1289 spin_lock(&dev_list_lock
);
1290 list_for_each_entry(dev
, &dev_list
, node
) {
1292 for (i
= 0; i
< dev
->queue_count
; i
++) {
1293 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1296 spin_lock_irq(&nvmeq
->q_lock
);
1297 if (nvme_process_cq(nvmeq
))
1298 printk("process_cq did something\n");
1299 nvme_cancel_ios(nvmeq
, true);
1300 nvme_resubmit_bios(nvmeq
);
1301 spin_unlock_irq(&nvmeq
->q_lock
);
1304 spin_unlock(&dev_list_lock
);
1305 set_current_state(TASK_INTERRUPTIBLE
);
1306 schedule_timeout(HZ
);
1311 static DEFINE_IDA(nvme_index_ida
);
1313 static int nvme_get_ns_idx(void)
1318 if (!ida_pre_get(&nvme_index_ida
, GFP_KERNEL
))
1321 spin_lock(&dev_list_lock
);
1322 error
= ida_get_new(&nvme_index_ida
, &index
);
1323 spin_unlock(&dev_list_lock
);
1324 } while (error
== -EAGAIN
);
1331 static void nvme_put_ns_idx(int index
)
1333 spin_lock(&dev_list_lock
);
1334 ida_remove(&nvme_index_ida
, index
);
1335 spin_unlock(&dev_list_lock
);
1338 static struct nvme_ns
*nvme_alloc_ns(struct nvme_dev
*dev
, int nsid
,
1339 struct nvme_id_ns
*id
, struct nvme_lba_range_type
*rt
)
1342 struct gendisk
*disk
;
1345 if (rt
->attributes
& NVME_LBART_ATTRIB_HIDE
)
1348 ns
= kzalloc(sizeof(*ns
), GFP_KERNEL
);
1351 ns
->queue
= blk_alloc_queue(GFP_KERNEL
);
1354 ns
->queue
->queue_flags
= QUEUE_FLAG_DEFAULT
;
1355 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES
, ns
->queue
);
1356 queue_flag_set_unlocked(QUEUE_FLAG_NONROT
, ns
->queue
);
1357 /* queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); */
1358 blk_queue_make_request(ns
->queue
, nvme_make_request
);
1360 ns
->queue
->queuedata
= ns
;
1362 disk
= alloc_disk(NVME_MINORS
);
1364 goto out_free_queue
;
1367 lbaf
= id
->flbas
& 0xf;
1368 ns
->lba_shift
= id
->lbaf
[lbaf
].ds
;
1369 blk_queue_logical_block_size(ns
->queue
, 1 << ns
->lba_shift
);
1370 if (dev
->max_hw_sectors
)
1371 blk_queue_max_hw_sectors(ns
->queue
, dev
->max_hw_sectors
);
1373 disk
->major
= nvme_major
;
1374 disk
->minors
= NVME_MINORS
;
1375 disk
->first_minor
= NVME_MINORS
* nvme_get_ns_idx();
1376 disk
->fops
= &nvme_fops
;
1377 disk
->private_data
= ns
;
1378 disk
->queue
= ns
->queue
;
1379 disk
->driverfs_dev
= &dev
->pci_dev
->dev
;
1380 sprintf(disk
->disk_name
, "nvme%dn%d", dev
->instance
, nsid
);
1381 set_capacity(disk
, le64_to_cpup(&id
->nsze
) << (ns
->lba_shift
- 9));
1386 blk_cleanup_queue(ns
->queue
);
1392 static void nvme_ns_free(struct nvme_ns
*ns
)
1394 int index
= ns
->disk
->first_minor
/ NVME_MINORS
;
1396 nvme_put_ns_idx(index
);
1397 blk_cleanup_queue(ns
->queue
);
1401 static int set_queue_count(struct nvme_dev
*dev
, int count
)
1405 u32 q_count
= (count
- 1) | ((count
- 1) << 16);
1407 status
= nvme_set_features(dev
, NVME_FEAT_NUM_QUEUES
, q_count
, 0,
1411 return min(result
& 0xffff, result
>> 16) + 1;
1414 static int __devinit
nvme_setup_io_queues(struct nvme_dev
*dev
)
1416 int result
, cpu
, i
, nr_io_queues
, db_bar_size
, q_depth
;
1418 nr_io_queues
= num_online_cpus();
1419 result
= set_queue_count(dev
, nr_io_queues
);
1422 if (result
< nr_io_queues
)
1423 nr_io_queues
= result
;
1425 /* Deregister the admin queue's interrupt */
1426 free_irq(dev
->entry
[0].vector
, dev
->queues
[0]);
1428 db_bar_size
= 4096 + ((nr_io_queues
+ 1) << (dev
->db_stride
+ 3));
1429 if (db_bar_size
> 8192) {
1431 dev
->bar
= ioremap(pci_resource_start(dev
->pci_dev
, 0),
1433 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
1434 dev
->queues
[0]->q_db
= dev
->dbs
;
1437 for (i
= 0; i
< nr_io_queues
; i
++)
1438 dev
->entry
[i
].entry
= i
;
1440 result
= pci_enable_msix(dev
->pci_dev
, dev
->entry
,
1444 } else if (result
> 0) {
1445 nr_io_queues
= result
;
1453 result
= queue_request_irq(dev
, dev
->queues
[0], "nvme admin");
1454 /* XXX: handle failure here */
1456 cpu
= cpumask_first(cpu_online_mask
);
1457 for (i
= 0; i
< nr_io_queues
; i
++) {
1458 irq_set_affinity_hint(dev
->entry
[i
].vector
, get_cpu_mask(cpu
));
1459 cpu
= cpumask_next(cpu
, cpu_online_mask
);
1462 q_depth
= min_t(int, NVME_CAP_MQES(readq(&dev
->bar
->cap
)) + 1,
1464 for (i
= 0; i
< nr_io_queues
; i
++) {
1465 dev
->queues
[i
+ 1] = nvme_create_queue(dev
, i
+ 1, q_depth
, i
);
1466 if (IS_ERR(dev
->queues
[i
+ 1]))
1467 return PTR_ERR(dev
->queues
[i
+ 1]);
1471 for (; i
< num_possible_cpus(); i
++) {
1472 int target
= i
% rounddown_pow_of_two(dev
->queue_count
- 1);
1473 dev
->queues
[i
+ 1] = dev
->queues
[target
+ 1];
1479 static void nvme_free_queues(struct nvme_dev
*dev
)
1483 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
1484 nvme_free_queue(dev
, i
);
1487 static int __devinit
nvme_dev_add(struct nvme_dev
*dev
)
1490 struct nvme_ns
*ns
, *next
;
1491 struct nvme_id_ctrl
*ctrl
;
1492 struct nvme_id_ns
*id_ns
;
1494 dma_addr_t dma_addr
;
1496 res
= nvme_setup_io_queues(dev
);
1500 mem
= dma_alloc_coherent(&dev
->pci_dev
->dev
, 8192, &dma_addr
,
1503 res
= nvme_identify(dev
, 0, 1, dma_addr
);
1510 nn
= le32_to_cpup(&ctrl
->nn
);
1511 memcpy(dev
->serial
, ctrl
->sn
, sizeof(ctrl
->sn
));
1512 memcpy(dev
->model
, ctrl
->mn
, sizeof(ctrl
->mn
));
1513 memcpy(dev
->firmware_rev
, ctrl
->fr
, sizeof(ctrl
->fr
));
1515 int shift
= NVME_CAP_MPSMIN(readq(&dev
->bar
->cap
)) + 12;
1516 dev
->max_hw_sectors
= 1 << (ctrl
->mdts
+ shift
- 9);
1520 for (i
= 1; i
<= nn
; i
++) {
1521 res
= nvme_identify(dev
, i
, 0, dma_addr
);
1525 if (id_ns
->ncap
== 0)
1528 res
= nvme_get_features(dev
, NVME_FEAT_LBA_RANGE
, i
,
1533 ns
= nvme_alloc_ns(dev
, i
, mem
, mem
+ 4096);
1535 list_add_tail(&ns
->list
, &dev
->namespaces
);
1537 list_for_each_entry(ns
, &dev
->namespaces
, list
)
1543 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1544 list_del(&ns
->list
);
1549 dma_free_coherent(&dev
->pci_dev
->dev
, 8192, mem
, dma_addr
);
1553 static int nvme_dev_remove(struct nvme_dev
*dev
)
1555 struct nvme_ns
*ns
, *next
;
1557 spin_lock(&dev_list_lock
);
1558 list_del(&dev
->node
);
1559 spin_unlock(&dev_list_lock
);
1561 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1562 list_del(&ns
->list
);
1563 del_gendisk(ns
->disk
);
1567 nvme_free_queues(dev
);
1572 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1574 struct device
*dmadev
= &dev
->pci_dev
->dev
;
1575 dev
->prp_page_pool
= dma_pool_create("prp list page", dmadev
,
1576 PAGE_SIZE
, PAGE_SIZE
, 0);
1577 if (!dev
->prp_page_pool
)
1580 /* Optimisation for I/Os between 4k and 128k */
1581 dev
->prp_small_pool
= dma_pool_create("prp list 256", dmadev
,
1583 if (!dev
->prp_small_pool
) {
1584 dma_pool_destroy(dev
->prp_page_pool
);
1590 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1592 dma_pool_destroy(dev
->prp_page_pool
);
1593 dma_pool_destroy(dev
->prp_small_pool
);
1596 static DEFINE_IDA(nvme_instance_ida
);
1598 static int nvme_set_instance(struct nvme_dev
*dev
)
1600 int instance
, error
;
1603 if (!ida_pre_get(&nvme_instance_ida
, GFP_KERNEL
))
1606 spin_lock(&dev_list_lock
);
1607 error
= ida_get_new(&nvme_instance_ida
, &instance
);
1608 spin_unlock(&dev_list_lock
);
1609 } while (error
== -EAGAIN
);
1614 dev
->instance
= instance
;
1618 static void nvme_release_instance(struct nvme_dev
*dev
)
1620 spin_lock(&dev_list_lock
);
1621 ida_remove(&nvme_instance_ida
, dev
->instance
);
1622 spin_unlock(&dev_list_lock
);
1625 static int __devinit
nvme_probe(struct pci_dev
*pdev
,
1626 const struct pci_device_id
*id
)
1628 int bars
, result
= -ENOMEM
;
1629 struct nvme_dev
*dev
;
1631 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1634 dev
->entry
= kcalloc(num_possible_cpus(), sizeof(*dev
->entry
),
1638 dev
->queues
= kcalloc(num_possible_cpus() + 1, sizeof(void *),
1643 if (pci_enable_device_mem(pdev
))
1645 pci_set_master(pdev
);
1646 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1647 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1650 INIT_LIST_HEAD(&dev
->namespaces
);
1651 dev
->pci_dev
= pdev
;
1652 pci_set_drvdata(pdev
, dev
);
1653 dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1654 dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1655 result
= nvme_set_instance(dev
);
1659 dev
->entry
[0].vector
= pdev
->irq
;
1661 result
= nvme_setup_prp_pools(dev
);
1665 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1671 result
= nvme_configure_admin_queue(dev
);
1676 spin_lock(&dev_list_lock
);
1677 list_add(&dev
->node
, &dev_list
);
1678 spin_unlock(&dev_list_lock
);
1680 result
= nvme_dev_add(dev
);
1687 spin_lock(&dev_list_lock
);
1688 list_del(&dev
->node
);
1689 spin_unlock(&dev_list_lock
);
1691 nvme_free_queues(dev
);
1695 pci_disable_msix(pdev
);
1696 nvme_release_instance(dev
);
1697 nvme_release_prp_pools(dev
);
1699 pci_disable_device(pdev
);
1700 pci_release_regions(pdev
);
1708 static void __devexit
nvme_remove(struct pci_dev
*pdev
)
1710 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
1711 nvme_dev_remove(dev
);
1712 pci_disable_msix(pdev
);
1714 nvme_release_instance(dev
);
1715 nvme_release_prp_pools(dev
);
1716 pci_disable_device(pdev
);
1717 pci_release_regions(pdev
);
1723 /* These functions are yet to be implemented */
1724 #define nvme_error_detected NULL
1725 #define nvme_dump_registers NULL
1726 #define nvme_link_reset NULL
1727 #define nvme_slot_reset NULL
1728 #define nvme_error_resume NULL
1729 #define nvme_suspend NULL
1730 #define nvme_resume NULL
1732 static const struct pci_error_handlers nvme_err_handler
= {
1733 .error_detected
= nvme_error_detected
,
1734 .mmio_enabled
= nvme_dump_registers
,
1735 .link_reset
= nvme_link_reset
,
1736 .slot_reset
= nvme_slot_reset
,
1737 .resume
= nvme_error_resume
,
1740 /* Move to pci_ids.h later */
1741 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1743 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table
) = {
1744 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
1747 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
1749 static struct pci_driver nvme_driver
= {
1751 .id_table
= nvme_id_table
,
1752 .probe
= nvme_probe
,
1753 .remove
= __devexit_p(nvme_remove
),
1754 .suspend
= nvme_suspend
,
1755 .resume
= nvme_resume
,
1756 .err_handler
= &nvme_err_handler
,
1759 static int __init
nvme_init(void)
1763 nvme_thread
= kthread_run(nvme_kthread
, NULL
, "nvme");
1764 if (IS_ERR(nvme_thread
))
1765 return PTR_ERR(nvme_thread
);
1767 result
= register_blkdev(nvme_major
, "nvme");
1770 else if (result
> 0)
1771 nvme_major
= result
;
1773 result
= pci_register_driver(&nvme_driver
);
1775 goto unregister_blkdev
;
1779 unregister_blkdev(nvme_major
, "nvme");
1781 kthread_stop(nvme_thread
);
1785 static void __exit
nvme_exit(void)
1787 pci_unregister_driver(&nvme_driver
);
1788 unregister_blkdev(nvme_major
, "nvme");
1789 kthread_stop(nvme_thread
);
1792 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1793 MODULE_LICENSE("GPL");
1794 MODULE_VERSION("0.8");
1795 module_init(nvme_init
);
1796 module_exit(nvme_exit
);