NVMe: Free cmdid on nvme_submit_bio error
[deliverable/linux.git] / drivers / block / nvme.c
1 /*
2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <linux/fs.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42
43 #include <asm-generic/io-64-nonatomic-lo-hi.h>
44
45 #define NVME_Q_DEPTH 1024
46 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
48 #define NVME_MINORS 64
49 #define NVME_IO_TIMEOUT (5 * HZ)
50 #define ADMIN_TIMEOUT (60 * HZ)
51
52 static int nvme_major;
53 module_param(nvme_major, int, 0);
54
55 static int use_threaded_interrupts;
56 module_param(use_threaded_interrupts, int, 0);
57
58 static DEFINE_SPINLOCK(dev_list_lock);
59 static LIST_HEAD(dev_list);
60 static struct task_struct *nvme_thread;
61
62 /*
63 * Represents an NVM Express device. Each nvme_dev is a PCI function.
64 */
65 struct nvme_dev {
66 struct list_head node;
67 struct nvme_queue **queues;
68 u32 __iomem *dbs;
69 struct pci_dev *pci_dev;
70 struct dma_pool *prp_page_pool;
71 struct dma_pool *prp_small_pool;
72 int instance;
73 int queue_count;
74 int db_stride;
75 u32 ctrl_config;
76 struct msix_entry *entry;
77 struct nvme_bar __iomem *bar;
78 struct list_head namespaces;
79 char serial[20];
80 char model[40];
81 char firmware_rev[8];
82 u32 max_hw_sectors;
83 };
84
85 /*
86 * An NVM Express namespace is equivalent to a SCSI LUN
87 */
88 struct nvme_ns {
89 struct list_head list;
90
91 struct nvme_dev *dev;
92 struct request_queue *queue;
93 struct gendisk *disk;
94
95 int ns_id;
96 int lba_shift;
97 };
98
99 /*
100 * An NVM Express queue. Each device has at least two (one for admin
101 * commands and one for I/O commands).
102 */
103 struct nvme_queue {
104 struct device *q_dmadev;
105 struct nvme_dev *dev;
106 spinlock_t q_lock;
107 struct nvme_command *sq_cmds;
108 volatile struct nvme_completion *cqes;
109 dma_addr_t sq_dma_addr;
110 dma_addr_t cq_dma_addr;
111 wait_queue_head_t sq_full;
112 wait_queue_t sq_cong_wait;
113 struct bio_list sq_cong;
114 u32 __iomem *q_db;
115 u16 q_depth;
116 u16 cq_vector;
117 u16 sq_head;
118 u16 sq_tail;
119 u16 cq_head;
120 u16 cq_phase;
121 unsigned long cmdid_data[];
122 };
123
124 /*
125 * Check we didin't inadvertently grow the command struct
126 */
127 static inline void _nvme_check_size(void)
128 {
129 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
132 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
134 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
135 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
136 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
137 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
138 }
139
140 typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
141 struct nvme_completion *);
142
143 struct nvme_cmd_info {
144 nvme_completion_fn fn;
145 void *ctx;
146 unsigned long timeout;
147 };
148
149 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
150 {
151 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
152 }
153
154 /**
155 * alloc_cmdid() - Allocate a Command ID
156 * @nvmeq: The queue that will be used for this command
157 * @ctx: A pointer that will be passed to the handler
158 * @handler: The function to call on completion
159 *
160 * Allocate a Command ID for a queue. The data passed in will
161 * be passed to the completion handler. This is implemented by using
162 * the bottom two bits of the ctx pointer to store the handler ID.
163 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
164 * We can change this if it becomes a problem.
165 *
166 * May be called with local interrupts disabled and the q_lock held,
167 * or with interrupts enabled and no locks held.
168 */
169 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
170 nvme_completion_fn handler, unsigned timeout)
171 {
172 int depth = nvmeq->q_depth - 1;
173 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
174 int cmdid;
175
176 do {
177 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
178 if (cmdid >= depth)
179 return -EBUSY;
180 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
181
182 info[cmdid].fn = handler;
183 info[cmdid].ctx = ctx;
184 info[cmdid].timeout = jiffies + timeout;
185 return cmdid;
186 }
187
188 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
189 nvme_completion_fn handler, unsigned timeout)
190 {
191 int cmdid;
192 wait_event_killable(nvmeq->sq_full,
193 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
194 return (cmdid < 0) ? -EINTR : cmdid;
195 }
196
197 /* Special values must be less than 0x1000 */
198 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
199 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
200 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
201 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
202 #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
203
204 static void special_completion(struct nvme_dev *dev, void *ctx,
205 struct nvme_completion *cqe)
206 {
207 if (ctx == CMD_CTX_CANCELLED)
208 return;
209 if (ctx == CMD_CTX_FLUSH)
210 return;
211 if (ctx == CMD_CTX_COMPLETED) {
212 dev_warn(&dev->pci_dev->dev,
213 "completed id %d twice on queue %d\n",
214 cqe->command_id, le16_to_cpup(&cqe->sq_id));
215 return;
216 }
217 if (ctx == CMD_CTX_INVALID) {
218 dev_warn(&dev->pci_dev->dev,
219 "invalid id %d completed on queue %d\n",
220 cqe->command_id, le16_to_cpup(&cqe->sq_id));
221 return;
222 }
223
224 dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
225 }
226
227 /*
228 * Called with local interrupts disabled and the q_lock held. May not sleep.
229 */
230 static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
231 nvme_completion_fn *fn)
232 {
233 void *ctx;
234 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
235
236 if (cmdid >= nvmeq->q_depth) {
237 *fn = special_completion;
238 return CMD_CTX_INVALID;
239 }
240 if (fn)
241 *fn = info[cmdid].fn;
242 ctx = info[cmdid].ctx;
243 info[cmdid].fn = special_completion;
244 info[cmdid].ctx = CMD_CTX_COMPLETED;
245 clear_bit(cmdid, nvmeq->cmdid_data);
246 wake_up(&nvmeq->sq_full);
247 return ctx;
248 }
249
250 static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
251 nvme_completion_fn *fn)
252 {
253 void *ctx;
254 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
255 if (fn)
256 *fn = info[cmdid].fn;
257 ctx = info[cmdid].ctx;
258 info[cmdid].fn = special_completion;
259 info[cmdid].ctx = CMD_CTX_CANCELLED;
260 return ctx;
261 }
262
263 static struct nvme_queue *get_nvmeq(struct nvme_dev *dev)
264 {
265 return dev->queues[get_cpu() + 1];
266 }
267
268 static void put_nvmeq(struct nvme_queue *nvmeq)
269 {
270 put_cpu();
271 }
272
273 /**
274 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
275 * @nvmeq: The queue to use
276 * @cmd: The command to send
277 *
278 * Safe to use from interrupt context
279 */
280 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
281 {
282 unsigned long flags;
283 u16 tail;
284 spin_lock_irqsave(&nvmeq->q_lock, flags);
285 tail = nvmeq->sq_tail;
286 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
287 if (++tail == nvmeq->q_depth)
288 tail = 0;
289 writel(tail, nvmeq->q_db);
290 nvmeq->sq_tail = tail;
291 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
292
293 return 0;
294 }
295
296 /*
297 * The nvme_iod describes the data in an I/O, including the list of PRP
298 * entries. You can't see it in this data structure because C doesn't let
299 * me express that. Use nvme_alloc_iod to ensure there's enough space
300 * allocated to store the PRP list.
301 */
302 struct nvme_iod {
303 void *private; /* For the use of the submitter of the I/O */
304 int npages; /* In the PRP list. 0 means small pool in use */
305 int offset; /* Of PRP list */
306 int nents; /* Used in scatterlist */
307 int length; /* Of data, in bytes */
308 dma_addr_t first_dma;
309 struct scatterlist sg[0];
310 };
311
312 static __le64 **iod_list(struct nvme_iod *iod)
313 {
314 return ((void *)iod) + iod->offset;
315 }
316
317 /*
318 * Will slightly overestimate the number of pages needed. This is OK
319 * as it only leads to a small amount of wasted memory for the lifetime of
320 * the I/O.
321 */
322 static int nvme_npages(unsigned size)
323 {
324 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
325 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
326 }
327
328 static struct nvme_iod *
329 nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
330 {
331 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
332 sizeof(__le64 *) * nvme_npages(nbytes) +
333 sizeof(struct scatterlist) * nseg, gfp);
334
335 if (iod) {
336 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
337 iod->npages = -1;
338 iod->length = nbytes;
339 }
340
341 return iod;
342 }
343
344 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
345 {
346 const int last_prp = PAGE_SIZE / 8 - 1;
347 int i;
348 __le64 **list = iod_list(iod);
349 dma_addr_t prp_dma = iod->first_dma;
350
351 if (iod->npages == 0)
352 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
353 for (i = 0; i < iod->npages; i++) {
354 __le64 *prp_list = list[i];
355 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
356 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
357 prp_dma = next_prp_dma;
358 }
359 kfree(iod);
360 }
361
362 static void requeue_bio(struct nvme_dev *dev, struct bio *bio)
363 {
364 struct nvme_queue *nvmeq = get_nvmeq(dev);
365 if (bio_list_empty(&nvmeq->sq_cong))
366 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
367 bio_list_add(&nvmeq->sq_cong, bio);
368 put_nvmeq(nvmeq);
369 wake_up_process(nvme_thread);
370 }
371
372 static void bio_completion(struct nvme_dev *dev, void *ctx,
373 struct nvme_completion *cqe)
374 {
375 struct nvme_iod *iod = ctx;
376 struct bio *bio = iod->private;
377 u16 status = le16_to_cpup(&cqe->status) >> 1;
378
379 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
380 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
381 nvme_free_iod(dev, iod);
382 if (status) {
383 bio_endio(bio, -EIO);
384 } else if (bio->bi_vcnt > bio->bi_idx) {
385 requeue_bio(dev, bio);
386 } else {
387 bio_endio(bio, 0);
388 }
389 }
390
391 /* length is in bytes. gfp flags indicates whether we may sleep. */
392 static int nvme_setup_prps(struct nvme_dev *dev,
393 struct nvme_common_command *cmd, struct nvme_iod *iod,
394 int total_len, gfp_t gfp)
395 {
396 struct dma_pool *pool;
397 int length = total_len;
398 struct scatterlist *sg = iod->sg;
399 int dma_len = sg_dma_len(sg);
400 u64 dma_addr = sg_dma_address(sg);
401 int offset = offset_in_page(dma_addr);
402 __le64 *prp_list;
403 __le64 **list = iod_list(iod);
404 dma_addr_t prp_dma;
405 int nprps, i;
406
407 cmd->prp1 = cpu_to_le64(dma_addr);
408 length -= (PAGE_SIZE - offset);
409 if (length <= 0)
410 return total_len;
411
412 dma_len -= (PAGE_SIZE - offset);
413 if (dma_len) {
414 dma_addr += (PAGE_SIZE - offset);
415 } else {
416 sg = sg_next(sg);
417 dma_addr = sg_dma_address(sg);
418 dma_len = sg_dma_len(sg);
419 }
420
421 if (length <= PAGE_SIZE) {
422 cmd->prp2 = cpu_to_le64(dma_addr);
423 return total_len;
424 }
425
426 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
427 if (nprps <= (256 / 8)) {
428 pool = dev->prp_small_pool;
429 iod->npages = 0;
430 } else {
431 pool = dev->prp_page_pool;
432 iod->npages = 1;
433 }
434
435 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
436 if (!prp_list) {
437 cmd->prp2 = cpu_to_le64(dma_addr);
438 iod->npages = -1;
439 return (total_len - length) + PAGE_SIZE;
440 }
441 list[0] = prp_list;
442 iod->first_dma = prp_dma;
443 cmd->prp2 = cpu_to_le64(prp_dma);
444 i = 0;
445 for (;;) {
446 if (i == PAGE_SIZE / 8) {
447 __le64 *old_prp_list = prp_list;
448 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
449 if (!prp_list)
450 return total_len - length;
451 list[iod->npages++] = prp_list;
452 prp_list[0] = old_prp_list[i - 1];
453 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
454 i = 1;
455 }
456 prp_list[i++] = cpu_to_le64(dma_addr);
457 dma_len -= PAGE_SIZE;
458 dma_addr += PAGE_SIZE;
459 length -= PAGE_SIZE;
460 if (length <= 0)
461 break;
462 if (dma_len > 0)
463 continue;
464 BUG_ON(dma_len < 0);
465 sg = sg_next(sg);
466 dma_addr = sg_dma_address(sg);
467 dma_len = sg_dma_len(sg);
468 }
469
470 return total_len;
471 }
472
473 /* NVMe scatterlists require no holes in the virtual address */
474 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
475 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
476
477 static int nvme_map_bio(struct device *dev, struct nvme_iod *iod,
478 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
479 {
480 struct bio_vec *bvec, *bvprv = NULL;
481 struct scatterlist *sg = NULL;
482 int i, old_idx, length = 0, nsegs = 0;
483
484 sg_init_table(iod->sg, psegs);
485 old_idx = bio->bi_idx;
486 bio_for_each_segment(bvec, bio, i) {
487 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
488 sg->length += bvec->bv_len;
489 } else {
490 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
491 break;
492 sg = sg ? sg + 1 : iod->sg;
493 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
494 bvec->bv_offset);
495 nsegs++;
496 }
497 length += bvec->bv_len;
498 bvprv = bvec;
499 }
500 bio->bi_idx = i;
501 iod->nents = nsegs;
502 sg_mark_end(sg);
503 if (dma_map_sg(dev, iod->sg, iod->nents, dma_dir) == 0) {
504 bio->bi_idx = old_idx;
505 return -ENOMEM;
506 }
507 return length;
508 }
509
510 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
511 int cmdid)
512 {
513 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
514
515 memset(cmnd, 0, sizeof(*cmnd));
516 cmnd->common.opcode = nvme_cmd_flush;
517 cmnd->common.command_id = cmdid;
518 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
519
520 if (++nvmeq->sq_tail == nvmeq->q_depth)
521 nvmeq->sq_tail = 0;
522 writel(nvmeq->sq_tail, nvmeq->q_db);
523
524 return 0;
525 }
526
527 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
528 {
529 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
530 special_completion, NVME_IO_TIMEOUT);
531 if (unlikely(cmdid < 0))
532 return cmdid;
533
534 return nvme_submit_flush(nvmeq, ns, cmdid);
535 }
536
537 /*
538 * Called with local interrupts disabled and the q_lock held. May not sleep.
539 */
540 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
541 struct bio *bio)
542 {
543 struct nvme_command *cmnd;
544 struct nvme_iod *iod;
545 enum dma_data_direction dma_dir;
546 int cmdid, length, result = -ENOMEM;
547 u16 control;
548 u32 dsmgmt;
549 int psegs = bio_phys_segments(ns->queue, bio);
550
551 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
552 result = nvme_submit_flush_data(nvmeq, ns);
553 if (result)
554 return result;
555 }
556
557 iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC);
558 if (!iod)
559 goto nomem;
560 iod->private = bio;
561
562 result = -EBUSY;
563 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
564 if (unlikely(cmdid < 0))
565 goto free_iod;
566
567 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
568 return nvme_submit_flush(nvmeq, ns, cmdid);
569
570 control = 0;
571 if (bio->bi_rw & REQ_FUA)
572 control |= NVME_RW_FUA;
573 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
574 control |= NVME_RW_LR;
575
576 dsmgmt = 0;
577 if (bio->bi_rw & REQ_RAHEAD)
578 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
579
580 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
581
582 memset(cmnd, 0, sizeof(*cmnd));
583 if (bio_data_dir(bio)) {
584 cmnd->rw.opcode = nvme_cmd_write;
585 dma_dir = DMA_TO_DEVICE;
586 } else {
587 cmnd->rw.opcode = nvme_cmd_read;
588 dma_dir = DMA_FROM_DEVICE;
589 }
590
591 result = nvme_map_bio(nvmeq->q_dmadev, iod, bio, dma_dir, psegs);
592 if (result < 0)
593 goto free_cmdid;
594 length = result;
595
596 cmnd->rw.command_id = cmdid;
597 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
598 length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
599 GFP_ATOMIC);
600 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
601 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
602 cmnd->rw.control = cpu_to_le16(control);
603 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
604
605 bio->bi_sector += length >> 9;
606
607 if (++nvmeq->sq_tail == nvmeq->q_depth)
608 nvmeq->sq_tail = 0;
609 writel(nvmeq->sq_tail, nvmeq->q_db);
610
611 return 0;
612
613 free_cmdid:
614 free_cmdid(nvmeq, cmdid, NULL);
615 free_iod:
616 nvme_free_iod(nvmeq->dev, iod);
617 nomem:
618 return result;
619 }
620
621 static void nvme_make_request(struct request_queue *q, struct bio *bio)
622 {
623 struct nvme_ns *ns = q->queuedata;
624 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
625 int result = -EBUSY;
626
627 spin_lock_irq(&nvmeq->q_lock);
628 if (bio_list_empty(&nvmeq->sq_cong))
629 result = nvme_submit_bio_queue(nvmeq, ns, bio);
630 if (unlikely(result)) {
631 if (bio_list_empty(&nvmeq->sq_cong))
632 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
633 bio_list_add(&nvmeq->sq_cong, bio);
634 }
635
636 spin_unlock_irq(&nvmeq->q_lock);
637 put_nvmeq(nvmeq);
638 }
639
640 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
641 {
642 u16 head, phase;
643
644 head = nvmeq->cq_head;
645 phase = nvmeq->cq_phase;
646
647 for (;;) {
648 void *ctx;
649 nvme_completion_fn fn;
650 struct nvme_completion cqe = nvmeq->cqes[head];
651 if ((le16_to_cpu(cqe.status) & 1) != phase)
652 break;
653 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
654 if (++head == nvmeq->q_depth) {
655 head = 0;
656 phase = !phase;
657 }
658
659 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
660 fn(nvmeq->dev, ctx, &cqe);
661 }
662
663 /* If the controller ignores the cq head doorbell and continuously
664 * writes to the queue, it is theoretically possible to wrap around
665 * the queue twice and mistakenly return IRQ_NONE. Linux only
666 * requires that 0.1% of your interrupts are handled, so this isn't
667 * a big problem.
668 */
669 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
670 return IRQ_NONE;
671
672 writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride));
673 nvmeq->cq_head = head;
674 nvmeq->cq_phase = phase;
675
676 return IRQ_HANDLED;
677 }
678
679 static irqreturn_t nvme_irq(int irq, void *data)
680 {
681 irqreturn_t result;
682 struct nvme_queue *nvmeq = data;
683 spin_lock(&nvmeq->q_lock);
684 result = nvme_process_cq(nvmeq);
685 spin_unlock(&nvmeq->q_lock);
686 return result;
687 }
688
689 static irqreturn_t nvme_irq_check(int irq, void *data)
690 {
691 struct nvme_queue *nvmeq = data;
692 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
693 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
694 return IRQ_NONE;
695 return IRQ_WAKE_THREAD;
696 }
697
698 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
699 {
700 spin_lock_irq(&nvmeq->q_lock);
701 cancel_cmdid(nvmeq, cmdid, NULL);
702 spin_unlock_irq(&nvmeq->q_lock);
703 }
704
705 struct sync_cmd_info {
706 struct task_struct *task;
707 u32 result;
708 int status;
709 };
710
711 static void sync_completion(struct nvme_dev *dev, void *ctx,
712 struct nvme_completion *cqe)
713 {
714 struct sync_cmd_info *cmdinfo = ctx;
715 cmdinfo->result = le32_to_cpup(&cqe->result);
716 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
717 wake_up_process(cmdinfo->task);
718 }
719
720 /*
721 * Returns 0 on success. If the result is negative, it's a Linux error code;
722 * if the result is positive, it's an NVM Express status code
723 */
724 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
725 struct nvme_command *cmd, u32 *result, unsigned timeout)
726 {
727 int cmdid;
728 struct sync_cmd_info cmdinfo;
729
730 cmdinfo.task = current;
731 cmdinfo.status = -EINTR;
732
733 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
734 timeout);
735 if (cmdid < 0)
736 return cmdid;
737 cmd->common.command_id = cmdid;
738
739 set_current_state(TASK_KILLABLE);
740 nvme_submit_cmd(nvmeq, cmd);
741 schedule();
742
743 if (cmdinfo.status == -EINTR) {
744 nvme_abort_command(nvmeq, cmdid);
745 return -EINTR;
746 }
747
748 if (result)
749 *result = cmdinfo.result;
750
751 return cmdinfo.status;
752 }
753
754 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
755 u32 *result)
756 {
757 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
758 }
759
760 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
761 {
762 int status;
763 struct nvme_command c;
764
765 memset(&c, 0, sizeof(c));
766 c.delete_queue.opcode = opcode;
767 c.delete_queue.qid = cpu_to_le16(id);
768
769 status = nvme_submit_admin_cmd(dev, &c, NULL);
770 if (status)
771 return -EIO;
772 return 0;
773 }
774
775 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
776 struct nvme_queue *nvmeq)
777 {
778 int status;
779 struct nvme_command c;
780 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
781
782 memset(&c, 0, sizeof(c));
783 c.create_cq.opcode = nvme_admin_create_cq;
784 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
785 c.create_cq.cqid = cpu_to_le16(qid);
786 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
787 c.create_cq.cq_flags = cpu_to_le16(flags);
788 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
789
790 status = nvme_submit_admin_cmd(dev, &c, NULL);
791 if (status)
792 return -EIO;
793 return 0;
794 }
795
796 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
797 struct nvme_queue *nvmeq)
798 {
799 int status;
800 struct nvme_command c;
801 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
802
803 memset(&c, 0, sizeof(c));
804 c.create_sq.opcode = nvme_admin_create_sq;
805 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
806 c.create_sq.sqid = cpu_to_le16(qid);
807 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
808 c.create_sq.sq_flags = cpu_to_le16(flags);
809 c.create_sq.cqid = cpu_to_le16(qid);
810
811 status = nvme_submit_admin_cmd(dev, &c, NULL);
812 if (status)
813 return -EIO;
814 return 0;
815 }
816
817 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
818 {
819 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
820 }
821
822 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
823 {
824 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
825 }
826
827 static int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
828 dma_addr_t dma_addr)
829 {
830 struct nvme_command c;
831
832 memset(&c, 0, sizeof(c));
833 c.identify.opcode = nvme_admin_identify;
834 c.identify.nsid = cpu_to_le32(nsid);
835 c.identify.prp1 = cpu_to_le64(dma_addr);
836 c.identify.cns = cpu_to_le32(cns);
837
838 return nvme_submit_admin_cmd(dev, &c, NULL);
839 }
840
841 static int nvme_get_features(struct nvme_dev *dev, unsigned fid,
842 unsigned nsid, dma_addr_t dma_addr)
843 {
844 struct nvme_command c;
845
846 memset(&c, 0, sizeof(c));
847 c.features.opcode = nvme_admin_get_features;
848 c.features.nsid = cpu_to_le32(nsid);
849 c.features.prp1 = cpu_to_le64(dma_addr);
850 c.features.fid = cpu_to_le32(fid);
851
852 return nvme_submit_admin_cmd(dev, &c, NULL);
853 }
854
855 static int nvme_set_features(struct nvme_dev *dev, unsigned fid,
856 unsigned dword11, dma_addr_t dma_addr, u32 *result)
857 {
858 struct nvme_command c;
859
860 memset(&c, 0, sizeof(c));
861 c.features.opcode = nvme_admin_set_features;
862 c.features.prp1 = cpu_to_le64(dma_addr);
863 c.features.fid = cpu_to_le32(fid);
864 c.features.dword11 = cpu_to_le32(dword11);
865
866 return nvme_submit_admin_cmd(dev, &c, result);
867 }
868
869 /**
870 * nvme_cancel_ios - Cancel outstanding I/Os
871 * @queue: The queue to cancel I/Os on
872 * @timeout: True to only cancel I/Os which have timed out
873 */
874 static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
875 {
876 int depth = nvmeq->q_depth - 1;
877 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
878 unsigned long now = jiffies;
879 int cmdid;
880
881 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
882 void *ctx;
883 nvme_completion_fn fn;
884 static struct nvme_completion cqe = {
885 .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1,
886 };
887
888 if (timeout && !time_after(now, info[cmdid].timeout))
889 continue;
890 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid);
891 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
892 fn(nvmeq->dev, ctx, &cqe);
893 }
894 }
895
896 static void nvme_free_queue_mem(struct nvme_queue *nvmeq)
897 {
898 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
899 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
900 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
901 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
902 kfree(nvmeq);
903 }
904
905 static void nvme_free_queue(struct nvme_dev *dev, int qid)
906 {
907 struct nvme_queue *nvmeq = dev->queues[qid];
908 int vector = dev->entry[nvmeq->cq_vector].vector;
909
910 spin_lock_irq(&nvmeq->q_lock);
911 nvme_cancel_ios(nvmeq, false);
912 spin_unlock_irq(&nvmeq->q_lock);
913
914 irq_set_affinity_hint(vector, NULL);
915 free_irq(vector, nvmeq);
916
917 /* Don't tell the adapter to delete the admin queue */
918 if (qid) {
919 adapter_delete_sq(dev, qid);
920 adapter_delete_cq(dev, qid);
921 }
922
923 nvme_free_queue_mem(nvmeq);
924 }
925
926 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
927 int depth, int vector)
928 {
929 struct device *dmadev = &dev->pci_dev->dev;
930 unsigned extra = DIV_ROUND_UP(depth, 8) + (depth *
931 sizeof(struct nvme_cmd_info));
932 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
933 if (!nvmeq)
934 return NULL;
935
936 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
937 &nvmeq->cq_dma_addr, GFP_KERNEL);
938 if (!nvmeq->cqes)
939 goto free_nvmeq;
940 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
941
942 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
943 &nvmeq->sq_dma_addr, GFP_KERNEL);
944 if (!nvmeq->sq_cmds)
945 goto free_cqdma;
946
947 nvmeq->q_dmadev = dmadev;
948 nvmeq->dev = dev;
949 spin_lock_init(&nvmeq->q_lock);
950 nvmeq->cq_head = 0;
951 nvmeq->cq_phase = 1;
952 init_waitqueue_head(&nvmeq->sq_full);
953 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
954 bio_list_init(&nvmeq->sq_cong);
955 nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
956 nvmeq->q_depth = depth;
957 nvmeq->cq_vector = vector;
958
959 return nvmeq;
960
961 free_cqdma:
962 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
963 nvmeq->cq_dma_addr);
964 free_nvmeq:
965 kfree(nvmeq);
966 return NULL;
967 }
968
969 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
970 const char *name)
971 {
972 if (use_threaded_interrupts)
973 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
974 nvme_irq_check, nvme_irq,
975 IRQF_DISABLED | IRQF_SHARED,
976 name, nvmeq);
977 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
978 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
979 }
980
981 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
982 int qid, int cq_size, int vector)
983 {
984 int result;
985 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
986
987 if (!nvmeq)
988 return ERR_PTR(-ENOMEM);
989
990 result = adapter_alloc_cq(dev, qid, nvmeq);
991 if (result < 0)
992 goto free_nvmeq;
993
994 result = adapter_alloc_sq(dev, qid, nvmeq);
995 if (result < 0)
996 goto release_cq;
997
998 result = queue_request_irq(dev, nvmeq, "nvme");
999 if (result < 0)
1000 goto release_sq;
1001
1002 return nvmeq;
1003
1004 release_sq:
1005 adapter_delete_sq(dev, qid);
1006 release_cq:
1007 adapter_delete_cq(dev, qid);
1008 free_nvmeq:
1009 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1010 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1011 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1012 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1013 kfree(nvmeq);
1014 return ERR_PTR(result);
1015 }
1016
1017 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
1018 {
1019 int result = 0;
1020 u32 aqa;
1021 u64 cap;
1022 unsigned long timeout;
1023 struct nvme_queue *nvmeq;
1024
1025 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1026
1027 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1028 if (!nvmeq)
1029 return -ENOMEM;
1030
1031 aqa = nvmeq->q_depth - 1;
1032 aqa |= aqa << 16;
1033
1034 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1035 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1036 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1037 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1038
1039 writel(0, &dev->bar->cc);
1040 writel(aqa, &dev->bar->aqa);
1041 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1042 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1043 writel(dev->ctrl_config, &dev->bar->cc);
1044
1045 cap = readq(&dev->bar->cap);
1046 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1047 dev->db_stride = NVME_CAP_STRIDE(cap);
1048
1049 while (!result && !(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
1050 msleep(100);
1051 if (fatal_signal_pending(current))
1052 result = -EINTR;
1053 if (time_after(jiffies, timeout)) {
1054 dev_err(&dev->pci_dev->dev,
1055 "Device not ready; aborting initialisation\n");
1056 result = -ENODEV;
1057 }
1058 }
1059
1060 if (result) {
1061 nvme_free_queue_mem(nvmeq);
1062 return result;
1063 }
1064
1065 result = queue_request_irq(dev, nvmeq, "nvme admin");
1066 dev->queues[0] = nvmeq;
1067 return result;
1068 }
1069
1070 static struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1071 unsigned long addr, unsigned length)
1072 {
1073 int i, err, count, nents, offset;
1074 struct scatterlist *sg;
1075 struct page **pages;
1076 struct nvme_iod *iod;
1077
1078 if (addr & 3)
1079 return ERR_PTR(-EINVAL);
1080 if (!length)
1081 return ERR_PTR(-EINVAL);
1082
1083 offset = offset_in_page(addr);
1084 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1085 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1086 if (!pages)
1087 return ERR_PTR(-ENOMEM);
1088
1089 err = get_user_pages_fast(addr, count, 1, pages);
1090 if (err < count) {
1091 count = err;
1092 err = -EFAULT;
1093 goto put_pages;
1094 }
1095
1096 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1097 sg = iod->sg;
1098 sg_init_table(sg, count);
1099 for (i = 0; i < count; i++) {
1100 sg_set_page(&sg[i], pages[i],
1101 min_t(int, length, PAGE_SIZE - offset), offset);
1102 length -= (PAGE_SIZE - offset);
1103 offset = 0;
1104 }
1105 sg_mark_end(&sg[i - 1]);
1106 iod->nents = count;
1107
1108 err = -ENOMEM;
1109 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1110 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1111 if (!nents)
1112 goto free_iod;
1113
1114 kfree(pages);
1115 return iod;
1116
1117 free_iod:
1118 kfree(iod);
1119 put_pages:
1120 for (i = 0; i < count; i++)
1121 put_page(pages[i]);
1122 kfree(pages);
1123 return ERR_PTR(err);
1124 }
1125
1126 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1127 struct nvme_iod *iod)
1128 {
1129 int i;
1130
1131 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1132 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1133
1134 for (i = 0; i < iod->nents; i++)
1135 put_page(sg_page(&iod->sg[i]));
1136 }
1137
1138 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1139 {
1140 struct nvme_dev *dev = ns->dev;
1141 struct nvme_queue *nvmeq;
1142 struct nvme_user_io io;
1143 struct nvme_command c;
1144 unsigned length;
1145 int status;
1146 struct nvme_iod *iod;
1147
1148 if (copy_from_user(&io, uio, sizeof(io)))
1149 return -EFAULT;
1150 length = (io.nblocks + 1) << ns->lba_shift;
1151
1152 switch (io.opcode) {
1153 case nvme_cmd_write:
1154 case nvme_cmd_read:
1155 case nvme_cmd_compare:
1156 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
1157 break;
1158 default:
1159 return -EINVAL;
1160 }
1161
1162 if (IS_ERR(iod))
1163 return PTR_ERR(iod);
1164
1165 memset(&c, 0, sizeof(c));
1166 c.rw.opcode = io.opcode;
1167 c.rw.flags = io.flags;
1168 c.rw.nsid = cpu_to_le32(ns->ns_id);
1169 c.rw.slba = cpu_to_le64(io.slba);
1170 c.rw.length = cpu_to_le16(io.nblocks);
1171 c.rw.control = cpu_to_le16(io.control);
1172 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1173 c.rw.reftag = io.reftag;
1174 c.rw.apptag = io.apptag;
1175 c.rw.appmask = io.appmask;
1176 /* XXX: metadata */
1177 length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
1178
1179 nvmeq = get_nvmeq(dev);
1180 /*
1181 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1182 * disabled. We may be preempted at any point, and be rescheduled
1183 * to a different CPU. That will cause cacheline bouncing, but no
1184 * additional races since q_lock already protects against other CPUs.
1185 */
1186 put_nvmeq(nvmeq);
1187 if (length != (io.nblocks + 1) << ns->lba_shift)
1188 status = -ENOMEM;
1189 else
1190 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
1191
1192 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
1193 nvme_free_iod(dev, iod);
1194 return status;
1195 }
1196
1197 static int nvme_user_admin_cmd(struct nvme_dev *dev,
1198 struct nvme_admin_cmd __user *ucmd)
1199 {
1200 struct nvme_admin_cmd cmd;
1201 struct nvme_command c;
1202 int status, length;
1203 struct nvme_iod *uninitialized_var(iod);
1204
1205 if (!capable(CAP_SYS_ADMIN))
1206 return -EACCES;
1207 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1208 return -EFAULT;
1209
1210 memset(&c, 0, sizeof(c));
1211 c.common.opcode = cmd.opcode;
1212 c.common.flags = cmd.flags;
1213 c.common.nsid = cpu_to_le32(cmd.nsid);
1214 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1215 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1216 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1217 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1218 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1219 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1220 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1221 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1222
1223 length = cmd.data_len;
1224 if (cmd.data_len) {
1225 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1226 length);
1227 if (IS_ERR(iod))
1228 return PTR_ERR(iod);
1229 length = nvme_setup_prps(dev, &c.common, iod, length,
1230 GFP_KERNEL);
1231 }
1232
1233 if (length != cmd.data_len)
1234 status = -ENOMEM;
1235 else
1236 status = nvme_submit_admin_cmd(dev, &c, NULL);
1237
1238 if (cmd.data_len) {
1239 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1240 nvme_free_iod(dev, iod);
1241 }
1242 return status;
1243 }
1244
1245 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1246 unsigned long arg)
1247 {
1248 struct nvme_ns *ns = bdev->bd_disk->private_data;
1249
1250 switch (cmd) {
1251 case NVME_IOCTL_ID:
1252 return ns->ns_id;
1253 case NVME_IOCTL_ADMIN_CMD:
1254 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
1255 case NVME_IOCTL_SUBMIT_IO:
1256 return nvme_submit_io(ns, (void __user *)arg);
1257 default:
1258 return -ENOTTY;
1259 }
1260 }
1261
1262 static const struct block_device_operations nvme_fops = {
1263 .owner = THIS_MODULE,
1264 .ioctl = nvme_ioctl,
1265 .compat_ioctl = nvme_ioctl,
1266 };
1267
1268 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1269 {
1270 while (bio_list_peek(&nvmeq->sq_cong)) {
1271 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1272 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1273 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1274 bio_list_add_head(&nvmeq->sq_cong, bio);
1275 break;
1276 }
1277 if (bio_list_empty(&nvmeq->sq_cong))
1278 remove_wait_queue(&nvmeq->sq_full,
1279 &nvmeq->sq_cong_wait);
1280 }
1281 }
1282
1283 static int nvme_kthread(void *data)
1284 {
1285 struct nvme_dev *dev;
1286
1287 while (!kthread_should_stop()) {
1288 __set_current_state(TASK_RUNNING);
1289 spin_lock(&dev_list_lock);
1290 list_for_each_entry(dev, &dev_list, node) {
1291 int i;
1292 for (i = 0; i < dev->queue_count; i++) {
1293 struct nvme_queue *nvmeq = dev->queues[i];
1294 if (!nvmeq)
1295 continue;
1296 spin_lock_irq(&nvmeq->q_lock);
1297 if (nvme_process_cq(nvmeq))
1298 printk("process_cq did something\n");
1299 nvme_cancel_ios(nvmeq, true);
1300 nvme_resubmit_bios(nvmeq);
1301 spin_unlock_irq(&nvmeq->q_lock);
1302 }
1303 }
1304 spin_unlock(&dev_list_lock);
1305 set_current_state(TASK_INTERRUPTIBLE);
1306 schedule_timeout(HZ);
1307 }
1308 return 0;
1309 }
1310
1311 static DEFINE_IDA(nvme_index_ida);
1312
1313 static int nvme_get_ns_idx(void)
1314 {
1315 int index, error;
1316
1317 do {
1318 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1319 return -1;
1320
1321 spin_lock(&dev_list_lock);
1322 error = ida_get_new(&nvme_index_ida, &index);
1323 spin_unlock(&dev_list_lock);
1324 } while (error == -EAGAIN);
1325
1326 if (error)
1327 index = -1;
1328 return index;
1329 }
1330
1331 static void nvme_put_ns_idx(int index)
1332 {
1333 spin_lock(&dev_list_lock);
1334 ida_remove(&nvme_index_ida, index);
1335 spin_unlock(&dev_list_lock);
1336 }
1337
1338 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid,
1339 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1340 {
1341 struct nvme_ns *ns;
1342 struct gendisk *disk;
1343 int lbaf;
1344
1345 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1346 return NULL;
1347
1348 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1349 if (!ns)
1350 return NULL;
1351 ns->queue = blk_alloc_queue(GFP_KERNEL);
1352 if (!ns->queue)
1353 goto out_free_ns;
1354 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1355 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1356 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1357 /* queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); */
1358 blk_queue_make_request(ns->queue, nvme_make_request);
1359 ns->dev = dev;
1360 ns->queue->queuedata = ns;
1361
1362 disk = alloc_disk(NVME_MINORS);
1363 if (!disk)
1364 goto out_free_queue;
1365 ns->ns_id = nsid;
1366 ns->disk = disk;
1367 lbaf = id->flbas & 0xf;
1368 ns->lba_shift = id->lbaf[lbaf].ds;
1369 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1370 if (dev->max_hw_sectors)
1371 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
1372
1373 disk->major = nvme_major;
1374 disk->minors = NVME_MINORS;
1375 disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
1376 disk->fops = &nvme_fops;
1377 disk->private_data = ns;
1378 disk->queue = ns->queue;
1379 disk->driverfs_dev = &dev->pci_dev->dev;
1380 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1381 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1382
1383 return ns;
1384
1385 out_free_queue:
1386 blk_cleanup_queue(ns->queue);
1387 out_free_ns:
1388 kfree(ns);
1389 return NULL;
1390 }
1391
1392 static void nvme_ns_free(struct nvme_ns *ns)
1393 {
1394 int index = ns->disk->first_minor / NVME_MINORS;
1395 put_disk(ns->disk);
1396 nvme_put_ns_idx(index);
1397 blk_cleanup_queue(ns->queue);
1398 kfree(ns);
1399 }
1400
1401 static int set_queue_count(struct nvme_dev *dev, int count)
1402 {
1403 int status;
1404 u32 result;
1405 u32 q_count = (count - 1) | ((count - 1) << 16);
1406
1407 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1408 &result);
1409 if (status)
1410 return -EIO;
1411 return min(result & 0xffff, result >> 16) + 1;
1412 }
1413
1414 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1415 {
1416 int result, cpu, i, nr_io_queues, db_bar_size, q_depth;
1417
1418 nr_io_queues = num_online_cpus();
1419 result = set_queue_count(dev, nr_io_queues);
1420 if (result < 0)
1421 return result;
1422 if (result < nr_io_queues)
1423 nr_io_queues = result;
1424
1425 /* Deregister the admin queue's interrupt */
1426 free_irq(dev->entry[0].vector, dev->queues[0]);
1427
1428 db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
1429 if (db_bar_size > 8192) {
1430 iounmap(dev->bar);
1431 dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0),
1432 db_bar_size);
1433 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1434 dev->queues[0]->q_db = dev->dbs;
1435 }
1436
1437 for (i = 0; i < nr_io_queues; i++)
1438 dev->entry[i].entry = i;
1439 for (;;) {
1440 result = pci_enable_msix(dev->pci_dev, dev->entry,
1441 nr_io_queues);
1442 if (result == 0) {
1443 break;
1444 } else if (result > 0) {
1445 nr_io_queues = result;
1446 continue;
1447 } else {
1448 nr_io_queues = 1;
1449 break;
1450 }
1451 }
1452
1453 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1454 /* XXX: handle failure here */
1455
1456 cpu = cpumask_first(cpu_online_mask);
1457 for (i = 0; i < nr_io_queues; i++) {
1458 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1459 cpu = cpumask_next(cpu, cpu_online_mask);
1460 }
1461
1462 q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1,
1463 NVME_Q_DEPTH);
1464 for (i = 0; i < nr_io_queues; i++) {
1465 dev->queues[i + 1] = nvme_create_queue(dev, i + 1, q_depth, i);
1466 if (IS_ERR(dev->queues[i + 1]))
1467 return PTR_ERR(dev->queues[i + 1]);
1468 dev->queue_count++;
1469 }
1470
1471 for (; i < num_possible_cpus(); i++) {
1472 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1473 dev->queues[i + 1] = dev->queues[target + 1];
1474 }
1475
1476 return 0;
1477 }
1478
1479 static void nvme_free_queues(struct nvme_dev *dev)
1480 {
1481 int i;
1482
1483 for (i = dev->queue_count - 1; i >= 0; i--)
1484 nvme_free_queue(dev, i);
1485 }
1486
1487 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1488 {
1489 int res, nn, i;
1490 struct nvme_ns *ns, *next;
1491 struct nvme_id_ctrl *ctrl;
1492 struct nvme_id_ns *id_ns;
1493 void *mem;
1494 dma_addr_t dma_addr;
1495
1496 res = nvme_setup_io_queues(dev);
1497 if (res)
1498 return res;
1499
1500 mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1501 GFP_KERNEL);
1502
1503 res = nvme_identify(dev, 0, 1, dma_addr);
1504 if (res) {
1505 res = -EIO;
1506 goto out_free;
1507 }
1508
1509 ctrl = mem;
1510 nn = le32_to_cpup(&ctrl->nn);
1511 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1512 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1513 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1514 if (ctrl->mdts) {
1515 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
1516 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
1517 }
1518
1519 id_ns = mem;
1520 for (i = 1; i <= nn; i++) {
1521 res = nvme_identify(dev, i, 0, dma_addr);
1522 if (res)
1523 continue;
1524
1525 if (id_ns->ncap == 0)
1526 continue;
1527
1528 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
1529 dma_addr + 4096);
1530 if (res)
1531 continue;
1532
1533 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
1534 if (ns)
1535 list_add_tail(&ns->list, &dev->namespaces);
1536 }
1537 list_for_each_entry(ns, &dev->namespaces, list)
1538 add_disk(ns->disk);
1539
1540 goto out;
1541
1542 out_free:
1543 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1544 list_del(&ns->list);
1545 nvme_ns_free(ns);
1546 }
1547
1548 out:
1549 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
1550 return res;
1551 }
1552
1553 static int nvme_dev_remove(struct nvme_dev *dev)
1554 {
1555 struct nvme_ns *ns, *next;
1556
1557 spin_lock(&dev_list_lock);
1558 list_del(&dev->node);
1559 spin_unlock(&dev_list_lock);
1560
1561 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1562 list_del(&ns->list);
1563 del_gendisk(ns->disk);
1564 nvme_ns_free(ns);
1565 }
1566
1567 nvme_free_queues(dev);
1568
1569 return 0;
1570 }
1571
1572 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1573 {
1574 struct device *dmadev = &dev->pci_dev->dev;
1575 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1576 PAGE_SIZE, PAGE_SIZE, 0);
1577 if (!dev->prp_page_pool)
1578 return -ENOMEM;
1579
1580 /* Optimisation for I/Os between 4k and 128k */
1581 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1582 256, 256, 0);
1583 if (!dev->prp_small_pool) {
1584 dma_pool_destroy(dev->prp_page_pool);
1585 return -ENOMEM;
1586 }
1587 return 0;
1588 }
1589
1590 static void nvme_release_prp_pools(struct nvme_dev *dev)
1591 {
1592 dma_pool_destroy(dev->prp_page_pool);
1593 dma_pool_destroy(dev->prp_small_pool);
1594 }
1595
1596 static DEFINE_IDA(nvme_instance_ida);
1597
1598 static int nvme_set_instance(struct nvme_dev *dev)
1599 {
1600 int instance, error;
1601
1602 do {
1603 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
1604 return -ENODEV;
1605
1606 spin_lock(&dev_list_lock);
1607 error = ida_get_new(&nvme_instance_ida, &instance);
1608 spin_unlock(&dev_list_lock);
1609 } while (error == -EAGAIN);
1610
1611 if (error)
1612 return -ENODEV;
1613
1614 dev->instance = instance;
1615 return 0;
1616 }
1617
1618 static void nvme_release_instance(struct nvme_dev *dev)
1619 {
1620 spin_lock(&dev_list_lock);
1621 ida_remove(&nvme_instance_ida, dev->instance);
1622 spin_unlock(&dev_list_lock);
1623 }
1624
1625 static int __devinit nvme_probe(struct pci_dev *pdev,
1626 const struct pci_device_id *id)
1627 {
1628 int bars, result = -ENOMEM;
1629 struct nvme_dev *dev;
1630
1631 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1632 if (!dev)
1633 return -ENOMEM;
1634 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1635 GFP_KERNEL);
1636 if (!dev->entry)
1637 goto free;
1638 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1639 GFP_KERNEL);
1640 if (!dev->queues)
1641 goto free;
1642
1643 if (pci_enable_device_mem(pdev))
1644 goto free;
1645 pci_set_master(pdev);
1646 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1647 if (pci_request_selected_regions(pdev, bars, "nvme"))
1648 goto disable;
1649
1650 INIT_LIST_HEAD(&dev->namespaces);
1651 dev->pci_dev = pdev;
1652 pci_set_drvdata(pdev, dev);
1653 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1654 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1655 result = nvme_set_instance(dev);
1656 if (result)
1657 goto disable;
1658
1659 dev->entry[0].vector = pdev->irq;
1660
1661 result = nvme_setup_prp_pools(dev);
1662 if (result)
1663 goto disable_msix;
1664
1665 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1666 if (!dev->bar) {
1667 result = -ENOMEM;
1668 goto disable_msix;
1669 }
1670
1671 result = nvme_configure_admin_queue(dev);
1672 if (result)
1673 goto unmap;
1674 dev->queue_count++;
1675
1676 spin_lock(&dev_list_lock);
1677 list_add(&dev->node, &dev_list);
1678 spin_unlock(&dev_list_lock);
1679
1680 result = nvme_dev_add(dev);
1681 if (result)
1682 goto delete;
1683
1684 return 0;
1685
1686 delete:
1687 spin_lock(&dev_list_lock);
1688 list_del(&dev->node);
1689 spin_unlock(&dev_list_lock);
1690
1691 nvme_free_queues(dev);
1692 unmap:
1693 iounmap(dev->bar);
1694 disable_msix:
1695 pci_disable_msix(pdev);
1696 nvme_release_instance(dev);
1697 nvme_release_prp_pools(dev);
1698 disable:
1699 pci_disable_device(pdev);
1700 pci_release_regions(pdev);
1701 free:
1702 kfree(dev->queues);
1703 kfree(dev->entry);
1704 kfree(dev);
1705 return result;
1706 }
1707
1708 static void __devexit nvme_remove(struct pci_dev *pdev)
1709 {
1710 struct nvme_dev *dev = pci_get_drvdata(pdev);
1711 nvme_dev_remove(dev);
1712 pci_disable_msix(pdev);
1713 iounmap(dev->bar);
1714 nvme_release_instance(dev);
1715 nvme_release_prp_pools(dev);
1716 pci_disable_device(pdev);
1717 pci_release_regions(pdev);
1718 kfree(dev->queues);
1719 kfree(dev->entry);
1720 kfree(dev);
1721 }
1722
1723 /* These functions are yet to be implemented */
1724 #define nvme_error_detected NULL
1725 #define nvme_dump_registers NULL
1726 #define nvme_link_reset NULL
1727 #define nvme_slot_reset NULL
1728 #define nvme_error_resume NULL
1729 #define nvme_suspend NULL
1730 #define nvme_resume NULL
1731
1732 static const struct pci_error_handlers nvme_err_handler = {
1733 .error_detected = nvme_error_detected,
1734 .mmio_enabled = nvme_dump_registers,
1735 .link_reset = nvme_link_reset,
1736 .slot_reset = nvme_slot_reset,
1737 .resume = nvme_error_resume,
1738 };
1739
1740 /* Move to pci_ids.h later */
1741 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1742
1743 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1744 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1745 { 0, }
1746 };
1747 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1748
1749 static struct pci_driver nvme_driver = {
1750 .name = "nvme",
1751 .id_table = nvme_id_table,
1752 .probe = nvme_probe,
1753 .remove = __devexit_p(nvme_remove),
1754 .suspend = nvme_suspend,
1755 .resume = nvme_resume,
1756 .err_handler = &nvme_err_handler,
1757 };
1758
1759 static int __init nvme_init(void)
1760 {
1761 int result;
1762
1763 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1764 if (IS_ERR(nvme_thread))
1765 return PTR_ERR(nvme_thread);
1766
1767 result = register_blkdev(nvme_major, "nvme");
1768 if (result < 0)
1769 goto kill_kthread;
1770 else if (result > 0)
1771 nvme_major = result;
1772
1773 result = pci_register_driver(&nvme_driver);
1774 if (result)
1775 goto unregister_blkdev;
1776 return 0;
1777
1778 unregister_blkdev:
1779 unregister_blkdev(nvme_major, "nvme");
1780 kill_kthread:
1781 kthread_stop(nvme_thread);
1782 return result;
1783 }
1784
1785 static void __exit nvme_exit(void)
1786 {
1787 pci_unregister_driver(&nvme_driver);
1788 unregister_blkdev(nvme_major, "nvme");
1789 kthread_stop(nvme_thread);
1790 }
1791
1792 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1793 MODULE_LICENSE("GPL");
1794 MODULE_VERSION("0.8");
1795 module_init(nvme_init);
1796 module_exit(nvme_exit);
This page took 0.06643 seconds and 6 git commands to generate.