drivers/bus/omap_l3_noc.h

   1 /*
   2  * OMAP L3 Interconnect  error handling driver header
   3  *
   4  * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
   5  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   6  *      sricharan <r.sricharan@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17 #ifndef __OMAP_L3_NOC_H
  18 #define __OMAP_L3_NOC_H
  19
  20 #define MAX_L3_MODULES                  3
  21 #define MAX_CLKDM_TARGETS               31
  22
  23 #define CLEAR_STDERR_LOG                (1 << 31)
  24 #define CUSTOM_ERROR                    0x2
  25 #define STANDARD_ERROR                  0x0
  26 #define INBAND_ERROR                    0x0
  27 #define L3_APPLICATION_ERROR            0x0
  28 #define L3_DEBUG_ERROR                  0x1
  29
  30 /* L3 TARG register offsets */
  31 #define L3_TARG_STDERRLOG_MAIN          0x48
  32 #define L3_TARG_STDERRLOG_SLVOFSLSB     0x5c
  33 #define L3_TARG_STDERRLOG_MSTADDR       0x68
  34 #define L3_FLAGMUX_REGERR0              0xc
  35 #define L3_FLAGMUX_MASK0                0x8
  36
  37 #define L3_TARGET_NOT_SUPPORTED         NULL
  38
  39 /**
  40  * struct l3_masters_data - L3 Master information
  41  * @id:         ID of the L3 Master
  42  * @name:       master name
  43  */
  44 struct l3_masters_data {
  45         u32 id;
  46         char *name;
  47 };
  48
  49 /**
  50  * struct l3_target_data - L3 Target information
  51  * @offset:     Offset from base for L3 Target
  52  * @name:       Target name
  53  *
  54  * Target information is organized indexed by bit field definitions.
  55  */
  56 struct l3_target_data {
  57         u32 offset;
  58         char *name;
  59 };
  60
  61 /**
  62  * struct l3_flagmux_data - Flag Mux information
  63  * @offset:     offset from base for flagmux register
  64  * @l3_targ:    array indexed by flagmux index (bit offset) pointing to the
  65  *              target data. unsupported ones are marked with
  66  *              L3_TARGET_NOT_SUPPORTED
  67  * @num_targ_data: number of entries in target data
  68  */
  69 struct l3_flagmux_data {
  70         u32 offset;
  71         struct l3_target_data *l3_targ;
  72         u8 num_targ_data;
  73 };
  74
  75
  76 /**
  77  * struct omap_l3 - Description of data relevant for L3 bus.
  78  * @dev:        device representing the bus (populated runtime)
  79  * @l3_base:    base addresses of modules (populated runtime)
  80  * @l3_flag_mux: array containing flag mux data per module
  81  *               offset from corresponding module base indexed per
  82  *               module.
  83  * @num_modules: number of clock domains / modules.
  84  * @l3_masters: array pointing to master data containing name and register
  85  *              offset for the master.
  86  * @num_master: number of masters
  87  * @debug_irq:  irq number of the debug interrupt (populated runtime)
  88  * @app_irq:    irq number of the application interrupt (populated runtime)
  89  */
  90 struct omap_l3 {
  91         struct device *dev;
  92
  93         void __iomem *l3_base[MAX_L3_MODULES];
  94         struct l3_flagmux_data **l3_flagmux;
  95         int num_modules;
  96
  97         struct l3_masters_data *l3_masters;
  98         int num_masters;
  99
 100         int debug_irq;
 101         int app_irq;
 102 };
 103
 104 static struct l3_target_data omap_l3_target_data_clk1[] = {
 105         {0x100, "DMM1",},
 106         {0x200, "DMM2",},
 107         {0x300, "ABE",},
 108         {0x400, "L4CFG",},
 109         {0x600, "CLK2PWRDISC",},
 110         {0x0,   "HOSTCLK1",},
 111         {0x900, "L4WAKEUP",},
 112 };
 113
 114 static struct l3_flagmux_data omap_l3_flagmux_clk1 = {
 115         .offset = 0x500,
 116         .l3_targ = omap_l3_target_data_clk1,
 117         .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1),
 118 };
 119
 120
 121 static struct l3_target_data omap_l3_target_data_clk2[] = {
 122         {0x500, "CORTEXM3",},
 123         {0x300, "DSS",},
 124         {0x100, "GPMC",},
 125         {0x400, "ISS",},
 126         {0x700, "IVAHD",},
 127         {0xD00, "AES1",},
 128         {0x900, "L4PER0",},
 129         {0x200, "OCMRAM",},
 130         {0x100, "GPMCsERROR",},
 131         {0x600, "SGX",},
 132         {0x800, "SL2",},
 133         {0x1600, "C2C",},
 134         {0x1100, "PWRDISCCLK1",},
 135         {0xF00, "SHA1",},
 136         {0xE00, "AES2",},
 137         {0xC00, "L4PER3",},
 138         {0xA00, "L4PER1",},
 139         {0xB00, "L4PER2",},
 140         {0x0,   "HOSTCLK2",},
 141         {0x1800, "CAL",},
 142         {0x1700, "LLI",},
 143 };
 144
 145 static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
 146         .offset = 0x1000,
 147         .l3_targ = omap_l3_target_data_clk2,
 148         .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2),
 149 };
 150
 151
 152 static struct l3_target_data omap_l3_target_data_clk3[] = {
 153         {0x0100, "EMUSS",},
 154         {0x0300, "DEBUG SOURCE",},
 155         {0x0,   "HOST CLK3",},
 156 };
 157
 158 static struct l3_flagmux_data omap_l3_flagmux_clk3 = {
 159         .offset = 0x0200,
 160         .l3_targ = omap_l3_target_data_clk3,
 161         .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk3),
 162 };
 163
 164 static struct l3_masters_data omap_l3_masters[] = {
 165         { 0x0 , "MPU"},
 166         { 0x10, "CS_ADP"},
 167         { 0x14, "xxx"},
 168         { 0x20, "DSP"},
 169         { 0x30, "IVAHD"},
 170         { 0x40, "ISS"},
 171         { 0x44, "DucatiM3"},
 172         { 0x48, "FaceDetect"},
 173         { 0x50, "SDMA_Rd"},
 174         { 0x54, "SDMA_Wr"},
 175         { 0x58, "xxx"},
 176         { 0x5C, "xxx"},
 177         { 0x60, "SGX"},
 178         { 0x70, "DSS"},
 179         { 0x80, "C2C"},
 180         { 0x88, "xxx"},
 181         { 0x8C, "xxx"},
 182         { 0x90, "HSI"},
 183         { 0xA0, "MMC1"},
 184         { 0xA4, "MMC2"},
 185         { 0xA8, "MMC6"},
 186         { 0xB0, "UNIPRO1"},
 187         { 0xC0, "USBHOSTHS"},
 188         { 0xC4, "USBOTGHS"},
 189         { 0xC8, "USBHOSTFS"}
 190 };
 191
 192 static struct l3_flagmux_data *omap_l3_flagmux[] = {
 193         &omap_l3_flagmux_clk1,
 194         &omap_l3_flagmux_clk2,
 195         &omap_l3_flagmux_clk3,
 196 };
 197
 198 static const struct omap_l3 omap_l3_data = {
 199         .l3_flagmux = omap_l3_flagmux,
 200         .num_modules = ARRAY_SIZE(omap_l3_flagmux),
 201         .l3_masters = omap_l3_masters,
 202         .num_masters = ARRAY_SIZE(omap_l3_masters),
 203 };
 204
 205 #endif  /* __OMAP_L3_NOC_H */