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[PATCH] i945G patch for agpgart
[deliverable/linux.git] / drivers / char / agp / intel-agp.c
1 /*
2 * Intel AGPGART routines.
3 */
4
5 /*
6 * Intel(R) 855GM/852GM and 865G support added by David Dawes
7 * <dawes@tungstengraphics.com>.
8 *
9 * Intel(R) 915G/915GM support added by Alan Hourihane
10 * <alanh@tungstengraphics.com>.
11 */
12
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/init.h>
16 #include <linux/pagemap.h>
17 #include <linux/agp_backend.h>
18 #include "agp.h"
19
20 /* Intel 815 register */
21 #define INTEL_815_APCONT 0x51
22 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
23
24 /* Intel i820 registers */
25 #define INTEL_I820_RDCR 0x51
26 #define INTEL_I820_ERRSTS 0xc8
27
28 /* Intel i840 registers */
29 #define INTEL_I840_MCHCFG 0x50
30 #define INTEL_I840_ERRSTS 0xc8
31
32 /* Intel i850 registers */
33 #define INTEL_I850_MCHCFG 0x50
34 #define INTEL_I850_ERRSTS 0xc8
35
36 /* intel 915G registers */
37 #define I915_GMADDR 0x18
38 #define I915_MMADDR 0x10
39 #define I915_PTEADDR 0x1C
40 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
41 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
42
43
44 /* Intel 7505 registers */
45 #define INTEL_I7505_APSIZE 0x74
46 #define INTEL_I7505_NCAPID 0x60
47 #define INTEL_I7505_NISTAT 0x6c
48 #define INTEL_I7505_ATTBASE 0x78
49 #define INTEL_I7505_ERRSTS 0x42
50 #define INTEL_I7505_AGPCTRL 0x70
51 #define INTEL_I7505_MCHCFG 0x50
52
53 static struct aper_size_info_fixed intel_i810_sizes[] =
54 {
55 {64, 16384, 4},
56 /* The 32M mode still requires a 64k gatt */
57 {32, 8192, 4}
58 };
59
60 #define AGP_DCACHE_MEMORY 1
61 #define AGP_PHYS_MEMORY 2
62
63 static struct gatt_mask intel_i810_masks[] =
64 {
65 {.mask = I810_PTE_VALID, .type = 0},
66 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
67 {.mask = I810_PTE_VALID, .type = 0}
68 };
69
70 static struct _intel_i810_private {
71 struct pci_dev *i810_dev; /* device one */
72 volatile u8 __iomem *registers;
73 int num_dcache_entries;
74 } intel_i810_private;
75
76 static int intel_i810_fetch_size(void)
77 {
78 u32 smram_miscc;
79 struct aper_size_info_fixed *values;
80
81 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
82 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
83
84 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
85 printk(KERN_WARNING PFX "i810 is disabled\n");
86 return 0;
87 }
88 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
89 agp_bridge->previous_size =
90 agp_bridge->current_size = (void *) (values + 1);
91 agp_bridge->aperture_size_idx = 1;
92 return values[1].size;
93 } else {
94 agp_bridge->previous_size =
95 agp_bridge->current_size = (void *) (values);
96 agp_bridge->aperture_size_idx = 0;
97 return values[0].size;
98 }
99
100 return 0;
101 }
102
103 static int intel_i810_configure(void)
104 {
105 struct aper_size_info_fixed *current_size;
106 u32 temp;
107 int i;
108
109 current_size = A_SIZE_FIX(agp_bridge->current_size);
110
111 pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp);
112 temp &= 0xfff80000;
113
114 intel_i810_private.registers = ioremap(temp, 128 * 4096);
115 if (!intel_i810_private.registers) {
116 printk(KERN_ERR PFX "Unable to remap memory.\n");
117 return -ENOMEM;
118 }
119
120 if ((readl(intel_i810_private.registers+I810_DRAM_CTL)
121 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
122 /* This will need to be dynamically assigned */
123 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
124 intel_i810_private.num_dcache_entries = 1024;
125 }
126 pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp);
127 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
128 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_i810_private.registers+I810_PGETBL_CTL);
129 readl(intel_i810_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
130
131 if (agp_bridge->driver->needs_scratch_page) {
132 for (i = 0; i < current_size->num_entries; i++) {
133 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4));
134 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
135 }
136 }
137 global_cache_flush();
138 return 0;
139 }
140
141 static void intel_i810_cleanup(void)
142 {
143 writel(0, intel_i810_private.registers+I810_PGETBL_CTL);
144 readl(intel_i810_private.registers); /* PCI Posting. */
145 iounmap(intel_i810_private.registers);
146 }
147
148 static void intel_i810_tlbflush(struct agp_memory *mem)
149 {
150 return;
151 }
152
153 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
154 {
155 return;
156 }
157
158 /* Exists to support ARGB cursors */
159 static void *i8xx_alloc_pages(void)
160 {
161 struct page * page;
162
163 page = alloc_pages(GFP_KERNEL, 2);
164 if (page == NULL)
165 return NULL;
166
167 if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
168 global_flush_tlb();
169 __free_page(page);
170 return NULL;
171 }
172 global_flush_tlb();
173 get_page(page);
174 SetPageLocked(page);
175 atomic_inc(&agp_bridge->current_memory_agp);
176 return page_address(page);
177 }
178
179 static void i8xx_destroy_pages(void *addr)
180 {
181 struct page *page;
182
183 if (addr == NULL)
184 return;
185
186 page = virt_to_page(addr);
187 change_page_attr(page, 4, PAGE_KERNEL);
188 global_flush_tlb();
189 put_page(page);
190 unlock_page(page);
191 free_pages((unsigned long)addr, 2);
192 atomic_dec(&agp_bridge->current_memory_agp);
193 }
194
195 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
196 int type)
197 {
198 int i, j, num_entries;
199 void *temp;
200
201 temp = agp_bridge->current_size;
202 num_entries = A_SIZE_FIX(temp)->num_entries;
203
204 if ((pg_start + mem->page_count) > num_entries) {
205 return -EINVAL;
206 }
207 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
208 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
209 return -EBUSY;
210 }
211
212 if (type != 0 || mem->type != 0) {
213 if ((type == AGP_DCACHE_MEMORY) && (mem->type == AGP_DCACHE_MEMORY)) {
214 /* special insert */
215 global_cache_flush();
216 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
217 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, intel_i810_private.registers+I810_PTE_BASE+(i*4));
218 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
219 }
220 global_cache_flush();
221 agp_bridge->driver->tlb_flush(mem);
222 return 0;
223 }
224 if((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY))
225 goto insert;
226 return -EINVAL;
227 }
228
229 insert:
230 global_cache_flush();
231 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
232 writel(agp_bridge->driver->mask_memory(agp_bridge,
233 mem->memory[i], mem->type),
234 intel_i810_private.registers+I810_PTE_BASE+(j*4));
235 readl(intel_i810_private.registers+I810_PTE_BASE+(j*4)); /* PCI Posting. */
236 }
237 global_cache_flush();
238
239 agp_bridge->driver->tlb_flush(mem);
240 return 0;
241 }
242
243 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
244 int type)
245 {
246 int i;
247
248 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
249 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4));
250 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
251 }
252
253 global_cache_flush();
254 agp_bridge->driver->tlb_flush(mem);
255 return 0;
256 }
257
258 /*
259 * The i810/i830 requires a physical address to program its mouse
260 * pointer into hardware.
261 * However the Xserver still writes to it through the agp aperture.
262 */
263 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
264 {
265 struct agp_memory *new;
266 void *addr;
267
268 if (pg_count != 1 && pg_count != 4)
269 return NULL;
270
271 switch (pg_count) {
272 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
273 break;
274 case 4:
275 /* kludge to get 4 physical pages for ARGB cursor */
276 addr = i8xx_alloc_pages();
277 break;
278 default:
279 return NULL;
280 }
281
282 if (addr == NULL)
283 return NULL;
284
285 new = agp_create_memory(pg_count);
286 if (new == NULL)
287 return NULL;
288
289 new->memory[0] = virt_to_phys(addr);
290 if (pg_count == 4) {
291 /* kludge to get 4 physical pages for ARGB cursor */
292 new->memory[1] = new->memory[0] + PAGE_SIZE;
293 new->memory[2] = new->memory[1] + PAGE_SIZE;
294 new->memory[3] = new->memory[2] + PAGE_SIZE;
295 }
296 new->page_count = pg_count;
297 new->num_scratch_pages = pg_count;
298 new->type = AGP_PHYS_MEMORY;
299 new->physical = new->memory[0];
300 return new;
301 }
302
303 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
304 {
305 struct agp_memory *new;
306
307 if (type == AGP_DCACHE_MEMORY) {
308 if (pg_count != intel_i810_private.num_dcache_entries)
309 return NULL;
310
311 new = agp_create_memory(1);
312 if (new == NULL)
313 return NULL;
314
315 new->type = AGP_DCACHE_MEMORY;
316 new->page_count = pg_count;
317 new->num_scratch_pages = 0;
318 vfree(new->memory);
319 return new;
320 }
321 if (type == AGP_PHYS_MEMORY)
322 return alloc_agpphysmem_i8xx(pg_count, type);
323
324 return NULL;
325 }
326
327 static void intel_i810_free_by_type(struct agp_memory *curr)
328 {
329 agp_free_key(curr->key);
330 if(curr->type == AGP_PHYS_MEMORY) {
331 if (curr->page_count == 4)
332 i8xx_destroy_pages(phys_to_virt(curr->memory[0]));
333 else
334 agp_bridge->driver->agp_destroy_page(
335 phys_to_virt(curr->memory[0]));
336 vfree(curr->memory);
337 }
338 kfree(curr);
339 }
340
341 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
342 unsigned long addr, int type)
343 {
344 /* Type checking must be done elsewhere */
345 return addr | bridge->driver->masks[type].mask;
346 }
347
348 static struct aper_size_info_fixed intel_i830_sizes[] =
349 {
350 {128, 32768, 5},
351 /* The 64M mode still requires a 128k gatt */
352 {64, 16384, 5},
353 {256, 65536, 6},
354 };
355
356 static struct _intel_i830_private {
357 struct pci_dev *i830_dev; /* device one */
358 volatile u8 __iomem *registers;
359 volatile u32 __iomem *gtt; /* I915G */
360 int gtt_entries;
361 } intel_i830_private;
362
363 static void intel_i830_init_gtt_entries(void)
364 {
365 u16 gmch_ctrl;
366 int gtt_entries;
367 u8 rdct;
368 int local = 0;
369 static const int ddt[4] = { 0, 16, 32, 64 };
370 int size;
371
372 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
373
374 /* We obtain the size of the GTT, which is also stored (for some
375 * reason) at the top of stolen memory. Then we add 4KB to that
376 * for the video BIOS popup, which is also stored in there. */
377 size = agp_bridge->driver->fetch_size() + 4;
378
379 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
380 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
381 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
382 case I830_GMCH_GMS_STOLEN_512:
383 gtt_entries = KB(512) - KB(size);
384 break;
385 case I830_GMCH_GMS_STOLEN_1024:
386 gtt_entries = MB(1) - KB(size);
387 break;
388 case I830_GMCH_GMS_STOLEN_8192:
389 gtt_entries = MB(8) - KB(size);
390 break;
391 case I830_GMCH_GMS_LOCAL:
392 rdct = readb(intel_i830_private.registers+I830_RDRAM_CHANNEL_TYPE);
393 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
394 MB(ddt[I830_RDRAM_DDT(rdct)]);
395 local = 1;
396 break;
397 default:
398 gtt_entries = 0;
399 break;
400 }
401 } else {
402 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
403 case I855_GMCH_GMS_STOLEN_1M:
404 gtt_entries = MB(1) - KB(size);
405 break;
406 case I855_GMCH_GMS_STOLEN_4M:
407 gtt_entries = MB(4) - KB(size);
408 break;
409 case I855_GMCH_GMS_STOLEN_8M:
410 gtt_entries = MB(8) - KB(size);
411 break;
412 case I855_GMCH_GMS_STOLEN_16M:
413 gtt_entries = MB(16) - KB(size);
414 break;
415 case I855_GMCH_GMS_STOLEN_32M:
416 gtt_entries = MB(32) - KB(size);
417 break;
418 case I915_GMCH_GMS_STOLEN_48M:
419 /* Check it's really I915G */
420 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
421 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
422 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB)
423 gtt_entries = MB(48) - KB(size);
424 else
425 gtt_entries = 0;
426 break;
427 case I915_GMCH_GMS_STOLEN_64M:
428 /* Check it's really I915G */
429 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
430 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
431 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB)
432 gtt_entries = MB(64) - KB(size);
433 else
434 gtt_entries = 0;
435 default:
436 gtt_entries = 0;
437 break;
438 }
439 }
440 if (gtt_entries > 0)
441 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
442 gtt_entries / KB(1), local ? "local" : "stolen");
443 else
444 printk(KERN_INFO PFX
445 "No pre-allocated video memory detected.\n");
446 gtt_entries /= KB(4);
447
448 intel_i830_private.gtt_entries = gtt_entries;
449 }
450
451 /* The intel i830 automatically initializes the agp aperture during POST.
452 * Use the memory already set aside for in the GTT.
453 */
454 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
455 {
456 int page_order;
457 struct aper_size_info_fixed *size;
458 int num_entries;
459 u32 temp;
460
461 size = agp_bridge->current_size;
462 page_order = size->page_order;
463 num_entries = size->num_entries;
464 agp_bridge->gatt_table_real = NULL;
465
466 pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp);
467 temp &= 0xfff80000;
468
469 intel_i830_private.registers = ioremap(temp,128 * 4096);
470 if (!intel_i830_private.registers)
471 return -ENOMEM;
472
473 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
474 global_cache_flush(); /* FIXME: ?? */
475
476 /* we have to call this as early as possible after the MMIO base address is known */
477 intel_i830_init_gtt_entries();
478
479 agp_bridge->gatt_table = NULL;
480
481 agp_bridge->gatt_bus_addr = temp;
482
483 return 0;
484 }
485
486 /* Return the gatt table to a sane state. Use the top of stolen
487 * memory for the GTT.
488 */
489 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
490 {
491 return 0;
492 }
493
494 static int intel_i830_fetch_size(void)
495 {
496 u16 gmch_ctrl;
497 struct aper_size_info_fixed *values;
498
499 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
500
501 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
502 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
503 /* 855GM/852GM/865G has 128MB aperture size */
504 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
505 agp_bridge->aperture_size_idx = 0;
506 return values[0].size;
507 }
508
509 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
510
511 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
512 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
513 agp_bridge->aperture_size_idx = 0;
514 return values[0].size;
515 } else {
516 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
517 agp_bridge->aperture_size_idx = 1;
518 return values[1].size;
519 }
520
521 return 0;
522 }
523
524 static int intel_i830_configure(void)
525 {
526 struct aper_size_info_fixed *current_size;
527 u32 temp;
528 u16 gmch_ctrl;
529 int i;
530
531 current_size = A_SIZE_FIX(agp_bridge->current_size);
532
533 pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp);
534 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
535
536 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
537 gmch_ctrl |= I830_GMCH_ENABLED;
538 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
539
540 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL);
541 readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
542
543 if (agp_bridge->driver->needs_scratch_page) {
544 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) {
545 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4));
546 readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
547 }
548 }
549
550 global_cache_flush();
551 return 0;
552 }
553
554 static void intel_i830_cleanup(void)
555 {
556 iounmap(intel_i830_private.registers);
557 }
558
559 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
560 {
561 int i,j,num_entries;
562 void *temp;
563
564 temp = agp_bridge->current_size;
565 num_entries = A_SIZE_FIX(temp)->num_entries;
566
567 if (pg_start < intel_i830_private.gtt_entries) {
568 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n",
569 pg_start,intel_i830_private.gtt_entries);
570
571 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
572 return -EINVAL;
573 }
574
575 if ((pg_start + mem->page_count) > num_entries)
576 return -EINVAL;
577
578 /* The i830 can't check the GTT for entries since its read only,
579 * depend on the caller to make the correct offset decisions.
580 */
581
582 if ((type != 0 && type != AGP_PHYS_MEMORY) ||
583 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY))
584 return -EINVAL;
585
586 global_cache_flush(); /* FIXME: Necessary ?*/
587
588 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
589 writel(agp_bridge->driver->mask_memory(agp_bridge,
590 mem->memory[i], mem->type),
591 intel_i830_private.registers+I810_PTE_BASE+(j*4));
592 readl(intel_i830_private.registers+I810_PTE_BASE+(j*4)); /* PCI Posting. */
593 }
594
595 global_cache_flush();
596 agp_bridge->driver->tlb_flush(mem);
597 return 0;
598 }
599
600 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
601 int type)
602 {
603 int i;
604
605 global_cache_flush();
606
607 if (pg_start < intel_i830_private.gtt_entries) {
608 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
609 return -EINVAL;
610 }
611
612 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
613 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4));
614 readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
615 }
616
617 global_cache_flush();
618 agp_bridge->driver->tlb_flush(mem);
619 return 0;
620 }
621
622 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
623 {
624 if (type == AGP_PHYS_MEMORY)
625 return alloc_agpphysmem_i8xx(pg_count, type);
626
627 /* always return NULL for other allocation types for now */
628 return NULL;
629 }
630
631 static int intel_i915_configure(void)
632 {
633 struct aper_size_info_fixed *current_size;
634 u32 temp;
635 u16 gmch_ctrl;
636 int i;
637
638 current_size = A_SIZE_FIX(agp_bridge->current_size);
639
640 pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp);
641
642 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
643
644 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
645 gmch_ctrl |= I830_GMCH_ENABLED;
646 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
647
648 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL);
649 readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
650
651 if (agp_bridge->driver->needs_scratch_page) {
652 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) {
653 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i);
654 readl(intel_i830_private.gtt+i); /* PCI Posting. */
655 }
656 }
657
658 global_cache_flush();
659 return 0;
660 }
661
662 static void intel_i915_cleanup(void)
663 {
664 iounmap(intel_i830_private.gtt);
665 iounmap(intel_i830_private.registers);
666 }
667
668 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
669 int type)
670 {
671 int i,j,num_entries;
672 void *temp;
673
674 temp = agp_bridge->current_size;
675 num_entries = A_SIZE_FIX(temp)->num_entries;
676
677 if (pg_start < intel_i830_private.gtt_entries) {
678 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n",
679 pg_start,intel_i830_private.gtt_entries);
680
681 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
682 return -EINVAL;
683 }
684
685 if ((pg_start + mem->page_count) > num_entries)
686 return -EINVAL;
687
688 /* The i830 can't check the GTT for entries since its read only,
689 * depend on the caller to make the correct offset decisions.
690 */
691
692 if ((type != 0 && type != AGP_PHYS_MEMORY) ||
693 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY))
694 return -EINVAL;
695
696 global_cache_flush();
697
698 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
699 writel(agp_bridge->driver->mask_memory(agp_bridge,
700 mem->memory[i], mem->type), intel_i830_private.gtt+j);
701 readl(intel_i830_private.gtt+j); /* PCI Posting. */
702 }
703
704 global_cache_flush();
705 agp_bridge->driver->tlb_flush(mem);
706 return 0;
707 }
708
709 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
710 int type)
711 {
712 int i;
713
714 global_cache_flush();
715
716 if (pg_start < intel_i830_private.gtt_entries) {
717 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
718 return -EINVAL;
719 }
720
721 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
722 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i);
723 readl(intel_i830_private.gtt+i);
724 }
725
726 global_cache_flush();
727 agp_bridge->driver->tlb_flush(mem);
728 return 0;
729 }
730
731 static int intel_i915_fetch_size(void)
732 {
733 struct aper_size_info_fixed *values;
734 u32 temp, offset = 0;
735
736 #define I915_256MB_ADDRESS_MASK (1<<27)
737
738 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
739
740 pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp);
741 if (temp & I915_256MB_ADDRESS_MASK)
742 offset = 0; /* 128MB aperture */
743 else
744 offset = 2; /* 256MB aperture */
745 agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset);
746 return values[offset].size;
747 }
748
749 /* The intel i915 automatically initializes the agp aperture during POST.
750 * Use the memory already set aside for in the GTT.
751 */
752 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
753 {
754 int page_order;
755 struct aper_size_info_fixed *size;
756 int num_entries;
757 u32 temp, temp2;
758
759 size = agp_bridge->current_size;
760 page_order = size->page_order;
761 num_entries = size->num_entries;
762 agp_bridge->gatt_table_real = NULL;
763
764 pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp);
765 pci_read_config_dword(intel_i830_private.i830_dev, I915_PTEADDR,&temp2);
766
767 intel_i830_private.gtt = ioremap(temp2, 256 * 1024);
768 if (!intel_i830_private.gtt)
769 return -ENOMEM;
770
771 temp &= 0xfff80000;
772
773 intel_i830_private.registers = ioremap(temp,128 * 4096);
774 if (!intel_i830_private.registers)
775 return -ENOMEM;
776
777 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
778 global_cache_flush(); /* FIXME: ? */
779
780 /* we have to call this as early as possible after the MMIO base address is known */
781 intel_i830_init_gtt_entries();
782
783 agp_bridge->gatt_table = NULL;
784
785 agp_bridge->gatt_bus_addr = temp;
786
787 return 0;
788 }
789
790 static int intel_fetch_size(void)
791 {
792 int i;
793 u16 temp;
794 struct aper_size_info_16 *values;
795
796 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
797 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
798
799 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
800 if (temp == values[i].size_value) {
801 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
802 agp_bridge->aperture_size_idx = i;
803 return values[i].size;
804 }
805 }
806
807 return 0;
808 }
809
810 static int __intel_8xx_fetch_size(u8 temp)
811 {
812 int i;
813 struct aper_size_info_8 *values;
814
815 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
816
817 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
818 if (temp == values[i].size_value) {
819 agp_bridge->previous_size =
820 agp_bridge->current_size = (void *) (values + i);
821 agp_bridge->aperture_size_idx = i;
822 return values[i].size;
823 }
824 }
825 return 0;
826 }
827
828 static int intel_8xx_fetch_size(void)
829 {
830 u8 temp;
831
832 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
833 return __intel_8xx_fetch_size(temp);
834 }
835
836 static int intel_815_fetch_size(void)
837 {
838 u8 temp;
839
840 /* Intel 815 chipsets have a _weird_ APSIZE register with only
841 * one non-reserved bit, so mask the others out ... */
842 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
843 temp &= (1 << 3);
844
845 return __intel_8xx_fetch_size(temp);
846 }
847
848 static void intel_tlbflush(struct agp_memory *mem)
849 {
850 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
851 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
852 }
853
854
855 static void intel_8xx_tlbflush(struct agp_memory *mem)
856 {
857 u32 temp;
858 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
859 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
860 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
861 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
862 }
863
864
865 static void intel_cleanup(void)
866 {
867 u16 temp;
868 struct aper_size_info_16 *previous_size;
869
870 previous_size = A_SIZE_16(agp_bridge->previous_size);
871 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
872 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
873 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
874 }
875
876
877 static void intel_8xx_cleanup(void)
878 {
879 u16 temp;
880 struct aper_size_info_8 *previous_size;
881
882 previous_size = A_SIZE_8(agp_bridge->previous_size);
883 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
884 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
885 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
886 }
887
888
889 static int intel_configure(void)
890 {
891 u32 temp;
892 u16 temp2;
893 struct aper_size_info_16 *current_size;
894
895 current_size = A_SIZE_16(agp_bridge->current_size);
896
897 /* aperture size */
898 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
899
900 /* address to map to */
901 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
902 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
903
904 /* attbase - aperture base */
905 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
906
907 /* agpctrl */
908 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
909
910 /* paccfg/nbxcfg */
911 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
912 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
913 (temp2 & ~(1 << 10)) | (1 << 9));
914 /* clear any possible error conditions */
915 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
916 return 0;
917 }
918
919 static int intel_815_configure(void)
920 {
921 u32 temp, addr;
922 u8 temp2;
923 struct aper_size_info_8 *current_size;
924
925 /* attbase - aperture base */
926 /* the Intel 815 chipset spec. says that bits 29-31 in the
927 * ATTBASE register are reserved -> try not to write them */
928 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
929 printk (KERN_EMERG PFX "gatt bus addr too high");
930 return -EINVAL;
931 }
932
933 current_size = A_SIZE_8(agp_bridge->current_size);
934
935 /* aperture size */
936 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
937 current_size->size_value);
938
939 /* address to map to */
940 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
941 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
942
943 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
944 addr &= INTEL_815_ATTBASE_MASK;
945 addr |= agp_bridge->gatt_bus_addr;
946 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
947
948 /* agpctrl */
949 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
950
951 /* apcont */
952 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
953 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
954
955 /* clear any possible error conditions */
956 /* Oddness : this chipset seems to have no ERRSTS register ! */
957 return 0;
958 }
959
960 static void intel_820_tlbflush(struct agp_memory *mem)
961 {
962 return;
963 }
964
965 static void intel_820_cleanup(void)
966 {
967 u8 temp;
968 struct aper_size_info_8 *previous_size;
969
970 previous_size = A_SIZE_8(agp_bridge->previous_size);
971 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
972 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
973 temp & ~(1 << 1));
974 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
975 previous_size->size_value);
976 }
977
978
979 static int intel_820_configure(void)
980 {
981 u32 temp;
982 u8 temp2;
983 struct aper_size_info_8 *current_size;
984
985 current_size = A_SIZE_8(agp_bridge->current_size);
986
987 /* aperture size */
988 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
989
990 /* address to map to */
991 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
992 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
993
994 /* attbase - aperture base */
995 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
996
997 /* agpctrl */
998 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
999
1000 /* global enable aperture access */
1001 /* This flag is not accessed through MCHCFG register as in */
1002 /* i850 chipset. */
1003 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1004 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1005 /* clear any possible AGP-related error conditions */
1006 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1007 return 0;
1008 }
1009
1010 static int intel_840_configure(void)
1011 {
1012 u32 temp;
1013 u16 temp2;
1014 struct aper_size_info_8 *current_size;
1015
1016 current_size = A_SIZE_8(agp_bridge->current_size);
1017
1018 /* aperture size */
1019 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1020
1021 /* address to map to */
1022 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1023 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1024
1025 /* attbase - aperture base */
1026 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1027
1028 /* agpctrl */
1029 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1030
1031 /* mcgcfg */
1032 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1033 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1034 /* clear any possible error conditions */
1035 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1036 return 0;
1037 }
1038
1039 static int intel_845_configure(void)
1040 {
1041 u32 temp;
1042 u8 temp2;
1043 struct aper_size_info_8 *current_size;
1044
1045 current_size = A_SIZE_8(agp_bridge->current_size);
1046
1047 /* aperture size */
1048 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1049
1050 /* address to map to */
1051 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1052 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1053
1054 /* attbase - aperture base */
1055 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1056
1057 /* agpctrl */
1058 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1059
1060 /* agpm */
1061 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1062 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1063 /* clear any possible error conditions */
1064 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1065 return 0;
1066 }
1067
1068 static int intel_850_configure(void)
1069 {
1070 u32 temp;
1071 u16 temp2;
1072 struct aper_size_info_8 *current_size;
1073
1074 current_size = A_SIZE_8(agp_bridge->current_size);
1075
1076 /* aperture size */
1077 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1078
1079 /* address to map to */
1080 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1081 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1082
1083 /* attbase - aperture base */
1084 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1085
1086 /* agpctrl */
1087 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1088
1089 /* mcgcfg */
1090 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1091 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1092 /* clear any possible AGP-related error conditions */
1093 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1094 return 0;
1095 }
1096
1097 static int intel_860_configure(void)
1098 {
1099 u32 temp;
1100 u16 temp2;
1101 struct aper_size_info_8 *current_size;
1102
1103 current_size = A_SIZE_8(agp_bridge->current_size);
1104
1105 /* aperture size */
1106 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1107
1108 /* address to map to */
1109 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1110 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1111
1112 /* attbase - aperture base */
1113 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1114
1115 /* agpctrl */
1116 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1117
1118 /* mcgcfg */
1119 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1120 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1121 /* clear any possible AGP-related error conditions */
1122 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1123 return 0;
1124 }
1125
1126 static int intel_830mp_configure(void)
1127 {
1128 u32 temp;
1129 u16 temp2;
1130 struct aper_size_info_8 *current_size;
1131
1132 current_size = A_SIZE_8(agp_bridge->current_size);
1133
1134 /* aperture size */
1135 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1136
1137 /* address to map to */
1138 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1139 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1140
1141 /* attbase - aperture base */
1142 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1143
1144 /* agpctrl */
1145 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1146
1147 /* gmch */
1148 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1149 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1150 /* clear any possible AGP-related error conditions */
1151 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1152 return 0;
1153 }
1154
1155 static int intel_7505_configure(void)
1156 {
1157 u32 temp;
1158 u16 temp2;
1159 struct aper_size_info_8 *current_size;
1160
1161 current_size = A_SIZE_8(agp_bridge->current_size);
1162
1163 /* aperture size */
1164 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1165
1166 /* address to map to */
1167 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1168 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1169
1170 /* attbase - aperture base */
1171 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1172
1173 /* agpctrl */
1174 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1175
1176 /* mchcfg */
1177 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1178 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1179
1180 return 0;
1181 }
1182
1183 /* Setup function */
1184 static struct gatt_mask intel_generic_masks[] =
1185 {
1186 {.mask = 0x00000017, .type = 0}
1187 };
1188
1189 static struct aper_size_info_8 intel_815_sizes[2] =
1190 {
1191 {64, 16384, 4, 0},
1192 {32, 8192, 3, 8},
1193 };
1194
1195 static struct aper_size_info_8 intel_8xx_sizes[7] =
1196 {
1197 {256, 65536, 6, 0},
1198 {128, 32768, 5, 32},
1199 {64, 16384, 4, 48},
1200 {32, 8192, 3, 56},
1201 {16, 4096, 2, 60},
1202 {8, 2048, 1, 62},
1203 {4, 1024, 0, 63}
1204 };
1205
1206 static struct aper_size_info_16 intel_generic_sizes[7] =
1207 {
1208 {256, 65536, 6, 0},
1209 {128, 32768, 5, 32},
1210 {64, 16384, 4, 48},
1211 {32, 8192, 3, 56},
1212 {16, 4096, 2, 60},
1213 {8, 2048, 1, 62},
1214 {4, 1024, 0, 63}
1215 };
1216
1217 static struct aper_size_info_8 intel_830mp_sizes[4] =
1218 {
1219 {256, 65536, 6, 0},
1220 {128, 32768, 5, 32},
1221 {64, 16384, 4, 48},
1222 {32, 8192, 3, 56}
1223 };
1224
1225 static struct agp_bridge_driver intel_generic_driver = {
1226 .owner = THIS_MODULE,
1227 .aperture_sizes = intel_generic_sizes,
1228 .size_type = U16_APER_SIZE,
1229 .num_aperture_sizes = 7,
1230 .configure = intel_configure,
1231 .fetch_size = intel_fetch_size,
1232 .cleanup = intel_cleanup,
1233 .tlb_flush = intel_tlbflush,
1234 .mask_memory = agp_generic_mask_memory,
1235 .masks = intel_generic_masks,
1236 .agp_enable = agp_generic_enable,
1237 .cache_flush = global_cache_flush,
1238 .create_gatt_table = agp_generic_create_gatt_table,
1239 .free_gatt_table = agp_generic_free_gatt_table,
1240 .insert_memory = agp_generic_insert_memory,
1241 .remove_memory = agp_generic_remove_memory,
1242 .alloc_by_type = agp_generic_alloc_by_type,
1243 .free_by_type = agp_generic_free_by_type,
1244 .agp_alloc_page = agp_generic_alloc_page,
1245 .agp_destroy_page = agp_generic_destroy_page,
1246 };
1247
1248 static struct agp_bridge_driver intel_810_driver = {
1249 .owner = THIS_MODULE,
1250 .aperture_sizes = intel_i810_sizes,
1251 .size_type = FIXED_APER_SIZE,
1252 .num_aperture_sizes = 2,
1253 .needs_scratch_page = TRUE,
1254 .configure = intel_i810_configure,
1255 .fetch_size = intel_i810_fetch_size,
1256 .cleanup = intel_i810_cleanup,
1257 .tlb_flush = intel_i810_tlbflush,
1258 .mask_memory = intel_i810_mask_memory,
1259 .masks = intel_i810_masks,
1260 .agp_enable = intel_i810_agp_enable,
1261 .cache_flush = global_cache_flush,
1262 .create_gatt_table = agp_generic_create_gatt_table,
1263 .free_gatt_table = agp_generic_free_gatt_table,
1264 .insert_memory = intel_i810_insert_entries,
1265 .remove_memory = intel_i810_remove_entries,
1266 .alloc_by_type = intel_i810_alloc_by_type,
1267 .free_by_type = intel_i810_free_by_type,
1268 .agp_alloc_page = agp_generic_alloc_page,
1269 .agp_destroy_page = agp_generic_destroy_page,
1270 };
1271
1272 static struct agp_bridge_driver intel_815_driver = {
1273 .owner = THIS_MODULE,
1274 .aperture_sizes = intel_815_sizes,
1275 .size_type = U8_APER_SIZE,
1276 .num_aperture_sizes = 2,
1277 .configure = intel_815_configure,
1278 .fetch_size = intel_815_fetch_size,
1279 .cleanup = intel_8xx_cleanup,
1280 .tlb_flush = intel_8xx_tlbflush,
1281 .mask_memory = agp_generic_mask_memory,
1282 .masks = intel_generic_masks,
1283 .agp_enable = agp_generic_enable,
1284 .cache_flush = global_cache_flush,
1285 .create_gatt_table = agp_generic_create_gatt_table,
1286 .free_gatt_table = agp_generic_free_gatt_table,
1287 .insert_memory = agp_generic_insert_memory,
1288 .remove_memory = agp_generic_remove_memory,
1289 .alloc_by_type = agp_generic_alloc_by_type,
1290 .free_by_type = agp_generic_free_by_type,
1291 .agp_alloc_page = agp_generic_alloc_page,
1292 .agp_destroy_page = agp_generic_destroy_page,
1293 };
1294
1295 static struct agp_bridge_driver intel_830_driver = {
1296 .owner = THIS_MODULE,
1297 .aperture_sizes = intel_i830_sizes,
1298 .size_type = FIXED_APER_SIZE,
1299 .num_aperture_sizes = 3,
1300 .needs_scratch_page = TRUE,
1301 .configure = intel_i830_configure,
1302 .fetch_size = intel_i830_fetch_size,
1303 .cleanup = intel_i830_cleanup,
1304 .tlb_flush = intel_i810_tlbflush,
1305 .mask_memory = intel_i810_mask_memory,
1306 .masks = intel_i810_masks,
1307 .agp_enable = intel_i810_agp_enable,
1308 .cache_flush = global_cache_flush,
1309 .create_gatt_table = intel_i830_create_gatt_table,
1310 .free_gatt_table = intel_i830_free_gatt_table,
1311 .insert_memory = intel_i830_insert_entries,
1312 .remove_memory = intel_i830_remove_entries,
1313 .alloc_by_type = intel_i830_alloc_by_type,
1314 .free_by_type = intel_i810_free_by_type,
1315 .agp_alloc_page = agp_generic_alloc_page,
1316 .agp_destroy_page = agp_generic_destroy_page,
1317 };
1318
1319 static struct agp_bridge_driver intel_820_driver = {
1320 .owner = THIS_MODULE,
1321 .aperture_sizes = intel_8xx_sizes,
1322 .size_type = U8_APER_SIZE,
1323 .num_aperture_sizes = 7,
1324 .configure = intel_820_configure,
1325 .fetch_size = intel_8xx_fetch_size,
1326 .cleanup = intel_820_cleanup,
1327 .tlb_flush = intel_820_tlbflush,
1328 .mask_memory = agp_generic_mask_memory,
1329 .masks = intel_generic_masks,
1330 .agp_enable = agp_generic_enable,
1331 .cache_flush = global_cache_flush,
1332 .create_gatt_table = agp_generic_create_gatt_table,
1333 .free_gatt_table = agp_generic_free_gatt_table,
1334 .insert_memory = agp_generic_insert_memory,
1335 .remove_memory = agp_generic_remove_memory,
1336 .alloc_by_type = agp_generic_alloc_by_type,
1337 .free_by_type = agp_generic_free_by_type,
1338 .agp_alloc_page = agp_generic_alloc_page,
1339 .agp_destroy_page = agp_generic_destroy_page,
1340 };
1341
1342 static struct agp_bridge_driver intel_830mp_driver = {
1343 .owner = THIS_MODULE,
1344 .aperture_sizes = intel_830mp_sizes,
1345 .size_type = U8_APER_SIZE,
1346 .num_aperture_sizes = 4,
1347 .configure = intel_830mp_configure,
1348 .fetch_size = intel_8xx_fetch_size,
1349 .cleanup = intel_8xx_cleanup,
1350 .tlb_flush = intel_8xx_tlbflush,
1351 .mask_memory = agp_generic_mask_memory,
1352 .masks = intel_generic_masks,
1353 .agp_enable = agp_generic_enable,
1354 .cache_flush = global_cache_flush,
1355 .create_gatt_table = agp_generic_create_gatt_table,
1356 .free_gatt_table = agp_generic_free_gatt_table,
1357 .insert_memory = agp_generic_insert_memory,
1358 .remove_memory = agp_generic_remove_memory,
1359 .alloc_by_type = agp_generic_alloc_by_type,
1360 .free_by_type = agp_generic_free_by_type,
1361 .agp_alloc_page = agp_generic_alloc_page,
1362 .agp_destroy_page = agp_generic_destroy_page,
1363 };
1364
1365 static struct agp_bridge_driver intel_840_driver = {
1366 .owner = THIS_MODULE,
1367 .aperture_sizes = intel_8xx_sizes,
1368 .size_type = U8_APER_SIZE,
1369 .num_aperture_sizes = 7,
1370 .configure = intel_840_configure,
1371 .fetch_size = intel_8xx_fetch_size,
1372 .cleanup = intel_8xx_cleanup,
1373 .tlb_flush = intel_8xx_tlbflush,
1374 .mask_memory = agp_generic_mask_memory,
1375 .masks = intel_generic_masks,
1376 .agp_enable = agp_generic_enable,
1377 .cache_flush = global_cache_flush,
1378 .create_gatt_table = agp_generic_create_gatt_table,
1379 .free_gatt_table = agp_generic_free_gatt_table,
1380 .insert_memory = agp_generic_insert_memory,
1381 .remove_memory = agp_generic_remove_memory,
1382 .alloc_by_type = agp_generic_alloc_by_type,
1383 .free_by_type = agp_generic_free_by_type,
1384 .agp_alloc_page = agp_generic_alloc_page,
1385 .agp_destroy_page = agp_generic_destroy_page,
1386 };
1387
1388 static struct agp_bridge_driver intel_845_driver = {
1389 .owner = THIS_MODULE,
1390 .aperture_sizes = intel_8xx_sizes,
1391 .size_type = U8_APER_SIZE,
1392 .num_aperture_sizes = 7,
1393 .configure = intel_845_configure,
1394 .fetch_size = intel_8xx_fetch_size,
1395 .cleanup = intel_8xx_cleanup,
1396 .tlb_flush = intel_8xx_tlbflush,
1397 .mask_memory = agp_generic_mask_memory,
1398 .masks = intel_generic_masks,
1399 .agp_enable = agp_generic_enable,
1400 .cache_flush = global_cache_flush,
1401 .create_gatt_table = agp_generic_create_gatt_table,
1402 .free_gatt_table = agp_generic_free_gatt_table,
1403 .insert_memory = agp_generic_insert_memory,
1404 .remove_memory = agp_generic_remove_memory,
1405 .alloc_by_type = agp_generic_alloc_by_type,
1406 .free_by_type = agp_generic_free_by_type,
1407 .agp_alloc_page = agp_generic_alloc_page,
1408 .agp_destroy_page = agp_generic_destroy_page,
1409 };
1410
1411 static struct agp_bridge_driver intel_850_driver = {
1412 .owner = THIS_MODULE,
1413 .aperture_sizes = intel_8xx_sizes,
1414 .size_type = U8_APER_SIZE,
1415 .num_aperture_sizes = 7,
1416 .configure = intel_850_configure,
1417 .fetch_size = intel_8xx_fetch_size,
1418 .cleanup = intel_8xx_cleanup,
1419 .tlb_flush = intel_8xx_tlbflush,
1420 .mask_memory = agp_generic_mask_memory,
1421 .masks = intel_generic_masks,
1422 .agp_enable = agp_generic_enable,
1423 .cache_flush = global_cache_flush,
1424 .create_gatt_table = agp_generic_create_gatt_table,
1425 .free_gatt_table = agp_generic_free_gatt_table,
1426 .insert_memory = agp_generic_insert_memory,
1427 .remove_memory = agp_generic_remove_memory,
1428 .alloc_by_type = agp_generic_alloc_by_type,
1429 .free_by_type = agp_generic_free_by_type,
1430 .agp_alloc_page = agp_generic_alloc_page,
1431 .agp_destroy_page = agp_generic_destroy_page,
1432 };
1433
1434 static struct agp_bridge_driver intel_860_driver = {
1435 .owner = THIS_MODULE,
1436 .aperture_sizes = intel_8xx_sizes,
1437 .size_type = U8_APER_SIZE,
1438 .num_aperture_sizes = 7,
1439 .configure = intel_860_configure,
1440 .fetch_size = intel_8xx_fetch_size,
1441 .cleanup = intel_8xx_cleanup,
1442 .tlb_flush = intel_8xx_tlbflush,
1443 .mask_memory = agp_generic_mask_memory,
1444 .masks = intel_generic_masks,
1445 .agp_enable = agp_generic_enable,
1446 .cache_flush = global_cache_flush,
1447 .create_gatt_table = agp_generic_create_gatt_table,
1448 .free_gatt_table = agp_generic_free_gatt_table,
1449 .insert_memory = agp_generic_insert_memory,
1450 .remove_memory = agp_generic_remove_memory,
1451 .alloc_by_type = agp_generic_alloc_by_type,
1452 .free_by_type = agp_generic_free_by_type,
1453 .agp_alloc_page = agp_generic_alloc_page,
1454 .agp_destroy_page = agp_generic_destroy_page,
1455 };
1456
1457 static struct agp_bridge_driver intel_915_driver = {
1458 .owner = THIS_MODULE,
1459 .aperture_sizes = intel_i830_sizes,
1460 .size_type = FIXED_APER_SIZE,
1461 .num_aperture_sizes = 3,
1462 .needs_scratch_page = TRUE,
1463 .configure = intel_i915_configure,
1464 .fetch_size = intel_i915_fetch_size,
1465 .cleanup = intel_i915_cleanup,
1466 .tlb_flush = intel_i810_tlbflush,
1467 .mask_memory = intel_i810_mask_memory,
1468 .masks = intel_i810_masks,
1469 .agp_enable = intel_i810_agp_enable,
1470 .cache_flush = global_cache_flush,
1471 .create_gatt_table = intel_i915_create_gatt_table,
1472 .free_gatt_table = intel_i830_free_gatt_table,
1473 .insert_memory = intel_i915_insert_entries,
1474 .remove_memory = intel_i915_remove_entries,
1475 .alloc_by_type = intel_i830_alloc_by_type,
1476 .free_by_type = intel_i810_free_by_type,
1477 .agp_alloc_page = agp_generic_alloc_page,
1478 .agp_destroy_page = agp_generic_destroy_page,
1479 };
1480
1481
1482 static struct agp_bridge_driver intel_7505_driver = {
1483 .owner = THIS_MODULE,
1484 .aperture_sizes = intel_8xx_sizes,
1485 .size_type = U8_APER_SIZE,
1486 .num_aperture_sizes = 7,
1487 .configure = intel_7505_configure,
1488 .fetch_size = intel_8xx_fetch_size,
1489 .cleanup = intel_8xx_cleanup,
1490 .tlb_flush = intel_8xx_tlbflush,
1491 .mask_memory = agp_generic_mask_memory,
1492 .masks = intel_generic_masks,
1493 .agp_enable = agp_generic_enable,
1494 .cache_flush = global_cache_flush,
1495 .create_gatt_table = agp_generic_create_gatt_table,
1496 .free_gatt_table = agp_generic_free_gatt_table,
1497 .insert_memory = agp_generic_insert_memory,
1498 .remove_memory = agp_generic_remove_memory,
1499 .alloc_by_type = agp_generic_alloc_by_type,
1500 .free_by_type = agp_generic_free_by_type,
1501 .agp_alloc_page = agp_generic_alloc_page,
1502 .agp_destroy_page = agp_generic_destroy_page,
1503 };
1504
1505 static int find_i810(u16 device)
1506 {
1507 struct pci_dev *i810_dev;
1508
1509 i810_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1510 if (!i810_dev)
1511 return 0;
1512 intel_i810_private.i810_dev = i810_dev;
1513 return 1;
1514 }
1515
1516 static int find_i830(u16 device)
1517 {
1518 struct pci_dev *i830_dev;
1519
1520 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1521 if (i830_dev && PCI_FUNC(i830_dev->devfn) != 0) {
1522 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
1523 device, i830_dev);
1524 }
1525
1526 if (!i830_dev)
1527 return 0;
1528
1529 intel_i830_private.i830_dev = i830_dev;
1530 return 1;
1531 }
1532
1533 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1534 const struct pci_device_id *ent)
1535 {
1536 struct agp_bridge_data *bridge;
1537 char *name = "(unknown)";
1538 u8 cap_ptr = 0;
1539 struct resource *r;
1540
1541 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1542
1543 bridge = agp_alloc_bridge();
1544 if (!bridge)
1545 return -ENOMEM;
1546
1547 switch (pdev->device) {
1548 case PCI_DEVICE_ID_INTEL_82443LX_0:
1549 bridge->driver = &intel_generic_driver;
1550 name = "440LX";
1551 break;
1552 case PCI_DEVICE_ID_INTEL_82443BX_0:
1553 bridge->driver = &intel_generic_driver;
1554 name = "440BX";
1555 break;
1556 case PCI_DEVICE_ID_INTEL_82443GX_0:
1557 bridge->driver = &intel_generic_driver;
1558 name = "440GX";
1559 break;
1560 case PCI_DEVICE_ID_INTEL_82810_MC1:
1561 name = "i810";
1562 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG1))
1563 goto fail;
1564 bridge->driver = &intel_810_driver;
1565 break;
1566 case PCI_DEVICE_ID_INTEL_82810_MC3:
1567 name = "i810 DC100";
1568 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG3))
1569 goto fail;
1570 bridge->driver = &intel_810_driver;
1571 break;
1572 case PCI_DEVICE_ID_INTEL_82810E_MC:
1573 name = "i810 E";
1574 if (!find_i810(PCI_DEVICE_ID_INTEL_82810E_IG))
1575 goto fail;
1576 bridge->driver = &intel_810_driver;
1577 break;
1578 case PCI_DEVICE_ID_INTEL_82815_MC:
1579 /*
1580 * The i815 can operate either as an i810 style
1581 * integrated device, or as an AGP4X motherboard.
1582 */
1583 if (find_i810(PCI_DEVICE_ID_INTEL_82815_CGC))
1584 bridge->driver = &intel_810_driver;
1585 else
1586 bridge->driver = &intel_815_driver;
1587 name = "i815";
1588 break;
1589 case PCI_DEVICE_ID_INTEL_82820_HB:
1590 case PCI_DEVICE_ID_INTEL_82820_UP_HB:
1591 bridge->driver = &intel_820_driver;
1592 name = "i820";
1593 break;
1594 case PCI_DEVICE_ID_INTEL_82830_HB:
1595 if (find_i830(PCI_DEVICE_ID_INTEL_82830_CGC)) {
1596 bridge->driver = &intel_830_driver;
1597 } else {
1598 bridge->driver = &intel_830mp_driver;
1599 }
1600 name = "830M";
1601 break;
1602 case PCI_DEVICE_ID_INTEL_82840_HB:
1603 bridge->driver = &intel_840_driver;
1604 name = "i840";
1605 break;
1606 case PCI_DEVICE_ID_INTEL_82845_HB:
1607 bridge->driver = &intel_845_driver;
1608 name = "i845";
1609 break;
1610 case PCI_DEVICE_ID_INTEL_82845G_HB:
1611 if (find_i830(PCI_DEVICE_ID_INTEL_82845G_IG)) {
1612 bridge->driver = &intel_830_driver;
1613 } else {
1614 bridge->driver = &intel_845_driver;
1615 }
1616 name = "845G";
1617 break;
1618 case PCI_DEVICE_ID_INTEL_82850_HB:
1619 bridge->driver = &intel_850_driver;
1620 name = "i850";
1621 break;
1622 case PCI_DEVICE_ID_INTEL_82855PM_HB:
1623 bridge->driver = &intel_845_driver;
1624 name = "855PM";
1625 break;
1626 case PCI_DEVICE_ID_INTEL_82855GM_HB:
1627 if (find_i830(PCI_DEVICE_ID_INTEL_82855GM_IG)) {
1628 bridge->driver = &intel_830_driver;
1629 name = "855";
1630 } else {
1631 bridge->driver = &intel_845_driver;
1632 name = "855GM";
1633 }
1634 break;
1635 case PCI_DEVICE_ID_INTEL_82860_HB:
1636 bridge->driver = &intel_860_driver;
1637 name = "i860";
1638 break;
1639 case PCI_DEVICE_ID_INTEL_82865_HB:
1640 if (find_i830(PCI_DEVICE_ID_INTEL_82865_IG)) {
1641 bridge->driver = &intel_830_driver;
1642 } else {
1643 bridge->driver = &intel_845_driver;
1644 }
1645 name = "865";
1646 break;
1647 case PCI_DEVICE_ID_INTEL_82875_HB:
1648 bridge->driver = &intel_845_driver;
1649 name = "i875";
1650 break;
1651 case PCI_DEVICE_ID_INTEL_82915G_HB:
1652 if (find_i830(PCI_DEVICE_ID_INTEL_82915G_IG)) {
1653 bridge->driver = &intel_915_driver;
1654 } else {
1655 bridge->driver = &intel_845_driver;
1656 }
1657 name = "915G";
1658 break;
1659 case PCI_DEVICE_ID_INTEL_82915GM_HB:
1660 if (find_i830(PCI_DEVICE_ID_INTEL_82915GM_IG)) {
1661 bridge->driver = &intel_915_driver;
1662 } else {
1663 bridge->driver = &intel_845_driver;
1664 }
1665 name = "915GM";
1666 break;
1667 case PCI_DEVICE_ID_INTEL_82945G_HB:
1668 if (find_i830(PCI_DEVICE_ID_INTEL_82945G_IG)) {
1669 bridge->driver = &intel_915_driver;
1670 } else {
1671 bridge->driver = &intel_845_driver;
1672 }
1673 name = "945G";
1674 break;
1675 case PCI_DEVICE_ID_INTEL_7505_0:
1676 bridge->driver = &intel_7505_driver;
1677 name = "E7505";
1678 break;
1679 case PCI_DEVICE_ID_INTEL_7205_0:
1680 bridge->driver = &intel_7505_driver;
1681 name = "E7205";
1682 break;
1683 default:
1684 if (cap_ptr)
1685 printk(KERN_WARNING PFX "Unsupported Intel chipset (device id: %04x)\n",
1686 pdev->device);
1687 agp_put_bridge(bridge);
1688 return -ENODEV;
1689 };
1690
1691 bridge->dev = pdev;
1692 bridge->capndx = cap_ptr;
1693
1694 if (bridge->driver == &intel_810_driver)
1695 bridge->dev_private_data = &intel_i810_private;
1696 else if (bridge->driver == &intel_830_driver)
1697 bridge->dev_private_data = &intel_i830_private;
1698
1699 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", name);
1700
1701 /*
1702 * The following fixes the case where the BIOS has "forgotten" to
1703 * provide an address range for the GART.
1704 * 20030610 - hamish@zot.org
1705 */
1706 r = &pdev->resource[0];
1707 if (!r->start && r->end) {
1708 if(pci_assign_resource(pdev, 0)) {
1709 printk(KERN_ERR PFX "could not assign resource 0\n");
1710 agp_put_bridge(bridge);
1711 return -ENODEV;
1712 }
1713 }
1714
1715 /*
1716 * If the device has not been properly setup, the following will catch
1717 * the problem and should stop the system from crashing.
1718 * 20030610 - hamish@zot.org
1719 */
1720 if (pci_enable_device(pdev)) {
1721 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1722 agp_put_bridge(bridge);
1723 return -ENODEV;
1724 }
1725
1726 /* Fill in the mode register */
1727 if (cap_ptr) {
1728 pci_read_config_dword(pdev,
1729 bridge->capndx+PCI_AGP_STATUS,
1730 &bridge->mode);
1731 }
1732
1733 pci_set_drvdata(pdev, bridge);
1734 return agp_add_bridge(bridge);
1735
1736 fail:
1737 printk(KERN_ERR PFX "Detected an Intel %s chipset, "
1738 "but could not find the secondary device.\n", name);
1739 agp_put_bridge(bridge);
1740 return -ENODEV;
1741 }
1742
1743 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1744 {
1745 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1746
1747 agp_remove_bridge(bridge);
1748
1749 if (intel_i810_private.i810_dev)
1750 pci_dev_put(intel_i810_private.i810_dev);
1751 if (intel_i830_private.i830_dev)
1752 pci_dev_put(intel_i830_private.i830_dev);
1753
1754 agp_put_bridge(bridge);
1755 }
1756
1757 static int agp_intel_resume(struct pci_dev *pdev)
1758 {
1759 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1760
1761 pci_restore_state(pdev);
1762
1763 if (bridge->driver == &intel_generic_driver)
1764 intel_configure();
1765 else if (bridge->driver == &intel_850_driver)
1766 intel_850_configure();
1767 else if (bridge->driver == &intel_845_driver)
1768 intel_845_configure();
1769 else if (bridge->driver == &intel_830mp_driver)
1770 intel_830mp_configure();
1771 else if (bridge->driver == &intel_915_driver)
1772 intel_i915_configure();
1773 else if (bridge->driver == &intel_830_driver)
1774 intel_i830_configure();
1775 else if (bridge->driver == &intel_810_driver)
1776 intel_i810_configure();
1777
1778 return 0;
1779 }
1780
1781 static struct pci_device_id agp_intel_pci_table[] = {
1782 #define ID(x) \
1783 { \
1784 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
1785 .class_mask = ~0, \
1786 .vendor = PCI_VENDOR_ID_INTEL, \
1787 .device = x, \
1788 .subvendor = PCI_ANY_ID, \
1789 .subdevice = PCI_ANY_ID, \
1790 }
1791 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
1792 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
1793 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
1794 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
1795 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
1796 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
1797 ID(PCI_DEVICE_ID_INTEL_82815_MC),
1798 ID(PCI_DEVICE_ID_INTEL_82820_HB),
1799 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
1800 ID(PCI_DEVICE_ID_INTEL_82830_HB),
1801 ID(PCI_DEVICE_ID_INTEL_82840_HB),
1802 ID(PCI_DEVICE_ID_INTEL_82845_HB),
1803 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
1804 ID(PCI_DEVICE_ID_INTEL_82850_HB),
1805 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
1806 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
1807 ID(PCI_DEVICE_ID_INTEL_82860_HB),
1808 ID(PCI_DEVICE_ID_INTEL_82865_HB),
1809 ID(PCI_DEVICE_ID_INTEL_82875_HB),
1810 ID(PCI_DEVICE_ID_INTEL_7505_0),
1811 ID(PCI_DEVICE_ID_INTEL_7205_0),
1812 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
1813 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
1814 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
1815 { }
1816 };
1817
1818 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
1819
1820 static struct pci_driver agp_intel_pci_driver = {
1821 .name = "agpgart-intel",
1822 .id_table = agp_intel_pci_table,
1823 .probe = agp_intel_probe,
1824 .remove = __devexit_p(agp_intel_remove),
1825 .resume = agp_intel_resume,
1826 };
1827
1828 static int __init agp_intel_init(void)
1829 {
1830 if (agp_off)
1831 return -EINVAL;
1832 return pci_register_driver(&agp_intel_pci_driver);
1833 }
1834
1835 static void __exit agp_intel_cleanup(void)
1836 {
1837 pci_unregister_driver(&agp_intel_pci_driver);
1838 }
1839
1840 module_init(agp_intel_init);
1841 module_exit(agp_intel_cleanup);
1842
1843 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
1844 MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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