2 * Intel GTT (Graphics Translation Table) routines
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
15 * /fairy-tale-mode off
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
26 #include "intel-agp.h"
27 #include <linux/intel-gtt.h>
28 #include <drm/intel-gtt.h>
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_DMAR).
34 * Only newer chipsets need to bother with this, of course.
37 #define USE_PCI_DMA_API 1
40 /* Max amount of stolen space, anything above will be returned to Linux */
41 int intel_max_stolen
= 32 * 1024 * 1024;
42 EXPORT_SYMBOL(intel_max_stolen
);
44 static const struct aper_size_info_fixed intel_i810_sizes
[] =
47 /* The 32M mode still requires a 64k gatt */
51 #define AGP_DCACHE_MEMORY 1
52 #define AGP_PHYS_MEMORY 2
53 #define INTEL_AGP_CACHED_MEMORY 3
55 static struct gatt_mask intel_i810_masks
[] =
57 {.mask
= I810_PTE_VALID
, .type
= 0},
58 {.mask
= (I810_PTE_VALID
| I810_PTE_LOCAL
), .type
= AGP_DCACHE_MEMORY
},
59 {.mask
= I810_PTE_VALID
, .type
= 0},
60 {.mask
= I810_PTE_VALID
| I830_PTE_SYSTEM_CACHED
,
61 .type
= INTEL_AGP_CACHED_MEMORY
}
64 #define INTEL_AGP_UNCACHED_MEMORY 0
65 #define INTEL_AGP_CACHED_MEMORY_LLC 1
66 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
67 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
68 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
70 static struct gatt_mask intel_gen6_masks
[] =
72 {.mask
= I810_PTE_VALID
| GEN6_PTE_UNCACHED
,
73 .type
= INTEL_AGP_UNCACHED_MEMORY
},
74 {.mask
= I810_PTE_VALID
| GEN6_PTE_LLC
,
75 .type
= INTEL_AGP_CACHED_MEMORY_LLC
},
76 {.mask
= I810_PTE_VALID
| GEN6_PTE_LLC
| GEN6_PTE_GFDT
,
77 .type
= INTEL_AGP_CACHED_MEMORY_LLC_GFDT
},
78 {.mask
= I810_PTE_VALID
| GEN6_PTE_LLC_MLC
,
79 .type
= INTEL_AGP_CACHED_MEMORY_LLC_MLC
},
80 {.mask
= I810_PTE_VALID
| GEN6_PTE_LLC_MLC
| GEN6_PTE_GFDT
,
81 .type
= INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT
},
84 static struct _intel_private
{
85 struct intel_gtt base
;
86 struct pci_dev
*pcidev
; /* device one */
87 struct pci_dev
*bridge_dev
;
88 u8 __iomem
*registers
;
89 u32 __iomem
*gtt
; /* I915G */
90 int num_dcache_entries
;
92 void __iomem
*i9xx_flush_page
;
93 void *i8xx_flush_page
;
95 struct page
*i8xx_page
;
96 struct resource ifp_resource
;
100 #ifdef USE_PCI_DMA_API
101 static int intel_agp_map_page(struct page
*page
, dma_addr_t
*ret
)
103 *ret
= pci_map_page(intel_private
.pcidev
, page
, 0,
104 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
105 if (pci_dma_mapping_error(intel_private
.pcidev
, *ret
))
110 static void intel_agp_unmap_page(struct page
*page
, dma_addr_t dma
)
112 pci_unmap_page(intel_private
.pcidev
, dma
,
113 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
116 static void intel_agp_free_sglist(struct agp_memory
*mem
)
120 st
.sgl
= mem
->sg_list
;
121 st
.orig_nents
= st
.nents
= mem
->page_count
;
129 static int intel_agp_map_memory(struct agp_memory
*mem
)
132 struct scatterlist
*sg
;
135 DBG("try mapping %lu pages\n", (unsigned long)mem
->page_count
);
137 if (sg_alloc_table(&st
, mem
->page_count
, GFP_KERNEL
))
140 mem
->sg_list
= sg
= st
.sgl
;
142 for (i
= 0 ; i
< mem
->page_count
; i
++, sg
= sg_next(sg
))
143 sg_set_page(sg
, mem
->pages
[i
], PAGE_SIZE
, 0);
145 mem
->num_sg
= pci_map_sg(intel_private
.pcidev
, mem
->sg_list
,
146 mem
->page_count
, PCI_DMA_BIDIRECTIONAL
);
147 if (unlikely(!mem
->num_sg
))
157 static void intel_agp_unmap_memory(struct agp_memory
*mem
)
159 DBG("try unmapping %lu pages\n", (unsigned long)mem
->page_count
);
161 pci_unmap_sg(intel_private
.pcidev
, mem
->sg_list
,
162 mem
->page_count
, PCI_DMA_BIDIRECTIONAL
);
163 intel_agp_free_sglist(mem
);
166 static void intel_agp_insert_sg_entries(struct agp_memory
*mem
,
167 off_t pg_start
, int mask_type
)
169 struct scatterlist
*sg
;
174 WARN_ON(!mem
->num_sg
);
176 if (mem
->num_sg
== mem
->page_count
) {
177 for_each_sg(mem
->sg_list
, sg
, mem
->page_count
, i
) {
178 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
179 sg_dma_address(sg
), mask_type
),
180 intel_private
.gtt
+j
);
184 /* sg may merge pages, but we have to separate
185 * per-page addr for GTT */
188 for_each_sg(mem
->sg_list
, sg
, mem
->num_sg
, i
) {
189 len
= sg_dma_len(sg
) / PAGE_SIZE
;
190 for (m
= 0; m
< len
; m
++) {
191 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
192 sg_dma_address(sg
) + m
* PAGE_SIZE
,
194 intel_private
.gtt
+j
);
199 readl(intel_private
.gtt
+j
-1);
204 static void intel_agp_insert_sg_entries(struct agp_memory
*mem
,
205 off_t pg_start
, int mask_type
)
209 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
210 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
211 page_to_phys(mem
->pages
[i
]), mask_type
),
212 intel_private
.gtt
+j
);
215 readl(intel_private
.gtt
+j
-1);
220 static int intel_i810_fetch_size(void)
223 struct aper_size_info_fixed
*values
;
225 pci_read_config_dword(intel_private
.bridge_dev
,
226 I810_SMRAM_MISCC
, &smram_miscc
);
227 values
= A_SIZE_FIX(agp_bridge
->driver
->aperture_sizes
);
229 if ((smram_miscc
& I810_GMS
) == I810_GMS_DISABLE
) {
230 dev_warn(&intel_private
.bridge_dev
->dev
, "i810 is disabled\n");
233 if ((smram_miscc
& I810_GFX_MEM_WIN_SIZE
) == I810_GFX_MEM_WIN_32M
) {
234 agp_bridge
->current_size
= (void *) (values
+ 1);
235 agp_bridge
->aperture_size_idx
= 1;
236 return values
[1].size
;
238 agp_bridge
->current_size
= (void *) (values
);
239 agp_bridge
->aperture_size_idx
= 0;
240 return values
[0].size
;
246 static int intel_i810_configure(void)
248 struct aper_size_info_fixed
*current_size
;
252 current_size
= A_SIZE_FIX(agp_bridge
->current_size
);
254 if (!intel_private
.registers
) {
255 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, &temp
);
258 intel_private
.registers
= ioremap(temp
, 128 * 4096);
259 if (!intel_private
.registers
) {
260 dev_err(&intel_private
.pcidev
->dev
,
261 "can't remap memory\n");
266 if ((readl(intel_private
.registers
+I810_DRAM_CTL
)
267 & I810_DRAM_ROW_0
) == I810_DRAM_ROW_0_SDRAM
) {
268 /* This will need to be dynamically assigned */
269 dev_info(&intel_private
.pcidev
->dev
,
270 "detected 4MB dedicated video ram\n");
271 intel_private
.num_dcache_entries
= 1024;
273 pci_read_config_dword(intel_private
.pcidev
, I810_GMADDR
, &temp
);
274 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
275 writel(agp_bridge
->gatt_bus_addr
| I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
276 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
278 if (agp_bridge
->driver
->needs_scratch_page
) {
279 for (i
= 0; i
< current_size
->num_entries
; i
++) {
280 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
282 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4)); /* PCI posting. */
284 global_cache_flush();
288 static void intel_i810_cleanup(void)
290 writel(0, intel_private
.registers
+I810_PGETBL_CTL
);
291 readl(intel_private
.registers
); /* PCI Posting. */
292 iounmap(intel_private
.registers
);
295 static void intel_i810_agp_enable(struct agp_bridge_data
*bridge
, u32 mode
)
300 /* Exists to support ARGB cursors */
301 static struct page
*i8xx_alloc_pages(void)
305 page
= alloc_pages(GFP_KERNEL
| GFP_DMA32
, 2);
309 if (set_pages_uc(page
, 4) < 0) {
310 set_pages_wb(page
, 4);
311 __free_pages(page
, 2);
315 atomic_inc(&agp_bridge
->current_memory_agp
);
319 static void i8xx_destroy_pages(struct page
*page
)
324 set_pages_wb(page
, 4);
326 __free_pages(page
, 2);
327 atomic_dec(&agp_bridge
->current_memory_agp
);
330 static int intel_i830_type_to_mask_type(struct agp_bridge_data
*bridge
,
333 if (type
< AGP_USER_TYPES
)
335 else if (type
== AGP_USER_CACHED_MEMORY
)
336 return INTEL_AGP_CACHED_MEMORY
;
341 static int intel_gen6_type_to_mask_type(struct agp_bridge_data
*bridge
,
344 unsigned int type_mask
= type
& ~AGP_USER_CACHED_MEMORY_GFDT
;
345 unsigned int gfdt
= type
& AGP_USER_CACHED_MEMORY_GFDT
;
347 if (type_mask
== AGP_USER_UNCACHED_MEMORY
)
348 return INTEL_AGP_UNCACHED_MEMORY
;
349 else if (type_mask
== AGP_USER_CACHED_MEMORY_LLC_MLC
)
350 return gfdt
? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT
:
351 INTEL_AGP_CACHED_MEMORY_LLC_MLC
;
352 else /* set 'normal'/'cached' to LLC by default */
353 return gfdt
? INTEL_AGP_CACHED_MEMORY_LLC_GFDT
:
354 INTEL_AGP_CACHED_MEMORY_LLC
;
358 static int intel_i810_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
361 int i
, j
, num_entries
;
366 if (mem
->page_count
== 0)
369 temp
= agp_bridge
->current_size
;
370 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
372 if ((pg_start
+ mem
->page_count
) > num_entries
)
376 for (j
= pg_start
; j
< (pg_start
+ mem
->page_count
); j
++) {
377 if (!PGE_EMPTY(agp_bridge
, readl(agp_bridge
->gatt_table
+j
))) {
383 if (type
!= mem
->type
)
386 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
389 case AGP_DCACHE_MEMORY
:
390 if (!mem
->is_flushed
)
391 global_cache_flush();
392 for (i
= pg_start
; i
< (pg_start
+ mem
->page_count
); i
++) {
393 writel((i
*4096)|I810_PTE_LOCAL
|I810_PTE_VALID
,
394 intel_private
.registers
+I810_PTE_BASE
+(i
*4));
396 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
398 case AGP_PHYS_MEMORY
:
399 case AGP_NORMAL_MEMORY
:
400 if (!mem
->is_flushed
)
401 global_cache_flush();
402 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
403 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
404 page_to_phys(mem
->pages
[i
]), mask_type
),
405 intel_private
.registers
+I810_PTE_BASE
+(j
*4));
407 readl(intel_private
.registers
+I810_PTE_BASE
+((j
-1)*4));
416 mem
->is_flushed
= true;
420 static int intel_i810_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
425 if (mem
->page_count
== 0)
428 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++) {
429 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
431 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
437 * The i810/i830 requires a physical address to program its mouse
438 * pointer into hardware.
439 * However the Xserver still writes to it through the agp aperture.
441 static struct agp_memory
*alloc_agpphysmem_i8xx(size_t pg_count
, int type
)
443 struct agp_memory
*new;
447 case 1: page
= agp_bridge
->driver
->agp_alloc_page(agp_bridge
);
450 /* kludge to get 4 physical pages for ARGB cursor */
451 page
= i8xx_alloc_pages();
460 new = agp_create_memory(pg_count
);
464 new->pages
[0] = page
;
466 /* kludge to get 4 physical pages for ARGB cursor */
467 new->pages
[1] = new->pages
[0] + 1;
468 new->pages
[2] = new->pages
[1] + 1;
469 new->pages
[3] = new->pages
[2] + 1;
471 new->page_count
= pg_count
;
472 new->num_scratch_pages
= pg_count
;
473 new->type
= AGP_PHYS_MEMORY
;
474 new->physical
= page_to_phys(new->pages
[0]);
478 static struct agp_memory
*intel_i810_alloc_by_type(size_t pg_count
, int type
)
480 struct agp_memory
*new;
482 if (type
== AGP_DCACHE_MEMORY
) {
483 if (pg_count
!= intel_private
.num_dcache_entries
)
486 new = agp_create_memory(1);
490 new->type
= AGP_DCACHE_MEMORY
;
491 new->page_count
= pg_count
;
492 new->num_scratch_pages
= 0;
493 agp_free_page_array(new);
496 if (type
== AGP_PHYS_MEMORY
)
497 return alloc_agpphysmem_i8xx(pg_count
, type
);
501 static void intel_i810_free_by_type(struct agp_memory
*curr
)
503 agp_free_key(curr
->key
);
504 if (curr
->type
== AGP_PHYS_MEMORY
) {
505 if (curr
->page_count
== 4)
506 i8xx_destroy_pages(curr
->pages
[0]);
508 agp_bridge
->driver
->agp_destroy_page(curr
->pages
[0],
509 AGP_PAGE_DESTROY_UNMAP
);
510 agp_bridge
->driver
->agp_destroy_page(curr
->pages
[0],
511 AGP_PAGE_DESTROY_FREE
);
513 agp_free_page_array(curr
);
518 static unsigned long intel_i810_mask_memory(struct agp_bridge_data
*bridge
,
519 dma_addr_t addr
, int type
)
521 /* Type checking must be done elsewhere */
522 return addr
| bridge
->driver
->masks
[type
].mask
;
525 static struct aper_size_info_fixed intel_i830_sizes
[] =
528 /* The 64M mode still requires a 128k gatt */
534 static unsigned int intel_gtt_stolen_entries(void)
539 static const int ddt
[4] = { 0, 16, 32, 64 };
540 unsigned int overhead_entries
, stolen_entries
;
541 unsigned int stolen_size
= 0;
543 pci_read_config_word(intel_private
.bridge_dev
,
544 I830_GMCH_CTRL
, &gmch_ctrl
);
546 if (IS_G4X
|| IS_PINEVIEW
)
547 overhead_entries
= 0;
549 overhead_entries
= intel_private
.base
.gtt_mappable_entries
552 overhead_entries
+= 1; /* BIOS popup */
554 if (intel_private
.bridge_dev
->device
== PCI_DEVICE_ID_INTEL_82830_HB
||
555 intel_private
.bridge_dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
) {
556 switch (gmch_ctrl
& I830_GMCH_GMS_MASK
) {
557 case I830_GMCH_GMS_STOLEN_512
:
558 stolen_size
= KB(512);
560 case I830_GMCH_GMS_STOLEN_1024
:
563 case I830_GMCH_GMS_STOLEN_8192
:
566 case I830_GMCH_GMS_LOCAL
:
567 rdct
= readb(intel_private
.registers
+I830_RDRAM_CHANNEL_TYPE
);
568 stolen_size
= (I830_RDRAM_ND(rdct
) + 1) *
569 MB(ddt
[I830_RDRAM_DDT(rdct
)]);
578 * SandyBridge has new memory control reg at 0x50.w
581 pci_read_config_word(intel_private
.pcidev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
582 switch (snb_gmch_ctl
& SNB_GMCH_GMS_STOLEN_MASK
) {
583 case SNB_GMCH_GMS_STOLEN_32M
:
584 stolen_size
= MB(32);
586 case SNB_GMCH_GMS_STOLEN_64M
:
587 stolen_size
= MB(64);
589 case SNB_GMCH_GMS_STOLEN_96M
:
590 stolen_size
= MB(96);
592 case SNB_GMCH_GMS_STOLEN_128M
:
593 stolen_size
= MB(128);
595 case SNB_GMCH_GMS_STOLEN_160M
:
596 stolen_size
= MB(160);
598 case SNB_GMCH_GMS_STOLEN_192M
:
599 stolen_size
= MB(192);
601 case SNB_GMCH_GMS_STOLEN_224M
:
602 stolen_size
= MB(224);
604 case SNB_GMCH_GMS_STOLEN_256M
:
605 stolen_size
= MB(256);
607 case SNB_GMCH_GMS_STOLEN_288M
:
608 stolen_size
= MB(288);
610 case SNB_GMCH_GMS_STOLEN_320M
:
611 stolen_size
= MB(320);
613 case SNB_GMCH_GMS_STOLEN_352M
:
614 stolen_size
= MB(352);
616 case SNB_GMCH_GMS_STOLEN_384M
:
617 stolen_size
= MB(384);
619 case SNB_GMCH_GMS_STOLEN_416M
:
620 stolen_size
= MB(416);
622 case SNB_GMCH_GMS_STOLEN_448M
:
623 stolen_size
= MB(448);
625 case SNB_GMCH_GMS_STOLEN_480M
:
626 stolen_size
= MB(480);
628 case SNB_GMCH_GMS_STOLEN_512M
:
629 stolen_size
= MB(512);
633 switch (gmch_ctrl
& I855_GMCH_GMS_MASK
) {
634 case I855_GMCH_GMS_STOLEN_1M
:
637 case I855_GMCH_GMS_STOLEN_4M
:
640 case I855_GMCH_GMS_STOLEN_8M
:
643 case I855_GMCH_GMS_STOLEN_16M
:
644 stolen_size
= MB(16);
646 case I855_GMCH_GMS_STOLEN_32M
:
647 stolen_size
= MB(32);
649 case I915_GMCH_GMS_STOLEN_48M
:
650 stolen_size
= MB(48);
652 case I915_GMCH_GMS_STOLEN_64M
:
653 stolen_size
= MB(64);
655 case G33_GMCH_GMS_STOLEN_128M
:
656 stolen_size
= MB(128);
658 case G33_GMCH_GMS_STOLEN_256M
:
659 stolen_size
= MB(256);
661 case INTEL_GMCH_GMS_STOLEN_96M
:
662 stolen_size
= MB(96);
664 case INTEL_GMCH_GMS_STOLEN_160M
:
665 stolen_size
= MB(160);
667 case INTEL_GMCH_GMS_STOLEN_224M
:
668 stolen_size
= MB(224);
670 case INTEL_GMCH_GMS_STOLEN_352M
:
671 stolen_size
= MB(352);
679 if (!local
&& stolen_size
> intel_max_stolen
) {
680 dev_info(&intel_private
.bridge_dev
->dev
,
681 "detected %dK stolen memory, trimming to %dK\n",
682 stolen_size
/ KB(1), intel_max_stolen
/ KB(1));
683 stolen_size
= intel_max_stolen
;
684 } else if (stolen_size
> 0) {
685 dev_info(&intel_private
.bridge_dev
->dev
, "detected %dK %s memory\n",
686 stolen_size
/ KB(1), local
? "local" : "stolen");
688 dev_info(&intel_private
.bridge_dev
->dev
,
689 "no pre-allocated video memory detected\n");
693 stolen_entries
= stolen_size
/KB(4) - overhead_entries
;
695 return stolen_entries
;
698 #if 0 /* extracted code in bad shape, needs some cleaning before use */
699 static unsigned int intel_gtt_total_entries(void)
706 pgetbl_ctl
= readl(intel_private
.registers
+I810_PGETBL_CTL
);
708 /* The 965 has a field telling us the size of the GTT,
709 * which may be larger than what is necessary to map the
712 switch (pgetbl_ctl
& I965_PGETBL_SIZE_MASK
) {
713 case I965_PGETBL_SIZE_128KB
:
716 case I965_PGETBL_SIZE_256KB
:
719 case I965_PGETBL_SIZE_512KB
:
722 case I965_PGETBL_SIZE_1MB
:
725 case I965_PGETBL_SIZE_2MB
:
728 case I965_PGETBL_SIZE_1_5MB
:
732 dev_info(&intel_private
.pcidev
->dev
,
733 "unknown page table size, assuming 512KB\n");
736 size
+= 4; /* add in BIOS popup space */
737 } else if (IS_G33
&& !IS_PINEVIEW
) {
738 /* G33's GTT size defined in gmch_ctrl */
739 switch (gmch_ctrl
& G33_PGETBL_SIZE_MASK
) {
740 case G33_PGETBL_SIZE_1M
:
743 case G33_PGETBL_SIZE_2M
:
747 dev_info(&intel_private
.bridge_dev
->dev
,
748 "unknown page table size 0x%x, assuming 512KB\n",
749 (gmch_ctrl
& G33_PGETBL_SIZE_MASK
));
753 } else if (IS_G4X
|| IS_PINEVIEW
) {
754 /* On 4 series hardware, GTT stolen is separate from graphics
755 * stolen, ignore it in stolen gtt entries counting. However,
756 * 4KB of the stolen memory doesn't get mapped to the GTT.
760 /* On previous hardware, the GTT size was just what was
761 * required to map the aperture.
763 size
= agp_bridge
->driver
->fetch_size() + 4;
770 static unsigned int intel_gtt_mappable_entries(void)
772 unsigned int aperture_size
;
775 aperture_size
= 1024 * 1024;
777 pci_read_config_word(intel_private
.bridge_dev
,
778 I830_GMCH_CTRL
, &gmch_ctrl
);
780 switch (intel_private
.pcidev
->device
) {
781 case PCI_DEVICE_ID_INTEL_82830_CGC
:
782 case PCI_DEVICE_ID_INTEL_82845G_IG
:
783 case PCI_DEVICE_ID_INTEL_82855GM_IG
:
784 case PCI_DEVICE_ID_INTEL_82865_IG
:
785 if ((gmch_ctrl
& I830_GMCH_MEM_MASK
) == I830_GMCH_MEM_64M
)
788 aperture_size
*= 128;
791 /* 9xx supports large sizes, just look at the length */
792 aperture_size
= pci_resource_len(intel_private
.pcidev
, 2);
796 return aperture_size
>> PAGE_SHIFT
;
799 static int intel_gtt_init(void)
801 /* we have to call this as early as possible after the MMIO base address is known */
802 intel_private
.base
.gtt_stolen_entries
= intel_gtt_stolen_entries();
803 if (intel_private
.base
.gtt_stolen_entries
== 0) {
804 iounmap(intel_private
.registers
);
811 static int intel_fake_agp_fetch_size(void)
813 unsigned int aper_size
;
815 int num_sizes
= ARRAY_SIZE(intel_i830_sizes
);
817 aper_size
= (intel_private
.base
.gtt_mappable_entries
<< PAGE_SHIFT
)
820 for (i
= 0; i
< num_sizes
; i
++) {
821 if (aper_size
== intel_i830_sizes
[i
].size
) {
822 agp_bridge
->current_size
= intel_i830_sizes
+ i
;
830 static void intel_i830_fini_flush(void)
832 kunmap(intel_private
.i8xx_page
);
833 intel_private
.i8xx_flush_page
= NULL
;
834 unmap_page_from_agp(intel_private
.i8xx_page
);
836 __free_page(intel_private
.i8xx_page
);
837 intel_private
.i8xx_page
= NULL
;
840 static void intel_i830_setup_flush(void)
842 /* return if we've already set the flush mechanism up */
843 if (intel_private
.i8xx_page
)
846 intel_private
.i8xx_page
= alloc_page(GFP_KERNEL
| __GFP_ZERO
| GFP_DMA32
);
847 if (!intel_private
.i8xx_page
)
850 intel_private
.i8xx_flush_page
= kmap(intel_private
.i8xx_page
);
851 if (!intel_private
.i8xx_flush_page
)
852 intel_i830_fini_flush();
855 /* The chipset_flush interface needs to get data that has already been
856 * flushed out of the CPU all the way out to main memory, because the GPU
857 * doesn't snoop those buffers.
859 * The 8xx series doesn't have the same lovely interface for flushing the
860 * chipset write buffers that the later chips do. According to the 865
861 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
862 * that buffer out, we just fill 1KB and clflush it out, on the assumption
863 * that it'll push whatever was in there out. It appears to work.
865 static void intel_i830_chipset_flush(struct agp_bridge_data
*bridge
)
867 unsigned int *pg
= intel_private
.i8xx_flush_page
;
872 clflush_cache_range(pg
, 1024);
873 else if (wbinvd_on_all_cpus() != 0)
874 printk(KERN_ERR
"Timed out waiting for cache flush.\n");
877 /* The intel i830 automatically initializes the agp aperture during POST.
878 * Use the memory already set aside for in the GTT.
880 static int intel_i830_create_gatt_table(struct agp_bridge_data
*bridge
)
883 struct aper_size_info_fixed
*size
;
887 size
= agp_bridge
->current_size
;
888 page_order
= size
->page_order
;
889 num_entries
= size
->num_entries
;
890 agp_bridge
->gatt_table_real
= NULL
;
892 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, &temp
);
895 intel_private
.registers
= ioremap(temp
, 128 * 4096);
896 if (!intel_private
.registers
)
899 temp
= readl(intel_private
.registers
+I810_PGETBL_CTL
) & 0xfffff000;
900 global_cache_flush(); /* FIXME: ?? */
902 ret
= intel_gtt_init();
906 agp_bridge
->gatt_table
= NULL
;
908 agp_bridge
->gatt_bus_addr
= temp
;
913 /* Return the gatt table to a sane state. Use the top of stolen
914 * memory for the GTT.
916 static int intel_i830_free_gatt_table(struct agp_bridge_data
*bridge
)
921 static int intel_i830_configure(void)
923 struct aper_size_info_fixed
*current_size
;
928 current_size
= A_SIZE_FIX(agp_bridge
->current_size
);
930 pci_read_config_dword(intel_private
.pcidev
, I810_GMADDR
, &temp
);
931 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
933 pci_read_config_word(intel_private
.bridge_dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
934 gmch_ctrl
|= I830_GMCH_ENABLED
;
935 pci_write_config_word(intel_private
.bridge_dev
, I830_GMCH_CTRL
, gmch_ctrl
);
937 writel(agp_bridge
->gatt_bus_addr
|I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
938 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
940 if (agp_bridge
->driver
->needs_scratch_page
) {
941 for (i
= intel_private
.base
.gtt_stolen_entries
; i
< current_size
->num_entries
; i
++) {
942 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
944 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4)); /* PCI Posting. */
947 global_cache_flush();
949 intel_i830_setup_flush();
953 static void intel_i830_cleanup(void)
955 iounmap(intel_private
.registers
);
958 static int intel_i830_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
961 int i
, j
, num_entries
;
966 if (mem
->page_count
== 0)
969 temp
= agp_bridge
->current_size
;
970 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
972 if (pg_start
< intel_private
.base
.gtt_stolen_entries
) {
973 dev_printk(KERN_DEBUG
, &intel_private
.pcidev
->dev
,
974 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
975 pg_start
, intel_private
.base
.gtt_stolen_entries
);
977 dev_info(&intel_private
.pcidev
->dev
,
978 "trying to insert into local/stolen memory\n");
982 if ((pg_start
+ mem
->page_count
) > num_entries
)
985 /* The i830 can't check the GTT for entries since its read only,
986 * depend on the caller to make the correct offset decisions.
989 if (type
!= mem
->type
)
992 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
994 if (mask_type
!= 0 && mask_type
!= AGP_PHYS_MEMORY
&&
995 mask_type
!= INTEL_AGP_CACHED_MEMORY
)
998 if (!mem
->is_flushed
)
999 global_cache_flush();
1001 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
1002 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
1003 page_to_phys(mem
->pages
[i
]), mask_type
),
1004 intel_private
.registers
+I810_PTE_BASE
+(j
*4));
1006 readl(intel_private
.registers
+I810_PTE_BASE
+((j
-1)*4));
1011 mem
->is_flushed
= true;
1015 static int intel_i830_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
1020 if (mem
->page_count
== 0)
1023 if (pg_start
< intel_private
.base
.gtt_stolen_entries
) {
1024 dev_info(&intel_private
.pcidev
->dev
,
1025 "trying to disable local/stolen memory\n");
1029 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++) {
1030 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
1032 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
1037 static struct agp_memory
*intel_i830_alloc_by_type(size_t pg_count
, int type
)
1039 if (type
== AGP_PHYS_MEMORY
)
1040 return alloc_agpphysmem_i8xx(pg_count
, type
);
1041 /* always return NULL for other allocation types for now */
1045 static int intel_alloc_chipset_flush_resource(void)
1048 ret
= pci_bus_alloc_resource(intel_private
.bridge_dev
->bus
, &intel_private
.ifp_resource
, PAGE_SIZE
,
1049 PAGE_SIZE
, PCIBIOS_MIN_MEM
, 0,
1050 pcibios_align_resource
, intel_private
.bridge_dev
);
1055 static void intel_i915_setup_chipset_flush(void)
1060 pci_read_config_dword(intel_private
.bridge_dev
, I915_IFPADDR
, &temp
);
1061 if (!(temp
& 0x1)) {
1062 intel_alloc_chipset_flush_resource();
1063 intel_private
.resource_valid
= 1;
1064 pci_write_config_dword(intel_private
.bridge_dev
, I915_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
1068 intel_private
.resource_valid
= 1;
1069 intel_private
.ifp_resource
.start
= temp
;
1070 intel_private
.ifp_resource
.end
= temp
+ PAGE_SIZE
;
1071 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
1072 /* some BIOSes reserve this area in a pnp some don't */
1074 intel_private
.resource_valid
= 0;
1078 static void intel_i965_g33_setup_chipset_flush(void)
1080 u32 temp_hi
, temp_lo
;
1083 pci_read_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
+ 4, &temp_hi
);
1084 pci_read_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
, &temp_lo
);
1086 if (!(temp_lo
& 0x1)) {
1088 intel_alloc_chipset_flush_resource();
1090 intel_private
.resource_valid
= 1;
1091 pci_write_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
+ 4,
1092 upper_32_bits(intel_private
.ifp_resource
.start
));
1093 pci_write_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
1098 l64
= ((u64
)temp_hi
<< 32) | temp_lo
;
1100 intel_private
.resource_valid
= 1;
1101 intel_private
.ifp_resource
.start
= l64
;
1102 intel_private
.ifp_resource
.end
= l64
+ PAGE_SIZE
;
1103 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
1104 /* some BIOSes reserve this area in a pnp some don't */
1106 intel_private
.resource_valid
= 0;
1110 static void intel_i9xx_setup_flush(void)
1112 /* return if already configured */
1113 if (intel_private
.ifp_resource
.start
)
1119 /* setup a resource for this object */
1120 intel_private
.ifp_resource
.name
= "Intel Flush Page";
1121 intel_private
.ifp_resource
.flags
= IORESOURCE_MEM
;
1123 /* Setup chipset flush for 915 */
1124 if (IS_I965
|| IS_G33
|| IS_G4X
) {
1125 intel_i965_g33_setup_chipset_flush();
1127 intel_i915_setup_chipset_flush();
1130 if (intel_private
.ifp_resource
.start
)
1131 intel_private
.i9xx_flush_page
= ioremap_nocache(intel_private
.ifp_resource
.start
, PAGE_SIZE
);
1132 if (!intel_private
.i9xx_flush_page
)
1133 dev_err(&intel_private
.pcidev
->dev
,
1134 "can't ioremap flush page - no chipset flushing\n");
1137 static int intel_i9xx_configure(void)
1139 struct aper_size_info_fixed
*current_size
;
1144 current_size
= A_SIZE_FIX(agp_bridge
->current_size
);
1146 pci_read_config_dword(intel_private
.pcidev
, I915_GMADDR
, &temp
);
1148 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1150 pci_read_config_word(intel_private
.bridge_dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
1151 gmch_ctrl
|= I830_GMCH_ENABLED
;
1152 pci_write_config_word(intel_private
.bridge_dev
, I830_GMCH_CTRL
, gmch_ctrl
);
1154 writel(agp_bridge
->gatt_bus_addr
|I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
1155 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
1157 if (agp_bridge
->driver
->needs_scratch_page
) {
1158 for (i
= intel_private
.base
.gtt_stolen_entries
; i
<
1159 intel_private
.base
.gtt_total_entries
; i
++) {
1160 writel(agp_bridge
->scratch_page
, intel_private
.gtt
+i
);
1162 readl(intel_private
.gtt
+i
-1); /* PCI Posting. */
1165 global_cache_flush();
1167 intel_i9xx_setup_flush();
1172 static void intel_i915_cleanup(void)
1174 if (intel_private
.i9xx_flush_page
)
1175 iounmap(intel_private
.i9xx_flush_page
);
1176 if (intel_private
.resource_valid
)
1177 release_resource(&intel_private
.ifp_resource
);
1178 intel_private
.ifp_resource
.start
= 0;
1179 intel_private
.resource_valid
= 0;
1180 iounmap(intel_private
.gtt
);
1181 iounmap(intel_private
.registers
);
1184 static void intel_i915_chipset_flush(struct agp_bridge_data
*bridge
)
1186 if (intel_private
.i9xx_flush_page
)
1187 writel(1, intel_private
.i9xx_flush_page
);
1190 static int intel_i915_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
1198 if (mem
->page_count
== 0)
1201 temp
= agp_bridge
->current_size
;
1202 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
1204 if (pg_start
< intel_private
.base
.gtt_stolen_entries
) {
1205 dev_printk(KERN_DEBUG
, &intel_private
.pcidev
->dev
,
1206 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1207 pg_start
, intel_private
.base
.gtt_stolen_entries
);
1209 dev_info(&intel_private
.pcidev
->dev
,
1210 "trying to insert into local/stolen memory\n");
1214 if ((pg_start
+ mem
->page_count
) > num_entries
)
1217 /* The i915 can't check the GTT for entries since it's read only;
1218 * depend on the caller to make the correct offset decisions.
1221 if (type
!= mem
->type
)
1224 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
1226 if (!IS_SNB
&& mask_type
!= 0 && mask_type
!= AGP_PHYS_MEMORY
&&
1227 mask_type
!= INTEL_AGP_CACHED_MEMORY
)
1230 if (!mem
->is_flushed
)
1231 global_cache_flush();
1233 intel_agp_insert_sg_entries(mem
, pg_start
, mask_type
);
1238 mem
->is_flushed
= true;
1242 static int intel_i915_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
1247 if (mem
->page_count
== 0)
1250 if (pg_start
< intel_private
.base
.gtt_stolen_entries
) {
1251 dev_info(&intel_private
.pcidev
->dev
,
1252 "trying to disable local/stolen memory\n");
1256 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++)
1257 writel(agp_bridge
->scratch_page
, intel_private
.gtt
+i
);
1259 readl(intel_private
.gtt
+i
-1);
1264 /* Return the aperture size by just checking the resource length. The effect
1265 * described in the spec of the MSAC registers is just changing of the
1268 static int intel_i915_get_gtt_size(void)
1275 /* G33's GTT size defined in gmch_ctrl */
1276 pci_read_config_word(intel_private
.bridge_dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
1277 switch (gmch_ctrl
& I830_GMCH_GMS_MASK
) {
1278 case I830_GMCH_GMS_STOLEN_512
:
1281 case I830_GMCH_GMS_STOLEN_1024
:
1284 case I830_GMCH_GMS_STOLEN_8192
:
1288 dev_info(&intel_private
.bridge_dev
->dev
,
1289 "unknown page table size 0x%x, assuming 512KB\n",
1290 (gmch_ctrl
& I830_GMCH_GMS_MASK
));
1294 /* On previous hardware, the GTT size was just what was
1295 * required to map the aperture.
1297 size
= agp_bridge
->driver
->fetch_size();
1303 /* The intel i915 automatically initializes the agp aperture during POST.
1304 * Use the memory already set aside for in the GTT.
1306 static int intel_i915_create_gatt_table(struct agp_bridge_data
*bridge
)
1308 int page_order
, ret
;
1309 struct aper_size_info_fixed
*size
;
1314 size
= agp_bridge
->current_size
;
1315 page_order
= size
->page_order
;
1316 num_entries
= size
->num_entries
;
1317 agp_bridge
->gatt_table_real
= NULL
;
1319 pci_read_config_dword(intel_private
.pcidev
, I915_MMADDR
, &temp
);
1320 pci_read_config_dword(intel_private
.pcidev
, I915_PTEADDR
, &temp2
);
1322 gtt_map_size
= intel_i915_get_gtt_size();
1324 intel_private
.gtt
= ioremap(temp2
, gtt_map_size
);
1325 if (!intel_private
.gtt
)
1328 intel_private
.base
.gtt_total_entries
= gtt_map_size
/ 4;
1332 intel_private
.registers
= ioremap(temp
, 128 * 4096);
1333 if (!intel_private
.registers
) {
1334 iounmap(intel_private
.gtt
);
1338 temp
= readl(intel_private
.registers
+I810_PGETBL_CTL
) & 0xfffff000;
1339 global_cache_flush(); /* FIXME: ? */
1341 ret
= intel_gtt_init();
1343 iounmap(intel_private
.gtt
);
1347 agp_bridge
->gatt_table
= NULL
;
1349 agp_bridge
->gatt_bus_addr
= temp
;
1355 * The i965 supports 36-bit physical addresses, but to keep
1356 * the format of the GTT the same, the bits that don't fit
1357 * in a 32-bit word are shifted down to bits 4..7.
1359 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1360 * is always zero on 32-bit architectures, so no need to make
1363 static unsigned long intel_i965_mask_memory(struct agp_bridge_data
*bridge
,
1364 dma_addr_t addr
, int type
)
1366 /* Shift high bits down */
1367 addr
|= (addr
>> 28) & 0xf0;
1369 /* Type checking must be done elsewhere */
1370 return addr
| bridge
->driver
->masks
[type
].mask
;
1373 static unsigned long intel_gen6_mask_memory(struct agp_bridge_data
*bridge
,
1374 dma_addr_t addr
, int type
)
1376 /* gen6 has bit11-4 for physical addr bit39-32 */
1377 addr
|= (addr
>> 28) & 0xff0;
1379 /* Type checking must be done elsewhere */
1380 return addr
| bridge
->driver
->masks
[type
].mask
;
1383 static void intel_i965_get_gtt_range(int *gtt_offset
, int *gtt_size
)
1387 switch (intel_private
.bridge_dev
->device
) {
1388 case PCI_DEVICE_ID_INTEL_GM45_HB
:
1389 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB
:
1390 case PCI_DEVICE_ID_INTEL_Q45_HB
:
1391 case PCI_DEVICE_ID_INTEL_G45_HB
:
1392 case PCI_DEVICE_ID_INTEL_G41_HB
:
1393 case PCI_DEVICE_ID_INTEL_B43_HB
:
1394 case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB
:
1395 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB
:
1396 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB
:
1397 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB
:
1398 *gtt_offset
= *gtt_size
= MB(2);
1400 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB
:
1401 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB
:
1402 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB
:
1403 *gtt_offset
= MB(2);
1405 pci_read_config_word(intel_private
.pcidev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
1406 switch (snb_gmch_ctl
& SNB_GTT_SIZE_MASK
) {
1408 case SNB_GTT_SIZE_0M
:
1409 printk(KERN_ERR
"Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl
);
1412 case SNB_GTT_SIZE_1M
:
1415 case SNB_GTT_SIZE_2M
:
1421 *gtt_offset
= *gtt_size
= KB(512);
1425 /* The intel i965 automatically initializes the agp aperture during POST.
1426 * Use the memory already set aside for in the GTT.
1428 static int intel_i965_create_gatt_table(struct agp_bridge_data
*bridge
)
1430 int page_order
, ret
;
1431 struct aper_size_info_fixed
*size
;
1434 int gtt_offset
, gtt_size
;
1436 size
= agp_bridge
->current_size
;
1437 page_order
= size
->page_order
;
1438 num_entries
= size
->num_entries
;
1439 agp_bridge
->gatt_table_real
= NULL
;
1441 pci_read_config_dword(intel_private
.pcidev
, I915_MMADDR
, &temp
);
1445 intel_i965_get_gtt_range(>t_offset
, >t_size
);
1447 intel_private
.gtt
= ioremap((temp
+ gtt_offset
) , gtt_size
);
1449 if (!intel_private
.gtt
)
1452 intel_private
.base
.gtt_total_entries
= gtt_size
/ 4;
1454 intel_private
.registers
= ioremap(temp
, 128 * 4096);
1455 if (!intel_private
.registers
) {
1456 iounmap(intel_private
.gtt
);
1460 temp
= readl(intel_private
.registers
+I810_PGETBL_CTL
) & 0xfffff000;
1461 global_cache_flush(); /* FIXME: ? */
1463 ret
= intel_gtt_init();
1465 iounmap(intel_private
.gtt
);
1469 agp_bridge
->gatt_table
= NULL
;
1471 agp_bridge
->gatt_bus_addr
= temp
;
1476 static const struct agp_bridge_driver intel_810_driver
= {
1477 .owner
= THIS_MODULE
,
1478 .aperture_sizes
= intel_i810_sizes
,
1479 .size_type
= FIXED_APER_SIZE
,
1480 .num_aperture_sizes
= 2,
1481 .needs_scratch_page
= true,
1482 .configure
= intel_i810_configure
,
1483 .fetch_size
= intel_i810_fetch_size
,
1484 .cleanup
= intel_i810_cleanup
,
1485 .mask_memory
= intel_i810_mask_memory
,
1486 .masks
= intel_i810_masks
,
1487 .agp_enable
= intel_i810_agp_enable
,
1488 .cache_flush
= global_cache_flush
,
1489 .create_gatt_table
= agp_generic_create_gatt_table
,
1490 .free_gatt_table
= agp_generic_free_gatt_table
,
1491 .insert_memory
= intel_i810_insert_entries
,
1492 .remove_memory
= intel_i810_remove_entries
,
1493 .alloc_by_type
= intel_i810_alloc_by_type
,
1494 .free_by_type
= intel_i810_free_by_type
,
1495 .agp_alloc_page
= agp_generic_alloc_page
,
1496 .agp_alloc_pages
= agp_generic_alloc_pages
,
1497 .agp_destroy_page
= agp_generic_destroy_page
,
1498 .agp_destroy_pages
= agp_generic_destroy_pages
,
1499 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
1502 static const struct agp_bridge_driver intel_830_driver
= {
1503 .owner
= THIS_MODULE
,
1504 .aperture_sizes
= intel_i830_sizes
,
1505 .size_type
= FIXED_APER_SIZE
,
1506 .num_aperture_sizes
= 4,
1507 .needs_scratch_page
= true,
1508 .configure
= intel_i830_configure
,
1509 .fetch_size
= intel_fake_agp_fetch_size
,
1510 .cleanup
= intel_i830_cleanup
,
1511 .mask_memory
= intel_i810_mask_memory
,
1512 .masks
= intel_i810_masks
,
1513 .agp_enable
= intel_i810_agp_enable
,
1514 .cache_flush
= global_cache_flush
,
1515 .create_gatt_table
= intel_i830_create_gatt_table
,
1516 .free_gatt_table
= intel_i830_free_gatt_table
,
1517 .insert_memory
= intel_i830_insert_entries
,
1518 .remove_memory
= intel_i830_remove_entries
,
1519 .alloc_by_type
= intel_i830_alloc_by_type
,
1520 .free_by_type
= intel_i810_free_by_type
,
1521 .agp_alloc_page
= agp_generic_alloc_page
,
1522 .agp_alloc_pages
= agp_generic_alloc_pages
,
1523 .agp_destroy_page
= agp_generic_destroy_page
,
1524 .agp_destroy_pages
= agp_generic_destroy_pages
,
1525 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1526 .chipset_flush
= intel_i830_chipset_flush
,
1529 static const struct agp_bridge_driver intel_915_driver
= {
1530 .owner
= THIS_MODULE
,
1531 .aperture_sizes
= intel_i830_sizes
,
1532 .size_type
= FIXED_APER_SIZE
,
1533 .num_aperture_sizes
= 4,
1534 .needs_scratch_page
= true,
1535 .configure
= intel_i9xx_configure
,
1536 .fetch_size
= intel_fake_agp_fetch_size
,
1537 .cleanup
= intel_i915_cleanup
,
1538 .mask_memory
= intel_i810_mask_memory
,
1539 .masks
= intel_i810_masks
,
1540 .agp_enable
= intel_i810_agp_enable
,
1541 .cache_flush
= global_cache_flush
,
1542 .create_gatt_table
= intel_i915_create_gatt_table
,
1543 .free_gatt_table
= intel_i830_free_gatt_table
,
1544 .insert_memory
= intel_i915_insert_entries
,
1545 .remove_memory
= intel_i915_remove_entries
,
1546 .alloc_by_type
= intel_i830_alloc_by_type
,
1547 .free_by_type
= intel_i810_free_by_type
,
1548 .agp_alloc_page
= agp_generic_alloc_page
,
1549 .agp_alloc_pages
= agp_generic_alloc_pages
,
1550 .agp_destroy_page
= agp_generic_destroy_page
,
1551 .agp_destroy_pages
= agp_generic_destroy_pages
,
1552 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1553 .chipset_flush
= intel_i915_chipset_flush
,
1554 #ifdef USE_PCI_DMA_API
1555 .agp_map_page
= intel_agp_map_page
,
1556 .agp_unmap_page
= intel_agp_unmap_page
,
1557 .agp_map_memory
= intel_agp_map_memory
,
1558 .agp_unmap_memory
= intel_agp_unmap_memory
,
1562 static const struct agp_bridge_driver intel_i965_driver
= {
1563 .owner
= THIS_MODULE
,
1564 .aperture_sizes
= intel_i830_sizes
,
1565 .size_type
= FIXED_APER_SIZE
,
1566 .num_aperture_sizes
= 4,
1567 .needs_scratch_page
= true,
1568 .configure
= intel_i9xx_configure
,
1569 .fetch_size
= intel_fake_agp_fetch_size
,
1570 .cleanup
= intel_i915_cleanup
,
1571 .mask_memory
= intel_i965_mask_memory
,
1572 .masks
= intel_i810_masks
,
1573 .agp_enable
= intel_i810_agp_enable
,
1574 .cache_flush
= global_cache_flush
,
1575 .create_gatt_table
= intel_i965_create_gatt_table
,
1576 .free_gatt_table
= intel_i830_free_gatt_table
,
1577 .insert_memory
= intel_i915_insert_entries
,
1578 .remove_memory
= intel_i915_remove_entries
,
1579 .alloc_by_type
= intel_i830_alloc_by_type
,
1580 .free_by_type
= intel_i810_free_by_type
,
1581 .agp_alloc_page
= agp_generic_alloc_page
,
1582 .agp_alloc_pages
= agp_generic_alloc_pages
,
1583 .agp_destroy_page
= agp_generic_destroy_page
,
1584 .agp_destroy_pages
= agp_generic_destroy_pages
,
1585 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1586 .chipset_flush
= intel_i915_chipset_flush
,
1587 #ifdef USE_PCI_DMA_API
1588 .agp_map_page
= intel_agp_map_page
,
1589 .agp_unmap_page
= intel_agp_unmap_page
,
1590 .agp_map_memory
= intel_agp_map_memory
,
1591 .agp_unmap_memory
= intel_agp_unmap_memory
,
1595 static const struct agp_bridge_driver intel_gen6_driver
= {
1596 .owner
= THIS_MODULE
,
1597 .aperture_sizes
= intel_i830_sizes
,
1598 .size_type
= FIXED_APER_SIZE
,
1599 .num_aperture_sizes
= 4,
1600 .needs_scratch_page
= true,
1601 .configure
= intel_i9xx_configure
,
1602 .fetch_size
= intel_fake_agp_fetch_size
,
1603 .cleanup
= intel_i915_cleanup
,
1604 .mask_memory
= intel_gen6_mask_memory
,
1605 .masks
= intel_gen6_masks
,
1606 .agp_enable
= intel_i810_agp_enable
,
1607 .cache_flush
= global_cache_flush
,
1608 .create_gatt_table
= intel_i965_create_gatt_table
,
1609 .free_gatt_table
= intel_i830_free_gatt_table
,
1610 .insert_memory
= intel_i915_insert_entries
,
1611 .remove_memory
= intel_i915_remove_entries
,
1612 .alloc_by_type
= intel_i830_alloc_by_type
,
1613 .free_by_type
= intel_i810_free_by_type
,
1614 .agp_alloc_page
= agp_generic_alloc_page
,
1615 .agp_alloc_pages
= agp_generic_alloc_pages
,
1616 .agp_destroy_page
= agp_generic_destroy_page
,
1617 .agp_destroy_pages
= agp_generic_destroy_pages
,
1618 .agp_type_to_mask_type
= intel_gen6_type_to_mask_type
,
1619 .chipset_flush
= intel_i915_chipset_flush
,
1620 #ifdef USE_PCI_DMA_API
1621 .agp_map_page
= intel_agp_map_page
,
1622 .agp_unmap_page
= intel_agp_unmap_page
,
1623 .agp_map_memory
= intel_agp_map_memory
,
1624 .agp_unmap_memory
= intel_agp_unmap_memory
,
1628 static const struct agp_bridge_driver intel_g33_driver
= {
1629 .owner
= THIS_MODULE
,
1630 .aperture_sizes
= intel_i830_sizes
,
1631 .size_type
= FIXED_APER_SIZE
,
1632 .num_aperture_sizes
= 4,
1633 .needs_scratch_page
= true,
1634 .configure
= intel_i9xx_configure
,
1635 .fetch_size
= intel_fake_agp_fetch_size
,
1636 .cleanup
= intel_i915_cleanup
,
1637 .mask_memory
= intel_i965_mask_memory
,
1638 .masks
= intel_i810_masks
,
1639 .agp_enable
= intel_i810_agp_enable
,
1640 .cache_flush
= global_cache_flush
,
1641 .create_gatt_table
= intel_i915_create_gatt_table
,
1642 .free_gatt_table
= intel_i830_free_gatt_table
,
1643 .insert_memory
= intel_i915_insert_entries
,
1644 .remove_memory
= intel_i915_remove_entries
,
1645 .alloc_by_type
= intel_i830_alloc_by_type
,
1646 .free_by_type
= intel_i810_free_by_type
,
1647 .agp_alloc_page
= agp_generic_alloc_page
,
1648 .agp_alloc_pages
= agp_generic_alloc_pages
,
1649 .agp_destroy_page
= agp_generic_destroy_page
,
1650 .agp_destroy_pages
= agp_generic_destroy_pages
,
1651 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1652 .chipset_flush
= intel_i915_chipset_flush
,
1653 #ifdef USE_PCI_DMA_API
1654 .agp_map_page
= intel_agp_map_page
,
1655 .agp_unmap_page
= intel_agp_unmap_page
,
1656 .agp_map_memory
= intel_agp_map_memory
,
1657 .agp_unmap_memory
= intel_agp_unmap_memory
,
1661 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1662 * driver and gmch_driver must be non-null, and find_gmch will determine
1663 * which one should be used if a gmch_chip_id is present.
1665 static const struct intel_gtt_driver_description
{
1666 unsigned int gmch_chip_id
;
1668 const struct agp_bridge_driver
*gmch_driver
;
1669 } intel_gtt_chipsets
[] = {
1670 { PCI_DEVICE_ID_INTEL_82810_IG1
, "i810", &intel_810_driver
},
1671 { PCI_DEVICE_ID_INTEL_82810_IG3
, "i810", &intel_810_driver
},
1672 { PCI_DEVICE_ID_INTEL_82810E_IG
, "i810", &intel_810_driver
},
1673 { PCI_DEVICE_ID_INTEL_82815_CGC
, "i815", &intel_810_driver
},
1674 { PCI_DEVICE_ID_INTEL_82830_CGC
, "830M", &intel_830_driver
},
1675 { PCI_DEVICE_ID_INTEL_82845G_IG
, "830M", &intel_830_driver
},
1676 { PCI_DEVICE_ID_INTEL_82854_IG
, "854", &intel_830_driver
},
1677 { PCI_DEVICE_ID_INTEL_82855GM_IG
, "855GM", &intel_830_driver
},
1678 { PCI_DEVICE_ID_INTEL_82865_IG
, "865", &intel_830_driver
},
1679 { PCI_DEVICE_ID_INTEL_E7221_IG
, "E7221 (i915)", &intel_915_driver
},
1680 { PCI_DEVICE_ID_INTEL_82915G_IG
, "915G", &intel_915_driver
},
1681 { PCI_DEVICE_ID_INTEL_82915GM_IG
, "915GM", &intel_915_driver
},
1682 { PCI_DEVICE_ID_INTEL_82945G_IG
, "945G", &intel_915_driver
},
1683 { PCI_DEVICE_ID_INTEL_82945GM_IG
, "945GM", &intel_915_driver
},
1684 { PCI_DEVICE_ID_INTEL_82945GME_IG
, "945GME", &intel_915_driver
},
1685 { PCI_DEVICE_ID_INTEL_82946GZ_IG
, "946GZ", &intel_i965_driver
},
1686 { PCI_DEVICE_ID_INTEL_82G35_IG
, "G35", &intel_i965_driver
},
1687 { PCI_DEVICE_ID_INTEL_82965Q_IG
, "965Q", &intel_i965_driver
},
1688 { PCI_DEVICE_ID_INTEL_82965G_IG
, "965G", &intel_i965_driver
},
1689 { PCI_DEVICE_ID_INTEL_82965GM_IG
, "965GM", &intel_i965_driver
},
1690 { PCI_DEVICE_ID_INTEL_82965GME_IG
, "965GME/GLE", &intel_i965_driver
},
1691 { PCI_DEVICE_ID_INTEL_G33_IG
, "G33", &intel_g33_driver
},
1692 { PCI_DEVICE_ID_INTEL_Q35_IG
, "Q35", &intel_g33_driver
},
1693 { PCI_DEVICE_ID_INTEL_Q33_IG
, "Q33", &intel_g33_driver
},
1694 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG
, "GMA3150", &intel_g33_driver
},
1695 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG
, "GMA3150", &intel_g33_driver
},
1696 { PCI_DEVICE_ID_INTEL_GM45_IG
, "GM45", &intel_i965_driver
},
1697 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG
, "Eaglelake", &intel_i965_driver
},
1698 { PCI_DEVICE_ID_INTEL_Q45_IG
, "Q45/Q43", &intel_i965_driver
},
1699 { PCI_DEVICE_ID_INTEL_G45_IG
, "G45/G43", &intel_i965_driver
},
1700 { PCI_DEVICE_ID_INTEL_B43_IG
, "B43", &intel_i965_driver
},
1701 { PCI_DEVICE_ID_INTEL_G41_IG
, "G41", &intel_i965_driver
},
1702 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG
,
1703 "HD Graphics", &intel_i965_driver
},
1704 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG
,
1705 "HD Graphics", &intel_i965_driver
},
1706 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG
,
1707 "Sandybridge", &intel_gen6_driver
},
1708 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG
,
1709 "Sandybridge", &intel_gen6_driver
},
1710 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG
,
1711 "Sandybridge", &intel_gen6_driver
},
1712 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG
,
1713 "Sandybridge", &intel_gen6_driver
},
1714 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG
,
1715 "Sandybridge", &intel_gen6_driver
},
1716 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG
,
1717 "Sandybridge", &intel_gen6_driver
},
1718 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG
,
1719 "Sandybridge", &intel_gen6_driver
},
1723 static int find_gmch(u16 device
)
1725 struct pci_dev
*gmch_device
;
1727 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
, device
, NULL
);
1728 if (gmch_device
&& PCI_FUNC(gmch_device
->devfn
) != 0) {
1729 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
,
1730 device
, gmch_device
);
1736 intel_private
.pcidev
= gmch_device
;
1740 int intel_gmch_probe(struct pci_dev
*pdev
,
1741 struct agp_bridge_data
*bridge
)
1744 bridge
->driver
= NULL
;
1746 for (i
= 0; intel_gtt_chipsets
[i
].name
!= NULL
; i
++) {
1747 if (find_gmch(intel_gtt_chipsets
[i
].gmch_chip_id
)) {
1749 intel_gtt_chipsets
[i
].gmch_driver
;
1754 if (!bridge
->driver
)
1757 bridge
->dev_private_data
= &intel_private
;
1760 intel_private
.bridge_dev
= pci_dev_get(pdev
);
1762 dev_info(&pdev
->dev
, "Intel %s Chipset\n", intel_gtt_chipsets
[i
].name
);
1764 if (bridge
->driver
->mask_memory
== intel_gen6_mask_memory
)
1766 else if (bridge
->driver
->mask_memory
== intel_i965_mask_memory
)
1771 if (pci_set_dma_mask(intel_private
.pcidev
, DMA_BIT_MASK(mask
)))
1772 dev_err(&intel_private
.pcidev
->dev
,
1773 "set gfx device dma mask %d-bit failed!\n", mask
);
1775 pci_set_consistent_dma_mask(intel_private
.pcidev
,
1776 DMA_BIT_MASK(mask
));
1778 if (bridge
->driver
== &intel_810_driver
)
1781 intel_private
.base
.gtt_mappable_entries
= intel_gtt_mappable_entries();
1785 EXPORT_SYMBOL(intel_gmch_probe
);
1787 void intel_gmch_remove(struct pci_dev
*pdev
)
1789 if (intel_private
.pcidev
)
1790 pci_dev_put(intel_private
.pcidev
);
1791 if (intel_private
.bridge_dev
)
1792 pci_dev_put(intel_private
.bridge_dev
);
1794 EXPORT_SYMBOL(intel_gmch_remove
);
1796 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1797 MODULE_LICENSE("GPL and additional rights");