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agp/intel-gtt: export the scratch page dma address
[deliverable/linux.git] / drivers / char / agp / intel-gtt.c
1 /*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <linux/delay.h>
25 #include <asm/smp.h>
26 #include "agp.h"
27 #include "intel-agp.h"
28 #include <drm/intel-gtt.h>
29
30 /*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
34 * Only newer chipsets need to bother with this, of course.
35 */
36 #ifdef CONFIG_INTEL_IOMMU
37 #define USE_PCI_DMA_API 1
38 #else
39 #define USE_PCI_DMA_API 0
40 #endif
41
42 struct intel_gtt_driver {
43 unsigned int gen : 8;
44 unsigned int is_g33 : 1;
45 unsigned int is_pineview : 1;
46 unsigned int is_ironlake : 1;
47 unsigned int has_pgtbl_enable : 1;
48 unsigned int dma_mask_size : 8;
49 /* Chipset specific GTT setup */
50 int (*setup)(void);
51 /* This should undo anything done in ->setup() save the unmapping
52 * of the mmio register file, that's done in the generic code. */
53 void (*cleanup)(void);
54 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
55 /* Flags is a more or less chipset specific opaque value.
56 * For chipsets that need to support old ums (non-gem) code, this
57 * needs to be identical to the various supported agp memory types! */
58 bool (*check_flags)(unsigned int flags);
59 void (*chipset_flush)(void);
60 };
61
62 static struct _intel_private {
63 struct intel_gtt base;
64 const struct intel_gtt_driver *driver;
65 struct pci_dev *pcidev; /* device one */
66 struct pci_dev *bridge_dev;
67 u8 __iomem *registers;
68 phys_addr_t gtt_bus_addr;
69 phys_addr_t gma_bus_addr;
70 u32 PGETBL_save;
71 u32 __iomem *gtt; /* I915G */
72 bool clear_fake_agp; /* on first access via agp, fill with scratch */
73 int num_dcache_entries;
74 void __iomem *i9xx_flush_page;
75 char *i81x_gtt_table;
76 struct resource ifp_resource;
77 int resource_valid;
78 struct page *scratch_page;
79 } intel_private;
80
81 #define INTEL_GTT_GEN intel_private.driver->gen
82 #define IS_G33 intel_private.driver->is_g33
83 #define IS_PINEVIEW intel_private.driver->is_pineview
84 #define IS_IRONLAKE intel_private.driver->is_ironlake
85 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
86
87 int intel_gtt_map_memory(struct page **pages, unsigned int num_entries,
88 struct scatterlist **sg_list, int *num_sg)
89 {
90 struct sg_table st;
91 struct scatterlist *sg;
92 int i;
93
94 if (*sg_list)
95 return 0; /* already mapped (for e.g. resume */
96
97 DBG("try mapping %lu pages\n", (unsigned long)num_entries);
98
99 if (sg_alloc_table(&st, num_entries, GFP_KERNEL))
100 goto err;
101
102 *sg_list = sg = st.sgl;
103
104 for (i = 0 ; i < num_entries; i++, sg = sg_next(sg))
105 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
106
107 *num_sg = pci_map_sg(intel_private.pcidev, *sg_list,
108 num_entries, PCI_DMA_BIDIRECTIONAL);
109 if (unlikely(!*num_sg))
110 goto err;
111
112 return 0;
113
114 err:
115 sg_free_table(&st);
116 return -ENOMEM;
117 }
118 EXPORT_SYMBOL(intel_gtt_map_memory);
119
120 void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
121 {
122 struct sg_table st;
123 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
124
125 pci_unmap_sg(intel_private.pcidev, sg_list,
126 num_sg, PCI_DMA_BIDIRECTIONAL);
127
128 st.sgl = sg_list;
129 st.orig_nents = st.nents = num_sg;
130
131 sg_free_table(&st);
132 }
133 EXPORT_SYMBOL(intel_gtt_unmap_memory);
134
135 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
136 {
137 return;
138 }
139
140 /* Exists to support ARGB cursors */
141 static struct page *i8xx_alloc_pages(void)
142 {
143 struct page *page;
144
145 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
146 if (page == NULL)
147 return NULL;
148
149 if (set_pages_uc(page, 4) < 0) {
150 set_pages_wb(page, 4);
151 __free_pages(page, 2);
152 return NULL;
153 }
154 get_page(page);
155 atomic_inc(&agp_bridge->current_memory_agp);
156 return page;
157 }
158
159 static void i8xx_destroy_pages(struct page *page)
160 {
161 if (page == NULL)
162 return;
163
164 set_pages_wb(page, 4);
165 put_page(page);
166 __free_pages(page, 2);
167 atomic_dec(&agp_bridge->current_memory_agp);
168 }
169
170 #define I810_GTT_ORDER 4
171 static int i810_setup(void)
172 {
173 u32 reg_addr;
174 char *gtt_table;
175
176 /* i81x does not preallocate the gtt. It's always 64kb in size. */
177 gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
178 if (gtt_table == NULL)
179 return -ENOMEM;
180 intel_private.i81x_gtt_table = gtt_table;
181
182 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
183 reg_addr &= 0xfff80000;
184
185 intel_private.registers = ioremap(reg_addr, KB(64));
186 if (!intel_private.registers)
187 return -ENOMEM;
188
189 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
190 intel_private.registers+I810_PGETBL_CTL);
191
192 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
193
194 if ((readl(intel_private.registers+I810_DRAM_CTL)
195 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
196 dev_info(&intel_private.pcidev->dev,
197 "detected 4MB dedicated video ram\n");
198 intel_private.num_dcache_entries = 1024;
199 }
200
201 return 0;
202 }
203
204 static void i810_cleanup(void)
205 {
206 writel(0, intel_private.registers+I810_PGETBL_CTL);
207 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
208 }
209
210 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
211 int type)
212 {
213 int i;
214
215 if ((pg_start + mem->page_count)
216 > intel_private.num_dcache_entries)
217 return -EINVAL;
218
219 if (!mem->is_flushed)
220 global_cache_flush();
221
222 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
223 dma_addr_t addr = i << PAGE_SHIFT;
224 intel_private.driver->write_entry(addr,
225 i, type);
226 }
227 readl(intel_private.gtt+i-1);
228
229 return 0;
230 }
231
232 /*
233 * The i810/i830 requires a physical address to program its mouse
234 * pointer into hardware.
235 * However the Xserver still writes to it through the agp aperture.
236 */
237 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
238 {
239 struct agp_memory *new;
240 struct page *page;
241
242 switch (pg_count) {
243 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
244 break;
245 case 4:
246 /* kludge to get 4 physical pages for ARGB cursor */
247 page = i8xx_alloc_pages();
248 break;
249 default:
250 return NULL;
251 }
252
253 if (page == NULL)
254 return NULL;
255
256 new = agp_create_memory(pg_count);
257 if (new == NULL)
258 return NULL;
259
260 new->pages[0] = page;
261 if (pg_count == 4) {
262 /* kludge to get 4 physical pages for ARGB cursor */
263 new->pages[1] = new->pages[0] + 1;
264 new->pages[2] = new->pages[1] + 1;
265 new->pages[3] = new->pages[2] + 1;
266 }
267 new->page_count = pg_count;
268 new->num_scratch_pages = pg_count;
269 new->type = AGP_PHYS_MEMORY;
270 new->physical = page_to_phys(new->pages[0]);
271 return new;
272 }
273
274 static void intel_i810_free_by_type(struct agp_memory *curr)
275 {
276 agp_free_key(curr->key);
277 if (curr->type == AGP_PHYS_MEMORY) {
278 if (curr->page_count == 4)
279 i8xx_destroy_pages(curr->pages[0]);
280 else {
281 agp_bridge->driver->agp_destroy_page(curr->pages[0],
282 AGP_PAGE_DESTROY_UNMAP);
283 agp_bridge->driver->agp_destroy_page(curr->pages[0],
284 AGP_PAGE_DESTROY_FREE);
285 }
286 agp_free_page_array(curr);
287 }
288 kfree(curr);
289 }
290
291 static int intel_gtt_setup_scratch_page(void)
292 {
293 struct page *page;
294 dma_addr_t dma_addr;
295
296 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
297 if (page == NULL)
298 return -ENOMEM;
299 get_page(page);
300 set_pages_uc(page, 1);
301
302 if (intel_private.base.needs_dmar) {
303 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
304 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
305 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
306 return -EINVAL;
307
308 intel_private.base.scratch_page_dma = dma_addr;
309 } else
310 intel_private.base.scratch_page_dma = page_to_phys(page);
311
312 intel_private.scratch_page = page;
313
314 return 0;
315 }
316
317 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
318 unsigned int flags)
319 {
320 u32 pte_flags = I810_PTE_VALID;
321
322 switch (flags) {
323 case AGP_DCACHE_MEMORY:
324 pte_flags |= I810_PTE_LOCAL;
325 break;
326 case AGP_USER_CACHED_MEMORY:
327 pte_flags |= I830_PTE_SYSTEM_CACHED;
328 break;
329 }
330
331 writel(addr | pte_flags, intel_private.gtt + entry);
332 }
333
334 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
335 {32, 8192, 3},
336 {64, 16384, 4},
337 {128, 32768, 5},
338 {256, 65536, 6},
339 {512, 131072, 7},
340 };
341
342 static unsigned int intel_gtt_stolen_size(void)
343 {
344 u16 gmch_ctrl;
345 u8 rdct;
346 int local = 0;
347 static const int ddt[4] = { 0, 16, 32, 64 };
348 unsigned int stolen_size = 0;
349
350 if (INTEL_GTT_GEN == 1)
351 return 0; /* no stolen mem on i81x */
352
353 pci_read_config_word(intel_private.bridge_dev,
354 I830_GMCH_CTRL, &gmch_ctrl);
355
356 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
357 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
358 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
359 case I830_GMCH_GMS_STOLEN_512:
360 stolen_size = KB(512);
361 break;
362 case I830_GMCH_GMS_STOLEN_1024:
363 stolen_size = MB(1);
364 break;
365 case I830_GMCH_GMS_STOLEN_8192:
366 stolen_size = MB(8);
367 break;
368 case I830_GMCH_GMS_LOCAL:
369 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
370 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
371 MB(ddt[I830_RDRAM_DDT(rdct)]);
372 local = 1;
373 break;
374 default:
375 stolen_size = 0;
376 break;
377 }
378 } else if (INTEL_GTT_GEN == 6) {
379 /*
380 * SandyBridge has new memory control reg at 0x50.w
381 */
382 u16 snb_gmch_ctl;
383 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
384 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
385 case SNB_GMCH_GMS_STOLEN_32M:
386 stolen_size = MB(32);
387 break;
388 case SNB_GMCH_GMS_STOLEN_64M:
389 stolen_size = MB(64);
390 break;
391 case SNB_GMCH_GMS_STOLEN_96M:
392 stolen_size = MB(96);
393 break;
394 case SNB_GMCH_GMS_STOLEN_128M:
395 stolen_size = MB(128);
396 break;
397 case SNB_GMCH_GMS_STOLEN_160M:
398 stolen_size = MB(160);
399 break;
400 case SNB_GMCH_GMS_STOLEN_192M:
401 stolen_size = MB(192);
402 break;
403 case SNB_GMCH_GMS_STOLEN_224M:
404 stolen_size = MB(224);
405 break;
406 case SNB_GMCH_GMS_STOLEN_256M:
407 stolen_size = MB(256);
408 break;
409 case SNB_GMCH_GMS_STOLEN_288M:
410 stolen_size = MB(288);
411 break;
412 case SNB_GMCH_GMS_STOLEN_320M:
413 stolen_size = MB(320);
414 break;
415 case SNB_GMCH_GMS_STOLEN_352M:
416 stolen_size = MB(352);
417 break;
418 case SNB_GMCH_GMS_STOLEN_384M:
419 stolen_size = MB(384);
420 break;
421 case SNB_GMCH_GMS_STOLEN_416M:
422 stolen_size = MB(416);
423 break;
424 case SNB_GMCH_GMS_STOLEN_448M:
425 stolen_size = MB(448);
426 break;
427 case SNB_GMCH_GMS_STOLEN_480M:
428 stolen_size = MB(480);
429 break;
430 case SNB_GMCH_GMS_STOLEN_512M:
431 stolen_size = MB(512);
432 break;
433 }
434 } else {
435 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
436 case I855_GMCH_GMS_STOLEN_1M:
437 stolen_size = MB(1);
438 break;
439 case I855_GMCH_GMS_STOLEN_4M:
440 stolen_size = MB(4);
441 break;
442 case I855_GMCH_GMS_STOLEN_8M:
443 stolen_size = MB(8);
444 break;
445 case I855_GMCH_GMS_STOLEN_16M:
446 stolen_size = MB(16);
447 break;
448 case I855_GMCH_GMS_STOLEN_32M:
449 stolen_size = MB(32);
450 break;
451 case I915_GMCH_GMS_STOLEN_48M:
452 stolen_size = MB(48);
453 break;
454 case I915_GMCH_GMS_STOLEN_64M:
455 stolen_size = MB(64);
456 break;
457 case G33_GMCH_GMS_STOLEN_128M:
458 stolen_size = MB(128);
459 break;
460 case G33_GMCH_GMS_STOLEN_256M:
461 stolen_size = MB(256);
462 break;
463 case INTEL_GMCH_GMS_STOLEN_96M:
464 stolen_size = MB(96);
465 break;
466 case INTEL_GMCH_GMS_STOLEN_160M:
467 stolen_size = MB(160);
468 break;
469 case INTEL_GMCH_GMS_STOLEN_224M:
470 stolen_size = MB(224);
471 break;
472 case INTEL_GMCH_GMS_STOLEN_352M:
473 stolen_size = MB(352);
474 break;
475 default:
476 stolen_size = 0;
477 break;
478 }
479 }
480
481 if (stolen_size > 0) {
482 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
483 stolen_size / KB(1), local ? "local" : "stolen");
484 } else {
485 dev_info(&intel_private.bridge_dev->dev,
486 "no pre-allocated video memory detected\n");
487 stolen_size = 0;
488 }
489
490 return stolen_size;
491 }
492
493 static void i965_adjust_pgetbl_size(unsigned int size_flag)
494 {
495 u32 pgetbl_ctl, pgetbl_ctl2;
496
497 /* ensure that ppgtt is disabled */
498 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
499 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
500 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
501
502 /* write the new ggtt size */
503 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
504 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
505 pgetbl_ctl |= size_flag;
506 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
507 }
508
509 static unsigned int i965_gtt_total_entries(void)
510 {
511 int size;
512 u32 pgetbl_ctl;
513 u16 gmch_ctl;
514
515 pci_read_config_word(intel_private.bridge_dev,
516 I830_GMCH_CTRL, &gmch_ctl);
517
518 if (INTEL_GTT_GEN == 5) {
519 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
520 case G4x_GMCH_SIZE_1M:
521 case G4x_GMCH_SIZE_VT_1M:
522 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
523 break;
524 case G4x_GMCH_SIZE_VT_1_5M:
525 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
526 break;
527 case G4x_GMCH_SIZE_2M:
528 case G4x_GMCH_SIZE_VT_2M:
529 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
530 break;
531 }
532 }
533
534 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
535
536 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
537 case I965_PGETBL_SIZE_128KB:
538 size = KB(128);
539 break;
540 case I965_PGETBL_SIZE_256KB:
541 size = KB(256);
542 break;
543 case I965_PGETBL_SIZE_512KB:
544 size = KB(512);
545 break;
546 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
547 case I965_PGETBL_SIZE_1MB:
548 size = KB(1024);
549 break;
550 case I965_PGETBL_SIZE_2MB:
551 size = KB(2048);
552 break;
553 case I965_PGETBL_SIZE_1_5MB:
554 size = KB(1024 + 512);
555 break;
556 default:
557 dev_info(&intel_private.pcidev->dev,
558 "unknown page table size, assuming 512KB\n");
559 size = KB(512);
560 }
561
562 return size/4;
563 }
564
565 static unsigned int intel_gtt_total_entries(void)
566 {
567 int size;
568
569 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
570 return i965_gtt_total_entries();
571 else if (INTEL_GTT_GEN == 6) {
572 u16 snb_gmch_ctl;
573
574 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
575 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
576 default:
577 case SNB_GTT_SIZE_0M:
578 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
579 size = MB(0);
580 break;
581 case SNB_GTT_SIZE_1M:
582 size = MB(1);
583 break;
584 case SNB_GTT_SIZE_2M:
585 size = MB(2);
586 break;
587 }
588 return size/4;
589 } else {
590 /* On previous hardware, the GTT size was just what was
591 * required to map the aperture.
592 */
593 return intel_private.base.gtt_mappable_entries;
594 }
595 }
596
597 static unsigned int intel_gtt_mappable_entries(void)
598 {
599 unsigned int aperture_size;
600
601 if (INTEL_GTT_GEN == 1) {
602 u32 smram_miscc;
603
604 pci_read_config_dword(intel_private.bridge_dev,
605 I810_SMRAM_MISCC, &smram_miscc);
606
607 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
608 == I810_GFX_MEM_WIN_32M)
609 aperture_size = MB(32);
610 else
611 aperture_size = MB(64);
612 } else if (INTEL_GTT_GEN == 2) {
613 u16 gmch_ctrl;
614
615 pci_read_config_word(intel_private.bridge_dev,
616 I830_GMCH_CTRL, &gmch_ctrl);
617
618 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
619 aperture_size = MB(64);
620 else
621 aperture_size = MB(128);
622 } else {
623 /* 9xx supports large sizes, just look at the length */
624 aperture_size = pci_resource_len(intel_private.pcidev, 2);
625 }
626
627 return aperture_size >> PAGE_SHIFT;
628 }
629
630 static void intel_gtt_teardown_scratch_page(void)
631 {
632 set_pages_wb(intel_private.scratch_page, 1);
633 pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma,
634 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
635 put_page(intel_private.scratch_page);
636 __free_page(intel_private.scratch_page);
637 }
638
639 static void intel_gtt_cleanup(void)
640 {
641 intel_private.driver->cleanup();
642
643 iounmap(intel_private.gtt);
644 iounmap(intel_private.registers);
645
646 intel_gtt_teardown_scratch_page();
647 }
648
649 static int intel_gtt_init(void)
650 {
651 u32 gtt_map_size;
652 int ret;
653
654 ret = intel_private.driver->setup();
655 if (ret != 0)
656 return ret;
657
658 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
659 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
660
661 /* save the PGETBL reg for resume */
662 intel_private.PGETBL_save =
663 readl(intel_private.registers+I810_PGETBL_CTL)
664 & ~I810_PGETBL_ENABLED;
665 /* we only ever restore the register when enabling the PGTBL... */
666 if (HAS_PGTBL_EN)
667 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
668
669 dev_info(&intel_private.bridge_dev->dev,
670 "detected gtt size: %dK total, %dK mappable\n",
671 intel_private.base.gtt_total_entries * 4,
672 intel_private.base.gtt_mappable_entries * 4);
673
674 gtt_map_size = intel_private.base.gtt_total_entries * 4;
675
676 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
677 gtt_map_size);
678 if (!intel_private.gtt) {
679 intel_private.driver->cleanup();
680 iounmap(intel_private.registers);
681 return -ENOMEM;
682 }
683
684 global_cache_flush(); /* FIXME: ? */
685
686 intel_private.base.stolen_size = intel_gtt_stolen_size();
687
688 intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
689
690 ret = intel_gtt_setup_scratch_page();
691 if (ret != 0) {
692 intel_gtt_cleanup();
693 return ret;
694 }
695
696 return 0;
697 }
698
699 static int intel_fake_agp_fetch_size(void)
700 {
701 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
702 unsigned int aper_size;
703 int i;
704
705 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
706 / MB(1);
707
708 for (i = 0; i < num_sizes; i++) {
709 if (aper_size == intel_fake_agp_sizes[i].size) {
710 agp_bridge->current_size =
711 (void *) (intel_fake_agp_sizes + i);
712 return aper_size;
713 }
714 }
715
716 return 0;
717 }
718
719 static void i830_cleanup(void)
720 {
721 }
722
723 /* The chipset_flush interface needs to get data that has already been
724 * flushed out of the CPU all the way out to main memory, because the GPU
725 * doesn't snoop those buffers.
726 *
727 * The 8xx series doesn't have the same lovely interface for flushing the
728 * chipset write buffers that the later chips do. According to the 865
729 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
730 * that buffer out, we just fill 1KB and clflush it out, on the assumption
731 * that it'll push whatever was in there out. It appears to work.
732 */
733 static void i830_chipset_flush(void)
734 {
735 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
736
737 /* Forcibly evict everything from the CPU write buffers.
738 * clflush appears to be insufficient.
739 */
740 wbinvd_on_all_cpus();
741
742 /* Now we've only seen documents for this magic bit on 855GM,
743 * we hope it exists for the other gen2 chipsets...
744 *
745 * Also works as advertised on my 845G.
746 */
747 writel(readl(intel_private.registers+I830_HIC) | (1<<31),
748 intel_private.registers+I830_HIC);
749
750 while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
751 if (time_after(jiffies, timeout))
752 break;
753
754 udelay(50);
755 }
756 }
757
758 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
759 unsigned int flags)
760 {
761 u32 pte_flags = I810_PTE_VALID;
762
763 if (flags == AGP_USER_CACHED_MEMORY)
764 pte_flags |= I830_PTE_SYSTEM_CACHED;
765
766 writel(addr | pte_flags, intel_private.gtt + entry);
767 }
768
769 static bool intel_enable_gtt(void)
770 {
771 u32 gma_addr;
772 u8 __iomem *reg;
773
774 if (INTEL_GTT_GEN <= 2)
775 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
776 &gma_addr);
777 else
778 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
779 &gma_addr);
780
781 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
782
783 if (INTEL_GTT_GEN >= 6)
784 return true;
785
786 if (INTEL_GTT_GEN == 2) {
787 u16 gmch_ctrl;
788
789 pci_read_config_word(intel_private.bridge_dev,
790 I830_GMCH_CTRL, &gmch_ctrl);
791 gmch_ctrl |= I830_GMCH_ENABLED;
792 pci_write_config_word(intel_private.bridge_dev,
793 I830_GMCH_CTRL, gmch_ctrl);
794
795 pci_read_config_word(intel_private.bridge_dev,
796 I830_GMCH_CTRL, &gmch_ctrl);
797 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
798 dev_err(&intel_private.pcidev->dev,
799 "failed to enable the GTT: GMCH_CTRL=%x\n",
800 gmch_ctrl);
801 return false;
802 }
803 }
804
805 /* On the resume path we may be adjusting the PGTBL value, so
806 * be paranoid and flush all chipset write buffers...
807 */
808 if (INTEL_GTT_GEN >= 3)
809 writel(0, intel_private.registers+GFX_FLSH_CNTL);
810
811 reg = intel_private.registers+I810_PGETBL_CTL;
812 writel(intel_private.PGETBL_save, reg);
813 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
814 dev_err(&intel_private.pcidev->dev,
815 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
816 readl(reg), intel_private.PGETBL_save);
817 return false;
818 }
819
820 if (INTEL_GTT_GEN >= 3)
821 writel(0, intel_private.registers+GFX_FLSH_CNTL);
822
823 return true;
824 }
825
826 static int i830_setup(void)
827 {
828 u32 reg_addr;
829
830 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
831 reg_addr &= 0xfff80000;
832
833 intel_private.registers = ioremap(reg_addr, KB(64));
834 if (!intel_private.registers)
835 return -ENOMEM;
836
837 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
838
839 return 0;
840 }
841
842 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
843 {
844 agp_bridge->gatt_table_real = NULL;
845 agp_bridge->gatt_table = NULL;
846 agp_bridge->gatt_bus_addr = 0;
847
848 return 0;
849 }
850
851 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
852 {
853 return 0;
854 }
855
856 static int intel_fake_agp_configure(void)
857 {
858 if (!intel_enable_gtt())
859 return -EIO;
860
861 intel_private.clear_fake_agp = true;
862 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
863
864 return 0;
865 }
866
867 static bool i830_check_flags(unsigned int flags)
868 {
869 switch (flags) {
870 case 0:
871 case AGP_PHYS_MEMORY:
872 case AGP_USER_CACHED_MEMORY:
873 case AGP_USER_MEMORY:
874 return true;
875 }
876
877 return false;
878 }
879
880 void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
881 unsigned int sg_len,
882 unsigned int pg_start,
883 unsigned int flags)
884 {
885 struct scatterlist *sg;
886 unsigned int len, m;
887 int i, j;
888
889 j = pg_start;
890
891 /* sg may merge pages, but we have to separate
892 * per-page addr for GTT */
893 for_each_sg(sg_list, sg, sg_len, i) {
894 len = sg_dma_len(sg) >> PAGE_SHIFT;
895 for (m = 0; m < len; m++) {
896 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
897 intel_private.driver->write_entry(addr,
898 j, flags);
899 j++;
900 }
901 }
902 readl(intel_private.gtt+j-1);
903 }
904 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
905
906 void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries,
907 struct page **pages, unsigned int flags)
908 {
909 int i, j;
910
911 for (i = 0, j = first_entry; i < num_entries; i++, j++) {
912 dma_addr_t addr = page_to_phys(pages[i]);
913 intel_private.driver->write_entry(addr,
914 j, flags);
915 }
916 readl(intel_private.gtt+j-1);
917 }
918 EXPORT_SYMBOL(intel_gtt_insert_pages);
919
920 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
921 off_t pg_start, int type)
922 {
923 int ret = -EINVAL;
924
925 if (intel_private.base.do_idle_maps)
926 return -ENODEV;
927
928 if (intel_private.clear_fake_agp) {
929 int start = intel_private.base.stolen_size / PAGE_SIZE;
930 int end = intel_private.base.gtt_mappable_entries;
931 intel_gtt_clear_range(start, end - start);
932 intel_private.clear_fake_agp = false;
933 }
934
935 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
936 return i810_insert_dcache_entries(mem, pg_start, type);
937
938 if (mem->page_count == 0)
939 goto out;
940
941 if (pg_start + mem->page_count > intel_private.base.gtt_total_entries)
942 goto out_err;
943
944 if (type != mem->type)
945 goto out_err;
946
947 if (!intel_private.driver->check_flags(type))
948 goto out_err;
949
950 if (!mem->is_flushed)
951 global_cache_flush();
952
953 if (intel_private.base.needs_dmar) {
954 ret = intel_gtt_map_memory(mem->pages, mem->page_count,
955 &mem->sg_list, &mem->num_sg);
956 if (ret != 0)
957 return ret;
958
959 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg,
960 pg_start, type);
961 } else
962 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
963 type);
964
965 out:
966 ret = 0;
967 out_err:
968 mem->is_flushed = true;
969 return ret;
970 }
971
972 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
973 {
974 unsigned int i;
975
976 for (i = first_entry; i < (first_entry + num_entries); i++) {
977 intel_private.driver->write_entry(intel_private.base.scratch_page_dma,
978 i, 0);
979 }
980 readl(intel_private.gtt+i-1);
981 }
982 EXPORT_SYMBOL(intel_gtt_clear_range);
983
984 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
985 off_t pg_start, int type)
986 {
987 if (mem->page_count == 0)
988 return 0;
989
990 if (intel_private.base.do_idle_maps)
991 return -ENODEV;
992
993 intel_gtt_clear_range(pg_start, mem->page_count);
994
995 if (intel_private.base.needs_dmar) {
996 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
997 mem->sg_list = NULL;
998 mem->num_sg = 0;
999 }
1000
1001 return 0;
1002 }
1003
1004 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1005 int type)
1006 {
1007 struct agp_memory *new;
1008
1009 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
1010 if (pg_count != intel_private.num_dcache_entries)
1011 return NULL;
1012
1013 new = agp_create_memory(1);
1014 if (new == NULL)
1015 return NULL;
1016
1017 new->type = AGP_DCACHE_MEMORY;
1018 new->page_count = pg_count;
1019 new->num_scratch_pages = 0;
1020 agp_free_page_array(new);
1021 return new;
1022 }
1023 if (type == AGP_PHYS_MEMORY)
1024 return alloc_agpphysmem_i8xx(pg_count, type);
1025 /* always return NULL for other allocation types for now */
1026 return NULL;
1027 }
1028
1029 static int intel_alloc_chipset_flush_resource(void)
1030 {
1031 int ret;
1032 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1033 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1034 pcibios_align_resource, intel_private.bridge_dev);
1035
1036 return ret;
1037 }
1038
1039 static void intel_i915_setup_chipset_flush(void)
1040 {
1041 int ret;
1042 u32 temp;
1043
1044 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1045 if (!(temp & 0x1)) {
1046 intel_alloc_chipset_flush_resource();
1047 intel_private.resource_valid = 1;
1048 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1049 } else {
1050 temp &= ~1;
1051
1052 intel_private.resource_valid = 1;
1053 intel_private.ifp_resource.start = temp;
1054 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1055 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1056 /* some BIOSes reserve this area in a pnp some don't */
1057 if (ret)
1058 intel_private.resource_valid = 0;
1059 }
1060 }
1061
1062 static void intel_i965_g33_setup_chipset_flush(void)
1063 {
1064 u32 temp_hi, temp_lo;
1065 int ret;
1066
1067 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1068 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1069
1070 if (!(temp_lo & 0x1)) {
1071
1072 intel_alloc_chipset_flush_resource();
1073
1074 intel_private.resource_valid = 1;
1075 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1076 upper_32_bits(intel_private.ifp_resource.start));
1077 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1078 } else {
1079 u64 l64;
1080
1081 temp_lo &= ~0x1;
1082 l64 = ((u64)temp_hi << 32) | temp_lo;
1083
1084 intel_private.resource_valid = 1;
1085 intel_private.ifp_resource.start = l64;
1086 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1087 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1088 /* some BIOSes reserve this area in a pnp some don't */
1089 if (ret)
1090 intel_private.resource_valid = 0;
1091 }
1092 }
1093
1094 static void intel_i9xx_setup_flush(void)
1095 {
1096 /* return if already configured */
1097 if (intel_private.ifp_resource.start)
1098 return;
1099
1100 if (INTEL_GTT_GEN == 6)
1101 return;
1102
1103 /* setup a resource for this object */
1104 intel_private.ifp_resource.name = "Intel Flush Page";
1105 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1106
1107 /* Setup chipset flush for 915 */
1108 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1109 intel_i965_g33_setup_chipset_flush();
1110 } else {
1111 intel_i915_setup_chipset_flush();
1112 }
1113
1114 if (intel_private.ifp_resource.start)
1115 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1116 if (!intel_private.i9xx_flush_page)
1117 dev_err(&intel_private.pcidev->dev,
1118 "can't ioremap flush page - no chipset flushing\n");
1119 }
1120
1121 static void i9xx_cleanup(void)
1122 {
1123 if (intel_private.i9xx_flush_page)
1124 iounmap(intel_private.i9xx_flush_page);
1125 if (intel_private.resource_valid)
1126 release_resource(&intel_private.ifp_resource);
1127 intel_private.ifp_resource.start = 0;
1128 intel_private.resource_valid = 0;
1129 }
1130
1131 static void i9xx_chipset_flush(void)
1132 {
1133 if (intel_private.i9xx_flush_page)
1134 writel(1, intel_private.i9xx_flush_page);
1135 }
1136
1137 static void i965_write_entry(dma_addr_t addr,
1138 unsigned int entry,
1139 unsigned int flags)
1140 {
1141 u32 pte_flags;
1142
1143 pte_flags = I810_PTE_VALID;
1144 if (flags == AGP_USER_CACHED_MEMORY)
1145 pte_flags |= I830_PTE_SYSTEM_CACHED;
1146
1147 /* Shift high bits down */
1148 addr |= (addr >> 28) & 0xf0;
1149 writel(addr | pte_flags, intel_private.gtt + entry);
1150 }
1151
1152 static bool gen6_check_flags(unsigned int flags)
1153 {
1154 return true;
1155 }
1156
1157 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1158 unsigned int flags)
1159 {
1160 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1161 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1162 u32 pte_flags;
1163
1164 if (type_mask == AGP_USER_MEMORY)
1165 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1166 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1167 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1168 if (gfdt)
1169 pte_flags |= GEN6_PTE_GFDT;
1170 } else { /* set 'normal'/'cached' to LLC by default */
1171 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1172 if (gfdt)
1173 pte_flags |= GEN6_PTE_GFDT;
1174 }
1175
1176 /* gen6 has bit11-4 for physical addr bit39-32 */
1177 addr |= (addr >> 28) & 0xff0;
1178 writel(addr | pte_flags, intel_private.gtt + entry);
1179 }
1180
1181 static void gen6_cleanup(void)
1182 {
1183 }
1184
1185 /* Certain Gen5 chipsets require require idling the GPU before
1186 * unmapping anything from the GTT when VT-d is enabled.
1187 */
1188 static inline int needs_idle_maps(void)
1189 {
1190 #ifdef CONFIG_INTEL_IOMMU
1191 const unsigned short gpu_devid = intel_private.pcidev->device;
1192 extern int intel_iommu_gfx_mapped;
1193
1194 /* Query intel_iommu to see if we need the workaround. Presumably that
1195 * was loaded first.
1196 */
1197 if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
1198 gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
1199 intel_iommu_gfx_mapped)
1200 return 1;
1201 #endif
1202 return 0;
1203 }
1204
1205 static int i9xx_setup(void)
1206 {
1207 u32 reg_addr;
1208
1209 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1210
1211 reg_addr &= 0xfff80000;
1212
1213 intel_private.registers = ioremap(reg_addr, 128 * 4096);
1214 if (!intel_private.registers)
1215 return -ENOMEM;
1216
1217 if (INTEL_GTT_GEN == 3) {
1218 u32 gtt_addr;
1219
1220 pci_read_config_dword(intel_private.pcidev,
1221 I915_PTEADDR, &gtt_addr);
1222 intel_private.gtt_bus_addr = gtt_addr;
1223 } else {
1224 u32 gtt_offset;
1225
1226 switch (INTEL_GTT_GEN) {
1227 case 5:
1228 case 6:
1229 gtt_offset = MB(2);
1230 break;
1231 case 4:
1232 default:
1233 gtt_offset = KB(512);
1234 break;
1235 }
1236 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1237 }
1238
1239 if (needs_idle_maps())
1240 intel_private.base.do_idle_maps = 1;
1241
1242 intel_i9xx_setup_flush();
1243
1244 return 0;
1245 }
1246
1247 static const struct agp_bridge_driver intel_fake_agp_driver = {
1248 .owner = THIS_MODULE,
1249 .size_type = FIXED_APER_SIZE,
1250 .aperture_sizes = intel_fake_agp_sizes,
1251 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1252 .configure = intel_fake_agp_configure,
1253 .fetch_size = intel_fake_agp_fetch_size,
1254 .cleanup = intel_gtt_cleanup,
1255 .agp_enable = intel_fake_agp_enable,
1256 .cache_flush = global_cache_flush,
1257 .create_gatt_table = intel_fake_agp_create_gatt_table,
1258 .free_gatt_table = intel_fake_agp_free_gatt_table,
1259 .insert_memory = intel_fake_agp_insert_entries,
1260 .remove_memory = intel_fake_agp_remove_entries,
1261 .alloc_by_type = intel_fake_agp_alloc_by_type,
1262 .free_by_type = intel_i810_free_by_type,
1263 .agp_alloc_page = agp_generic_alloc_page,
1264 .agp_alloc_pages = agp_generic_alloc_pages,
1265 .agp_destroy_page = agp_generic_destroy_page,
1266 .agp_destroy_pages = agp_generic_destroy_pages,
1267 };
1268
1269 static const struct intel_gtt_driver i81x_gtt_driver = {
1270 .gen = 1,
1271 .has_pgtbl_enable = 1,
1272 .dma_mask_size = 32,
1273 .setup = i810_setup,
1274 .cleanup = i810_cleanup,
1275 .check_flags = i830_check_flags,
1276 .write_entry = i810_write_entry,
1277 };
1278 static const struct intel_gtt_driver i8xx_gtt_driver = {
1279 .gen = 2,
1280 .has_pgtbl_enable = 1,
1281 .setup = i830_setup,
1282 .cleanup = i830_cleanup,
1283 .write_entry = i830_write_entry,
1284 .dma_mask_size = 32,
1285 .check_flags = i830_check_flags,
1286 .chipset_flush = i830_chipset_flush,
1287 };
1288 static const struct intel_gtt_driver i915_gtt_driver = {
1289 .gen = 3,
1290 .has_pgtbl_enable = 1,
1291 .setup = i9xx_setup,
1292 .cleanup = i9xx_cleanup,
1293 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1294 .write_entry = i830_write_entry,
1295 .dma_mask_size = 32,
1296 .check_flags = i830_check_flags,
1297 .chipset_flush = i9xx_chipset_flush,
1298 };
1299 static const struct intel_gtt_driver g33_gtt_driver = {
1300 .gen = 3,
1301 .is_g33 = 1,
1302 .setup = i9xx_setup,
1303 .cleanup = i9xx_cleanup,
1304 .write_entry = i965_write_entry,
1305 .dma_mask_size = 36,
1306 .check_flags = i830_check_flags,
1307 .chipset_flush = i9xx_chipset_flush,
1308 };
1309 static const struct intel_gtt_driver pineview_gtt_driver = {
1310 .gen = 3,
1311 .is_pineview = 1, .is_g33 = 1,
1312 .setup = i9xx_setup,
1313 .cleanup = i9xx_cleanup,
1314 .write_entry = i965_write_entry,
1315 .dma_mask_size = 36,
1316 .check_flags = i830_check_flags,
1317 .chipset_flush = i9xx_chipset_flush,
1318 };
1319 static const struct intel_gtt_driver i965_gtt_driver = {
1320 .gen = 4,
1321 .has_pgtbl_enable = 1,
1322 .setup = i9xx_setup,
1323 .cleanup = i9xx_cleanup,
1324 .write_entry = i965_write_entry,
1325 .dma_mask_size = 36,
1326 .check_flags = i830_check_flags,
1327 .chipset_flush = i9xx_chipset_flush,
1328 };
1329 static const struct intel_gtt_driver g4x_gtt_driver = {
1330 .gen = 5,
1331 .setup = i9xx_setup,
1332 .cleanup = i9xx_cleanup,
1333 .write_entry = i965_write_entry,
1334 .dma_mask_size = 36,
1335 .check_flags = i830_check_flags,
1336 .chipset_flush = i9xx_chipset_flush,
1337 };
1338 static const struct intel_gtt_driver ironlake_gtt_driver = {
1339 .gen = 5,
1340 .is_ironlake = 1,
1341 .setup = i9xx_setup,
1342 .cleanup = i9xx_cleanup,
1343 .write_entry = i965_write_entry,
1344 .dma_mask_size = 36,
1345 .check_flags = i830_check_flags,
1346 .chipset_flush = i9xx_chipset_flush,
1347 };
1348 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1349 .gen = 6,
1350 .setup = i9xx_setup,
1351 .cleanup = gen6_cleanup,
1352 .write_entry = gen6_write_entry,
1353 .dma_mask_size = 40,
1354 .check_flags = gen6_check_flags,
1355 .chipset_flush = i9xx_chipset_flush,
1356 };
1357
1358 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1359 * driver and gmch_driver must be non-null, and find_gmch will determine
1360 * which one should be used if a gmch_chip_id is present.
1361 */
1362 static const struct intel_gtt_driver_description {
1363 unsigned int gmch_chip_id;
1364 char *name;
1365 const struct intel_gtt_driver *gtt_driver;
1366 } intel_gtt_chipsets[] = {
1367 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1368 &i81x_gtt_driver},
1369 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1370 &i81x_gtt_driver},
1371 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1372 &i81x_gtt_driver},
1373 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1374 &i81x_gtt_driver},
1375 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1376 &i8xx_gtt_driver},
1377 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1378 &i8xx_gtt_driver},
1379 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1380 &i8xx_gtt_driver},
1381 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1382 &i8xx_gtt_driver},
1383 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1384 &i8xx_gtt_driver},
1385 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1386 &i915_gtt_driver },
1387 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1388 &i915_gtt_driver },
1389 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1390 &i915_gtt_driver },
1391 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1392 &i915_gtt_driver },
1393 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1394 &i915_gtt_driver },
1395 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1396 &i915_gtt_driver },
1397 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1398 &i965_gtt_driver },
1399 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1400 &i965_gtt_driver },
1401 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1402 &i965_gtt_driver },
1403 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1404 &i965_gtt_driver },
1405 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1406 &i965_gtt_driver },
1407 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1408 &i965_gtt_driver },
1409 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1410 &g33_gtt_driver },
1411 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1412 &g33_gtt_driver },
1413 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1414 &g33_gtt_driver },
1415 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1416 &pineview_gtt_driver },
1417 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1418 &pineview_gtt_driver },
1419 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1420 &g4x_gtt_driver },
1421 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1422 &g4x_gtt_driver },
1423 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1424 &g4x_gtt_driver },
1425 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1426 &g4x_gtt_driver },
1427 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1428 &g4x_gtt_driver },
1429 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1430 &g4x_gtt_driver },
1431 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1432 &g4x_gtt_driver },
1433 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1434 "HD Graphics", &ironlake_gtt_driver },
1435 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1436 "HD Graphics", &ironlake_gtt_driver },
1437 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1438 "Sandybridge", &sandybridge_gtt_driver },
1439 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1440 "Sandybridge", &sandybridge_gtt_driver },
1441 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1442 "Sandybridge", &sandybridge_gtt_driver },
1443 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1444 "Sandybridge", &sandybridge_gtt_driver },
1445 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1446 "Sandybridge", &sandybridge_gtt_driver },
1447 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1448 "Sandybridge", &sandybridge_gtt_driver },
1449 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1450 "Sandybridge", &sandybridge_gtt_driver },
1451 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG,
1452 "Ivybridge", &sandybridge_gtt_driver },
1453 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG,
1454 "Ivybridge", &sandybridge_gtt_driver },
1455 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG,
1456 "Ivybridge", &sandybridge_gtt_driver },
1457 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG,
1458 "Ivybridge", &sandybridge_gtt_driver },
1459 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
1460 "Ivybridge", &sandybridge_gtt_driver },
1461 { 0, NULL, NULL }
1462 };
1463
1464 static int find_gmch(u16 device)
1465 {
1466 struct pci_dev *gmch_device;
1467
1468 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1469 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1470 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1471 device, gmch_device);
1472 }
1473
1474 if (!gmch_device)
1475 return 0;
1476
1477 intel_private.pcidev = gmch_device;
1478 return 1;
1479 }
1480
1481 int intel_gmch_probe(struct pci_dev *pdev,
1482 struct agp_bridge_data *bridge)
1483 {
1484 int i, mask;
1485 intel_private.driver = NULL;
1486
1487 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1488 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1489 intel_private.driver =
1490 intel_gtt_chipsets[i].gtt_driver;
1491 break;
1492 }
1493 }
1494
1495 if (!intel_private.driver)
1496 return 0;
1497
1498 bridge->driver = &intel_fake_agp_driver;
1499 bridge->dev_private_data = &intel_private;
1500 bridge->dev = pdev;
1501
1502 intel_private.bridge_dev = pci_dev_get(pdev);
1503
1504 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1505
1506 mask = intel_private.driver->dma_mask_size;
1507 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1508 dev_err(&intel_private.pcidev->dev,
1509 "set gfx device dma mask %d-bit failed!\n", mask);
1510 else
1511 pci_set_consistent_dma_mask(intel_private.pcidev,
1512 DMA_BIT_MASK(mask));
1513
1514 /*if (bridge->driver == &intel_810_driver)
1515 return 1;*/
1516
1517 if (intel_gtt_init() != 0)
1518 return 0;
1519
1520 return 1;
1521 }
1522 EXPORT_SYMBOL(intel_gmch_probe);
1523
1524 const struct intel_gtt *intel_gtt_get(void)
1525 {
1526 return &intel_private.base;
1527 }
1528 EXPORT_SYMBOL(intel_gtt_get);
1529
1530 void intel_gtt_chipset_flush(void)
1531 {
1532 if (intel_private.driver->chipset_flush)
1533 intel_private.driver->chipset_flush();
1534 }
1535 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1536
1537 void intel_gmch_remove(struct pci_dev *pdev)
1538 {
1539 if (intel_private.pcidev)
1540 pci_dev_put(intel_private.pcidev);
1541 if (intel_private.bridge_dev)
1542 pci_dev_put(intel_private.bridge_dev);
1543 }
1544 EXPORT_SYMBOL(intel_gmch_remove);
1545
1546 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1547 MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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