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drm/i915: remove intel_gtt structure
[deliverable/linux.git] / drivers / char / agp / intel-gtt.c
1 /*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <linux/delay.h>
25 #include <asm/smp.h>
26 #include "agp.h"
27 #include "intel-agp.h"
28 #include <drm/intel-gtt.h>
29
30 /*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
34 * Only newer chipsets need to bother with this, of course.
35 */
36 #ifdef CONFIG_INTEL_IOMMU
37 #define USE_PCI_DMA_API 1
38 #else
39 #define USE_PCI_DMA_API 0
40 #endif
41
42 struct intel_gtt_driver {
43 unsigned int gen : 8;
44 unsigned int is_g33 : 1;
45 unsigned int is_pineview : 1;
46 unsigned int is_ironlake : 1;
47 unsigned int has_pgtbl_enable : 1;
48 unsigned int dma_mask_size : 8;
49 /* Chipset specific GTT setup */
50 int (*setup)(void);
51 /* This should undo anything done in ->setup() save the unmapping
52 * of the mmio register file, that's done in the generic code. */
53 void (*cleanup)(void);
54 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
55 /* Flags is a more or less chipset specific opaque value.
56 * For chipsets that need to support old ums (non-gem) code, this
57 * needs to be identical to the various supported agp memory types! */
58 bool (*check_flags)(unsigned int flags);
59 void (*chipset_flush)(void);
60 };
61
62 static struct _intel_private {
63 const struct intel_gtt_driver *driver;
64 struct pci_dev *pcidev; /* device one */
65 struct pci_dev *bridge_dev;
66 u8 __iomem *registers;
67 phys_addr_t gtt_bus_addr;
68 u32 PGETBL_save;
69 u32 __iomem *gtt; /* I915G */
70 bool clear_fake_agp; /* on first access via agp, fill with scratch */
71 int num_dcache_entries;
72 void __iomem *i9xx_flush_page;
73 char *i81x_gtt_table;
74 struct resource ifp_resource;
75 int resource_valid;
76 struct page *scratch_page;
77 phys_addr_t scratch_page_dma;
78 int refcount;
79 /* Whether i915 needs to use the dmar apis or not. */
80 unsigned int needs_dmar : 1;
81 phys_addr_t gma_bus_addr;
82 /* Size of memory reserved for graphics by the BIOS */
83 unsigned int stolen_size;
84 /* Total number of gtt entries. */
85 unsigned int gtt_total_entries;
86 /* Part of the gtt that is mappable by the cpu, for those chips where
87 * this is not the full gtt. */
88 unsigned int gtt_mappable_entries;
89 } intel_private;
90
91 #define INTEL_GTT_GEN intel_private.driver->gen
92 #define IS_G33 intel_private.driver->is_g33
93 #define IS_PINEVIEW intel_private.driver->is_pineview
94 #define IS_IRONLAKE intel_private.driver->is_ironlake
95 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
96
97 static int intel_gtt_map_memory(struct page **pages,
98 unsigned int num_entries,
99 struct sg_table *st)
100 {
101 struct scatterlist *sg;
102 int i;
103
104 DBG("try mapping %lu pages\n", (unsigned long)num_entries);
105
106 if (sg_alloc_table(st, num_entries, GFP_KERNEL))
107 goto err;
108
109 for_each_sg(st->sgl, sg, num_entries, i)
110 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
111
112 if (!pci_map_sg(intel_private.pcidev,
113 st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL))
114 goto err;
115
116 return 0;
117
118 err:
119 sg_free_table(st);
120 return -ENOMEM;
121 }
122
123 static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
124 {
125 struct sg_table st;
126 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
127
128 pci_unmap_sg(intel_private.pcidev, sg_list,
129 num_sg, PCI_DMA_BIDIRECTIONAL);
130
131 st.sgl = sg_list;
132 st.orig_nents = st.nents = num_sg;
133
134 sg_free_table(&st);
135 }
136
137 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
138 {
139 return;
140 }
141
142 /* Exists to support ARGB cursors */
143 static struct page *i8xx_alloc_pages(void)
144 {
145 struct page *page;
146
147 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
148 if (page == NULL)
149 return NULL;
150
151 if (set_pages_uc(page, 4) < 0) {
152 set_pages_wb(page, 4);
153 __free_pages(page, 2);
154 return NULL;
155 }
156 get_page(page);
157 atomic_inc(&agp_bridge->current_memory_agp);
158 return page;
159 }
160
161 static void i8xx_destroy_pages(struct page *page)
162 {
163 if (page == NULL)
164 return;
165
166 set_pages_wb(page, 4);
167 put_page(page);
168 __free_pages(page, 2);
169 atomic_dec(&agp_bridge->current_memory_agp);
170 }
171
172 #define I810_GTT_ORDER 4
173 static int i810_setup(void)
174 {
175 u32 reg_addr;
176 char *gtt_table;
177
178 /* i81x does not preallocate the gtt. It's always 64kb in size. */
179 gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
180 if (gtt_table == NULL)
181 return -ENOMEM;
182 intel_private.i81x_gtt_table = gtt_table;
183
184 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
185 reg_addr &= 0xfff80000;
186
187 intel_private.registers = ioremap(reg_addr, KB(64));
188 if (!intel_private.registers)
189 return -ENOMEM;
190
191 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
192 intel_private.registers+I810_PGETBL_CTL);
193
194 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
195
196 if ((readl(intel_private.registers+I810_DRAM_CTL)
197 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
198 dev_info(&intel_private.pcidev->dev,
199 "detected 4MB dedicated video ram\n");
200 intel_private.num_dcache_entries = 1024;
201 }
202
203 return 0;
204 }
205
206 static void i810_cleanup(void)
207 {
208 writel(0, intel_private.registers+I810_PGETBL_CTL);
209 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
210 }
211
212 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
213 int type)
214 {
215 int i;
216
217 if ((pg_start + mem->page_count)
218 > intel_private.num_dcache_entries)
219 return -EINVAL;
220
221 if (!mem->is_flushed)
222 global_cache_flush();
223
224 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
225 dma_addr_t addr = i << PAGE_SHIFT;
226 intel_private.driver->write_entry(addr,
227 i, type);
228 }
229 readl(intel_private.gtt+i-1);
230
231 return 0;
232 }
233
234 /*
235 * The i810/i830 requires a physical address to program its mouse
236 * pointer into hardware.
237 * However the Xserver still writes to it through the agp aperture.
238 */
239 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
240 {
241 struct agp_memory *new;
242 struct page *page;
243
244 switch (pg_count) {
245 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
246 break;
247 case 4:
248 /* kludge to get 4 physical pages for ARGB cursor */
249 page = i8xx_alloc_pages();
250 break;
251 default:
252 return NULL;
253 }
254
255 if (page == NULL)
256 return NULL;
257
258 new = agp_create_memory(pg_count);
259 if (new == NULL)
260 return NULL;
261
262 new->pages[0] = page;
263 if (pg_count == 4) {
264 /* kludge to get 4 physical pages for ARGB cursor */
265 new->pages[1] = new->pages[0] + 1;
266 new->pages[2] = new->pages[1] + 1;
267 new->pages[3] = new->pages[2] + 1;
268 }
269 new->page_count = pg_count;
270 new->num_scratch_pages = pg_count;
271 new->type = AGP_PHYS_MEMORY;
272 new->physical = page_to_phys(new->pages[0]);
273 return new;
274 }
275
276 static void intel_i810_free_by_type(struct agp_memory *curr)
277 {
278 agp_free_key(curr->key);
279 if (curr->type == AGP_PHYS_MEMORY) {
280 if (curr->page_count == 4)
281 i8xx_destroy_pages(curr->pages[0]);
282 else {
283 agp_bridge->driver->agp_destroy_page(curr->pages[0],
284 AGP_PAGE_DESTROY_UNMAP);
285 agp_bridge->driver->agp_destroy_page(curr->pages[0],
286 AGP_PAGE_DESTROY_FREE);
287 }
288 agp_free_page_array(curr);
289 }
290 kfree(curr);
291 }
292
293 static int intel_gtt_setup_scratch_page(void)
294 {
295 struct page *page;
296 dma_addr_t dma_addr;
297
298 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
299 if (page == NULL)
300 return -ENOMEM;
301 get_page(page);
302 set_pages_uc(page, 1);
303
304 if (intel_private.needs_dmar) {
305 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
306 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
307 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
308 return -EINVAL;
309
310 intel_private.scratch_page_dma = dma_addr;
311 } else
312 intel_private.scratch_page_dma = page_to_phys(page);
313
314 intel_private.scratch_page = page;
315
316 return 0;
317 }
318
319 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
320 unsigned int flags)
321 {
322 u32 pte_flags = I810_PTE_VALID;
323
324 switch (flags) {
325 case AGP_DCACHE_MEMORY:
326 pte_flags |= I810_PTE_LOCAL;
327 break;
328 case AGP_USER_CACHED_MEMORY:
329 pte_flags |= I830_PTE_SYSTEM_CACHED;
330 break;
331 }
332
333 writel(addr | pte_flags, intel_private.gtt + entry);
334 }
335
336 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
337 {32, 8192, 3},
338 {64, 16384, 4},
339 {128, 32768, 5},
340 {256, 65536, 6},
341 {512, 131072, 7},
342 };
343
344 static unsigned int intel_gtt_stolen_size(void)
345 {
346 u16 gmch_ctrl;
347 u8 rdct;
348 int local = 0;
349 static const int ddt[4] = { 0, 16, 32, 64 };
350 unsigned int stolen_size = 0;
351
352 if (INTEL_GTT_GEN == 1)
353 return 0; /* no stolen mem on i81x */
354
355 pci_read_config_word(intel_private.bridge_dev,
356 I830_GMCH_CTRL, &gmch_ctrl);
357
358 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
359 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
360 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
361 case I830_GMCH_GMS_STOLEN_512:
362 stolen_size = KB(512);
363 break;
364 case I830_GMCH_GMS_STOLEN_1024:
365 stolen_size = MB(1);
366 break;
367 case I830_GMCH_GMS_STOLEN_8192:
368 stolen_size = MB(8);
369 break;
370 case I830_GMCH_GMS_LOCAL:
371 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
372 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
373 MB(ddt[I830_RDRAM_DDT(rdct)]);
374 local = 1;
375 break;
376 default:
377 stolen_size = 0;
378 break;
379 }
380 } else {
381 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
382 case I855_GMCH_GMS_STOLEN_1M:
383 stolen_size = MB(1);
384 break;
385 case I855_GMCH_GMS_STOLEN_4M:
386 stolen_size = MB(4);
387 break;
388 case I855_GMCH_GMS_STOLEN_8M:
389 stolen_size = MB(8);
390 break;
391 case I855_GMCH_GMS_STOLEN_16M:
392 stolen_size = MB(16);
393 break;
394 case I855_GMCH_GMS_STOLEN_32M:
395 stolen_size = MB(32);
396 break;
397 case I915_GMCH_GMS_STOLEN_48M:
398 stolen_size = MB(48);
399 break;
400 case I915_GMCH_GMS_STOLEN_64M:
401 stolen_size = MB(64);
402 break;
403 case G33_GMCH_GMS_STOLEN_128M:
404 stolen_size = MB(128);
405 break;
406 case G33_GMCH_GMS_STOLEN_256M:
407 stolen_size = MB(256);
408 break;
409 case INTEL_GMCH_GMS_STOLEN_96M:
410 stolen_size = MB(96);
411 break;
412 case INTEL_GMCH_GMS_STOLEN_160M:
413 stolen_size = MB(160);
414 break;
415 case INTEL_GMCH_GMS_STOLEN_224M:
416 stolen_size = MB(224);
417 break;
418 case INTEL_GMCH_GMS_STOLEN_352M:
419 stolen_size = MB(352);
420 break;
421 default:
422 stolen_size = 0;
423 break;
424 }
425 }
426
427 if (stolen_size > 0) {
428 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
429 stolen_size / KB(1), local ? "local" : "stolen");
430 } else {
431 dev_info(&intel_private.bridge_dev->dev,
432 "no pre-allocated video memory detected\n");
433 stolen_size = 0;
434 }
435
436 return stolen_size;
437 }
438
439 static void i965_adjust_pgetbl_size(unsigned int size_flag)
440 {
441 u32 pgetbl_ctl, pgetbl_ctl2;
442
443 /* ensure that ppgtt is disabled */
444 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
445 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
446 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
447
448 /* write the new ggtt size */
449 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
450 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
451 pgetbl_ctl |= size_flag;
452 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
453 }
454
455 static unsigned int i965_gtt_total_entries(void)
456 {
457 int size;
458 u32 pgetbl_ctl;
459 u16 gmch_ctl;
460
461 pci_read_config_word(intel_private.bridge_dev,
462 I830_GMCH_CTRL, &gmch_ctl);
463
464 if (INTEL_GTT_GEN == 5) {
465 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
466 case G4x_GMCH_SIZE_1M:
467 case G4x_GMCH_SIZE_VT_1M:
468 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
469 break;
470 case G4x_GMCH_SIZE_VT_1_5M:
471 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
472 break;
473 case G4x_GMCH_SIZE_2M:
474 case G4x_GMCH_SIZE_VT_2M:
475 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
476 break;
477 }
478 }
479
480 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
481
482 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
483 case I965_PGETBL_SIZE_128KB:
484 size = KB(128);
485 break;
486 case I965_PGETBL_SIZE_256KB:
487 size = KB(256);
488 break;
489 case I965_PGETBL_SIZE_512KB:
490 size = KB(512);
491 break;
492 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
493 case I965_PGETBL_SIZE_1MB:
494 size = KB(1024);
495 break;
496 case I965_PGETBL_SIZE_2MB:
497 size = KB(2048);
498 break;
499 case I965_PGETBL_SIZE_1_5MB:
500 size = KB(1024 + 512);
501 break;
502 default:
503 dev_info(&intel_private.pcidev->dev,
504 "unknown page table size, assuming 512KB\n");
505 size = KB(512);
506 }
507
508 return size/4;
509 }
510
511 static unsigned int intel_gtt_total_entries(void)
512 {
513 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
514 return i965_gtt_total_entries();
515 else {
516 /* On previous hardware, the GTT size was just what was
517 * required to map the aperture.
518 */
519 return intel_private.gtt_mappable_entries;
520 }
521 }
522
523 static unsigned int intel_gtt_mappable_entries(void)
524 {
525 unsigned int aperture_size;
526
527 if (INTEL_GTT_GEN == 1) {
528 u32 smram_miscc;
529
530 pci_read_config_dword(intel_private.bridge_dev,
531 I810_SMRAM_MISCC, &smram_miscc);
532
533 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
534 == I810_GFX_MEM_WIN_32M)
535 aperture_size = MB(32);
536 else
537 aperture_size = MB(64);
538 } else if (INTEL_GTT_GEN == 2) {
539 u16 gmch_ctrl;
540
541 pci_read_config_word(intel_private.bridge_dev,
542 I830_GMCH_CTRL, &gmch_ctrl);
543
544 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
545 aperture_size = MB(64);
546 else
547 aperture_size = MB(128);
548 } else {
549 /* 9xx supports large sizes, just look at the length */
550 aperture_size = pci_resource_len(intel_private.pcidev, 2);
551 }
552
553 return aperture_size >> PAGE_SHIFT;
554 }
555
556 static void intel_gtt_teardown_scratch_page(void)
557 {
558 set_pages_wb(intel_private.scratch_page, 1);
559 pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
560 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
561 put_page(intel_private.scratch_page);
562 __free_page(intel_private.scratch_page);
563 }
564
565 static void intel_gtt_cleanup(void)
566 {
567 intel_private.driver->cleanup();
568
569 iounmap(intel_private.gtt);
570 iounmap(intel_private.registers);
571
572 intel_gtt_teardown_scratch_page();
573 }
574
575 static int intel_gtt_init(void)
576 {
577 u32 gma_addr;
578 u32 gtt_map_size;
579 int ret;
580
581 ret = intel_private.driver->setup();
582 if (ret != 0)
583 return ret;
584
585 intel_private.gtt_mappable_entries = intel_gtt_mappable_entries();
586 intel_private.gtt_total_entries = intel_gtt_total_entries();
587
588 /* save the PGETBL reg for resume */
589 intel_private.PGETBL_save =
590 readl(intel_private.registers+I810_PGETBL_CTL)
591 & ~I810_PGETBL_ENABLED;
592 /* we only ever restore the register when enabling the PGTBL... */
593 if (HAS_PGTBL_EN)
594 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
595
596 dev_info(&intel_private.bridge_dev->dev,
597 "detected gtt size: %dK total, %dK mappable\n",
598 intel_private.gtt_total_entries * 4,
599 intel_private.gtt_mappable_entries * 4);
600
601 gtt_map_size = intel_private.gtt_total_entries * 4;
602
603 intel_private.gtt = NULL;
604 if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2)
605 intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
606 gtt_map_size);
607 if (intel_private.gtt == NULL)
608 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
609 gtt_map_size);
610 if (intel_private.gtt == NULL) {
611 intel_private.driver->cleanup();
612 iounmap(intel_private.registers);
613 return -ENOMEM;
614 }
615
616 global_cache_flush(); /* FIXME: ? */
617
618 intel_private.stolen_size = intel_gtt_stolen_size();
619
620 intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
621
622 ret = intel_gtt_setup_scratch_page();
623 if (ret != 0) {
624 intel_gtt_cleanup();
625 return ret;
626 }
627
628 if (INTEL_GTT_GEN <= 2)
629 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
630 &gma_addr);
631 else
632 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
633 &gma_addr);
634
635 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
636
637 return 0;
638 }
639
640 static int intel_fake_agp_fetch_size(void)
641 {
642 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
643 unsigned int aper_size;
644 int i;
645
646 aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1);
647
648 for (i = 0; i < num_sizes; i++) {
649 if (aper_size == intel_fake_agp_sizes[i].size) {
650 agp_bridge->current_size =
651 (void *) (intel_fake_agp_sizes + i);
652 return aper_size;
653 }
654 }
655
656 return 0;
657 }
658
659 static void i830_cleanup(void)
660 {
661 }
662
663 /* The chipset_flush interface needs to get data that has already been
664 * flushed out of the CPU all the way out to main memory, because the GPU
665 * doesn't snoop those buffers.
666 *
667 * The 8xx series doesn't have the same lovely interface for flushing the
668 * chipset write buffers that the later chips do. According to the 865
669 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
670 * that buffer out, we just fill 1KB and clflush it out, on the assumption
671 * that it'll push whatever was in there out. It appears to work.
672 */
673 static void i830_chipset_flush(void)
674 {
675 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
676
677 /* Forcibly evict everything from the CPU write buffers.
678 * clflush appears to be insufficient.
679 */
680 wbinvd_on_all_cpus();
681
682 /* Now we've only seen documents for this magic bit on 855GM,
683 * we hope it exists for the other gen2 chipsets...
684 *
685 * Also works as advertised on my 845G.
686 */
687 writel(readl(intel_private.registers+I830_HIC) | (1<<31),
688 intel_private.registers+I830_HIC);
689
690 while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
691 if (time_after(jiffies, timeout))
692 break;
693
694 udelay(50);
695 }
696 }
697
698 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
699 unsigned int flags)
700 {
701 u32 pte_flags = I810_PTE_VALID;
702
703 if (flags == AGP_USER_CACHED_MEMORY)
704 pte_flags |= I830_PTE_SYSTEM_CACHED;
705
706 writel(addr | pte_flags, intel_private.gtt + entry);
707 }
708
709 bool intel_enable_gtt(void)
710 {
711 u8 __iomem *reg;
712
713 if (INTEL_GTT_GEN == 2) {
714 u16 gmch_ctrl;
715
716 pci_read_config_word(intel_private.bridge_dev,
717 I830_GMCH_CTRL, &gmch_ctrl);
718 gmch_ctrl |= I830_GMCH_ENABLED;
719 pci_write_config_word(intel_private.bridge_dev,
720 I830_GMCH_CTRL, gmch_ctrl);
721
722 pci_read_config_word(intel_private.bridge_dev,
723 I830_GMCH_CTRL, &gmch_ctrl);
724 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
725 dev_err(&intel_private.pcidev->dev,
726 "failed to enable the GTT: GMCH_CTRL=%x\n",
727 gmch_ctrl);
728 return false;
729 }
730 }
731
732 /* On the resume path we may be adjusting the PGTBL value, so
733 * be paranoid and flush all chipset write buffers...
734 */
735 if (INTEL_GTT_GEN >= 3)
736 writel(0, intel_private.registers+GFX_FLSH_CNTL);
737
738 reg = intel_private.registers+I810_PGETBL_CTL;
739 writel(intel_private.PGETBL_save, reg);
740 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
741 dev_err(&intel_private.pcidev->dev,
742 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
743 readl(reg), intel_private.PGETBL_save);
744 return false;
745 }
746
747 if (INTEL_GTT_GEN >= 3)
748 writel(0, intel_private.registers+GFX_FLSH_CNTL);
749
750 return true;
751 }
752 EXPORT_SYMBOL(intel_enable_gtt);
753
754 static int i830_setup(void)
755 {
756 u32 reg_addr;
757
758 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
759 reg_addr &= 0xfff80000;
760
761 intel_private.registers = ioremap(reg_addr, KB(64));
762 if (!intel_private.registers)
763 return -ENOMEM;
764
765 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
766
767 return 0;
768 }
769
770 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
771 {
772 agp_bridge->gatt_table_real = NULL;
773 agp_bridge->gatt_table = NULL;
774 agp_bridge->gatt_bus_addr = 0;
775
776 return 0;
777 }
778
779 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
780 {
781 return 0;
782 }
783
784 static int intel_fake_agp_configure(void)
785 {
786 if (!intel_enable_gtt())
787 return -EIO;
788
789 intel_private.clear_fake_agp = true;
790 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
791
792 return 0;
793 }
794
795 static bool i830_check_flags(unsigned int flags)
796 {
797 switch (flags) {
798 case 0:
799 case AGP_PHYS_MEMORY:
800 case AGP_USER_CACHED_MEMORY:
801 case AGP_USER_MEMORY:
802 return true;
803 }
804
805 return false;
806 }
807
808 void intel_gtt_insert_sg_entries(struct sg_table *st,
809 unsigned int pg_start,
810 unsigned int flags)
811 {
812 struct scatterlist *sg;
813 unsigned int len, m;
814 int i, j;
815
816 j = pg_start;
817
818 /* sg may merge pages, but we have to separate
819 * per-page addr for GTT */
820 for_each_sg(st->sgl, sg, st->nents, i) {
821 len = sg_dma_len(sg) >> PAGE_SHIFT;
822 for (m = 0; m < len; m++) {
823 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
824 intel_private.driver->write_entry(addr, j, flags);
825 j++;
826 }
827 }
828 readl(intel_private.gtt+j-1);
829 }
830 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
831
832 static void intel_gtt_insert_pages(unsigned int first_entry,
833 unsigned int num_entries,
834 struct page **pages,
835 unsigned int flags)
836 {
837 int i, j;
838
839 for (i = 0, j = first_entry; i < num_entries; i++, j++) {
840 dma_addr_t addr = page_to_phys(pages[i]);
841 intel_private.driver->write_entry(addr,
842 j, flags);
843 }
844 readl(intel_private.gtt+j-1);
845 }
846
847 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
848 off_t pg_start, int type)
849 {
850 int ret = -EINVAL;
851
852 if (intel_private.clear_fake_agp) {
853 int start = intel_private.stolen_size / PAGE_SIZE;
854 int end = intel_private.gtt_mappable_entries;
855 intel_gtt_clear_range(start, end - start);
856 intel_private.clear_fake_agp = false;
857 }
858
859 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
860 return i810_insert_dcache_entries(mem, pg_start, type);
861
862 if (mem->page_count == 0)
863 goto out;
864
865 if (pg_start + mem->page_count > intel_private.gtt_total_entries)
866 goto out_err;
867
868 if (type != mem->type)
869 goto out_err;
870
871 if (!intel_private.driver->check_flags(type))
872 goto out_err;
873
874 if (!mem->is_flushed)
875 global_cache_flush();
876
877 if (intel_private.needs_dmar) {
878 struct sg_table st;
879
880 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
881 if (ret != 0)
882 return ret;
883
884 intel_gtt_insert_sg_entries(&st, pg_start, type);
885 mem->sg_list = st.sgl;
886 mem->num_sg = st.nents;
887 } else
888 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
889 type);
890
891 out:
892 ret = 0;
893 out_err:
894 mem->is_flushed = true;
895 return ret;
896 }
897
898 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
899 {
900 unsigned int i;
901
902 for (i = first_entry; i < (first_entry + num_entries); i++) {
903 intel_private.driver->write_entry(intel_private.scratch_page_dma,
904 i, 0);
905 }
906 readl(intel_private.gtt+i-1);
907 }
908 EXPORT_SYMBOL(intel_gtt_clear_range);
909
910 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
911 off_t pg_start, int type)
912 {
913 if (mem->page_count == 0)
914 return 0;
915
916 intel_gtt_clear_range(pg_start, mem->page_count);
917
918 if (intel_private.needs_dmar) {
919 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
920 mem->sg_list = NULL;
921 mem->num_sg = 0;
922 }
923
924 return 0;
925 }
926
927 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
928 int type)
929 {
930 struct agp_memory *new;
931
932 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
933 if (pg_count != intel_private.num_dcache_entries)
934 return NULL;
935
936 new = agp_create_memory(1);
937 if (new == NULL)
938 return NULL;
939
940 new->type = AGP_DCACHE_MEMORY;
941 new->page_count = pg_count;
942 new->num_scratch_pages = 0;
943 agp_free_page_array(new);
944 return new;
945 }
946 if (type == AGP_PHYS_MEMORY)
947 return alloc_agpphysmem_i8xx(pg_count, type);
948 /* always return NULL for other allocation types for now */
949 return NULL;
950 }
951
952 static int intel_alloc_chipset_flush_resource(void)
953 {
954 int ret;
955 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
956 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
957 pcibios_align_resource, intel_private.bridge_dev);
958
959 return ret;
960 }
961
962 static void intel_i915_setup_chipset_flush(void)
963 {
964 int ret;
965 u32 temp;
966
967 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
968 if (!(temp & 0x1)) {
969 intel_alloc_chipset_flush_resource();
970 intel_private.resource_valid = 1;
971 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
972 } else {
973 temp &= ~1;
974
975 intel_private.resource_valid = 1;
976 intel_private.ifp_resource.start = temp;
977 intel_private.ifp_resource.end = temp + PAGE_SIZE;
978 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
979 /* some BIOSes reserve this area in a pnp some don't */
980 if (ret)
981 intel_private.resource_valid = 0;
982 }
983 }
984
985 static void intel_i965_g33_setup_chipset_flush(void)
986 {
987 u32 temp_hi, temp_lo;
988 int ret;
989
990 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
991 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
992
993 if (!(temp_lo & 0x1)) {
994
995 intel_alloc_chipset_flush_resource();
996
997 intel_private.resource_valid = 1;
998 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
999 upper_32_bits(intel_private.ifp_resource.start));
1000 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1001 } else {
1002 u64 l64;
1003
1004 temp_lo &= ~0x1;
1005 l64 = ((u64)temp_hi << 32) | temp_lo;
1006
1007 intel_private.resource_valid = 1;
1008 intel_private.ifp_resource.start = l64;
1009 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1010 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1011 /* some BIOSes reserve this area in a pnp some don't */
1012 if (ret)
1013 intel_private.resource_valid = 0;
1014 }
1015 }
1016
1017 static void intel_i9xx_setup_flush(void)
1018 {
1019 /* return if already configured */
1020 if (intel_private.ifp_resource.start)
1021 return;
1022
1023 if (INTEL_GTT_GEN == 6)
1024 return;
1025
1026 /* setup a resource for this object */
1027 intel_private.ifp_resource.name = "Intel Flush Page";
1028 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1029
1030 /* Setup chipset flush for 915 */
1031 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1032 intel_i965_g33_setup_chipset_flush();
1033 } else {
1034 intel_i915_setup_chipset_flush();
1035 }
1036
1037 if (intel_private.ifp_resource.start)
1038 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1039 if (!intel_private.i9xx_flush_page)
1040 dev_err(&intel_private.pcidev->dev,
1041 "can't ioremap flush page - no chipset flushing\n");
1042 }
1043
1044 static void i9xx_cleanup(void)
1045 {
1046 if (intel_private.i9xx_flush_page)
1047 iounmap(intel_private.i9xx_flush_page);
1048 if (intel_private.resource_valid)
1049 release_resource(&intel_private.ifp_resource);
1050 intel_private.ifp_resource.start = 0;
1051 intel_private.resource_valid = 0;
1052 }
1053
1054 static void i9xx_chipset_flush(void)
1055 {
1056 if (intel_private.i9xx_flush_page)
1057 writel(1, intel_private.i9xx_flush_page);
1058 }
1059
1060 static void i965_write_entry(dma_addr_t addr,
1061 unsigned int entry,
1062 unsigned int flags)
1063 {
1064 u32 pte_flags;
1065
1066 pte_flags = I810_PTE_VALID;
1067 if (flags == AGP_USER_CACHED_MEMORY)
1068 pte_flags |= I830_PTE_SYSTEM_CACHED;
1069
1070 /* Shift high bits down */
1071 addr |= (addr >> 28) & 0xf0;
1072 writel(addr | pte_flags, intel_private.gtt + entry);
1073 }
1074
1075
1076 static int i9xx_setup(void)
1077 {
1078 u32 reg_addr, gtt_addr;
1079 int size = KB(512);
1080
1081 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1082
1083 reg_addr &= 0xfff80000;
1084
1085 intel_private.registers = ioremap(reg_addr, size);
1086 if (!intel_private.registers)
1087 return -ENOMEM;
1088
1089 switch (INTEL_GTT_GEN) {
1090 case 3:
1091 pci_read_config_dword(intel_private.pcidev,
1092 I915_PTEADDR, &gtt_addr);
1093 intel_private.gtt_bus_addr = gtt_addr;
1094 break;
1095 case 5:
1096 intel_private.gtt_bus_addr = reg_addr + MB(2);
1097 break;
1098 default:
1099 intel_private.gtt_bus_addr = reg_addr + KB(512);
1100 break;
1101 }
1102
1103 intel_i9xx_setup_flush();
1104
1105 return 0;
1106 }
1107
1108 static const struct agp_bridge_driver intel_fake_agp_driver = {
1109 .owner = THIS_MODULE,
1110 .size_type = FIXED_APER_SIZE,
1111 .aperture_sizes = intel_fake_agp_sizes,
1112 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1113 .configure = intel_fake_agp_configure,
1114 .fetch_size = intel_fake_agp_fetch_size,
1115 .cleanup = intel_gtt_cleanup,
1116 .agp_enable = intel_fake_agp_enable,
1117 .cache_flush = global_cache_flush,
1118 .create_gatt_table = intel_fake_agp_create_gatt_table,
1119 .free_gatt_table = intel_fake_agp_free_gatt_table,
1120 .insert_memory = intel_fake_agp_insert_entries,
1121 .remove_memory = intel_fake_agp_remove_entries,
1122 .alloc_by_type = intel_fake_agp_alloc_by_type,
1123 .free_by_type = intel_i810_free_by_type,
1124 .agp_alloc_page = agp_generic_alloc_page,
1125 .agp_alloc_pages = agp_generic_alloc_pages,
1126 .agp_destroy_page = agp_generic_destroy_page,
1127 .agp_destroy_pages = agp_generic_destroy_pages,
1128 };
1129
1130 static const struct intel_gtt_driver i81x_gtt_driver = {
1131 .gen = 1,
1132 .has_pgtbl_enable = 1,
1133 .dma_mask_size = 32,
1134 .setup = i810_setup,
1135 .cleanup = i810_cleanup,
1136 .check_flags = i830_check_flags,
1137 .write_entry = i810_write_entry,
1138 };
1139 static const struct intel_gtt_driver i8xx_gtt_driver = {
1140 .gen = 2,
1141 .has_pgtbl_enable = 1,
1142 .setup = i830_setup,
1143 .cleanup = i830_cleanup,
1144 .write_entry = i830_write_entry,
1145 .dma_mask_size = 32,
1146 .check_flags = i830_check_flags,
1147 .chipset_flush = i830_chipset_flush,
1148 };
1149 static const struct intel_gtt_driver i915_gtt_driver = {
1150 .gen = 3,
1151 .has_pgtbl_enable = 1,
1152 .setup = i9xx_setup,
1153 .cleanup = i9xx_cleanup,
1154 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1155 .write_entry = i830_write_entry,
1156 .dma_mask_size = 32,
1157 .check_flags = i830_check_flags,
1158 .chipset_flush = i9xx_chipset_flush,
1159 };
1160 static const struct intel_gtt_driver g33_gtt_driver = {
1161 .gen = 3,
1162 .is_g33 = 1,
1163 .setup = i9xx_setup,
1164 .cleanup = i9xx_cleanup,
1165 .write_entry = i965_write_entry,
1166 .dma_mask_size = 36,
1167 .check_flags = i830_check_flags,
1168 .chipset_flush = i9xx_chipset_flush,
1169 };
1170 static const struct intel_gtt_driver pineview_gtt_driver = {
1171 .gen = 3,
1172 .is_pineview = 1, .is_g33 = 1,
1173 .setup = i9xx_setup,
1174 .cleanup = i9xx_cleanup,
1175 .write_entry = i965_write_entry,
1176 .dma_mask_size = 36,
1177 .check_flags = i830_check_flags,
1178 .chipset_flush = i9xx_chipset_flush,
1179 };
1180 static const struct intel_gtt_driver i965_gtt_driver = {
1181 .gen = 4,
1182 .has_pgtbl_enable = 1,
1183 .setup = i9xx_setup,
1184 .cleanup = i9xx_cleanup,
1185 .write_entry = i965_write_entry,
1186 .dma_mask_size = 36,
1187 .check_flags = i830_check_flags,
1188 .chipset_flush = i9xx_chipset_flush,
1189 };
1190 static const struct intel_gtt_driver g4x_gtt_driver = {
1191 .gen = 5,
1192 .setup = i9xx_setup,
1193 .cleanup = i9xx_cleanup,
1194 .write_entry = i965_write_entry,
1195 .dma_mask_size = 36,
1196 .check_flags = i830_check_flags,
1197 .chipset_flush = i9xx_chipset_flush,
1198 };
1199 static const struct intel_gtt_driver ironlake_gtt_driver = {
1200 .gen = 5,
1201 .is_ironlake = 1,
1202 .setup = i9xx_setup,
1203 .cleanup = i9xx_cleanup,
1204 .write_entry = i965_write_entry,
1205 .dma_mask_size = 36,
1206 .check_flags = i830_check_flags,
1207 .chipset_flush = i9xx_chipset_flush,
1208 };
1209
1210 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1211 * driver and gmch_driver must be non-null, and find_gmch will determine
1212 * which one should be used if a gmch_chip_id is present.
1213 */
1214 static const struct intel_gtt_driver_description {
1215 unsigned int gmch_chip_id;
1216 char *name;
1217 const struct intel_gtt_driver *gtt_driver;
1218 } intel_gtt_chipsets[] = {
1219 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1220 &i81x_gtt_driver},
1221 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1222 &i81x_gtt_driver},
1223 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1224 &i81x_gtt_driver},
1225 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1226 &i81x_gtt_driver},
1227 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1228 &i8xx_gtt_driver},
1229 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1230 &i8xx_gtt_driver},
1231 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1232 &i8xx_gtt_driver},
1233 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1234 &i8xx_gtt_driver},
1235 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1236 &i8xx_gtt_driver},
1237 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1238 &i915_gtt_driver },
1239 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1240 &i915_gtt_driver },
1241 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1242 &i915_gtt_driver },
1243 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1244 &i915_gtt_driver },
1245 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1246 &i915_gtt_driver },
1247 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1248 &i915_gtt_driver },
1249 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1250 &i965_gtt_driver },
1251 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1252 &i965_gtt_driver },
1253 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1254 &i965_gtt_driver },
1255 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1256 &i965_gtt_driver },
1257 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1258 &i965_gtt_driver },
1259 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1260 &i965_gtt_driver },
1261 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1262 &g33_gtt_driver },
1263 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1264 &g33_gtt_driver },
1265 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1266 &g33_gtt_driver },
1267 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1268 &pineview_gtt_driver },
1269 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1270 &pineview_gtt_driver },
1271 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1272 &g4x_gtt_driver },
1273 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1274 &g4x_gtt_driver },
1275 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1276 &g4x_gtt_driver },
1277 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1278 &g4x_gtt_driver },
1279 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1280 &g4x_gtt_driver },
1281 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1282 &g4x_gtt_driver },
1283 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1284 &g4x_gtt_driver },
1285 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1286 "HD Graphics", &ironlake_gtt_driver },
1287 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1288 "HD Graphics", &ironlake_gtt_driver },
1289 { 0, NULL, NULL }
1290 };
1291
1292 static int find_gmch(u16 device)
1293 {
1294 struct pci_dev *gmch_device;
1295
1296 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1297 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1298 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1299 device, gmch_device);
1300 }
1301
1302 if (!gmch_device)
1303 return 0;
1304
1305 intel_private.pcidev = gmch_device;
1306 return 1;
1307 }
1308
1309 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1310 struct agp_bridge_data *bridge)
1311 {
1312 int i, mask;
1313
1314 /*
1315 * Can be called from the fake agp driver but also directly from
1316 * drm/i915.ko. Hence we need to check whether everything is set up
1317 * already.
1318 */
1319 if (intel_private.driver) {
1320 intel_private.refcount++;
1321 return 1;
1322 }
1323
1324 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1325 if (gpu_pdev) {
1326 if (gpu_pdev->device ==
1327 intel_gtt_chipsets[i].gmch_chip_id) {
1328 intel_private.pcidev = pci_dev_get(gpu_pdev);
1329 intel_private.driver =
1330 intel_gtt_chipsets[i].gtt_driver;
1331
1332 break;
1333 }
1334 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1335 intel_private.driver =
1336 intel_gtt_chipsets[i].gtt_driver;
1337 break;
1338 }
1339 }
1340
1341 if (!intel_private.driver)
1342 return 0;
1343
1344 intel_private.refcount++;
1345
1346 if (bridge) {
1347 bridge->driver = &intel_fake_agp_driver;
1348 bridge->dev_private_data = &intel_private;
1349 bridge->dev = bridge_pdev;
1350 }
1351
1352 intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1353
1354 dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1355
1356 mask = intel_private.driver->dma_mask_size;
1357 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1358 dev_err(&intel_private.pcidev->dev,
1359 "set gfx device dma mask %d-bit failed!\n", mask);
1360 else
1361 pci_set_consistent_dma_mask(intel_private.pcidev,
1362 DMA_BIT_MASK(mask));
1363
1364 if (intel_gtt_init() != 0) {
1365 intel_gmch_remove();
1366
1367 return 0;
1368 }
1369
1370 return 1;
1371 }
1372 EXPORT_SYMBOL(intel_gmch_probe);
1373
1374 void intel_gtt_get(size_t *gtt_total, size_t *stolen_size)
1375 {
1376 *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
1377 *stolen_size = intel_private.stolen_size;
1378 }
1379 EXPORT_SYMBOL(intel_gtt_get);
1380
1381 void intel_gtt_chipset_flush(void)
1382 {
1383 if (intel_private.driver->chipset_flush)
1384 intel_private.driver->chipset_flush();
1385 }
1386 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1387
1388 void intel_gmch_remove(void)
1389 {
1390 if (--intel_private.refcount)
1391 return;
1392
1393 if (intel_private.pcidev)
1394 pci_dev_put(intel_private.pcidev);
1395 if (intel_private.bridge_dev)
1396 pci_dev_put(intel_private.bridge_dev);
1397 intel_private.driver = NULL;
1398 }
1399 EXPORT_SYMBOL(intel_gmch_remove);
1400
1401 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1402 MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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