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intel-gtt: store the dma mask size in intel_gtt_driver
[deliverable/linux.git] / drivers / char / agp / intel-gtt.c
1 /*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <asm/smp.h>
25 #include "agp.h"
26 #include "intel-agp.h"
27 #include <linux/intel-gtt.h>
28 #include <drm/intel-gtt.h>
29
30 /*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_DMAR).
34 * Only newer chipsets need to bother with this, of course.
35 */
36 #ifdef CONFIG_DMAR
37 #define USE_PCI_DMA_API 1
38 #else
39 #define USE_PCI_DMA_API 0
40 #endif
41
42 /* Max amount of stolen space, anything above will be returned to Linux */
43 int intel_max_stolen = 32 * 1024 * 1024;
44
45 static const struct aper_size_info_fixed intel_i810_sizes[] =
46 {
47 {64, 16384, 4},
48 /* The 32M mode still requires a 64k gatt */
49 {32, 8192, 4}
50 };
51
52 #define AGP_DCACHE_MEMORY 1
53 #define AGP_PHYS_MEMORY 2
54 #define INTEL_AGP_CACHED_MEMORY 3
55
56 static struct gatt_mask intel_i810_masks[] =
57 {
58 {.mask = I810_PTE_VALID, .type = 0},
59 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
60 {.mask = I810_PTE_VALID, .type = 0},
61 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
62 .type = INTEL_AGP_CACHED_MEMORY}
63 };
64
65 #define INTEL_AGP_UNCACHED_MEMORY 0
66 #define INTEL_AGP_CACHED_MEMORY_LLC 1
67 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
68 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
69 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
70
71 struct intel_gtt_driver {
72 unsigned int gen : 8;
73 unsigned int is_g33 : 1;
74 unsigned int is_pineview : 1;
75 unsigned int is_ironlake : 1;
76 unsigned int dma_mask_size : 8;
77 /* Chipset specific GTT setup */
78 int (*setup)(void);
79 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
80 /* Flags is a more or less chipset specific opaque value.
81 * For chipsets that need to support old ums (non-gem) code, this
82 * needs to be identical to the various supported agp memory types! */
83 bool (*check_flags)(unsigned int flags);
84 void (*chipset_flush)(void);
85 };
86
87 static struct _intel_private {
88 struct intel_gtt base;
89 const struct intel_gtt_driver *driver;
90 struct pci_dev *pcidev; /* device one */
91 struct pci_dev *bridge_dev;
92 u8 __iomem *registers;
93 phys_addr_t gtt_bus_addr;
94 phys_addr_t gma_bus_addr;
95 phys_addr_t pte_bus_addr;
96 u32 __iomem *gtt; /* I915G */
97 int num_dcache_entries;
98 union {
99 void __iomem *i9xx_flush_page;
100 void *i8xx_flush_page;
101 };
102 struct page *i8xx_page;
103 struct resource ifp_resource;
104 int resource_valid;
105 struct page *scratch_page;
106 dma_addr_t scratch_page_dma;
107 } intel_private;
108
109 #define INTEL_GTT_GEN intel_private.driver->gen
110 #define IS_G33 intel_private.driver->is_g33
111 #define IS_PINEVIEW intel_private.driver->is_pineview
112 #define IS_IRONLAKE intel_private.driver->is_ironlake
113
114 static void intel_agp_free_sglist(struct agp_memory *mem)
115 {
116 struct sg_table st;
117
118 st.sgl = mem->sg_list;
119 st.orig_nents = st.nents = mem->page_count;
120
121 sg_free_table(&st);
122
123 mem->sg_list = NULL;
124 mem->num_sg = 0;
125 }
126
127 static int intel_agp_map_memory(struct agp_memory *mem)
128 {
129 struct sg_table st;
130 struct scatterlist *sg;
131 int i;
132
133 if (mem->sg_list)
134 return 0; /* already mapped (for e.g. resume */
135
136 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
137
138 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
139 goto err;
140
141 mem->sg_list = sg = st.sgl;
142
143 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
144 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
145
146 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
147 mem->page_count, PCI_DMA_BIDIRECTIONAL);
148 if (unlikely(!mem->num_sg))
149 goto err;
150
151 return 0;
152
153 err:
154 sg_free_table(&st);
155 return -ENOMEM;
156 }
157
158 static void intel_agp_unmap_memory(struct agp_memory *mem)
159 {
160 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
161
162 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
163 mem->page_count, PCI_DMA_BIDIRECTIONAL);
164 intel_agp_free_sglist(mem);
165 }
166
167 static int intel_i810_fetch_size(void)
168 {
169 u32 smram_miscc;
170 struct aper_size_info_fixed *values;
171
172 pci_read_config_dword(intel_private.bridge_dev,
173 I810_SMRAM_MISCC, &smram_miscc);
174 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
175
176 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
177 dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
178 return 0;
179 }
180 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
181 agp_bridge->current_size = (void *) (values + 1);
182 agp_bridge->aperture_size_idx = 1;
183 return values[1].size;
184 } else {
185 agp_bridge->current_size = (void *) (values);
186 agp_bridge->aperture_size_idx = 0;
187 return values[0].size;
188 }
189
190 return 0;
191 }
192
193 static int intel_i810_configure(void)
194 {
195 struct aper_size_info_fixed *current_size;
196 u32 temp;
197 int i;
198
199 current_size = A_SIZE_FIX(agp_bridge->current_size);
200
201 if (!intel_private.registers) {
202 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
203 temp &= 0xfff80000;
204
205 intel_private.registers = ioremap(temp, 128 * 4096);
206 if (!intel_private.registers) {
207 dev_err(&intel_private.pcidev->dev,
208 "can't remap memory\n");
209 return -ENOMEM;
210 }
211 }
212
213 if ((readl(intel_private.registers+I810_DRAM_CTL)
214 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
215 /* This will need to be dynamically assigned */
216 dev_info(&intel_private.pcidev->dev,
217 "detected 4MB dedicated video ram\n");
218 intel_private.num_dcache_entries = 1024;
219 }
220 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
221 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
222 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
223 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
224
225 if (agp_bridge->driver->needs_scratch_page) {
226 for (i = 0; i < current_size->num_entries; i++) {
227 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
228 }
229 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
230 }
231 global_cache_flush();
232 return 0;
233 }
234
235 static void intel_i810_cleanup(void)
236 {
237 writel(0, intel_private.registers+I810_PGETBL_CTL);
238 readl(intel_private.registers); /* PCI Posting. */
239 iounmap(intel_private.registers);
240 }
241
242 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
243 {
244 return;
245 }
246
247 /* Exists to support ARGB cursors */
248 static struct page *i8xx_alloc_pages(void)
249 {
250 struct page *page;
251
252 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
253 if (page == NULL)
254 return NULL;
255
256 if (set_pages_uc(page, 4) < 0) {
257 set_pages_wb(page, 4);
258 __free_pages(page, 2);
259 return NULL;
260 }
261 get_page(page);
262 atomic_inc(&agp_bridge->current_memory_agp);
263 return page;
264 }
265
266 static void i8xx_destroy_pages(struct page *page)
267 {
268 if (page == NULL)
269 return;
270
271 set_pages_wb(page, 4);
272 put_page(page);
273 __free_pages(page, 2);
274 atomic_dec(&agp_bridge->current_memory_agp);
275 }
276
277 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
278 int type)
279 {
280 int i, j, num_entries;
281 void *temp;
282 int ret = -EINVAL;
283 int mask_type;
284
285 if (mem->page_count == 0)
286 goto out;
287
288 temp = agp_bridge->current_size;
289 num_entries = A_SIZE_FIX(temp)->num_entries;
290
291 if ((pg_start + mem->page_count) > num_entries)
292 goto out_err;
293
294
295 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
296 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
297 ret = -EBUSY;
298 goto out_err;
299 }
300 }
301
302 if (type != mem->type)
303 goto out_err;
304
305 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
306
307 switch (mask_type) {
308 case AGP_DCACHE_MEMORY:
309 if (!mem->is_flushed)
310 global_cache_flush();
311 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
312 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
313 intel_private.registers+I810_PTE_BASE+(i*4));
314 }
315 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
316 break;
317 case AGP_PHYS_MEMORY:
318 case AGP_NORMAL_MEMORY:
319 if (!mem->is_flushed)
320 global_cache_flush();
321 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
322 writel(agp_bridge->driver->mask_memory(agp_bridge,
323 page_to_phys(mem->pages[i]), mask_type),
324 intel_private.registers+I810_PTE_BASE+(j*4));
325 }
326 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
327 break;
328 default:
329 goto out_err;
330 }
331
332 out:
333 ret = 0;
334 out_err:
335 mem->is_flushed = true;
336 return ret;
337 }
338
339 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
340 int type)
341 {
342 int i;
343
344 if (mem->page_count == 0)
345 return 0;
346
347 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
348 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
349 }
350 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
351
352 return 0;
353 }
354
355 /*
356 * The i810/i830 requires a physical address to program its mouse
357 * pointer into hardware.
358 * However the Xserver still writes to it through the agp aperture.
359 */
360 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
361 {
362 struct agp_memory *new;
363 struct page *page;
364
365 switch (pg_count) {
366 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
367 break;
368 case 4:
369 /* kludge to get 4 physical pages for ARGB cursor */
370 page = i8xx_alloc_pages();
371 break;
372 default:
373 return NULL;
374 }
375
376 if (page == NULL)
377 return NULL;
378
379 new = agp_create_memory(pg_count);
380 if (new == NULL)
381 return NULL;
382
383 new->pages[0] = page;
384 if (pg_count == 4) {
385 /* kludge to get 4 physical pages for ARGB cursor */
386 new->pages[1] = new->pages[0] + 1;
387 new->pages[2] = new->pages[1] + 1;
388 new->pages[3] = new->pages[2] + 1;
389 }
390 new->page_count = pg_count;
391 new->num_scratch_pages = pg_count;
392 new->type = AGP_PHYS_MEMORY;
393 new->physical = page_to_phys(new->pages[0]);
394 return new;
395 }
396
397 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
398 {
399 struct agp_memory *new;
400
401 if (type == AGP_DCACHE_MEMORY) {
402 if (pg_count != intel_private.num_dcache_entries)
403 return NULL;
404
405 new = agp_create_memory(1);
406 if (new == NULL)
407 return NULL;
408
409 new->type = AGP_DCACHE_MEMORY;
410 new->page_count = pg_count;
411 new->num_scratch_pages = 0;
412 agp_free_page_array(new);
413 return new;
414 }
415 if (type == AGP_PHYS_MEMORY)
416 return alloc_agpphysmem_i8xx(pg_count, type);
417 return NULL;
418 }
419
420 static void intel_i810_free_by_type(struct agp_memory *curr)
421 {
422 agp_free_key(curr->key);
423 if (curr->type == AGP_PHYS_MEMORY) {
424 if (curr->page_count == 4)
425 i8xx_destroy_pages(curr->pages[0]);
426 else {
427 agp_bridge->driver->agp_destroy_page(curr->pages[0],
428 AGP_PAGE_DESTROY_UNMAP);
429 agp_bridge->driver->agp_destroy_page(curr->pages[0],
430 AGP_PAGE_DESTROY_FREE);
431 }
432 agp_free_page_array(curr);
433 }
434 kfree(curr);
435 }
436
437 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
438 dma_addr_t addr, int type)
439 {
440 /* Type checking must be done elsewhere */
441 return addr | bridge->driver->masks[type].mask;
442 }
443
444 static int intel_gtt_setup_scratch_page(void)
445 {
446 struct page *page;
447 dma_addr_t dma_addr;
448
449 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
450 if (page == NULL)
451 return -ENOMEM;
452 get_page(page);
453 set_pages_uc(page, 1);
454
455 if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) {
456 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
457 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
458 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
459 return -EINVAL;
460
461 intel_private.scratch_page_dma = dma_addr;
462 } else
463 intel_private.scratch_page_dma = page_to_phys(page);
464
465 intel_private.scratch_page = page;
466
467 return 0;
468 }
469
470 static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = {
471 {128, 32768, 5},
472 /* The 64M mode still requires a 128k gatt */
473 {64, 16384, 5},
474 {256, 65536, 6},
475 {512, 131072, 7},
476 };
477
478 static unsigned int intel_gtt_stolen_entries(void)
479 {
480 u16 gmch_ctrl;
481 u8 rdct;
482 int local = 0;
483 static const int ddt[4] = { 0, 16, 32, 64 };
484 unsigned int overhead_entries, stolen_entries;
485 unsigned int stolen_size = 0;
486
487 pci_read_config_word(intel_private.bridge_dev,
488 I830_GMCH_CTRL, &gmch_ctrl);
489
490 if (INTEL_GTT_GEN > 4 || IS_PINEVIEW)
491 overhead_entries = 0;
492 else
493 overhead_entries = intel_private.base.gtt_mappable_entries
494 / 1024;
495
496 overhead_entries += 1; /* BIOS popup */
497
498 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
499 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
500 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
501 case I830_GMCH_GMS_STOLEN_512:
502 stolen_size = KB(512);
503 break;
504 case I830_GMCH_GMS_STOLEN_1024:
505 stolen_size = MB(1);
506 break;
507 case I830_GMCH_GMS_STOLEN_8192:
508 stolen_size = MB(8);
509 break;
510 case I830_GMCH_GMS_LOCAL:
511 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
512 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
513 MB(ddt[I830_RDRAM_DDT(rdct)]);
514 local = 1;
515 break;
516 default:
517 stolen_size = 0;
518 break;
519 }
520 } else if (INTEL_GTT_GEN == 6) {
521 /*
522 * SandyBridge has new memory control reg at 0x50.w
523 */
524 u16 snb_gmch_ctl;
525 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
526 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
527 case SNB_GMCH_GMS_STOLEN_32M:
528 stolen_size = MB(32);
529 break;
530 case SNB_GMCH_GMS_STOLEN_64M:
531 stolen_size = MB(64);
532 break;
533 case SNB_GMCH_GMS_STOLEN_96M:
534 stolen_size = MB(96);
535 break;
536 case SNB_GMCH_GMS_STOLEN_128M:
537 stolen_size = MB(128);
538 break;
539 case SNB_GMCH_GMS_STOLEN_160M:
540 stolen_size = MB(160);
541 break;
542 case SNB_GMCH_GMS_STOLEN_192M:
543 stolen_size = MB(192);
544 break;
545 case SNB_GMCH_GMS_STOLEN_224M:
546 stolen_size = MB(224);
547 break;
548 case SNB_GMCH_GMS_STOLEN_256M:
549 stolen_size = MB(256);
550 break;
551 case SNB_GMCH_GMS_STOLEN_288M:
552 stolen_size = MB(288);
553 break;
554 case SNB_GMCH_GMS_STOLEN_320M:
555 stolen_size = MB(320);
556 break;
557 case SNB_GMCH_GMS_STOLEN_352M:
558 stolen_size = MB(352);
559 break;
560 case SNB_GMCH_GMS_STOLEN_384M:
561 stolen_size = MB(384);
562 break;
563 case SNB_GMCH_GMS_STOLEN_416M:
564 stolen_size = MB(416);
565 break;
566 case SNB_GMCH_GMS_STOLEN_448M:
567 stolen_size = MB(448);
568 break;
569 case SNB_GMCH_GMS_STOLEN_480M:
570 stolen_size = MB(480);
571 break;
572 case SNB_GMCH_GMS_STOLEN_512M:
573 stolen_size = MB(512);
574 break;
575 }
576 } else {
577 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
578 case I855_GMCH_GMS_STOLEN_1M:
579 stolen_size = MB(1);
580 break;
581 case I855_GMCH_GMS_STOLEN_4M:
582 stolen_size = MB(4);
583 break;
584 case I855_GMCH_GMS_STOLEN_8M:
585 stolen_size = MB(8);
586 break;
587 case I855_GMCH_GMS_STOLEN_16M:
588 stolen_size = MB(16);
589 break;
590 case I855_GMCH_GMS_STOLEN_32M:
591 stolen_size = MB(32);
592 break;
593 case I915_GMCH_GMS_STOLEN_48M:
594 stolen_size = MB(48);
595 break;
596 case I915_GMCH_GMS_STOLEN_64M:
597 stolen_size = MB(64);
598 break;
599 case G33_GMCH_GMS_STOLEN_128M:
600 stolen_size = MB(128);
601 break;
602 case G33_GMCH_GMS_STOLEN_256M:
603 stolen_size = MB(256);
604 break;
605 case INTEL_GMCH_GMS_STOLEN_96M:
606 stolen_size = MB(96);
607 break;
608 case INTEL_GMCH_GMS_STOLEN_160M:
609 stolen_size = MB(160);
610 break;
611 case INTEL_GMCH_GMS_STOLEN_224M:
612 stolen_size = MB(224);
613 break;
614 case INTEL_GMCH_GMS_STOLEN_352M:
615 stolen_size = MB(352);
616 break;
617 default:
618 stolen_size = 0;
619 break;
620 }
621 }
622
623 if (!local && stolen_size > intel_max_stolen) {
624 dev_info(&intel_private.bridge_dev->dev,
625 "detected %dK stolen memory, trimming to %dK\n",
626 stolen_size / KB(1), intel_max_stolen / KB(1));
627 stolen_size = intel_max_stolen;
628 } else if (stolen_size > 0) {
629 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
630 stolen_size / KB(1), local ? "local" : "stolen");
631 } else {
632 dev_info(&intel_private.bridge_dev->dev,
633 "no pre-allocated video memory detected\n");
634 stolen_size = 0;
635 }
636
637 stolen_entries = stolen_size/KB(4) - overhead_entries;
638
639 return stolen_entries;
640 }
641
642 static unsigned int intel_gtt_total_entries(void)
643 {
644 int size;
645
646 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) {
647 u32 pgetbl_ctl;
648 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
649
650 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
651 case I965_PGETBL_SIZE_128KB:
652 size = KB(128);
653 break;
654 case I965_PGETBL_SIZE_256KB:
655 size = KB(256);
656 break;
657 case I965_PGETBL_SIZE_512KB:
658 size = KB(512);
659 break;
660 case I965_PGETBL_SIZE_1MB:
661 size = KB(1024);
662 break;
663 case I965_PGETBL_SIZE_2MB:
664 size = KB(2048);
665 break;
666 case I965_PGETBL_SIZE_1_5MB:
667 size = KB(1024 + 512);
668 break;
669 default:
670 dev_info(&intel_private.pcidev->dev,
671 "unknown page table size, assuming 512KB\n");
672 size = KB(512);
673 }
674
675 return size/4;
676 } else if (INTEL_GTT_GEN == 6) {
677 u16 snb_gmch_ctl;
678
679 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
680 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
681 default:
682 case SNB_GTT_SIZE_0M:
683 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
684 size = MB(0);
685 break;
686 case SNB_GTT_SIZE_1M:
687 size = MB(1);
688 break;
689 case SNB_GTT_SIZE_2M:
690 size = MB(2);
691 break;
692 }
693 return size/4;
694 } else {
695 /* On previous hardware, the GTT size was just what was
696 * required to map the aperture.
697 */
698 return intel_private.base.gtt_mappable_entries;
699 }
700 }
701
702 static unsigned int intel_gtt_mappable_entries(void)
703 {
704 unsigned int aperture_size;
705
706 if (INTEL_GTT_GEN == 2) {
707 u16 gmch_ctrl;
708
709 pci_read_config_word(intel_private.bridge_dev,
710 I830_GMCH_CTRL, &gmch_ctrl);
711
712 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
713 aperture_size = MB(64);
714 else
715 aperture_size = MB(128);
716 } else {
717 /* 9xx supports large sizes, just look at the length */
718 aperture_size = pci_resource_len(intel_private.pcidev, 2);
719 }
720
721 return aperture_size >> PAGE_SHIFT;
722 }
723
724 static void intel_gtt_teardown_scratch_page(void)
725 {
726 set_pages_wb(intel_private.scratch_page, 1);
727 pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
728 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
729 put_page(intel_private.scratch_page);
730 __free_page(intel_private.scratch_page);
731 }
732
733 static void intel_gtt_cleanup(void)
734 {
735 if (intel_private.i9xx_flush_page)
736 iounmap(intel_private.i9xx_flush_page);
737 if (intel_private.resource_valid)
738 release_resource(&intel_private.ifp_resource);
739 intel_private.ifp_resource.start = 0;
740 intel_private.resource_valid = 0;
741 iounmap(intel_private.gtt);
742 iounmap(intel_private.registers);
743
744 intel_gtt_teardown_scratch_page();
745 }
746
747 static int intel_gtt_init(void)
748 {
749 u32 gtt_map_size;
750 int ret;
751
752 ret = intel_private.driver->setup();
753 if (ret != 0)
754 return ret;
755
756 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
757 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
758
759 dev_info(&intel_private.bridge_dev->dev,
760 "detected gtt size: %dK total, %dK mappable\n",
761 intel_private.base.gtt_total_entries * 4,
762 intel_private.base.gtt_mappable_entries * 4);
763
764 gtt_map_size = intel_private.base.gtt_total_entries * 4;
765
766 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
767 gtt_map_size);
768 if (!intel_private.gtt) {
769 iounmap(intel_private.registers);
770 return -ENOMEM;
771 }
772
773 global_cache_flush(); /* FIXME: ? */
774
775 /* we have to call this as early as possible after the MMIO base address is known */
776 intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries();
777 if (intel_private.base.gtt_stolen_entries == 0) {
778 iounmap(intel_private.registers);
779 iounmap(intel_private.gtt);
780 return -ENOMEM;
781 }
782
783 ret = intel_gtt_setup_scratch_page();
784 if (ret != 0) {
785 intel_gtt_cleanup();
786 return ret;
787 }
788
789 return 0;
790 }
791
792 static int intel_fake_agp_fetch_size(void)
793 {
794 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
795 unsigned int aper_size;
796 int i;
797
798 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
799 / MB(1);
800
801 for (i = 0; i < num_sizes; i++) {
802 if (aper_size == intel_fake_agp_sizes[i].size) {
803 agp_bridge->current_size =
804 (void *) (intel_fake_agp_sizes + i);
805 return aper_size;
806 }
807 }
808
809 return 0;
810 }
811
812 static void intel_i830_fini_flush(void)
813 {
814 kunmap(intel_private.i8xx_page);
815 intel_private.i8xx_flush_page = NULL;
816 unmap_page_from_agp(intel_private.i8xx_page);
817
818 __free_page(intel_private.i8xx_page);
819 intel_private.i8xx_page = NULL;
820 }
821
822 static void intel_i830_setup_flush(void)
823 {
824 /* return if we've already set the flush mechanism up */
825 if (intel_private.i8xx_page)
826 return;
827
828 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
829 if (!intel_private.i8xx_page)
830 return;
831
832 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
833 if (!intel_private.i8xx_flush_page)
834 intel_i830_fini_flush();
835 }
836
837 /* The chipset_flush interface needs to get data that has already been
838 * flushed out of the CPU all the way out to main memory, because the GPU
839 * doesn't snoop those buffers.
840 *
841 * The 8xx series doesn't have the same lovely interface for flushing the
842 * chipset write buffers that the later chips do. According to the 865
843 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
844 * that buffer out, we just fill 1KB and clflush it out, on the assumption
845 * that it'll push whatever was in there out. It appears to work.
846 */
847 static void i830_chipset_flush(void)
848 {
849 unsigned int *pg = intel_private.i8xx_flush_page;
850
851 memset(pg, 0, 1024);
852
853 if (cpu_has_clflush)
854 clflush_cache_range(pg, 1024);
855 else if (wbinvd_on_all_cpus() != 0)
856 printk(KERN_ERR "Timed out waiting for cache flush.\n");
857 }
858
859 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
860 unsigned int flags)
861 {
862 u32 pte_flags = I810_PTE_VALID;
863
864 switch (flags) {
865 case AGP_DCACHE_MEMORY:
866 pte_flags |= I810_PTE_LOCAL;
867 break;
868 case AGP_USER_CACHED_MEMORY:
869 pte_flags |= I830_PTE_SYSTEM_CACHED;
870 break;
871 }
872
873 writel(addr | pte_flags, intel_private.gtt + entry);
874 }
875
876 static void intel_enable_gtt(void)
877 {
878 u32 gma_addr;
879 u16 gmch_ctrl;
880
881 if (INTEL_GTT_GEN == 2)
882 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
883 &gma_addr);
884 else
885 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
886 &gma_addr);
887
888 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
889
890 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
891 gmch_ctrl |= I830_GMCH_ENABLED;
892 pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
893
894 writel(intel_private.pte_bus_addr|I810_PGETBL_ENABLED,
895 intel_private.registers+I810_PGETBL_CTL);
896 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
897 }
898
899 static int i830_setup(void)
900 {
901 u32 reg_addr;
902
903 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
904 reg_addr &= 0xfff80000;
905
906 intel_private.registers = ioremap(reg_addr, KB(64));
907 if (!intel_private.registers)
908 return -ENOMEM;
909
910 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
911 intel_private.pte_bus_addr =
912 readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
913
914 intel_i830_setup_flush();
915
916 return 0;
917 }
918
919 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
920 {
921 agp_bridge->gatt_table_real = NULL;
922 agp_bridge->gatt_table = NULL;
923 agp_bridge->gatt_bus_addr = 0;
924
925 return 0;
926 }
927
928 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
929 {
930 return 0;
931 }
932
933 static int intel_fake_agp_configure(void)
934 {
935 int i;
936
937 intel_enable_gtt();
938
939 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
940
941 for (i = intel_private.base.gtt_stolen_entries;
942 i < intel_private.base.gtt_total_entries; i++) {
943 intel_private.driver->write_entry(intel_private.scratch_page_dma,
944 i, 0);
945 }
946 readl(intel_private.gtt+i-1); /* PCI Posting. */
947
948 global_cache_flush();
949
950 return 0;
951 }
952
953 static bool i830_check_flags(unsigned int flags)
954 {
955 switch (flags) {
956 case 0:
957 case AGP_PHYS_MEMORY:
958 case AGP_USER_CACHED_MEMORY:
959 case AGP_USER_MEMORY:
960 return true;
961 }
962
963 return false;
964 }
965
966 static void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
967 unsigned int sg_len,
968 unsigned int pg_start,
969 unsigned int flags)
970 {
971 struct scatterlist *sg;
972 unsigned int len, m;
973 int i, j;
974
975 j = pg_start;
976
977 /* sg may merge pages, but we have to separate
978 * per-page addr for GTT */
979 for_each_sg(sg_list, sg, sg_len, i) {
980 len = sg_dma_len(sg) >> PAGE_SHIFT;
981 for (m = 0; m < len; m++) {
982 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
983 intel_private.driver->write_entry(addr,
984 j, flags);
985 j++;
986 }
987 }
988 readl(intel_private.gtt+j-1);
989 }
990
991 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
992 off_t pg_start, int type)
993 {
994 int i, j;
995 int ret = -EINVAL;
996
997 if (mem->page_count == 0)
998 goto out;
999
1000 if (pg_start < intel_private.base.gtt_stolen_entries) {
1001 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1002 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1003 pg_start, intel_private.base.gtt_stolen_entries);
1004
1005 dev_info(&intel_private.pcidev->dev,
1006 "trying to insert into local/stolen memory\n");
1007 goto out_err;
1008 }
1009
1010 if ((pg_start + mem->page_count) > intel_private.base.gtt_total_entries)
1011 goto out_err;
1012
1013 if (type != mem->type)
1014 goto out_err;
1015
1016 if (!intel_private.driver->check_flags(type))
1017 goto out_err;
1018
1019 if (!mem->is_flushed)
1020 global_cache_flush();
1021
1022 if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) {
1023 ret = intel_agp_map_memory(mem);
1024 if (ret != 0)
1025 return ret;
1026
1027 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg,
1028 pg_start, type);
1029 } else {
1030 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1031 dma_addr_t addr = page_to_phys(mem->pages[i]);
1032 intel_private.driver->write_entry(addr,
1033 j, type);
1034 }
1035 readl(intel_private.gtt+j-1);
1036 }
1037
1038 out:
1039 ret = 0;
1040 out_err:
1041 mem->is_flushed = true;
1042 return ret;
1043 }
1044
1045 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
1046 off_t pg_start, int type)
1047 {
1048 int i;
1049
1050 if (mem->page_count == 0)
1051 return 0;
1052
1053 if (pg_start < intel_private.base.gtt_stolen_entries) {
1054 dev_info(&intel_private.pcidev->dev,
1055 "trying to disable local/stolen memory\n");
1056 return -EINVAL;
1057 }
1058
1059 if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2)
1060 intel_agp_unmap_memory(mem);
1061
1062 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1063 intel_private.driver->write_entry(intel_private.scratch_page_dma,
1064 i, 0);
1065 }
1066 readl(intel_private.gtt+i-1);
1067
1068 return 0;
1069 }
1070
1071 static void intel_fake_agp_chipset_flush(struct agp_bridge_data *bridge)
1072 {
1073 intel_private.driver->chipset_flush();
1074 }
1075
1076 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1077 int type)
1078 {
1079 if (type == AGP_PHYS_MEMORY)
1080 return alloc_agpphysmem_i8xx(pg_count, type);
1081 /* always return NULL for other allocation types for now */
1082 return NULL;
1083 }
1084
1085 static int intel_alloc_chipset_flush_resource(void)
1086 {
1087 int ret;
1088 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1089 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1090 pcibios_align_resource, intel_private.bridge_dev);
1091
1092 return ret;
1093 }
1094
1095 static void intel_i915_setup_chipset_flush(void)
1096 {
1097 int ret;
1098 u32 temp;
1099
1100 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1101 if (!(temp & 0x1)) {
1102 intel_alloc_chipset_flush_resource();
1103 intel_private.resource_valid = 1;
1104 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1105 } else {
1106 temp &= ~1;
1107
1108 intel_private.resource_valid = 1;
1109 intel_private.ifp_resource.start = temp;
1110 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1111 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1112 /* some BIOSes reserve this area in a pnp some don't */
1113 if (ret)
1114 intel_private.resource_valid = 0;
1115 }
1116 }
1117
1118 static void intel_i965_g33_setup_chipset_flush(void)
1119 {
1120 u32 temp_hi, temp_lo;
1121 int ret;
1122
1123 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1124 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1125
1126 if (!(temp_lo & 0x1)) {
1127
1128 intel_alloc_chipset_flush_resource();
1129
1130 intel_private.resource_valid = 1;
1131 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1132 upper_32_bits(intel_private.ifp_resource.start));
1133 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1134 } else {
1135 u64 l64;
1136
1137 temp_lo &= ~0x1;
1138 l64 = ((u64)temp_hi << 32) | temp_lo;
1139
1140 intel_private.resource_valid = 1;
1141 intel_private.ifp_resource.start = l64;
1142 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1143 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1144 /* some BIOSes reserve this area in a pnp some don't */
1145 if (ret)
1146 intel_private.resource_valid = 0;
1147 }
1148 }
1149
1150 static void intel_i9xx_setup_flush(void)
1151 {
1152 /* return if already configured */
1153 if (intel_private.ifp_resource.start)
1154 return;
1155
1156 if (INTEL_GTT_GEN == 6)
1157 return;
1158
1159 /* setup a resource for this object */
1160 intel_private.ifp_resource.name = "Intel Flush Page";
1161 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1162
1163 /* Setup chipset flush for 915 */
1164 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1165 intel_i965_g33_setup_chipset_flush();
1166 } else {
1167 intel_i915_setup_chipset_flush();
1168 }
1169
1170 if (intel_private.ifp_resource.start)
1171 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1172 if (!intel_private.i9xx_flush_page)
1173 dev_err(&intel_private.pcidev->dev,
1174 "can't ioremap flush page - no chipset flushing\n");
1175 }
1176
1177 static void i9xx_chipset_flush(void)
1178 {
1179 if (intel_private.i9xx_flush_page)
1180 writel(1, intel_private.i9xx_flush_page);
1181 }
1182
1183 static void i965_write_entry(dma_addr_t addr, unsigned int entry,
1184 unsigned int flags)
1185 {
1186 /* Shift high bits down */
1187 addr |= (addr >> 28) & 0xf0;
1188 writel(addr | I810_PTE_VALID, intel_private.gtt + entry);
1189 }
1190
1191 static bool gen6_check_flags(unsigned int flags)
1192 {
1193 return true;
1194 }
1195
1196 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1197 unsigned int flags)
1198 {
1199 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1200 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1201 u32 pte_flags;
1202
1203 if (type_mask == AGP_USER_UNCACHED_MEMORY)
1204 pte_flags = GEN6_PTE_UNCACHED;
1205 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1206 pte_flags = GEN6_PTE_LLC;
1207 if (gfdt)
1208 pte_flags |= GEN6_PTE_GFDT;
1209 } else { /* set 'normal'/'cached' to LLC by default */
1210 pte_flags = GEN6_PTE_LLC_MLC;
1211 if (gfdt)
1212 pte_flags |= GEN6_PTE_GFDT;
1213 }
1214
1215 /* gen6 has bit11-4 for physical addr bit39-32 */
1216 addr |= (addr >> 28) & 0xff0;
1217 writel(addr | pte_flags, intel_private.gtt + entry);
1218 }
1219
1220 static int i9xx_setup(void)
1221 {
1222 u32 reg_addr;
1223
1224 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1225
1226 reg_addr &= 0xfff80000;
1227
1228 intel_private.registers = ioremap(reg_addr, 128 * 4096);
1229 if (!intel_private.registers)
1230 return -ENOMEM;
1231
1232 if (INTEL_GTT_GEN == 3) {
1233 u32 gtt_addr;
1234
1235 pci_read_config_dword(intel_private.pcidev,
1236 I915_PTEADDR, &gtt_addr);
1237 intel_private.gtt_bus_addr = gtt_addr;
1238 } else {
1239 u32 gtt_offset;
1240
1241 switch (INTEL_GTT_GEN) {
1242 case 5:
1243 case 6:
1244 gtt_offset = MB(2);
1245 break;
1246 case 4:
1247 default:
1248 gtt_offset = KB(512);
1249 break;
1250 }
1251 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1252 }
1253
1254 intel_private.pte_bus_addr =
1255 readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1256
1257 intel_i9xx_setup_flush();
1258
1259 return 0;
1260 }
1261
1262 static const struct agp_bridge_driver intel_810_driver = {
1263 .owner = THIS_MODULE,
1264 .aperture_sizes = intel_i810_sizes,
1265 .size_type = FIXED_APER_SIZE,
1266 .num_aperture_sizes = 2,
1267 .needs_scratch_page = true,
1268 .configure = intel_i810_configure,
1269 .fetch_size = intel_i810_fetch_size,
1270 .cleanup = intel_i810_cleanup,
1271 .mask_memory = intel_i810_mask_memory,
1272 .masks = intel_i810_masks,
1273 .agp_enable = intel_fake_agp_enable,
1274 .cache_flush = global_cache_flush,
1275 .create_gatt_table = agp_generic_create_gatt_table,
1276 .free_gatt_table = agp_generic_free_gatt_table,
1277 .insert_memory = intel_i810_insert_entries,
1278 .remove_memory = intel_i810_remove_entries,
1279 .alloc_by_type = intel_i810_alloc_by_type,
1280 .free_by_type = intel_i810_free_by_type,
1281 .agp_alloc_page = agp_generic_alloc_page,
1282 .agp_alloc_pages = agp_generic_alloc_pages,
1283 .agp_destroy_page = agp_generic_destroy_page,
1284 .agp_destroy_pages = agp_generic_destroy_pages,
1285 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1286 };
1287
1288 static const struct agp_bridge_driver intel_fake_agp_driver = {
1289 .owner = THIS_MODULE,
1290 .size_type = FIXED_APER_SIZE,
1291 .aperture_sizes = intel_fake_agp_sizes,
1292 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1293 .configure = intel_fake_agp_configure,
1294 .fetch_size = intel_fake_agp_fetch_size,
1295 .cleanup = intel_gtt_cleanup,
1296 .agp_enable = intel_fake_agp_enable,
1297 .cache_flush = global_cache_flush,
1298 .create_gatt_table = intel_fake_agp_create_gatt_table,
1299 .free_gatt_table = intel_fake_agp_free_gatt_table,
1300 .insert_memory = intel_fake_agp_insert_entries,
1301 .remove_memory = intel_fake_agp_remove_entries,
1302 .alloc_by_type = intel_fake_agp_alloc_by_type,
1303 .free_by_type = intel_i810_free_by_type,
1304 .agp_alloc_page = agp_generic_alloc_page,
1305 .agp_alloc_pages = agp_generic_alloc_pages,
1306 .agp_destroy_page = agp_generic_destroy_page,
1307 .agp_destroy_pages = agp_generic_destroy_pages,
1308 .chipset_flush = intel_fake_agp_chipset_flush,
1309 };
1310
1311 static const struct intel_gtt_driver i81x_gtt_driver = {
1312 .gen = 1,
1313 .dma_mask_size = 32,
1314 };
1315 static const struct intel_gtt_driver i8xx_gtt_driver = {
1316 .gen = 2,
1317 .setup = i830_setup,
1318 .write_entry = i830_write_entry,
1319 .dma_mask_size = 32,
1320 .check_flags = i830_check_flags,
1321 .chipset_flush = i830_chipset_flush,
1322 };
1323 static const struct intel_gtt_driver i915_gtt_driver = {
1324 .gen = 3,
1325 .setup = i9xx_setup,
1326 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1327 .write_entry = i830_write_entry,
1328 .dma_mask_size = 32,
1329 .check_flags = i830_check_flags,
1330 .chipset_flush = i9xx_chipset_flush,
1331 };
1332 static const struct intel_gtt_driver g33_gtt_driver = {
1333 .gen = 3,
1334 .is_g33 = 1,
1335 .setup = i9xx_setup,
1336 .write_entry = i965_write_entry,
1337 .dma_mask_size = 36,
1338 .check_flags = i830_check_flags,
1339 .chipset_flush = i9xx_chipset_flush,
1340 };
1341 static const struct intel_gtt_driver pineview_gtt_driver = {
1342 .gen = 3,
1343 .is_pineview = 1, .is_g33 = 1,
1344 .setup = i9xx_setup,
1345 .write_entry = i965_write_entry,
1346 .dma_mask_size = 36,
1347 .check_flags = i830_check_flags,
1348 .chipset_flush = i9xx_chipset_flush,
1349 };
1350 static const struct intel_gtt_driver i965_gtt_driver = {
1351 .gen = 4,
1352 .setup = i9xx_setup,
1353 .write_entry = i965_write_entry,
1354 .dma_mask_size = 36,
1355 .check_flags = i830_check_flags,
1356 .chipset_flush = i9xx_chipset_flush,
1357 };
1358 static const struct intel_gtt_driver g4x_gtt_driver = {
1359 .gen = 5,
1360 .setup = i9xx_setup,
1361 .write_entry = i965_write_entry,
1362 .dma_mask_size = 36,
1363 .check_flags = i830_check_flags,
1364 .chipset_flush = i9xx_chipset_flush,
1365 };
1366 static const struct intel_gtt_driver ironlake_gtt_driver = {
1367 .gen = 5,
1368 .is_ironlake = 1,
1369 .setup = i9xx_setup,
1370 .write_entry = i965_write_entry,
1371 .dma_mask_size = 36,
1372 .check_flags = i830_check_flags,
1373 .chipset_flush = i9xx_chipset_flush,
1374 };
1375 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1376 .gen = 6,
1377 .setup = i9xx_setup,
1378 .write_entry = gen6_write_entry,
1379 .dma_mask_size = 40,
1380 .check_flags = gen6_check_flags,
1381 .chipset_flush = i9xx_chipset_flush,
1382 };
1383
1384 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1385 * driver and gmch_driver must be non-null, and find_gmch will determine
1386 * which one should be used if a gmch_chip_id is present.
1387 */
1388 static const struct intel_gtt_driver_description {
1389 unsigned int gmch_chip_id;
1390 char *name;
1391 const struct agp_bridge_driver *gmch_driver;
1392 const struct intel_gtt_driver *gtt_driver;
1393 } intel_gtt_chipsets[] = {
1394 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver,
1395 &i81x_gtt_driver},
1396 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver,
1397 &i81x_gtt_driver},
1398 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver,
1399 &i81x_gtt_driver},
1400 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver,
1401 &i81x_gtt_driver},
1402 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1403 &intel_fake_agp_driver, &i8xx_gtt_driver},
1404 { PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1405 &intel_fake_agp_driver, &i8xx_gtt_driver},
1406 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1407 &intel_fake_agp_driver, &i8xx_gtt_driver},
1408 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1409 &intel_fake_agp_driver, &i8xx_gtt_driver},
1410 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1411 &intel_fake_agp_driver, &i8xx_gtt_driver},
1412 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1413 &intel_fake_agp_driver, &i915_gtt_driver },
1414 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1415 &intel_fake_agp_driver, &i915_gtt_driver },
1416 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1417 &intel_fake_agp_driver, &i915_gtt_driver },
1418 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1419 &intel_fake_agp_driver, &i915_gtt_driver },
1420 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1421 &intel_fake_agp_driver, &i915_gtt_driver },
1422 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1423 &intel_fake_agp_driver, &i915_gtt_driver },
1424 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1425 &intel_fake_agp_driver, &i965_gtt_driver },
1426 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1427 &intel_fake_agp_driver, &i965_gtt_driver },
1428 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1429 &intel_fake_agp_driver, &i965_gtt_driver },
1430 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1431 &intel_fake_agp_driver, &i965_gtt_driver },
1432 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1433 &intel_fake_agp_driver, &i965_gtt_driver },
1434 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1435 &intel_fake_agp_driver, &i965_gtt_driver },
1436 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1437 &intel_fake_agp_driver, &g33_gtt_driver },
1438 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1439 &intel_fake_agp_driver, &g33_gtt_driver },
1440 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1441 &intel_fake_agp_driver, &g33_gtt_driver },
1442 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1443 &intel_fake_agp_driver, &pineview_gtt_driver },
1444 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1445 &intel_fake_agp_driver, &pineview_gtt_driver },
1446 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1447 &intel_fake_agp_driver, &g4x_gtt_driver },
1448 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1449 &intel_fake_agp_driver, &g4x_gtt_driver },
1450 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1451 &intel_fake_agp_driver, &g4x_gtt_driver },
1452 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1453 &intel_fake_agp_driver, &g4x_gtt_driver },
1454 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1455 &intel_fake_agp_driver, &g4x_gtt_driver },
1456 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1457 &intel_fake_agp_driver, &g4x_gtt_driver },
1458 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1459 &intel_fake_agp_driver, &g4x_gtt_driver },
1460 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1461 "HD Graphics", &intel_fake_agp_driver, &ironlake_gtt_driver },
1462 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1463 "HD Graphics", &intel_fake_agp_driver, &ironlake_gtt_driver },
1464 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1465 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1466 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1467 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1468 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1469 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1470 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1471 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1472 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1473 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1474 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1475 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1476 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1477 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1478 { 0, NULL, NULL }
1479 };
1480
1481 static int find_gmch(u16 device)
1482 {
1483 struct pci_dev *gmch_device;
1484
1485 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1486 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1487 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1488 device, gmch_device);
1489 }
1490
1491 if (!gmch_device)
1492 return 0;
1493
1494 intel_private.pcidev = gmch_device;
1495 return 1;
1496 }
1497
1498 int intel_gmch_probe(struct pci_dev *pdev,
1499 struct agp_bridge_data *bridge)
1500 {
1501 int i, mask;
1502 bridge->driver = NULL;
1503
1504 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1505 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1506 bridge->driver =
1507 intel_gtt_chipsets[i].gmch_driver;
1508 intel_private.driver =
1509 intel_gtt_chipsets[i].gtt_driver;
1510 break;
1511 }
1512 }
1513
1514 if (!bridge->driver)
1515 return 0;
1516
1517 bridge->dev_private_data = &intel_private;
1518 bridge->dev = pdev;
1519
1520 intel_private.bridge_dev = pci_dev_get(pdev);
1521
1522 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1523
1524 mask = intel_private.driver->dma_mask_size;
1525 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1526 dev_err(&intel_private.pcidev->dev,
1527 "set gfx device dma mask %d-bit failed!\n", mask);
1528 else
1529 pci_set_consistent_dma_mask(intel_private.pcidev,
1530 DMA_BIT_MASK(mask));
1531
1532 if (bridge->driver == &intel_810_driver)
1533 return 1;
1534
1535 if (intel_gtt_init() != 0)
1536 return 0;
1537
1538 return 1;
1539 }
1540 EXPORT_SYMBOL(intel_gmch_probe);
1541
1542 struct intel_gtt *intel_gtt_get(void)
1543 {
1544 return &intel_private.base;
1545 }
1546 EXPORT_SYMBOL(intel_gtt_get);
1547
1548 void intel_gmch_remove(struct pci_dev *pdev)
1549 {
1550 if (intel_private.pcidev)
1551 pci_dev_put(intel_private.pcidev);
1552 if (intel_private.bridge_dev)
1553 pci_dev_put(intel_private.bridge_dev);
1554 }
1555 EXPORT_SYMBOL(intel_gmch_remove);
1556
1557 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1558 MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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