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intel-gtt: consolidate i9xx setup
[deliverable/linux.git] / drivers / char / agp / intel-gtt.c
1 /*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <asm/smp.h>
25 #include "agp.h"
26 #include "intel-agp.h"
27 #include <linux/intel-gtt.h>
28 #include <drm/intel-gtt.h>
29
30 /*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_DMAR).
34 * Only newer chipsets need to bother with this, of course.
35 */
36 #ifdef CONFIG_DMAR
37 #define USE_PCI_DMA_API 1
38 #endif
39
40 /* Max amount of stolen space, anything above will be returned to Linux */
41 int intel_max_stolen = 32 * 1024 * 1024;
42 EXPORT_SYMBOL(intel_max_stolen);
43
44 static const struct aper_size_info_fixed intel_i810_sizes[] =
45 {
46 {64, 16384, 4},
47 /* The 32M mode still requires a 64k gatt */
48 {32, 8192, 4}
49 };
50
51 #define AGP_DCACHE_MEMORY 1
52 #define AGP_PHYS_MEMORY 2
53 #define INTEL_AGP_CACHED_MEMORY 3
54
55 static struct gatt_mask intel_i810_masks[] =
56 {
57 {.mask = I810_PTE_VALID, .type = 0},
58 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
59 {.mask = I810_PTE_VALID, .type = 0},
60 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
61 .type = INTEL_AGP_CACHED_MEMORY}
62 };
63
64 #define INTEL_AGP_UNCACHED_MEMORY 0
65 #define INTEL_AGP_CACHED_MEMORY_LLC 1
66 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
67 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
68 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
69
70 static struct gatt_mask intel_gen6_masks[] =
71 {
72 {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED,
73 .type = INTEL_AGP_UNCACHED_MEMORY },
74 {.mask = I810_PTE_VALID | GEN6_PTE_LLC,
75 .type = INTEL_AGP_CACHED_MEMORY_LLC },
76 {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT,
77 .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT },
78 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC,
79 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC },
80 {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT,
81 .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },
82 };
83
84 struct intel_gtt_driver {
85 unsigned int gen : 8;
86 unsigned int is_g33 : 1;
87 unsigned int is_pineview : 1;
88 unsigned int is_ironlake : 1;
89 /* Chipset specific GTT setup */
90 int (*setup)(void);
91 };
92
93 static struct _intel_private {
94 struct intel_gtt base;
95 const struct intel_gtt_driver *driver;
96 struct pci_dev *pcidev; /* device one */
97 struct pci_dev *bridge_dev;
98 u8 __iomem *registers;
99 phys_addr_t gtt_bus_addr;
100 phys_addr_t gma_bus_addr;
101 u32 __iomem *gtt; /* I915G */
102 int num_dcache_entries;
103 union {
104 void __iomem *i9xx_flush_page;
105 void *i8xx_flush_page;
106 };
107 struct page *i8xx_page;
108 struct resource ifp_resource;
109 int resource_valid;
110 } intel_private;
111
112 #define INTEL_GTT_GEN intel_private.driver->gen
113 #define IS_G33 intel_private.driver->is_g33
114 #define IS_PINEVIEW intel_private.driver->is_pineview
115 #define IS_IRONLAKE intel_private.driver->is_ironlake
116
117 #ifdef USE_PCI_DMA_API
118 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
119 {
120 *ret = pci_map_page(intel_private.pcidev, page, 0,
121 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
122 if (pci_dma_mapping_error(intel_private.pcidev, *ret))
123 return -EINVAL;
124 return 0;
125 }
126
127 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
128 {
129 pci_unmap_page(intel_private.pcidev, dma,
130 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
131 }
132
133 static void intel_agp_free_sglist(struct agp_memory *mem)
134 {
135 struct sg_table st;
136
137 st.sgl = mem->sg_list;
138 st.orig_nents = st.nents = mem->page_count;
139
140 sg_free_table(&st);
141
142 mem->sg_list = NULL;
143 mem->num_sg = 0;
144 }
145
146 static int intel_agp_map_memory(struct agp_memory *mem)
147 {
148 struct sg_table st;
149 struct scatterlist *sg;
150 int i;
151
152 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
153
154 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
155 goto err;
156
157 mem->sg_list = sg = st.sgl;
158
159 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
160 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
161
162 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
163 mem->page_count, PCI_DMA_BIDIRECTIONAL);
164 if (unlikely(!mem->num_sg))
165 goto err;
166
167 return 0;
168
169 err:
170 sg_free_table(&st);
171 return -ENOMEM;
172 }
173
174 static void intel_agp_unmap_memory(struct agp_memory *mem)
175 {
176 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
177
178 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
179 mem->page_count, PCI_DMA_BIDIRECTIONAL);
180 intel_agp_free_sglist(mem);
181 }
182
183 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
184 off_t pg_start, int mask_type)
185 {
186 struct scatterlist *sg;
187 int i, j;
188
189 j = pg_start;
190
191 WARN_ON(!mem->num_sg);
192
193 if (mem->num_sg == mem->page_count) {
194 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
195 writel(agp_bridge->driver->mask_memory(agp_bridge,
196 sg_dma_address(sg), mask_type),
197 intel_private.gtt+j);
198 j++;
199 }
200 } else {
201 /* sg may merge pages, but we have to separate
202 * per-page addr for GTT */
203 unsigned int len, m;
204
205 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
206 len = sg_dma_len(sg) / PAGE_SIZE;
207 for (m = 0; m < len; m++) {
208 writel(agp_bridge->driver->mask_memory(agp_bridge,
209 sg_dma_address(sg) + m * PAGE_SIZE,
210 mask_type),
211 intel_private.gtt+j);
212 j++;
213 }
214 }
215 }
216 readl(intel_private.gtt+j-1);
217 }
218
219 #else
220
221 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
222 off_t pg_start, int mask_type)
223 {
224 int i, j;
225
226 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
227 writel(agp_bridge->driver->mask_memory(agp_bridge,
228 page_to_phys(mem->pages[i]), mask_type),
229 intel_private.gtt+j);
230 }
231
232 readl(intel_private.gtt+j-1);
233 }
234
235 #endif
236
237 static int intel_i810_fetch_size(void)
238 {
239 u32 smram_miscc;
240 struct aper_size_info_fixed *values;
241
242 pci_read_config_dword(intel_private.bridge_dev,
243 I810_SMRAM_MISCC, &smram_miscc);
244 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
245
246 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
247 dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
248 return 0;
249 }
250 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
251 agp_bridge->current_size = (void *) (values + 1);
252 agp_bridge->aperture_size_idx = 1;
253 return values[1].size;
254 } else {
255 agp_bridge->current_size = (void *) (values);
256 agp_bridge->aperture_size_idx = 0;
257 return values[0].size;
258 }
259
260 return 0;
261 }
262
263 static int intel_i810_configure(void)
264 {
265 struct aper_size_info_fixed *current_size;
266 u32 temp;
267 int i;
268
269 current_size = A_SIZE_FIX(agp_bridge->current_size);
270
271 if (!intel_private.registers) {
272 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
273 temp &= 0xfff80000;
274
275 intel_private.registers = ioremap(temp, 128 * 4096);
276 if (!intel_private.registers) {
277 dev_err(&intel_private.pcidev->dev,
278 "can't remap memory\n");
279 return -ENOMEM;
280 }
281 }
282
283 if ((readl(intel_private.registers+I810_DRAM_CTL)
284 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
285 /* This will need to be dynamically assigned */
286 dev_info(&intel_private.pcidev->dev,
287 "detected 4MB dedicated video ram\n");
288 intel_private.num_dcache_entries = 1024;
289 }
290 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
291 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
292 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
293 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
294
295 if (agp_bridge->driver->needs_scratch_page) {
296 for (i = 0; i < current_size->num_entries; i++) {
297 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
298 }
299 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
300 }
301 global_cache_flush();
302 return 0;
303 }
304
305 static void intel_i810_cleanup(void)
306 {
307 writel(0, intel_private.registers+I810_PGETBL_CTL);
308 readl(intel_private.registers); /* PCI Posting. */
309 iounmap(intel_private.registers);
310 }
311
312 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
313 {
314 return;
315 }
316
317 /* Exists to support ARGB cursors */
318 static struct page *i8xx_alloc_pages(void)
319 {
320 struct page *page;
321
322 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
323 if (page == NULL)
324 return NULL;
325
326 if (set_pages_uc(page, 4) < 0) {
327 set_pages_wb(page, 4);
328 __free_pages(page, 2);
329 return NULL;
330 }
331 get_page(page);
332 atomic_inc(&agp_bridge->current_memory_agp);
333 return page;
334 }
335
336 static void i8xx_destroy_pages(struct page *page)
337 {
338 if (page == NULL)
339 return;
340
341 set_pages_wb(page, 4);
342 put_page(page);
343 __free_pages(page, 2);
344 atomic_dec(&agp_bridge->current_memory_agp);
345 }
346
347 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
348 int type)
349 {
350 if (type < AGP_USER_TYPES)
351 return type;
352 else if (type == AGP_USER_CACHED_MEMORY)
353 return INTEL_AGP_CACHED_MEMORY;
354 else
355 return 0;
356 }
357
358 static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge,
359 int type)
360 {
361 unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT;
362 unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT;
363
364 if (type_mask == AGP_USER_UNCACHED_MEMORY)
365 return INTEL_AGP_UNCACHED_MEMORY;
366 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
367 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT :
368 INTEL_AGP_CACHED_MEMORY_LLC_MLC;
369 else /* set 'normal'/'cached' to LLC by default */
370 return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT :
371 INTEL_AGP_CACHED_MEMORY_LLC;
372 }
373
374
375 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
376 int type)
377 {
378 int i, j, num_entries;
379 void *temp;
380 int ret = -EINVAL;
381 int mask_type;
382
383 if (mem->page_count == 0)
384 goto out;
385
386 temp = agp_bridge->current_size;
387 num_entries = A_SIZE_FIX(temp)->num_entries;
388
389 if ((pg_start + mem->page_count) > num_entries)
390 goto out_err;
391
392
393 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
394 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
395 ret = -EBUSY;
396 goto out_err;
397 }
398 }
399
400 if (type != mem->type)
401 goto out_err;
402
403 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
404
405 switch (mask_type) {
406 case AGP_DCACHE_MEMORY:
407 if (!mem->is_flushed)
408 global_cache_flush();
409 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
410 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
411 intel_private.registers+I810_PTE_BASE+(i*4));
412 }
413 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
414 break;
415 case AGP_PHYS_MEMORY:
416 case AGP_NORMAL_MEMORY:
417 if (!mem->is_flushed)
418 global_cache_flush();
419 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
420 writel(agp_bridge->driver->mask_memory(agp_bridge,
421 page_to_phys(mem->pages[i]), mask_type),
422 intel_private.registers+I810_PTE_BASE+(j*4));
423 }
424 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
425 break;
426 default:
427 goto out_err;
428 }
429
430 out:
431 ret = 0;
432 out_err:
433 mem->is_flushed = true;
434 return ret;
435 }
436
437 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
438 int type)
439 {
440 int i;
441
442 if (mem->page_count == 0)
443 return 0;
444
445 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
446 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
447 }
448 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
449
450 return 0;
451 }
452
453 /*
454 * The i810/i830 requires a physical address to program its mouse
455 * pointer into hardware.
456 * However the Xserver still writes to it through the agp aperture.
457 */
458 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
459 {
460 struct agp_memory *new;
461 struct page *page;
462
463 switch (pg_count) {
464 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
465 break;
466 case 4:
467 /* kludge to get 4 physical pages for ARGB cursor */
468 page = i8xx_alloc_pages();
469 break;
470 default:
471 return NULL;
472 }
473
474 if (page == NULL)
475 return NULL;
476
477 new = agp_create_memory(pg_count);
478 if (new == NULL)
479 return NULL;
480
481 new->pages[0] = page;
482 if (pg_count == 4) {
483 /* kludge to get 4 physical pages for ARGB cursor */
484 new->pages[1] = new->pages[0] + 1;
485 new->pages[2] = new->pages[1] + 1;
486 new->pages[3] = new->pages[2] + 1;
487 }
488 new->page_count = pg_count;
489 new->num_scratch_pages = pg_count;
490 new->type = AGP_PHYS_MEMORY;
491 new->physical = page_to_phys(new->pages[0]);
492 return new;
493 }
494
495 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
496 {
497 struct agp_memory *new;
498
499 if (type == AGP_DCACHE_MEMORY) {
500 if (pg_count != intel_private.num_dcache_entries)
501 return NULL;
502
503 new = agp_create_memory(1);
504 if (new == NULL)
505 return NULL;
506
507 new->type = AGP_DCACHE_MEMORY;
508 new->page_count = pg_count;
509 new->num_scratch_pages = 0;
510 agp_free_page_array(new);
511 return new;
512 }
513 if (type == AGP_PHYS_MEMORY)
514 return alloc_agpphysmem_i8xx(pg_count, type);
515 return NULL;
516 }
517
518 static void intel_i810_free_by_type(struct agp_memory *curr)
519 {
520 agp_free_key(curr->key);
521 if (curr->type == AGP_PHYS_MEMORY) {
522 if (curr->page_count == 4)
523 i8xx_destroy_pages(curr->pages[0]);
524 else {
525 agp_bridge->driver->agp_destroy_page(curr->pages[0],
526 AGP_PAGE_DESTROY_UNMAP);
527 agp_bridge->driver->agp_destroy_page(curr->pages[0],
528 AGP_PAGE_DESTROY_FREE);
529 }
530 agp_free_page_array(curr);
531 }
532 kfree(curr);
533 }
534
535 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
536 dma_addr_t addr, int type)
537 {
538 /* Type checking must be done elsewhere */
539 return addr | bridge->driver->masks[type].mask;
540 }
541
542 static struct aper_size_info_fixed intel_fake_agp_sizes[] =
543 {
544 {128, 32768, 5},
545 /* The 64M mode still requires a 128k gatt */
546 {64, 16384, 5},
547 {256, 65536, 6},
548 {512, 131072, 7},
549 };
550
551 static unsigned int intel_gtt_stolen_entries(void)
552 {
553 u16 gmch_ctrl;
554 u8 rdct;
555 int local = 0;
556 static const int ddt[4] = { 0, 16, 32, 64 };
557 unsigned int overhead_entries, stolen_entries;
558 unsigned int stolen_size = 0;
559
560 pci_read_config_word(intel_private.bridge_dev,
561 I830_GMCH_CTRL, &gmch_ctrl);
562
563 if (INTEL_GTT_GEN > 4 || IS_PINEVIEW)
564 overhead_entries = 0;
565 else
566 overhead_entries = intel_private.base.gtt_mappable_entries
567 / 1024;
568
569 overhead_entries += 1; /* BIOS popup */
570
571 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
572 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
573 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
574 case I830_GMCH_GMS_STOLEN_512:
575 stolen_size = KB(512);
576 break;
577 case I830_GMCH_GMS_STOLEN_1024:
578 stolen_size = MB(1);
579 break;
580 case I830_GMCH_GMS_STOLEN_8192:
581 stolen_size = MB(8);
582 break;
583 case I830_GMCH_GMS_LOCAL:
584 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
585 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
586 MB(ddt[I830_RDRAM_DDT(rdct)]);
587 local = 1;
588 break;
589 default:
590 stolen_size = 0;
591 break;
592 }
593 } else if (INTEL_GTT_GEN == 6) {
594 /*
595 * SandyBridge has new memory control reg at 0x50.w
596 */
597 u16 snb_gmch_ctl;
598 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
599 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
600 case SNB_GMCH_GMS_STOLEN_32M:
601 stolen_size = MB(32);
602 break;
603 case SNB_GMCH_GMS_STOLEN_64M:
604 stolen_size = MB(64);
605 break;
606 case SNB_GMCH_GMS_STOLEN_96M:
607 stolen_size = MB(96);
608 break;
609 case SNB_GMCH_GMS_STOLEN_128M:
610 stolen_size = MB(128);
611 break;
612 case SNB_GMCH_GMS_STOLEN_160M:
613 stolen_size = MB(160);
614 break;
615 case SNB_GMCH_GMS_STOLEN_192M:
616 stolen_size = MB(192);
617 break;
618 case SNB_GMCH_GMS_STOLEN_224M:
619 stolen_size = MB(224);
620 break;
621 case SNB_GMCH_GMS_STOLEN_256M:
622 stolen_size = MB(256);
623 break;
624 case SNB_GMCH_GMS_STOLEN_288M:
625 stolen_size = MB(288);
626 break;
627 case SNB_GMCH_GMS_STOLEN_320M:
628 stolen_size = MB(320);
629 break;
630 case SNB_GMCH_GMS_STOLEN_352M:
631 stolen_size = MB(352);
632 break;
633 case SNB_GMCH_GMS_STOLEN_384M:
634 stolen_size = MB(384);
635 break;
636 case SNB_GMCH_GMS_STOLEN_416M:
637 stolen_size = MB(416);
638 break;
639 case SNB_GMCH_GMS_STOLEN_448M:
640 stolen_size = MB(448);
641 break;
642 case SNB_GMCH_GMS_STOLEN_480M:
643 stolen_size = MB(480);
644 break;
645 case SNB_GMCH_GMS_STOLEN_512M:
646 stolen_size = MB(512);
647 break;
648 }
649 } else {
650 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
651 case I855_GMCH_GMS_STOLEN_1M:
652 stolen_size = MB(1);
653 break;
654 case I855_GMCH_GMS_STOLEN_4M:
655 stolen_size = MB(4);
656 break;
657 case I855_GMCH_GMS_STOLEN_8M:
658 stolen_size = MB(8);
659 break;
660 case I855_GMCH_GMS_STOLEN_16M:
661 stolen_size = MB(16);
662 break;
663 case I855_GMCH_GMS_STOLEN_32M:
664 stolen_size = MB(32);
665 break;
666 case I915_GMCH_GMS_STOLEN_48M:
667 stolen_size = MB(48);
668 break;
669 case I915_GMCH_GMS_STOLEN_64M:
670 stolen_size = MB(64);
671 break;
672 case G33_GMCH_GMS_STOLEN_128M:
673 stolen_size = MB(128);
674 break;
675 case G33_GMCH_GMS_STOLEN_256M:
676 stolen_size = MB(256);
677 break;
678 case INTEL_GMCH_GMS_STOLEN_96M:
679 stolen_size = MB(96);
680 break;
681 case INTEL_GMCH_GMS_STOLEN_160M:
682 stolen_size = MB(160);
683 break;
684 case INTEL_GMCH_GMS_STOLEN_224M:
685 stolen_size = MB(224);
686 break;
687 case INTEL_GMCH_GMS_STOLEN_352M:
688 stolen_size = MB(352);
689 break;
690 default:
691 stolen_size = 0;
692 break;
693 }
694 }
695
696 if (!local && stolen_size > intel_max_stolen) {
697 dev_info(&intel_private.bridge_dev->dev,
698 "detected %dK stolen memory, trimming to %dK\n",
699 stolen_size / KB(1), intel_max_stolen / KB(1));
700 stolen_size = intel_max_stolen;
701 } else if (stolen_size > 0) {
702 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
703 stolen_size / KB(1), local ? "local" : "stolen");
704 } else {
705 dev_info(&intel_private.bridge_dev->dev,
706 "no pre-allocated video memory detected\n");
707 stolen_size = 0;
708 }
709
710 stolen_entries = stolen_size/KB(4) - overhead_entries;
711
712 return stolen_entries;
713 }
714
715 static unsigned int intel_gtt_total_entries(void)
716 {
717 int size;
718
719 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) {
720 u32 pgetbl_ctl;
721 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
722
723 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
724 case I965_PGETBL_SIZE_128KB:
725 size = KB(128);
726 break;
727 case I965_PGETBL_SIZE_256KB:
728 size = KB(256);
729 break;
730 case I965_PGETBL_SIZE_512KB:
731 size = KB(512);
732 break;
733 case I965_PGETBL_SIZE_1MB:
734 size = KB(1024);
735 break;
736 case I965_PGETBL_SIZE_2MB:
737 size = KB(2048);
738 break;
739 case I965_PGETBL_SIZE_1_5MB:
740 size = KB(1024 + 512);
741 break;
742 default:
743 dev_info(&intel_private.pcidev->dev,
744 "unknown page table size, assuming 512KB\n");
745 size = KB(512);
746 }
747
748 return size/4;
749 } else if (INTEL_GTT_GEN == 6) {
750 u16 snb_gmch_ctl;
751
752 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
753 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
754 default:
755 case SNB_GTT_SIZE_0M:
756 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
757 size = MB(0);
758 break;
759 case SNB_GTT_SIZE_1M:
760 size = MB(1);
761 break;
762 case SNB_GTT_SIZE_2M:
763 size = MB(2);
764 break;
765 }
766 return size/4;
767 } else {
768 /* On previous hardware, the GTT size was just what was
769 * required to map the aperture.
770 */
771 return intel_private.base.gtt_mappable_entries;
772 }
773 }
774
775 static unsigned int intel_gtt_mappable_entries(void)
776 {
777 unsigned int aperture_size;
778 u16 gmch_ctrl;
779
780 aperture_size = 1024 * 1024;
781
782 pci_read_config_word(intel_private.bridge_dev,
783 I830_GMCH_CTRL, &gmch_ctrl);
784
785 switch (intel_private.pcidev->device) {
786 case PCI_DEVICE_ID_INTEL_82830_CGC:
787 case PCI_DEVICE_ID_INTEL_82845G_IG:
788 case PCI_DEVICE_ID_INTEL_82855GM_IG:
789 case PCI_DEVICE_ID_INTEL_82865_IG:
790 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
791 aperture_size *= 64;
792 else
793 aperture_size *= 128;
794 break;
795 default:
796 /* 9xx supports large sizes, just look at the length */
797 aperture_size = pci_resource_len(intel_private.pcidev, 2);
798 break;
799 }
800
801 return aperture_size >> PAGE_SHIFT;
802 }
803
804 static int intel_gtt_init(void)
805 {
806 u32 gtt_map_size;
807
808 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
809 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
810
811 gtt_map_size = intel_private.base.gtt_total_entries * 4;
812
813 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
814 gtt_map_size);
815 if (!intel_private.gtt) {
816 iounmap(intel_private.registers);
817 return -ENOMEM;
818 }
819
820 global_cache_flush(); /* FIXME: ? */
821
822 /* we have to call this as early as possible after the MMIO base address is known */
823 intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries();
824 if (intel_private.base.gtt_stolen_entries == 0) {
825 iounmap(intel_private.registers);
826 iounmap(intel_private.gtt);
827 return -ENOMEM;
828 }
829
830 return 0;
831 }
832
833 static int intel_fake_agp_fetch_size(void)
834 {
835 unsigned int aper_size;
836 int i;
837 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
838
839 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
840 / MB(1);
841
842 for (i = 0; i < num_sizes; i++) {
843 if (aper_size == intel_fake_agp_sizes[i].size) {
844 agp_bridge->current_size = intel_fake_agp_sizes + i;
845 return aper_size;
846 }
847 }
848
849 return 0;
850 }
851
852 static void intel_i830_fini_flush(void)
853 {
854 kunmap(intel_private.i8xx_page);
855 intel_private.i8xx_flush_page = NULL;
856 unmap_page_from_agp(intel_private.i8xx_page);
857
858 __free_page(intel_private.i8xx_page);
859 intel_private.i8xx_page = NULL;
860 }
861
862 static void intel_i830_setup_flush(void)
863 {
864 /* return if we've already set the flush mechanism up */
865 if (intel_private.i8xx_page)
866 return;
867
868 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
869 if (!intel_private.i8xx_page)
870 return;
871
872 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
873 if (!intel_private.i8xx_flush_page)
874 intel_i830_fini_flush();
875 }
876
877 /* The chipset_flush interface needs to get data that has already been
878 * flushed out of the CPU all the way out to main memory, because the GPU
879 * doesn't snoop those buffers.
880 *
881 * The 8xx series doesn't have the same lovely interface for flushing the
882 * chipset write buffers that the later chips do. According to the 865
883 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
884 * that buffer out, we just fill 1KB and clflush it out, on the assumption
885 * that it'll push whatever was in there out. It appears to work.
886 */
887 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
888 {
889 unsigned int *pg = intel_private.i8xx_flush_page;
890
891 memset(pg, 0, 1024);
892
893 if (cpu_has_clflush)
894 clflush_cache_range(pg, 1024);
895 else if (wbinvd_on_all_cpus() != 0)
896 printk(KERN_ERR "Timed out waiting for cache flush.\n");
897 }
898
899 static void intel_enable_gtt(void)
900 {
901 u32 ptetbl_addr, gma_addr;
902 u16 gmch_ctrl;
903
904 ptetbl_addr = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
905
906 if (INTEL_GTT_GEN == 2)
907 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
908 &gma_addr);
909 else
910 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
911 &gma_addr);
912
913 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
914
915 pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl);
916 gmch_ctrl |= I830_GMCH_ENABLED;
917 pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
918
919 writel(ptetbl_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
920 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
921 }
922
923 static int i830_setup(void)
924 {
925 u32 reg_addr;
926
927 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
928 reg_addr &= 0xfff80000;
929
930 intel_private.registers = ioremap(reg_addr, KB(64));
931 if (!intel_private.registers)
932 return -ENOMEM;
933
934 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
935
936 intel_i830_setup_flush();
937
938 return 0;
939 }
940
941 /* The intel i830 automatically initializes the agp aperture during POST.
942 * Use the memory already set aside for in the GTT.
943 */
944 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
945 {
946 int ret;
947
948 ret = intel_private.driver->setup();
949 if (ret != 0)
950 return ret;
951
952 ret = intel_gtt_init();
953 if (ret != 0)
954 return ret;
955
956 agp_bridge->gatt_table_real = NULL;
957 agp_bridge->gatt_table = NULL;
958 agp_bridge->gatt_bus_addr = 0;
959
960 return 0;
961 }
962
963 /* Return the gatt table to a sane state. Use the top of stolen
964 * memory for the GTT.
965 */
966 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
967 {
968 return 0;
969 }
970
971 static int intel_i830_configure(void)
972 {
973 int i;
974
975 intel_enable_gtt();
976
977 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
978
979 if (agp_bridge->driver->needs_scratch_page) {
980 for (i = intel_private.base.gtt_stolen_entries;
981 i < intel_private.base.gtt_total_entries; i++) {
982 writel(agp_bridge->scratch_page, intel_private.gtt+i);
983 }
984 readl(intel_private.gtt+i-1); /* PCI Posting. */
985 }
986
987 global_cache_flush();
988
989 return 0;
990 }
991
992 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
993 int type)
994 {
995 int i, j, num_entries;
996 void *temp;
997 int ret = -EINVAL;
998 int mask_type;
999
1000 if (mem->page_count == 0)
1001 goto out;
1002
1003 temp = agp_bridge->current_size;
1004 num_entries = A_SIZE_FIX(temp)->num_entries;
1005
1006 if (pg_start < intel_private.base.gtt_stolen_entries) {
1007 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1008 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1009 pg_start, intel_private.base.gtt_stolen_entries);
1010
1011 dev_info(&intel_private.pcidev->dev,
1012 "trying to insert into local/stolen memory\n");
1013 goto out_err;
1014 }
1015
1016 if ((pg_start + mem->page_count) > num_entries)
1017 goto out_err;
1018
1019 /* The i830 can't check the GTT for entries since its read only,
1020 * depend on the caller to make the correct offset decisions.
1021 */
1022
1023 if (type != mem->type)
1024 goto out_err;
1025
1026 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1027
1028 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1029 mask_type != INTEL_AGP_CACHED_MEMORY)
1030 goto out_err;
1031
1032 if (!mem->is_flushed)
1033 global_cache_flush();
1034
1035 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1036 writel(agp_bridge->driver->mask_memory(agp_bridge,
1037 page_to_phys(mem->pages[i]), mask_type),
1038 intel_private.gtt+j);
1039 }
1040 readl(intel_private.gtt+j-1);
1041
1042 out:
1043 ret = 0;
1044 out_err:
1045 mem->is_flushed = true;
1046 return ret;
1047 }
1048
1049 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
1050 int type)
1051 {
1052 int i;
1053
1054 if (mem->page_count == 0)
1055 return 0;
1056
1057 if (pg_start < intel_private.base.gtt_stolen_entries) {
1058 dev_info(&intel_private.pcidev->dev,
1059 "trying to disable local/stolen memory\n");
1060 return -EINVAL;
1061 }
1062
1063 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1064 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1065 }
1066 readl(intel_private.gtt+i-1);
1067
1068 return 0;
1069 }
1070
1071 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1072 int type)
1073 {
1074 if (type == AGP_PHYS_MEMORY)
1075 return alloc_agpphysmem_i8xx(pg_count, type);
1076 /* always return NULL for other allocation types for now */
1077 return NULL;
1078 }
1079
1080 static int intel_alloc_chipset_flush_resource(void)
1081 {
1082 int ret;
1083 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1084 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1085 pcibios_align_resource, intel_private.bridge_dev);
1086
1087 return ret;
1088 }
1089
1090 static void intel_i915_setup_chipset_flush(void)
1091 {
1092 int ret;
1093 u32 temp;
1094
1095 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1096 if (!(temp & 0x1)) {
1097 intel_alloc_chipset_flush_resource();
1098 intel_private.resource_valid = 1;
1099 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1100 } else {
1101 temp &= ~1;
1102
1103 intel_private.resource_valid = 1;
1104 intel_private.ifp_resource.start = temp;
1105 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1106 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1107 /* some BIOSes reserve this area in a pnp some don't */
1108 if (ret)
1109 intel_private.resource_valid = 0;
1110 }
1111 }
1112
1113 static void intel_i965_g33_setup_chipset_flush(void)
1114 {
1115 u32 temp_hi, temp_lo;
1116 int ret;
1117
1118 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1119 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1120
1121 if (!(temp_lo & 0x1)) {
1122
1123 intel_alloc_chipset_flush_resource();
1124
1125 intel_private.resource_valid = 1;
1126 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1127 upper_32_bits(intel_private.ifp_resource.start));
1128 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1129 } else {
1130 u64 l64;
1131
1132 temp_lo &= ~0x1;
1133 l64 = ((u64)temp_hi << 32) | temp_lo;
1134
1135 intel_private.resource_valid = 1;
1136 intel_private.ifp_resource.start = l64;
1137 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1138 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1139 /* some BIOSes reserve this area in a pnp some don't */
1140 if (ret)
1141 intel_private.resource_valid = 0;
1142 }
1143 }
1144
1145 static void intel_i9xx_setup_flush(void)
1146 {
1147 /* return if already configured */
1148 if (intel_private.ifp_resource.start)
1149 return;
1150
1151 if (INTEL_GTT_GEN == 6)
1152 return;
1153
1154 /* setup a resource for this object */
1155 intel_private.ifp_resource.name = "Intel Flush Page";
1156 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1157
1158 /* Setup chipset flush for 915 */
1159 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1160 intel_i965_g33_setup_chipset_flush();
1161 } else {
1162 intel_i915_setup_chipset_flush();
1163 }
1164
1165 if (intel_private.ifp_resource.start)
1166 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1167 if (!intel_private.i9xx_flush_page)
1168 dev_err(&intel_private.pcidev->dev,
1169 "can't ioremap flush page - no chipset flushing\n");
1170 }
1171
1172 static int intel_i9xx_configure(void)
1173 {
1174 int i;
1175
1176 intel_enable_gtt();
1177
1178 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
1179
1180 if (agp_bridge->driver->needs_scratch_page) {
1181 for (i = intel_private.base.gtt_stolen_entries; i <
1182 intel_private.base.gtt_total_entries; i++) {
1183 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1184 }
1185 readl(intel_private.gtt+i-1); /* PCI Posting. */
1186 }
1187
1188 global_cache_flush();
1189
1190 return 0;
1191 }
1192
1193 static void intel_gtt_cleanup(void)
1194 {
1195 if (intel_private.i9xx_flush_page)
1196 iounmap(intel_private.i9xx_flush_page);
1197 if (intel_private.resource_valid)
1198 release_resource(&intel_private.ifp_resource);
1199 intel_private.ifp_resource.start = 0;
1200 intel_private.resource_valid = 0;
1201 iounmap(intel_private.gtt);
1202 iounmap(intel_private.registers);
1203 }
1204
1205 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1206 {
1207 if (intel_private.i9xx_flush_page)
1208 writel(1, intel_private.i9xx_flush_page);
1209 }
1210
1211 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1212 int type)
1213 {
1214 int num_entries;
1215 void *temp;
1216 int ret = -EINVAL;
1217 int mask_type;
1218
1219 if (mem->page_count == 0)
1220 goto out;
1221
1222 temp = agp_bridge->current_size;
1223 num_entries = A_SIZE_FIX(temp)->num_entries;
1224
1225 if (pg_start < intel_private.base.gtt_stolen_entries) {
1226 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1227 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1228 pg_start, intel_private.base.gtt_stolen_entries);
1229
1230 dev_info(&intel_private.pcidev->dev,
1231 "trying to insert into local/stolen memory\n");
1232 goto out_err;
1233 }
1234
1235 if ((pg_start + mem->page_count) > num_entries)
1236 goto out_err;
1237
1238 /* The i915 can't check the GTT for entries since it's read only;
1239 * depend on the caller to make the correct offset decisions.
1240 */
1241
1242 if (type != mem->type)
1243 goto out_err;
1244
1245 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1246
1247 if (INTEL_GTT_GEN != 6 && mask_type != 0 &&
1248 mask_type != AGP_PHYS_MEMORY &&
1249 mask_type != INTEL_AGP_CACHED_MEMORY)
1250 goto out_err;
1251
1252 if (!mem->is_flushed)
1253 global_cache_flush();
1254
1255 intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1256
1257 out:
1258 ret = 0;
1259 out_err:
1260 mem->is_flushed = true;
1261 return ret;
1262 }
1263
1264 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1265 int type)
1266 {
1267 int i;
1268
1269 if (mem->page_count == 0)
1270 return 0;
1271
1272 if (pg_start < intel_private.base.gtt_stolen_entries) {
1273 dev_info(&intel_private.pcidev->dev,
1274 "trying to disable local/stolen memory\n");
1275 return -EINVAL;
1276 }
1277
1278 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1279 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1280
1281 readl(intel_private.gtt+i-1);
1282
1283 return 0;
1284 }
1285
1286 static int i9xx_setup(void)
1287 {
1288 u32 reg_addr;
1289
1290 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1291
1292 reg_addr &= 0xfff80000;
1293
1294 intel_private.registers = ioremap(reg_addr, 128 * 4096);
1295 if (!intel_private.registers)
1296 return -ENOMEM;
1297
1298 if (INTEL_GTT_GEN == 3) {
1299 u32 gtt_addr;
1300 pci_read_config_dword(intel_private.pcidev,
1301 I915_PTEADDR, &gtt_addr);
1302 intel_private.gtt_bus_addr = gtt_addr;
1303 } else {
1304 u32 gtt_offset;
1305
1306 switch (INTEL_GTT_GEN) {
1307 case 5:
1308 case 6:
1309 gtt_offset = MB(2);
1310 break;
1311 case 4:
1312 default:
1313 gtt_offset = KB(512);
1314 break;
1315 }
1316 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1317 }
1318
1319 intel_i9xx_setup_flush();
1320
1321 return 0;
1322 }
1323
1324 /* The intel i915 automatically initializes the agp aperture during POST.
1325 * Use the memory already set aside for in the GTT.
1326 */
1327 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1328 {
1329 int ret;
1330
1331 ret = intel_private.driver->setup();
1332 if (ret != 0)
1333 return ret;
1334
1335 ret = intel_gtt_init();
1336 if (ret != 0)
1337 return ret;
1338
1339 agp_bridge->gatt_table_real = NULL;
1340 agp_bridge->gatt_table = NULL;
1341 agp_bridge->gatt_bus_addr = 0;
1342
1343 return 0;
1344 }
1345
1346 /*
1347 * The i965 supports 36-bit physical addresses, but to keep
1348 * the format of the GTT the same, the bits that don't fit
1349 * in a 32-bit word are shifted down to bits 4..7.
1350 *
1351 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1352 * is always zero on 32-bit architectures, so no need to make
1353 * this conditional.
1354 */
1355 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1356 dma_addr_t addr, int type)
1357 {
1358 /* Shift high bits down */
1359 addr |= (addr >> 28) & 0xf0;
1360
1361 /* Type checking must be done elsewhere */
1362 return addr | bridge->driver->masks[type].mask;
1363 }
1364
1365 static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
1366 dma_addr_t addr, int type)
1367 {
1368 /* gen6 has bit11-4 for physical addr bit39-32 */
1369 addr |= (addr >> 28) & 0xff0;
1370
1371 /* Type checking must be done elsewhere */
1372 return addr | bridge->driver->masks[type].mask;
1373 }
1374
1375 static const struct agp_bridge_driver intel_810_driver = {
1376 .owner = THIS_MODULE,
1377 .aperture_sizes = intel_i810_sizes,
1378 .size_type = FIXED_APER_SIZE,
1379 .num_aperture_sizes = 2,
1380 .needs_scratch_page = true,
1381 .configure = intel_i810_configure,
1382 .fetch_size = intel_i810_fetch_size,
1383 .cleanup = intel_i810_cleanup,
1384 .mask_memory = intel_i810_mask_memory,
1385 .masks = intel_i810_masks,
1386 .agp_enable = intel_fake_agp_enable,
1387 .cache_flush = global_cache_flush,
1388 .create_gatt_table = agp_generic_create_gatt_table,
1389 .free_gatt_table = agp_generic_free_gatt_table,
1390 .insert_memory = intel_i810_insert_entries,
1391 .remove_memory = intel_i810_remove_entries,
1392 .alloc_by_type = intel_i810_alloc_by_type,
1393 .free_by_type = intel_i810_free_by_type,
1394 .agp_alloc_page = agp_generic_alloc_page,
1395 .agp_alloc_pages = agp_generic_alloc_pages,
1396 .agp_destroy_page = agp_generic_destroy_page,
1397 .agp_destroy_pages = agp_generic_destroy_pages,
1398 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1399 };
1400
1401 static const struct agp_bridge_driver intel_830_driver = {
1402 .owner = THIS_MODULE,
1403 .aperture_sizes = intel_fake_agp_sizes,
1404 .size_type = FIXED_APER_SIZE,
1405 .num_aperture_sizes = 4,
1406 .needs_scratch_page = true,
1407 .configure = intel_i830_configure,
1408 .fetch_size = intel_fake_agp_fetch_size,
1409 .cleanup = intel_gtt_cleanup,
1410 .mask_memory = intel_i810_mask_memory,
1411 .masks = intel_i810_masks,
1412 .agp_enable = intel_fake_agp_enable,
1413 .cache_flush = global_cache_flush,
1414 .create_gatt_table = intel_i830_create_gatt_table,
1415 .free_gatt_table = intel_fake_agp_free_gatt_table,
1416 .insert_memory = intel_i830_insert_entries,
1417 .remove_memory = intel_i830_remove_entries,
1418 .alloc_by_type = intel_fake_agp_alloc_by_type,
1419 .free_by_type = intel_i810_free_by_type,
1420 .agp_alloc_page = agp_generic_alloc_page,
1421 .agp_alloc_pages = agp_generic_alloc_pages,
1422 .agp_destroy_page = agp_generic_destroy_page,
1423 .agp_destroy_pages = agp_generic_destroy_pages,
1424 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1425 .chipset_flush = intel_i830_chipset_flush,
1426 };
1427
1428 static const struct agp_bridge_driver intel_915_driver = {
1429 .owner = THIS_MODULE,
1430 .aperture_sizes = intel_fake_agp_sizes,
1431 .size_type = FIXED_APER_SIZE,
1432 .num_aperture_sizes = 4,
1433 .needs_scratch_page = true,
1434 .configure = intel_i9xx_configure,
1435 .fetch_size = intel_fake_agp_fetch_size,
1436 .cleanup = intel_gtt_cleanup,
1437 .mask_memory = intel_i810_mask_memory,
1438 .masks = intel_i810_masks,
1439 .agp_enable = intel_fake_agp_enable,
1440 .cache_flush = global_cache_flush,
1441 .create_gatt_table = intel_i915_create_gatt_table,
1442 .free_gatt_table = intel_fake_agp_free_gatt_table,
1443 .insert_memory = intel_i915_insert_entries,
1444 .remove_memory = intel_i915_remove_entries,
1445 .alloc_by_type = intel_fake_agp_alloc_by_type,
1446 .free_by_type = intel_i810_free_by_type,
1447 .agp_alloc_page = agp_generic_alloc_page,
1448 .agp_alloc_pages = agp_generic_alloc_pages,
1449 .agp_destroy_page = agp_generic_destroy_page,
1450 .agp_destroy_pages = agp_generic_destroy_pages,
1451 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1452 .chipset_flush = intel_i915_chipset_flush,
1453 #ifdef USE_PCI_DMA_API
1454 .agp_map_page = intel_agp_map_page,
1455 .agp_unmap_page = intel_agp_unmap_page,
1456 .agp_map_memory = intel_agp_map_memory,
1457 .agp_unmap_memory = intel_agp_unmap_memory,
1458 #endif
1459 };
1460
1461 static const struct agp_bridge_driver intel_i965_driver = {
1462 .owner = THIS_MODULE,
1463 .aperture_sizes = intel_fake_agp_sizes,
1464 .size_type = FIXED_APER_SIZE,
1465 .num_aperture_sizes = 4,
1466 .needs_scratch_page = true,
1467 .configure = intel_i9xx_configure,
1468 .fetch_size = intel_fake_agp_fetch_size,
1469 .cleanup = intel_gtt_cleanup,
1470 .mask_memory = intel_i965_mask_memory,
1471 .masks = intel_i810_masks,
1472 .agp_enable = intel_fake_agp_enable,
1473 .cache_flush = global_cache_flush,
1474 .create_gatt_table = intel_i915_create_gatt_table,
1475 .free_gatt_table = intel_fake_agp_free_gatt_table,
1476 .insert_memory = intel_i915_insert_entries,
1477 .remove_memory = intel_i915_remove_entries,
1478 .alloc_by_type = intel_fake_agp_alloc_by_type,
1479 .free_by_type = intel_i810_free_by_type,
1480 .agp_alloc_page = agp_generic_alloc_page,
1481 .agp_alloc_pages = agp_generic_alloc_pages,
1482 .agp_destroy_page = agp_generic_destroy_page,
1483 .agp_destroy_pages = agp_generic_destroy_pages,
1484 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1485 .chipset_flush = intel_i915_chipset_flush,
1486 #ifdef USE_PCI_DMA_API
1487 .agp_map_page = intel_agp_map_page,
1488 .agp_unmap_page = intel_agp_unmap_page,
1489 .agp_map_memory = intel_agp_map_memory,
1490 .agp_unmap_memory = intel_agp_unmap_memory,
1491 #endif
1492 };
1493
1494 static const struct agp_bridge_driver intel_gen6_driver = {
1495 .owner = THIS_MODULE,
1496 .aperture_sizes = intel_fake_agp_sizes,
1497 .size_type = FIXED_APER_SIZE,
1498 .num_aperture_sizes = 4,
1499 .needs_scratch_page = true,
1500 .configure = intel_i9xx_configure,
1501 .fetch_size = intel_fake_agp_fetch_size,
1502 .cleanup = intel_gtt_cleanup,
1503 .mask_memory = intel_gen6_mask_memory,
1504 .masks = intel_gen6_masks,
1505 .agp_enable = intel_fake_agp_enable,
1506 .cache_flush = global_cache_flush,
1507 .create_gatt_table = intel_i915_create_gatt_table,
1508 .free_gatt_table = intel_fake_agp_free_gatt_table,
1509 .insert_memory = intel_i915_insert_entries,
1510 .remove_memory = intel_i915_remove_entries,
1511 .alloc_by_type = intel_fake_agp_alloc_by_type,
1512 .free_by_type = intel_i810_free_by_type,
1513 .agp_alloc_page = agp_generic_alloc_page,
1514 .agp_alloc_pages = agp_generic_alloc_pages,
1515 .agp_destroy_page = agp_generic_destroy_page,
1516 .agp_destroy_pages = agp_generic_destroy_pages,
1517 .agp_type_to_mask_type = intel_gen6_type_to_mask_type,
1518 .chipset_flush = intel_i915_chipset_flush,
1519 #ifdef USE_PCI_DMA_API
1520 .agp_map_page = intel_agp_map_page,
1521 .agp_unmap_page = intel_agp_unmap_page,
1522 .agp_map_memory = intel_agp_map_memory,
1523 .agp_unmap_memory = intel_agp_unmap_memory,
1524 #endif
1525 };
1526
1527 static const struct agp_bridge_driver intel_g33_driver = {
1528 .owner = THIS_MODULE,
1529 .aperture_sizes = intel_fake_agp_sizes,
1530 .size_type = FIXED_APER_SIZE,
1531 .num_aperture_sizes = 4,
1532 .needs_scratch_page = true,
1533 .configure = intel_i9xx_configure,
1534 .fetch_size = intel_fake_agp_fetch_size,
1535 .cleanup = intel_gtt_cleanup,
1536 .mask_memory = intel_i965_mask_memory,
1537 .masks = intel_i810_masks,
1538 .agp_enable = intel_fake_agp_enable,
1539 .cache_flush = global_cache_flush,
1540 .create_gatt_table = intel_i915_create_gatt_table,
1541 .free_gatt_table = intel_fake_agp_free_gatt_table,
1542 .insert_memory = intel_i915_insert_entries,
1543 .remove_memory = intel_i915_remove_entries,
1544 .alloc_by_type = intel_fake_agp_alloc_by_type,
1545 .free_by_type = intel_i810_free_by_type,
1546 .agp_alloc_page = agp_generic_alloc_page,
1547 .agp_alloc_pages = agp_generic_alloc_pages,
1548 .agp_destroy_page = agp_generic_destroy_page,
1549 .agp_destroy_pages = agp_generic_destroy_pages,
1550 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1551 .chipset_flush = intel_i915_chipset_flush,
1552 #ifdef USE_PCI_DMA_API
1553 .agp_map_page = intel_agp_map_page,
1554 .agp_unmap_page = intel_agp_unmap_page,
1555 .agp_map_memory = intel_agp_map_memory,
1556 .agp_unmap_memory = intel_agp_unmap_memory,
1557 #endif
1558 };
1559
1560 static const struct intel_gtt_driver i8xx_gtt_driver = {
1561 .gen = 2,
1562 .setup = i830_setup,
1563 };
1564 static const struct intel_gtt_driver i915_gtt_driver = {
1565 .gen = 3,
1566 .setup = i9xx_setup,
1567 };
1568 static const struct intel_gtt_driver g33_gtt_driver = {
1569 .gen = 3,
1570 .is_g33 = 1,
1571 .setup = i9xx_setup,
1572 };
1573 static const struct intel_gtt_driver pineview_gtt_driver = {
1574 .gen = 3,
1575 .is_pineview = 1, .is_g33 = 1,
1576 .setup = i9xx_setup,
1577 };
1578 static const struct intel_gtt_driver i965_gtt_driver = {
1579 .gen = 4,
1580 .setup = i9xx_setup,
1581 };
1582 static const struct intel_gtt_driver g4x_gtt_driver = {
1583 .gen = 5,
1584 .setup = i9xx_setup,
1585 };
1586 static const struct intel_gtt_driver ironlake_gtt_driver = {
1587 .gen = 5,
1588 .is_ironlake = 1,
1589 .setup = i9xx_setup,
1590 };
1591 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1592 .gen = 6,
1593 .setup = i9xx_setup,
1594 };
1595
1596 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1597 * driver and gmch_driver must be non-null, and find_gmch will determine
1598 * which one should be used if a gmch_chip_id is present.
1599 */
1600 static const struct intel_gtt_driver_description {
1601 unsigned int gmch_chip_id;
1602 char *name;
1603 const struct agp_bridge_driver *gmch_driver;
1604 const struct intel_gtt_driver *gtt_driver;
1605 } intel_gtt_chipsets[] = {
1606 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver , NULL},
1607 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver , NULL},
1608 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver , NULL},
1609 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver , NULL},
1610 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1611 &intel_830_driver , &i8xx_gtt_driver},
1612 { PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1613 &intel_830_driver , &i8xx_gtt_driver},
1614 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1615 &intel_830_driver , &i8xx_gtt_driver},
1616 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1617 &intel_830_driver , &i8xx_gtt_driver},
1618 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1619 &intel_830_driver , &i8xx_gtt_driver},
1620 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1621 &intel_915_driver , &i915_gtt_driver },
1622 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1623 &intel_915_driver , &i915_gtt_driver },
1624 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1625 &intel_915_driver , &i915_gtt_driver },
1626 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1627 &intel_915_driver , &i915_gtt_driver },
1628 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1629 &intel_915_driver , &i915_gtt_driver },
1630 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1631 &intel_915_driver , &i915_gtt_driver },
1632 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1633 &intel_i965_driver , &i965_gtt_driver },
1634 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1635 &intel_i965_driver , &i965_gtt_driver },
1636 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1637 &intel_i965_driver , &i965_gtt_driver },
1638 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1639 &intel_i965_driver , &i965_gtt_driver },
1640 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1641 &intel_i965_driver , &i965_gtt_driver },
1642 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1643 &intel_i965_driver , &i965_gtt_driver },
1644 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1645 &intel_g33_driver , &g33_gtt_driver },
1646 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1647 &intel_g33_driver , &g33_gtt_driver },
1648 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1649 &intel_g33_driver , &g33_gtt_driver },
1650 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1651 &intel_g33_driver , &pineview_gtt_driver },
1652 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1653 &intel_g33_driver , &pineview_gtt_driver },
1654 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1655 &intel_i965_driver , &g4x_gtt_driver },
1656 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1657 &intel_i965_driver , &g4x_gtt_driver },
1658 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1659 &intel_i965_driver , &g4x_gtt_driver },
1660 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1661 &intel_i965_driver , &g4x_gtt_driver },
1662 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1663 &intel_i965_driver , &g4x_gtt_driver },
1664 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1665 &intel_i965_driver , &g4x_gtt_driver },
1666 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1667 "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1668 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1669 "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver },
1670 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1671 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1672 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1673 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1674 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1675 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1676 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1677 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1678 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1679 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1680 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1681 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1682 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1683 "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver },
1684 { 0, NULL, NULL }
1685 };
1686
1687 static int find_gmch(u16 device)
1688 {
1689 struct pci_dev *gmch_device;
1690
1691 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1692 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1693 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1694 device, gmch_device);
1695 }
1696
1697 if (!gmch_device)
1698 return 0;
1699
1700 intel_private.pcidev = gmch_device;
1701 return 1;
1702 }
1703
1704 int intel_gmch_probe(struct pci_dev *pdev,
1705 struct agp_bridge_data *bridge)
1706 {
1707 int i, mask;
1708 bridge->driver = NULL;
1709
1710 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1711 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1712 bridge->driver =
1713 intel_gtt_chipsets[i].gmch_driver;
1714 intel_private.driver =
1715 intel_gtt_chipsets[i].gtt_driver;
1716 break;
1717 }
1718 }
1719
1720 if (!bridge->driver)
1721 return 0;
1722
1723 bridge->dev_private_data = &intel_private;
1724 bridge->dev = pdev;
1725
1726 intel_private.bridge_dev = pci_dev_get(pdev);
1727
1728 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1729
1730 if (bridge->driver->mask_memory == intel_gen6_mask_memory)
1731 mask = 40;
1732 else if (bridge->driver->mask_memory == intel_i965_mask_memory)
1733 mask = 36;
1734 else
1735 mask = 32;
1736
1737 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1738 dev_err(&intel_private.pcidev->dev,
1739 "set gfx device dma mask %d-bit failed!\n", mask);
1740 else
1741 pci_set_consistent_dma_mask(intel_private.pcidev,
1742 DMA_BIT_MASK(mask));
1743
1744 if (bridge->driver == &intel_810_driver)
1745 return 1;
1746
1747 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
1748
1749 return 1;
1750 }
1751 EXPORT_SYMBOL(intel_gmch_probe);
1752
1753 void intel_gmch_remove(struct pci_dev *pdev)
1754 {
1755 if (intel_private.pcidev)
1756 pci_dev_put(intel_private.pcidev);
1757 if (intel_private.bridge_dev)
1758 pci_dev_put(intel_private.bridge_dev);
1759 }
1760 EXPORT_SYMBOL(intel_gmch_remove);
1761
1762 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1763 MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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